From: Robert Hoo <robert.hu@linux.intel.com>
To: Richard Henderson <richard.henderson@linaro.org>,
pbonzini@redhat.com, ehabkost@redhat.com
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH v3] i386/cpu_dump: support AVX512 ZMM regs dump
Date: Fri, 26 Mar 2021 22:16:41 +0800 [thread overview]
Message-ID: <5f2371ec8a0a67947a0ace04348b18308f34c55c.camel@linux.intel.com> (raw)
In-Reply-To: <54b5fe3c-5bfe-209a-9600-4a86fefb7b2c@linaro.org>
On Fri, 2021-03-26 at 07:11 -0600, Richard Henderson wrote:
> On 3/25/21 7:47 PM, Robert Hoo wrote:
> > On Thu, 2021-03-25 at 06:39 -0600, Richard Henderson wrote:
> > > On 3/24/21 9:15 PM, Robert Hoo wrote:
> > > > > > + } else if (env->xcr0 & XFEATURE_AVX) {
> > > > >
> > > > > This is normally a 2-bit test.
> > > >
> > > > I beg your pardon. What 2 bits?
> > >
> > > I forget the names, but isn't the usual test xcr0 & 6 == 6?
> >
> > 6 stands for SSE state-component and AVX state-component.
> > I'm not sure about this.
> > Can you remember where did you this "xcr0 & 6 == 6"? I can look
> > into
> > that.
>
> IA-64 and IA32 Software developers manual, Vol 1 Basic Architecture,
> Section
> 14.3 Detection of AVX instructions.
OK, thanks Richard. If use the feature detection criteria here, then
AVX512 case will also need XCR0[2:1]='11b'.
I'm going to send v4 soon.
>
>
> r~
prev parent reply other threads:[~2021-03-26 14:17 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-24 8:00 [PATCH v3] i386/cpu_dump: support AVX512 ZMM regs dump Robert Hoo
2021-03-24 13:44 ` Richard Henderson
2021-03-25 3:15 ` Robert Hoo
2021-03-25 12:39 ` Richard Henderson
2021-03-26 1:47 ` Robert Hoo
2021-03-26 13:11 ` Richard Henderson
2021-03-26 14:16 ` Robert Hoo [this message]
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