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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id ka36-20020a056a0093a400b006e48e0499dfsm1866046pfb.39.2024.02.21.10.50.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Feb 2024 10:50:10 -0800 (PST) Message-ID: <5f25d9cf-3ca0-4adb-860e-71a8fac3b504@linaro.org> Date: Wed, 21 Feb 2024 08:50:07 -1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v2 03/22] target/arm: Add PSTATE.ALLINT Content-Language: en-US To: Jinjie Ruan , peter.maydell@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20240221130823.677762-1-ruanjinjie@huawei.com> <20240221130823.677762-4-ruanjinjie@huawei.com> From: Richard Henderson In-Reply-To: <20240221130823.677762-4-ruanjinjie@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/21/24 03:08, Jinjie Ruan via wrote: > The ALLINT bit in PSTATE is used to mask all IRQ or FIQ interrupts. > > Place this in its own field within ENV, as that will > make it easier to reset from within TCG generated code. > > With the change to pstate_read/write, exception entry > and return are automatically handled. > > Signed-off-by: Jinjie Ruan > --- > target/arm/cpu.c | 3 +++ > target/arm/cpu.h | 9 +++++++-- > 2 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 5fa86bc8d5..5e5978c302 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1104,6 +1104,9 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) > if (cpu_isar_feature(aa64_bti, cpu)) { > qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); > } > + if (cpu_isar_feature(aa64_nmi, cpu)) { > + qemu_fprintf(f, " ALLINT=%d", (psr & PSTATE_ALLINT) >> 13); > + } This is one bit -- !!(psr & ALLINT) is better We don't individually print DAIF either; why is this bit more special? > @@ -224,6 +224,7 @@ typedef struct CPUArchState { > * semantics as for AArch32, as described in the comments on each field) > * nRW (also known as M[4]) is kept, inverted, in env->aarch64 > * DAIF (exception masks) are kept in env->daif > + * ALLINT (all IRQ or FIQ interrupts masks) are kept in env->allint > * BTYPE is kept in env->btype > * SM and ZA are kept in env->svcr > * all other bits are stored in their correct places in env->pstate > @@ -261,6 +262,7 @@ typedef struct CPUArchState { > uint32_t btype; /* BTI branch type. spsr[11:10]. */ > uint64_t daif; /* exception masks, in the bits they are in PSTATE */ > uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ > + uint64_t allint; /* All IRQ or FIQ interrupt mask, in the bit in PSTATE */ Why is this split out from env->pstate? The allint bit matches the documentation for SPSR_EL1, which is how env->pstate is documented. The other exclusions have some performance imperative which I don't see for allint. r~