From: Weiwei Li <liweiwei@iscas.ac.cn>
To: Lawrence Hunter <lawrence.hunter@codethink.co.uk>, qemu-devel@nongnu.org
Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk,
kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com,
palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, pbonzini@redhat.com,
philipp.tomsich@vrull.eu, kvm@vger.kernel.org,
qemu-riscv@nongnu.org, richard.henderson@linaro.org,
liweiwei@iscas.ac.cn
Subject: Re: [PATCH v3 06/19] target/riscv: Refactor translation of vector-widening instruction
Date: Sat, 29 Apr 2023 11:06:39 +0800 [thread overview]
Message-ID: <5f35016c-a207-22d9-f13a-ba6985d7a299@iscas.ac.cn> (raw)
In-Reply-To: <20230428144757.57530-7-lawrence.hunter@codethink.co.uk>
On 2023/4/28 22:47, Lawrence Hunter wrote:
> From: Dickon Hood <dickon.hood@codethink.co.uk>
>
> Zvbb (implemented in later commit) has a widening instruction, which
> requires an extra check on the enabled extensions. Refactor
> GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing
> it.
>
> Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Weiwei Li
> target/riscv/insn_trans/trans_rvv.c.inc | 52 +++++++++++--------------
> 1 file changed, 23 insertions(+), 29 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 21731b784ec..2c2a097b76d 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1526,30 +1526,24 @@ static bool opivx_widen_check(DisasContext *s, arg_rmrr *a)
> vext_check_ds(s, a->rd, a->rs2, a->vm);
> }
>
> -static bool do_opivx_widen(DisasContext *s, arg_rmrr *a,
> - gen_helper_opivx *fn)
> -{
> - if (opivx_widen_check(s, a)) {
> - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
> - }
> - return false;
> +#define GEN_OPIVX_WIDEN_TRANS(NAME, CHECK) \
> +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> +{ \
> + if (CHECK(s, a)) { \
> + static gen_helper_opivx * const fns[3] = { \
> + gen_helper_##NAME##_b, \
> + gen_helper_##NAME##_h, \
> + gen_helper_##NAME##_w \
> + }; \
> + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s); \
> + } \
> + return false; \
> }
>
> -#define GEN_OPIVX_WIDEN_TRANS(NAME) \
> -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> -{ \
> - static gen_helper_opivx * const fns[3] = { \
> - gen_helper_##NAME##_b, \
> - gen_helper_##NAME##_h, \
> - gen_helper_##NAME##_w \
> - }; \
> - return do_opivx_widen(s, a, fns[s->sew]); \
> -}
> -
> -GEN_OPIVX_WIDEN_TRANS(vwaddu_vx)
> -GEN_OPIVX_WIDEN_TRANS(vwadd_vx)
> -GEN_OPIVX_WIDEN_TRANS(vwsubu_vx)
> -GEN_OPIVX_WIDEN_TRANS(vwsub_vx)
> +GEN_OPIVX_WIDEN_TRANS(vwaddu_vx, opivx_widen_check)
> +GEN_OPIVX_WIDEN_TRANS(vwadd_vx, opivx_widen_check)
> +GEN_OPIVX_WIDEN_TRANS(vwsubu_vx, opivx_widen_check)
> +GEN_OPIVX_WIDEN_TRANS(vwsub_vx, opivx_widen_check)
>
> /* WIDEN OPIVV with WIDEN */
> static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a)
> @@ -1997,9 +1991,9 @@ GEN_OPIVX_TRANS(vrem_vx, opivx_check)
> GEN_OPIVV_WIDEN_TRANS(vwmul_vv, opivv_widen_check)
> GEN_OPIVV_WIDEN_TRANS(vwmulu_vv, opivv_widen_check)
> GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check)
> -GEN_OPIVX_WIDEN_TRANS(vwmul_vx)
> -GEN_OPIVX_WIDEN_TRANS(vwmulu_vx)
> -GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx)
> +GEN_OPIVX_WIDEN_TRANS(vwmul_vx, opivx_widen_check)
> +GEN_OPIVX_WIDEN_TRANS(vwmulu_vx, opivx_widen_check)
> +GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx, opivx_widen_check)
>
> /* Vector Single-Width Integer Multiply-Add Instructions */
> GEN_OPIVV_TRANS(vmacc_vv, opivv_check)
> @@ -2015,10 +2009,10 @@ GEN_OPIVX_TRANS(vnmsub_vx, opivx_check)
> GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check)
> GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check)
> GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check)
> -GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx)
> -GEN_OPIVX_WIDEN_TRANS(vwmacc_vx)
> -GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx)
> -GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx)
> +GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx, opivx_widen_check)
> +GEN_OPIVX_WIDEN_TRANS(vwmacc_vx, opivx_widen_check)
> +GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx, opivx_widen_check)
> +GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx, opivx_widen_check)
>
> /* Vector Integer Merge and Move Instructions */
> static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
next prev parent reply other threads:[~2023-04-29 3:07 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-28 14:47 [PATCH v3 00/19] Add RISC-V vector cryptographic instruction set support Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 01/19] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-04-29 1:29 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 02/19] target/riscv: Refactor vector-vector translation macro Lawrence Hunter
2023-04-29 1:31 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 03/19] target/riscv: Remove redundant "cpu_vl == 0" checks Lawrence Hunter
2023-04-29 2:36 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 04/19] target/riscv: Add Zvbc ISA extension support Lawrence Hunter
2023-04-29 2:58 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 05/19] target/riscv: Move vector translation checks Lawrence Hunter
2023-04-29 3:04 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 06/19] target/riscv: Refactor translation of vector-widening instruction Lawrence Hunter
2023-04-29 3:06 ` Weiwei Li [this message]
2023-04-28 14:47 ` [PATCH v3 07/19] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-04-29 3:10 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 08/19] qemu/bitops.h: Limit rotate amounts Lawrence Hunter
2023-05-01 19:56 ` Richard Henderson
2023-05-02 20:11 ` Richard Henderson
2023-04-28 14:47 ` [PATCH v3 09/19] tcg: Add andcs and rotrs tcg gvec ops Lawrence Hunter
2023-05-01 20:20 ` Richard Henderson
2023-04-28 14:47 ` [PATCH v3 10/19] qemu/host-utils.h: Add clz and ctz functions for lower-bit integers Lawrence Hunter
2023-05-01 19:56 ` Richard Henderson
2023-04-28 14:47 ` [PATCH v3 11/19] target/riscv: Add Zvbb ISA extension support Lawrence Hunter
2023-04-29 3:15 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 12/19] target/riscv: Add Zvkned " Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 13/19] target/riscv: Add Zvknh " Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 14/19] target/riscv: Add Zvksh " Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 15/19] target/riscv: Add Zvkg " Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 16/19] crypto: Create sm4_subword Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 17/19] crypto: Add SM4 constant parameter CK Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 18/19] target/riscv: Add Zvksed ISA extension support Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 19/19] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties Lawrence Hunter
2023-04-29 3:21 ` Weiwei Li
2023-06-16 9:21 ` [PATCH v3 00/19] Add RISC-V vector cryptographic instruction set support Daniel Henrique Barboza
2023-06-16 15:03 ` Max Chou
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