Re: [PULL v2 00/45] riscv-to-apply queue

[Thomas Huth <thuth@redhat.com>]

On 21/12/2022 23.39, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
> 
> The following changes since commit 222059a0fccf4af3be776fe35a5ea2d6a68f9a0b:
> 
>    Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into staging (2022-12-21 18:08:09 +0000)
> 
> are available in the Git repository at:
> 
>    https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20221222-1
> 
> for you to fetch changes up to 71a9bc59728a054036f3db7dd82dab8f8bd2baf9:
> 
>    hw/intc: sifive_plic: Fix the pending register range check (2022-12-22 08:36:30 +1000)
> 
> ----------------------------------------------------------------
> First RISC-V PR for QEMU 8.0
> 
> * Fix PMP propagation for tlb
> * Collection of bug fixes
> * Add the `FIELDx_1CLEAR()` macro
> * Bump the OpenTitan supported version
> * Add smstateen support
> * Support native debug icount trigger
> * Remove the redundant ipi-id property in the virt machine
> * Support cache-related PMU events in virtual mode
> * Add some missing PolarFire SoC io regions
> * Fix mret exception cause when no pmp rule is configured
> * Fix bug where disabling compressed instructions would crash QEMU
> * Add Zawrs ISA extension support
> * A range of code refactoring and cleanups
> 
> ----------------------------------------------------------------
> Anup Patel (1):
>        target/riscv: Typo fix in sstc() predicate
> 
> Atish Patra (1):
>        hw/riscv: virt: Remove the redundant ipi-id property
> 
> Bin Meng (20):
>        target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()
>        target/riscv: Fix mret exception cause when no pmp rule is configured
>        target/riscv: Simplify helper_sret() a little bit
>        target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+
>        hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
>        hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers
>        hw/riscv: Fix opentitan dependency to SIFIVE_PLIC
>        hw/riscv: Sort machines Kconfig options in alphabetical order
>        hw/riscv: spike: Remove misleading comments
>        hw/intc: sifive_plic: Drop PLICMode_H
>        hw/intc: sifive_plic: Improve robustness of the PLIC config parser
>        hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize()
>        hw/intc: sifive_plic: Update "num-sources" property default value
>        hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC
>        hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC
>        hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"
>        hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb
>        hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0
>        hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization
>        hw/intc: sifive_plic: Fix the pending register range check
> 
> Christoph Muellner (1):
>        RISC-V: Add Zawrs ISA extension support
> 
> Conor Dooley (3):
>        hw/misc: pfsoc: add fabric clocks to ioscb
>        hw/riscv: pfsoc: add missing FICs as unimplemented
>        hw/{misc, riscv}: pfsoc: add system controller as unimplemented
> 
> Frédéric Pétrot (1):
>        hw/intc: sifive_plic: Renumber the S irqs for numa support
> 
> Jim Shu (2):
>        target/riscv: support cache-related PMU events in virtual mode
>        hw/intc: sifive_plic: fix out-of-bound access of source_priority array
> 
> LIU Zhiwei (5):
>        target/riscv: Fix PMP propagation for tlb
>        target/riscv: Add itrigger support when icount is not enabled
>        target/riscv: Add itrigger support when icount is enabled
>        target/riscv: Enable native debug itrigger
>        target/riscv: Add itrigger_enabled field to CPURISCVState
> 
> Mayuresh Chitale (3):
>        target/riscv: Add smstateen support
>        target/riscv: smstateen check for h/s/envcfg
>        target/riscv: generate virtual instruction exception
> 
> Richard Henderson (4):
>        tcg/riscv: Fix range matched by TCG_CT_CONST_M12
>        tcg/riscv: Fix reg overlap case in tcg_out_addsub2
>        tcg/riscv: Fix base register for user-only qemu_ld/st
>        target/riscv: Set pc_succ_insn for !rvc illegal insn
> 
> Wilfred Mallawa (4):
>        hw/registerfields: add `FIELDx_1CLEAR()` macro
>        hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro
>        hw/riscv/opentitan: bump opentitan
>        hw/riscv/opentitan: add aon_timer base unimpl
> 
>   include/hw/intc/sifive_plic.h                  |   1 -
>   include/hw/misc/mchp_pfsoc_ioscb.h             |   4 +
>   include/hw/misc/mchp_pfsoc_sysreg.h            |   1 +
>   include/hw/registerfields.h                    |  22 ++
>   include/hw/riscv/microchip_pfsoc.h             |   7 +-
>   include/hw/riscv/opentitan.h                   |  10 +-
>   include/hw/riscv/shakti_c.h                    |   2 +-
>   include/hw/riscv/sifive_e.h                    |   9 +-
>   include/hw/riscv/sifive_u.h                    |   2 +-
>   include/hw/riscv/virt.h                        |   8 +-
>   target/riscv/cpu.h                             |  10 +
>   target/riscv/cpu_bits.h                        |  37 +++
>   target/riscv/debug.h                           |  13 +
>   target/riscv/helper.h                          |   2 +
>   target/riscv/pmp.h                             |   6 +-
>   target/riscv/insn32.decode                     |   4 +
>   hw/intc/sifive_plic.c                          |  66 +++--
>   hw/misc/mchp_pfsoc_ioscb.c                     |  78 ++++-
>   hw/misc/mchp_pfsoc_sysreg.c                    |  18 +-
>   hw/riscv/microchip_pfsoc.c                     | 121 ++++----
>   hw/riscv/opentitan.c                           |  26 +-
>   hw/riscv/sifive_u.c                            |   3 +-
>   hw/riscv/spike.c                               |   1 -
>   hw/riscv/virt.c                                |   7 +-
>   hw/ssi/ibex_spi_host.c                         |  21 +-

FYI, this seems to cause problems in the MSYS2 Cirrus-CI job:

  https://cirrus-ci.com/task/6444497832247296?logs=main#L2159

  Thomas