qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
* [PULL v2 00/45] riscv-to-apply queue
@ 2022-12-21 22:39 Alistair Francis
  2022-12-21 22:39 ` [PULL v2 01/45] target/riscv: Fix PMP propagation for tlb Alistair Francis
                   ` (45 more replies)
  0 siblings, 46 replies; 55+ messages in thread
From: Alistair Francis @ 2022-12-21 22:39 UTC (permalink / raw)
  To: qemu-devel; +Cc: alistair23, Alistair Francis

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 222059a0fccf4af3be776fe35a5ea2d6a68f9a0b:

  Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into staging (2022-12-21 18:08:09 +0000)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20221222-1

for you to fetch changes up to 71a9bc59728a054036f3db7dd82dab8f8bd2baf9:

  hw/intc: sifive_plic: Fix the pending register range check (2022-12-22 08:36:30 +1000)

----------------------------------------------------------------
First RISC-V PR for QEMU 8.0

* Fix PMP propagation for tlb
* Collection of bug fixes
* Add the `FIELDx_1CLEAR()` macro
* Bump the OpenTitan supported version
* Add smstateen support
* Support native debug icount trigger
* Remove the redundant ipi-id property in the virt machine
* Support cache-related PMU events in virtual mode
* Add some missing PolarFire SoC io regions
* Fix mret exception cause when no pmp rule is configured
* Fix bug where disabling compressed instructions would crash QEMU
* Add Zawrs ISA extension support
* A range of code refactoring and cleanups

----------------------------------------------------------------
Anup Patel (1):
      target/riscv: Typo fix in sstc() predicate

Atish Patra (1):
      hw/riscv: virt: Remove the redundant ipi-id property

Bin Meng (20):
      target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()
      target/riscv: Fix mret exception cause when no pmp rule is configured
      target/riscv: Simplify helper_sret() a little bit
      target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+
      hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
      hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers
      hw/riscv: Fix opentitan dependency to SIFIVE_PLIC
      hw/riscv: Sort machines Kconfig options in alphabetical order
      hw/riscv: spike: Remove misleading comments
      hw/intc: sifive_plic: Drop PLICMode_H
      hw/intc: sifive_plic: Improve robustness of the PLIC config parser
      hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize()
      hw/intc: sifive_plic: Update "num-sources" property default value
      hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC
      hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC
      hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"
      hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb
      hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0
      hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization
      hw/intc: sifive_plic: Fix the pending register range check

Christoph Muellner (1):
      RISC-V: Add Zawrs ISA extension support

Conor Dooley (3):
      hw/misc: pfsoc: add fabric clocks to ioscb
      hw/riscv: pfsoc: add missing FICs as unimplemented
      hw/{misc, riscv}: pfsoc: add system controller as unimplemented

Frédéric Pétrot (1):
      hw/intc: sifive_plic: Renumber the S irqs for numa support

Jim Shu (2):
      target/riscv: support cache-related PMU events in virtual mode
      hw/intc: sifive_plic: fix out-of-bound access of source_priority array

LIU Zhiwei (5):
      target/riscv: Fix PMP propagation for tlb
      target/riscv: Add itrigger support when icount is not enabled
      target/riscv: Add itrigger support when icount is enabled
      target/riscv: Enable native debug itrigger
      target/riscv: Add itrigger_enabled field to CPURISCVState

Mayuresh Chitale (3):
      target/riscv: Add smstateen support
      target/riscv: smstateen check for h/s/envcfg
      target/riscv: generate virtual instruction exception

Richard Henderson (4):
      tcg/riscv: Fix range matched by TCG_CT_CONST_M12
      tcg/riscv: Fix reg overlap case in tcg_out_addsub2
      tcg/riscv: Fix base register for user-only qemu_ld/st
      target/riscv: Set pc_succ_insn for !rvc illegal insn

Wilfred Mallawa (4):
      hw/registerfields: add `FIELDx_1CLEAR()` macro
      hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro
      hw/riscv/opentitan: bump opentitan
      hw/riscv/opentitan: add aon_timer base unimpl

 include/hw/intc/sifive_plic.h                  |   1 -
 include/hw/misc/mchp_pfsoc_ioscb.h             |   4 +
 include/hw/misc/mchp_pfsoc_sysreg.h            |   1 +
 include/hw/registerfields.h                    |  22 ++
 include/hw/riscv/microchip_pfsoc.h             |   7 +-
 include/hw/riscv/opentitan.h                   |  10 +-
 include/hw/riscv/shakti_c.h                    |   2 +-
 include/hw/riscv/sifive_e.h                    |   9 +-
 include/hw/riscv/sifive_u.h                    |   2 +-
 include/hw/riscv/virt.h                        |   8 +-
 target/riscv/cpu.h                             |  10 +
 target/riscv/cpu_bits.h                        |  37 +++
 target/riscv/debug.h                           |  13 +
 target/riscv/helper.h                          |   2 +
 target/riscv/pmp.h                             |   6 +-
 target/riscv/insn32.decode                     |   4 +
 hw/intc/sifive_plic.c                          |  66 +++--
 hw/misc/mchp_pfsoc_ioscb.c                     |  78 ++++-
 hw/misc/mchp_pfsoc_sysreg.c                    |  18 +-
 hw/riscv/microchip_pfsoc.c                     | 121 ++++----
 hw/riscv/opentitan.c                           |  26 +-
 hw/riscv/sifive_u.c                            |   3 +-
 hw/riscv/spike.c                               |   1 -
 hw/riscv/virt.c                                |   7 +-
 hw/ssi/ibex_spi_host.c                         |  21 +-
 target/riscv/cpu.c                             |  11 +
 target/riscv/cpu_helper.c                      |  26 +-
 target/riscv/csr.c                             | 393 ++++++++++++++++++++++++-
 target/riscv/debug.c                           | 205 +++++++++++++
 target/riscv/machine.c                         |  36 +++
 target/riscv/op_helper.c                       |  28 +-
 target/riscv/pmp.c                             |  90 ++----
 target/riscv/translate.c                       |  54 +++-
 target/riscv/insn_trans/trans_privileged.c.inc |   4 +-
 target/riscv/insn_trans/trans_rvi.c.inc        |   8 +-
 target/riscv/insn_trans/trans_rvv.c.inc        |   4 +-
 target/riscv/insn_trans/trans_rvzawrs.c.inc    |  51 ++++
 tcg/riscv/tcg-target.c.inc                     |  68 +++--
 hw/intc/Kconfig                                |   3 +
 hw/riscv/Kconfig                               |  22 +-
 tests/tcg/Makefile.target                      |   2 +
 tests/tcg/riscv64/Makefile.target              |   6 +
 tests/tcg/riscv64/test-noc.S                   |  32 ++
 43 files changed, 1256 insertions(+), 266 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvzawrs.c.inc
 create mode 100644 tests/tcg/riscv64/test-noc.S


^ permalink raw reply	[flat|nested] 55+ messages in thread
* [PULL v2 00/45] riscv-to-apply queue
@ 2023-09-11  6:42 Alistair Francis
  2023-09-11 15:19 ` Stefan Hajnoczi
  2023-09-12 10:26 ` Michael Tokarev
  0 siblings, 2 replies; 55+ messages in thread
From: Alistair Francis @ 2023-09-11  6:42 UTC (permalink / raw)
  To: qemu-devel; +Cc: alistair23, Alistair Francis

The following changes since commit c5ea91da443b458352c1b629b490ee6631775cb4:

  Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging (2023-09-08 10:06:25 -0400)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230911

for you to fetch changes up to e7a03409f29e2da59297d55afbaec98c96e43e3a:

  target/riscv: don't read CSR in riscv_csrrw_do64 (2023-09-11 11:45:55 +1000)

----------------------------------------------------------------
First RISC-V PR for 8.2

 * Remove 'host' CPU from TCG
 * riscv_htif Fixup printing on big endian hosts
 * Add zmmul isa string
 * Add smepmp isa string
 * Fix page_check_range use in fault-only-first
 * Use existing lookup tables for MixColumns
 * Add RISC-V vector cryptographic instruction set support
 * Implement WARL behaviour for mcountinhibit/mcounteren
 * Add Zihintntl extension ISA string to DTS
 * Fix zfa fleq.d and fltq.d
 * Fix upper/lower mtime write calculation
 * Make rtc variable names consistent
 * Use abi type for linux-user target_ucontext
 * Add RISC-V KVM AIA Support
 * Fix riscv,pmu DT node path in the virt machine
 * Update CSR bits name for svadu extension
 * Mark zicond non-experimental
 * Fix satp_mode_finalize() when satp_mode.supported = 0
 * Fix non-KVM --enable-debug build
 * Add new extensions to hwprobe
 * Use accelerated helper for AES64KS1I
 * Allocate itrigger timers only once
 * Respect mseccfg.RLB for pmpaddrX changes
 * Align the AIA model to v1.0 ratified spec
 * Don't read the CSR in riscv_csrrw_do64

----------------------------------------------------------------
Akihiko Odaki (1):
      target/riscv: Allocate itrigger timers only once

Ard Biesheuvel (2):
      target/riscv: Use existing lookup tables for MixColumns
      target/riscv: Use accelerated helper for AES64KS1I

Conor Dooley (1):
      hw/riscv: virt: Fix riscv,pmu DT node path

Daniel Henrique Barboza (6):
      target/riscv/cpu.c: do not run 'host' CPU with TCG
      target/riscv/cpu.c: add zmmul isa string
      target/riscv/cpu.c: add smepmp isa string
      target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0
      hw/riscv/virt.c: fix non-KVM --enable-debug build
      hw/intc/riscv_aplic.c fix non-KVM --enable-debug build

Dickon Hood (2):
      target/riscv: Refactor translation of vector-widening instruction
      target/riscv: Add Zvbb ISA extension support

Jason Chien (3):
      target/riscv: Add Zihintntl extension ISA string to DTS
      hw/intc: Fix upper/lower mtime write calculation
      hw/intc: Make rtc variable names consistent

Kiran Ostrolenk (4):
      target/riscv: Refactor some of the generic vector functionality
      target/riscv: Refactor vector-vector translation macro
      target/riscv: Refactor some of the generic vector functionality
      target/riscv: Add Zvknh ISA extension support

LIU Zhiwei (3):
      target/riscv: Fix page_check_range use in fault-only-first
      target/riscv: Fix zfa fleq.d and fltq.d
      linux-user/riscv: Use abi type for target_ucontext

Lawrence Hunter (2):
      target/riscv: Add Zvbc ISA extension support
      target/riscv: Add Zvksh ISA extension support

Leon Schuermann (1):
      target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes

Max Chou (3):
      crypto: Create sm4_subword
      crypto: Add SM4 constant parameter CK
      target/riscv: Add Zvksed ISA extension support

Nazar Kazakov (4):
      target/riscv: Remove redundant "cpu_vl == 0" checks
      target/riscv: Move vector translation checks
      target/riscv: Add Zvkned ISA extension support
      target/riscv: Add Zvkg ISA extension support

Nikita Shubin (1):
      target/riscv: don't read CSR in riscv_csrrw_do64

Rob Bradford (1):
      target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren

Robbin Ehn (1):
      linux-user/riscv: Add new extensions to hwprobe

Thomas Huth (2):
      hw/char/riscv_htif: Fix printing of console characters on big endian hosts
      hw/char/riscv_htif: Fix the console syscall on big endian hosts

Tommy Wu (1):
      target/riscv: Align the AIA model to v1.0 ratified spec

Vineet Gupta (1):
      riscv: zicond: make non-experimental

Weiwei Li (1):
      target/riscv: Update CSR bits name for svadu extension

Yong-Xuan Wang (5):
      target/riscv: support the AIA device emulation with KVM enabled
      target/riscv: check the in-kernel irqchip support
      target/riscv: Create an KVM AIA irqchip
      target/riscv: update APLIC and IMSIC to support KVM AIA
      target/riscv: select KVM AIA in riscv virt machine

 include/crypto/aes.h                      |   7 +
 include/crypto/sm4.h                      |   9 +
 target/riscv/cpu_bits.h                   |   8 +-
 target/riscv/cpu_cfg.h                    |   9 +
 target/riscv/debug.h                      |   3 +-
 target/riscv/helper.h                     |  98 +++
 target/riscv/kvm_riscv.h                  |   5 +
 target/riscv/vector_internals.h           | 228 +++++++
 target/riscv/insn32.decode                |  58 ++
 crypto/aes.c                              |   4 +-
 crypto/sm4.c                              |  10 +
 hw/char/riscv_htif.c                      |  12 +-
 hw/intc/riscv_aclint.c                    |  11 +-
 hw/intc/riscv_aplic.c                     |  52 +-
 hw/intc/riscv_imsic.c                     |  25 +-
 hw/riscv/virt.c                           | 374 ++++++------
 linux-user/riscv/signal.c                 |   4 +-
 linux-user/syscall.c                      |  14 +-
 target/arm/tcg/crypto_helper.c            |  10 +-
 target/riscv/cpu.c                        |  83 ++-
 target/riscv/cpu_helper.c                 |   6 +-
 target/riscv/crypto_helper.c              |  51 +-
 target/riscv/csr.c                        |  54 +-
 target/riscv/debug.c                      |  15 +-
 target/riscv/kvm.c                        | 201 ++++++-
 target/riscv/pmp.c                        |   4 +
 target/riscv/translate.c                  |   1 +
 target/riscv/vcrypto_helper.c             | 970 ++++++++++++++++++++++++++++++
 target/riscv/vector_helper.c              | 245 +-------
 target/riscv/vector_internals.c           |  81 +++
 target/riscv/insn_trans/trans_rvv.c.inc   | 171 +++---
 target/riscv/insn_trans/trans_rvvk.c.inc  | 606 +++++++++++++++++++
 target/riscv/insn_trans/trans_rvzfa.c.inc |   4 +-
 target/riscv/meson.build                  |   4 +-
 34 files changed, 2785 insertions(+), 652 deletions(-)
 create mode 100644 target/riscv/vector_internals.h
 create mode 100644 target/riscv/vcrypto_helper.c
 create mode 100644 target/riscv/vector_internals.c
 create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc


^ permalink raw reply	[flat|nested] 55+ messages in thread
end of thread, other threads:[~2023-09-14  3:09 UTC | newest]

Thread overview: 55+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-12-21 22:39 [PULL v2 00/45] riscv-to-apply queue Alistair Francis
2022-12-21 22:39 ` [PULL v2 01/45] target/riscv: Fix PMP propagation for tlb Alistair Francis
2022-12-21 22:39 ` [PULL v2 02/45] hw/registerfields: add `FIELDx_1CLEAR()` macro Alistair Francis
2022-12-21 22:39 ` [PULL v2 03/45] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro Alistair Francis
2023-01-04  9:38   ` Philippe Mathieu-Daudé
2023-01-04 12:30   ` Alistair Francis
2023-01-04 22:55     ` Wilfred Mallawa
2022-12-21 22:39 ` [PULL v2 04/45] tcg/riscv: Fix range matched by TCG_CT_CONST_M12 Alistair Francis
2022-12-21 22:39 ` [PULL v2 05/45] tcg/riscv: Fix reg overlap case in tcg_out_addsub2 Alistair Francis
2022-12-21 22:39 ` [PULL v2 06/45] tcg/riscv: Fix base register for user-only qemu_ld/st Alistair Francis
2022-12-21 22:39 ` [PULL v2 07/45] hw/riscv/opentitan: bump opentitan Alistair Francis
2022-12-21 22:39 ` [PULL v2 08/45] hw/riscv/opentitan: add aon_timer base unimpl Alistair Francis
2022-12-21 22:39 ` [PULL v2 09/45] target/riscv: Add smstateen support Alistair Francis
2022-12-21 22:39 ` [PULL v2 10/45] target/riscv: smstateen check for h/s/envcfg Alistair Francis
2022-12-21 22:39 ` [PULL v2 11/45] target/riscv: generate virtual instruction exception Alistair Francis
2022-12-21 22:39 ` [PULL v2 12/45] target/riscv: Add itrigger support when icount is not enabled Alistair Francis
2022-12-21 22:39 ` [PULL v2 13/45] target/riscv: Add itrigger support when icount is enabled Alistair Francis
2022-12-21 22:39 ` [PULL v2 14/45] target/riscv: Enable native debug itrigger Alistair Francis
2022-12-21 22:39 ` [PULL v2 15/45] target/riscv: Add itrigger_enabled field to CPURISCVState Alistair Francis
2022-12-21 22:39 ` [PULL v2 16/45] hw/intc: sifive_plic: Renumber the S irqs for numa support Alistair Francis
2022-12-21 22:39 ` [PULL v2 17/45] target/riscv: Typo fix in sstc() predicate Alistair Francis
2022-12-21 22:39 ` [PULL v2 18/45] hw/riscv: virt: Remove the redundant ipi-id property Alistair Francis
2022-12-21 22:39 ` [PULL v2 19/45] target/riscv: support cache-related PMU events in virtual mode Alistair Francis
2022-12-21 22:39 ` [PULL v2 20/45] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state() Alistair Francis
2022-12-21 22:39 ` [PULL v2 21/45] hw/misc: pfsoc: add fabric clocks to ioscb Alistair Francis
2022-12-21 22:39 ` [PULL v2 22/45] hw/riscv: pfsoc: add missing FICs as unimplemented Alistair Francis
2022-12-21 22:40 ` [PULL v2 23/45] hw/{misc, riscv}: pfsoc: add system controller " Alistair Francis
2022-12-21 22:40 ` [PULL v2 24/45] hw/intc: sifive_plic: fix out-of-bound access of source_priority array Alistair Francis
2022-12-21 22:40 ` [PULL v2 25/45] target/riscv: Fix mret exception cause when no pmp rule is configured Alistair Francis
2022-12-21 22:40 ` [PULL v2 26/45] target/riscv: Set pc_succ_insn for !rvc illegal insn Alistair Francis
2022-12-21 22:40 ` [PULL v2 27/45] target/riscv: Simplify helper_sret() a little bit Alistair Francis
2022-12-21 22:40 ` [PULL v2 28/45] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+ Alistair Francis
2022-12-21 22:40 ` [PULL v2 29/45] RISC-V: Add Zawrs ISA extension support Alistair Francis
2022-12-21 22:40 ` [PULL v2 30/45] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Alistair Francis
2022-12-21 22:40 ` [PULL v2 31/45] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Alistair Francis
2022-12-21 22:40 ` [PULL v2 32/45] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Alistair Francis
2022-12-21 22:40 ` [PULL v2 33/45] hw/riscv: Sort machines Kconfig options in alphabetical order Alistair Francis
2022-12-21 22:40 ` [PULL v2 34/45] hw/riscv: spike: Remove misleading comments Alistair Francis
2022-12-21 22:40 ` [PULL v2 35/45] hw/intc: sifive_plic: Drop PLICMode_H Alistair Francis
2022-12-21 22:40 ` [PULL v2 36/45] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Alistair Francis
2022-12-21 22:40 ` [PULL v2 37/45] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() Alistair Francis
2022-12-21 22:40 ` [PULL v2 38/45] hw/intc: sifive_plic: Update "num-sources" property default value Alistair Francis
2022-12-21 22:40 ` [PULL v2 39/45] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Alistair Francis
2022-12-21 22:40 ` [PULL v2 40/45] hw/riscv: sifive_e: " Alistair Francis
2022-12-21 22:40 ` [PULL v2 41/45] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" Alistair Francis
2022-12-21 22:40 ` [PULL v2 42/45] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Alistair Francis
2022-12-21 22:40 ` [PULL v2 43/45] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Alistair Francis
2022-12-21 22:40 ` [PULL v2 44/45] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Alistair Francis
2022-12-21 22:40 ` [PULL v2 45/45] hw/intc: sifive_plic: Fix the pending register range check Alistair Francis
2023-01-04  9:20 ` [PULL v2 00/45] riscv-to-apply queue Thomas Huth
2023-01-04 14:53   ` Peter Maydell
  -- strict thread matches above, loose matches on Subject: below --
2023-09-11  6:42 Alistair Francis
2023-09-11 15:19 ` Stefan Hajnoczi
2023-09-12 10:26 ` Michael Tokarev
2023-09-14  3:08   ` Alistair Francis

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).