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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v2 17/25] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , David Gibson , Greg Kurz , qemu-ppc@nongnu.org References: <20230307183503.2512684-1-richard.henderson@linaro.org> <20230307183503.2512684-18-richard.henderson@linaro.org> From: Daniel Henrique Barboza In-Reply-To: <20230307183503.2512684-18-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x234.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/7/23 15:34, Richard Henderson wrote: > All remaining uses are strictly read-only. > > Signed-off-by: Richard Henderson > --- Reviewed-by: Daniel Henrique Barboza > Cc: Daniel Henrique Barboza > Cc: Cédric Le Goater > Cc: David Gibson > Cc: Greg Kurz > Cc: qemu-ppc@nongnu.org > --- > target/ppc/translate/vsx-impl.c.inc | 28 ++++++++++++++-------------- > 1 file changed, 14 insertions(+), 14 deletions(-) > > diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc > index 9916784e64..0f5b0056f1 100644 > --- a/target/ppc/translate/vsx-impl.c.inc > +++ b/target/ppc/translate/vsx-impl.c.inc > @@ -154,7 +154,7 @@ static void gen_lxvdsx(DisasContext *ctx) > static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl, > TCGv_i64 inh, TCGv_i64 inl) > { > - TCGv_i64 mask = tcg_const_i64(0x00FF00FF00FF00FF); > + TCGv_i64 mask = tcg_constant_i64(0x00FF00FF00FF00FF); > TCGv_i64 t0 = tcg_temp_new_i64(); > TCGv_i64 t1 = tcg_temp_new_i64(); > > @@ -825,7 +825,7 @@ static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a) > REQUIRE_INSNS_FLAGS2(ctx, ISA300); > REQUIRE_VSX(ctx); > > - ro = tcg_const_i32(a->rc); > + ro = tcg_constant_i32(a->rc); > > xt = gen_avr_ptr(a->rt); > xb = gen_avr_ptr(a->rb); > @@ -860,7 +860,7 @@ static void gen_##name(DisasContext *ctx) \ > gen_exception(ctx, POWERPC_EXCP_VSXU); \ > return; \ > } \ > - opc = tcg_const_i32(ctx->opcode); \ > + opc = tcg_constant_i32(ctx->opcode); \ > gen_helper_##name(cpu_env, opc); \ > } > > @@ -900,7 +900,7 @@ static void gen_##name(DisasContext *ctx) \ > gen_exception(ctx, POWERPC_EXCP_VSXU); \ > return; \ > } \ > - opc = tcg_const_i32(ctx->opcode); \ > + opc = tcg_constant_i32(ctx->opcode); \ > xa = gen_vsr_ptr(xA(ctx->opcode)); \ > xb = gen_vsr_ptr(xB(ctx->opcode)); \ > gen_helper_##name(cpu_env, opc, xa, xb); \ > @@ -915,7 +915,7 @@ static void gen_##name(DisasContext *ctx) \ > gen_exception(ctx, POWERPC_EXCP_VSXU); \ > return; \ > } \ > - opc = tcg_const_i32(ctx->opcode); \ > + opc = tcg_constant_i32(ctx->opcode); \ > xb = gen_vsr_ptr(xB(ctx->opcode)); \ > gen_helper_##name(cpu_env, opc, xb); \ > } > @@ -929,7 +929,7 @@ static void gen_##name(DisasContext *ctx) \ > gen_exception(ctx, POWERPC_EXCP_VSXU); \ > return; \ > } \ > - opc = tcg_const_i32(ctx->opcode); \ > + opc = tcg_constant_i32(ctx->opcode); \ > xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \ > xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \ > xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \ > @@ -945,7 +945,7 @@ static void gen_##name(DisasContext *ctx) \ > gen_exception(ctx, POWERPC_EXCP_VSXU); \ > return; \ > } \ > - opc = tcg_const_i32(ctx->opcode); \ > + opc = tcg_constant_i32(ctx->opcode); \ > xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \ > xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \ > gen_helper_##name(cpu_env, opc, xt, xb); \ > @@ -960,7 +960,7 @@ static void gen_##name(DisasContext *ctx) \ > gen_exception(ctx, POWERPC_EXCP_VSXU); \ > return; \ > } \ > - opc = tcg_const_i32(ctx->opcode); \ > + opc = tcg_constant_i32(ctx->opcode); \ > xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \ > xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \ > gen_helper_##name(cpu_env, opc, xa, xb); \ > @@ -1994,8 +1994,8 @@ static void gen_xsxsigdp(DisasContext *ctx) > exp = tcg_temp_new_i64(); > t0 = tcg_temp_new_i64(); > t1 = tcg_temp_new_i64(); > - zr = tcg_const_i64(0); > - nan = tcg_const_i64(2047); > + zr = tcg_constant_i64(0); > + nan = tcg_constant_i64(2047); > > get_cpu_vsr(t1, xB(ctx->opcode), true); > tcg_gen_extract_i64(exp, t1, 52, 11); > @@ -2026,8 +2026,8 @@ static void gen_xsxsigqp(DisasContext *ctx) > get_cpu_vsr(xbl, rB(ctx->opcode) + 32, false); > exp = tcg_temp_new_i64(); > t0 = tcg_temp_new_i64(); > - zr = tcg_const_i64(0); > - nan = tcg_const_i64(32767); > + zr = tcg_constant_i64(0); > + nan = tcg_constant_i64(32767); > > tcg_gen_extract_i64(exp, xbh, 48, 15); > tcg_gen_movi_i64(t0, 0x0001000000000000); > @@ -2193,8 +2193,8 @@ static void gen_xvxsigdp(DisasContext *ctx) > get_cpu_vsr(xbl, xB(ctx->opcode), false); > exp = tcg_temp_new_i64(); > t0 = tcg_temp_new_i64(); > - zr = tcg_const_i64(0); > - nan = tcg_const_i64(2047); > + zr = tcg_constant_i64(0); > + nan = tcg_constant_i64(2047); > > tcg_gen_extract_i64(exp, xbh, 52, 11); > tcg_gen_movi_i64(t0, 0x0010000000000000);