From: Richard Henderson <richard.henderson@linaro.org>
To: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>, qemu-devel@nongnu.org
Cc: f4bug@amsat.org, jiaxun.yang@flygoat.com, aurelien@aurel32.net,
aleksandar.rikalo@syrmia.com
Subject: Re: [PATCH v2 3/3] target/mips: implement Octeon-specific arithmetic instructions
Date: Thu, 9 Jun 2022 08:53:46 -0700 [thread overview]
Message-ID: <5f8a2a73-dc3b-821c-8ee3-127d4e0c78d2@linaro.org> (raw)
In-Reply-To: <165476302832.40568.14732977026786901317.stgit@pasha-ThinkPad-X280>
On 6/9/22 01:23, Pavel Dovgalyuk wrote:
> +static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a)
> +{
> + TCGv t0, t1;
> +
> + if (a->rt == 0) {
> + /* nop */
> + return true;
> + }
I believe that we're standardizing on using gen_store_gpr, and not checking for r0 everywhere.
> +static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a)
> +{
> + TCGv t0;
> +
> + if (a->rt == 0) {
> + /* nop */
> + return true;
> + }
> +
> + t0 = tcg_temp_new();
> + gen_load_gpr(t0, a->rs);
> + tcg_gen_sextract_tl(t0, t0, a->p, a->lenm1);
a->lenm1 + 1.
> + tcg_gen_deposit_z_tl(t0, t0, a->p, a->lenm1);
Likewise.
r~
next prev parent reply other threads:[~2022-06-09 17:40 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-09 8:23 [PATCH v2 0/3] Cavium Octeon MIPS extensions Pavel Dovgalyuk
2022-06-09 8:23 ` [PATCH v2 1/3] target/mips: introduce Cavium Octeon CPU model Pavel Dovgalyuk
2022-06-10 13:28 ` Philippe Mathieu-Daudé via
2022-06-09 8:23 ` [PATCH v2 2/3] target/mips: implement Octeon-specific BBIT instructions Pavel Dovgalyuk
2022-06-09 14:19 ` Richard Henderson
2022-06-09 8:23 ` [PATCH v2 3/3] target/mips: implement Octeon-specific arithmetic instructions Pavel Dovgalyuk
2022-06-09 15:53 ` Richard Henderson [this message]
2022-06-14 5:55 ` Pavel Dovgalyuk
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