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([2604:3d08:9384:1d00::27bd]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7127add68desm8387424b3a.29.2024.08.20.09.02.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 20 Aug 2024 09:02:02 -0700 (PDT) Message-ID: <5fcf8fcb-c100-4d3b-aca0-a9a46a7b7040@linaro.org> Date: Tue, 20 Aug 2024 09:02:01 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH for-9.1] target/i386: Fix tss access size in switch_tss_ra Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20240819074052.207783-1-richard.henderson@linaro.org> From: Pierrick Bouvier In-Reply-To: <20240819074052.207783-1-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/19/24 00:40, Richard Henderson wrote: > The two limit_max variables represent size - 1, just like the > encoding in the GDT, thus the 'old' access was off by one. > Access the minimal size of the new tss: the complete tss contains > the iopb, which may be a larger block than the access api expects, > and irrelevant because the iopb is not accessed during the > switch itself. > > Fixes: 8b131065080a ("target/i386/tcg: use X86Access for TSS access") > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2511 > Signed-off-by: Richard Henderson > --- > target/i386/tcg/seg_helper.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c > index bab552cd53..3b8fd827e1 100644 > --- a/target/i386/tcg/seg_helper.c > +++ b/target/i386/tcg/seg_helper.c > @@ -378,7 +378,7 @@ static int switch_tss_ra(CPUX86State *env, int tss_selector, > > /* X86Access avoids memory exceptions during the task switch */ > mmu_index = cpu_mmu_index_kernel(env); > - access_prepare_mmu(&old, env, env->tr.base, old_tss_limit_max, > + access_prepare_mmu(&old, env, env->tr.base, old_tss_limit_max + 1, > MMU_DATA_STORE, mmu_index, retaddr); > > if (source == SWITCH_TSS_CALL) { > @@ -386,7 +386,8 @@ static int switch_tss_ra(CPUX86State *env, int tss_selector, > probe_access(env, tss_base, 2, MMU_DATA_STORE, > mmu_index, retaddr); > } > - access_prepare_mmu(&new, env, tss_base, tss_limit, > + /* While true tss_limit may be larger, we don't access the iopb here. */ > + access_prepare_mmu(&new, env, tss_base, tss_limit_max + 1, > MMU_DATA_LOAD, mmu_index, retaddr); > > /* save the current state in the old TSS */ Reviewed-by: Pierrick Bouvier