From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 20C54C433F5 for ; Fri, 21 Jan 2022 00:30:52 +0000 (UTC) Received: from localhost ([::1]:40514 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAhpK-0003MB-Qq for qemu-devel@archiver.kernel.org; Thu, 20 Jan 2022 19:30:50 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43608) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAfkE-0000AJ-11; Thu, 20 Jan 2022 17:17:28 -0500 Received: from smtpout4.mo529.mail-out.ovh.net ([217.182.185.173]:50871) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAfkB-0002Fn-Vd; Thu, 20 Jan 2022 17:17:25 -0500 Received: from mxplan5.mail.ovh.net (unknown [10.109.146.28]) by mo529.mail-out.ovh.net (Postfix) with ESMTPS id 79FE2D90D3FB; Thu, 20 Jan 2022 23:17:20 +0100 (CET) Received: from kaod.org (37.59.142.97) by DAG4EX1.mxp5.local (172.16.2.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Thu, 20 Jan 2022 23:17:19 +0100 Authentication-Results: garm.ovh; auth=pass (GARM-97G002b0697770-c55b-48b3-ad53-ee900dccc87f, 55E834D54A8FC5F4505B49AAC2A2F9003410B5FE) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 Message-ID: <5fec11da-ab38-72c8-9fe2-043f5f42786d@kaod.org> Date: Thu, 20 Jan 2022 23:17:19 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.3.0 Subject: Re: [PATCH v2 12/14] target/ppc: 405: Instruction storage interrupt cleanup Content-Language: en-US To: Fabiano Rosas , References: <20220118184448.852996-1-farosas@linux.ibm.com> <20220118184448.852996-13-farosas@linux.ibm.com> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= In-Reply-To: <20220118184448.852996-13-farosas@linux.ibm.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [37.59.142.97] X-ClientProxiedBy: DAG3EX2.mxp5.local (172.16.2.22) To DAG4EX1.mxp5.local (172.16.2.31) X-Ovh-Tracer-GUID: ed95aba6-0a61-4c4a-855f-7a749157337e X-Ovh-Tracer-Id: 16100368671100734246 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedvvddrudekgdduheejucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhepkfffgggfuffvfhfhjggtgfhisehtjeertddtfeejnecuhfhrohhmpeevrogurhhitggpnfgvpgfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuggftrfgrthhtvghrnhephffhleegueektdetffdvffeuieeugfekkeelheelteeftdfgtefffeehueegleehnecukfhppedtrddtrddtrddtpdefjedrheelrddugedvrdeljeenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphhouhhtpdhhvghlohepmhigphhlrghnhedrmhgrihhlrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdpnhgspghrtghpthhtohepuddprhgtphhtthhopegsrghlrghtohhnsegvihhkrdgsmhgvrdhhuh Received-SPF: pass client-ip=217.182.185.173; envelope-from=clg@kaod.org; helo=smtpout4.mo529.mail-out.ovh.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: danielhb413@gmail.com, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 1/18/22 19:44, Fabiano Rosas wrote: > The 405 ISI does not set SRR1 with any exception syndrome bits, only a > clean copy of the MSR. > > Signed-off-by: Fabiano Rosas > --- > target/ppc/excp_helper.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c > index e4e513322c..13674a102f 100644 > --- a/target/ppc/excp_helper.c > +++ b/target/ppc/excp_helper.c > @@ -715,7 +715,6 @@ static inline void powerpc_excp_legacy(PowerPCCPU *cpu, int excp) This change is done in the wrong routine. Thanks, C. > break; > case POWERPC_EXCP_ISI: /* Instruction storage exception */ > trace_ppc_excp_isi(msr, env->nip); > - msr |= env->error_code; > break; > case POWERPC_EXCP_EXTERNAL: /* External input */ > { >