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Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH 02/62] target/arm: Enable PageEntryExtra Content-Language: en-US To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20220703082419.770989-1-richard.henderson@linaro.org> <20220703082419.770989-3-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/4/22 20:52, Peter Maydell wrote: > On Sun, 3 Jul 2022 at 09:25, Richard Henderson > wrote: >> >> Copy attrs, sharability, and the NS bit into the TLB. >> >> Signed-off-by: Richard Henderson >> --- >> target/arm/cpu-param.h | 8 ++++++++ >> target/arm/internals.h | 5 +++++ >> target/arm/tlb_helper.c | 14 ++++++++++++-- >> 3 files changed, 25 insertions(+), 2 deletions(-) >> >> diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h >> index 68ffb12427..a14f167d11 100644 >> --- a/target/arm/cpu-param.h >> +++ b/target/arm/cpu-param.h >> @@ -30,6 +30,14 @@ >> */ >> # define TARGET_PAGE_BITS_VARY >> # define TARGET_PAGE_BITS_MIN 10 >> +/* >> + * Extra information stored in softmmu page tables. >> + */ >> +# define TARGET_PAGE_ENTRY_EXTRA >> +struct PageEntryExtra { >> + /* See PAGEENTRYEXTRA fields in cpu.h */ >> + uint64_t x; >> +}; >> #endif >> >> #define NB_MMU_MODES 15 >> diff --git a/target/arm/internals.h b/target/arm/internals.h >> index c66f74a0db..2b38a83574 100644 >> --- a/target/arm/internals.h >> +++ b/target/arm/internals.h >> @@ -74,6 +74,11 @@ FIELD(V7M_EXCRET, DCRS, 5, 1) >> FIELD(V7M_EXCRET, S, 6, 1) >> FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ >> >> +/* Bit definitions for PageEntryExtra */ >> +FIELD(PAGEENTRYEXTRA, ATTRS, 0, 8) >> +FIELD(PAGEENTRYEXTRA, SHAREABILITY, 8, 2) >> +FIELD(PAGEENTRYEXTRA, PA, 12, 52) > > So why do we want these things in particular? It would be > helpful to describe the intended uses in the commit message > to save the reader having to read the next 60 patches to > find out :-) Heh, yes. Basically, it's what S1_ptw_translate requires (pa, attrs), so that we can report a stage1 ptw failure, and what do_ats_write requires (pa, sh, attrs) for filling in PAR_EL1. Although within these 62 patches I didn't came back to finish converting do_ats_write to use probe_access_flags_extra instead of using get_phys_addr directly, it was a goal. > Is wanting to cache the physaddr an Arm-specific thing, or is it > something we should consider having in the core softmmu code? I'm not sure what other targets require for their 2-stage page table walks. I guess I should have a look (riscv, i386, ?). It *is* possible to recover the phys addr from the iommutlb, because I was doing that in mte_helper.c (see code removed in patch 5), but it's certainly not simple. >> if (likely(!ret)) { >> + PageEntryExtra extra = {}; >> + >> /* >> * Map a single [sub]page. Regions smaller than our declared >> * target page size are handled specially, so for those we >> - * pass in the exact addresses. >> + * pass in the exact addresses. This only happens for M-profile, >> + * which does not use or require PageEntryExtra. >> */ > > Do we have to exclude M-profile here because the PageEntryExtra > data is strictly-per-page, or because the way we've formatted > our extra uint64_t requires the physaddr to be page-aligned, or both? Because our extra uint64_t requires page alignment, and reuses those bits. r~