From: Richard Henderson <richard.henderson@linaro.org>
To: Jinjie Ruan <ruanjinjie@huawei.com>,
peter.maydell@linaro.org, eduardo@habkost.net,
marcel.apfelbaum@gmail.com, philmd@linaro.org,
wangyanan55@huawei.com, qemu-devel@nongnu.org,
qemu-arm@nongnu.org
Subject: Re: [RFC PATCH v3 18/21] hw/intc/arm_gicv3: Implement NMI interrupt prioirty
Date: Fri, 23 Feb 2024 11:23:33 -1000 [thread overview]
Message-ID: <603344eb-d67c-4aa6-8e4b-09b9f570759b@linaro.org> (raw)
In-Reply-To: <20240223103221.1142518-19-ruanjinjie@huawei.com>
On 2/23/24 00:32, Jinjie Ruan via wrote:
> If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI prioirty
> is higher than 0x80, otherwise it is higher than 0x0. And save NMI
> super prioirty information in hppi.superprio to deliver NMI exception.
> Since both GICR and GICD can deliver NMI, it is both necessary to check
> whether the pending irq is NMI in gicv3_redist_update_noirqset and
> gicv3_update_noirqset. And In irqbetter(), only a non-NMI with the same
> priority and a smaller interrupt number can be preempted but not NMI.
>
> Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
> ---
> v3:
> - Add missing brace
> ---
> hw/intc/arm_gicv3.c | 63 ++++++++++++++++++++++++++++++++++++++++-----
> 1 file changed, 56 insertions(+), 7 deletions(-)
>
> diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
> index 0b8f79a122..75999edd19 100644
> --- a/hw/intc/arm_gicv3.c
> +++ b/hw/intc/arm_gicv3.c
> @@ -21,7 +21,7 @@
> #include "hw/intc/arm_gicv3.h"
> #include "gicv3_internal.h"
>
> -static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio)
> +static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio, bool is_nmi)
> {
> /* Return true if this IRQ at this priority should take
> * precedence over the current recorded highest priority
> @@ -33,11 +33,21 @@ static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio)
> if (prio < cs->hppi.prio) {
> return true;
> }
> +
> + /*
> + * Current highest prioirity pending interrupt is not a NMI
> + * and the new IRQ is a NMI with same priority.
> + */
> + if (prio == cs->hppi.prio && !cs->hppi.superprio && is_nmi) {
It would be best to not mix terminology -- superpriority or nmi but not a mix. It's
unfortunate that the manual does so...
It is very tempting expand prio to more bits so that all of the rest of this Just Works.
Because of...
> + if (superprio) {
> + is_nmi = 1;
> +
> + /* DS = 0 & Non-secure NMI */
> + if ((!(cs->gic->gicd_ctlr & GICD_CTLR_DS)) &&
> + extract32(cs->gicr_igroupr0, i, 1)) {
> + prio = 0x80;
> + } else {
> + prio = 0x0;
> + }
> + } else {
> + is_nmi = 0;
> + prio = cs->gicr_ipriorityr[i];
... the need to check GICD_CTLR_DS for interpreting superpriority within the continuum,
per section 4.8.1 (NMI prioritization), it would seem that we could map
Secure NMI -> 0
Non-secure NMI -> 0x100
prio 0x00 .. 0xff -> prio * 2 + 1
which matches the ordering in Figure 4-6.
> @@ -240,10 +271,28 @@ static void gicv3_update_noirqset(GICv3State *s, int start, int len)
> */
> continue;
> }
> - prio = s->gicd_ipriority[i];
> - if (irqbetter(cs, i, prio)) {
> +
> + superprio = *gic_bmp_ptr32(s->superprio, i);
> + /* NMI */
> + if (superprio & (1 << (i & 0x1f))) {
> + is_nmi = 1;
> +
> + /* DS = 0 & Non-secure NMI */
> + if ((!(s->gicd_ctlr & GICD_CTLR_DS)) &&
> + gicv3_gicd_group_test(s, i)) {
> + prio = 0x80;
> + } else {
> + prio = 0x0;
> + }
> + } else {
> + is_nmi = 0;
> + prio = s->gicd_ipriority[i];
> + }
In any case, let's not have two copies of this resolution.
r~
next prev parent reply other threads:[~2024-02-23 22:04 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-23 10:32 [RFC PATCH v3 00/21] target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI Jinjie Ruan via
2024-02-23 10:32 ` [RFC PATCH v3 01/21] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI Jinjie Ruan via
2024-02-23 10:32 ` [RFC PATCH v3 02/21] target/arm: Add PSTATE.ALLINT Jinjie Ruan via
2024-02-23 18:39 ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 03/21] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt Jinjie Ruan via
2024-02-23 10:32 ` [RFC PATCH v3 04/21] target/arm: Implement ALLINT MSR (immediate) Jinjie Ruan via
2024-02-23 19:03 ` Richard Henderson
2024-02-26 2:22 ` Jinjie Ruan via
2024-02-26 19:16 ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 05/21] target/arm: Support MSR access to ALLINT Jinjie Ruan via
2024-02-23 19:08 ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 06/21] target/arm: Add support for Non-maskable Interrupt Jinjie Ruan via
2024-02-23 19:55 ` Richard Henderson
2024-02-26 7:00 ` Jinjie Ruan via
2024-02-23 10:32 ` [RFC PATCH v3 07/21] target/arm: Add support for NMI in arm_phys_excp_target_el() Jinjie Ruan via
2024-02-23 19:58 ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 08/21] target/arm: Handle IS/FS in ISR_EL1 for NMI Jinjie Ruan via
2024-02-23 20:05 ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 09/21] target/arm: Handle PSTATE.ALLINT on taking an exception Jinjie Ruan via
2024-02-23 10:32 ` [RFC PATCH v3 10/21] hw/arm/virt: Wire NMI and VNMI irq lines from GIC to CPU Jinjie Ruan via
2024-02-23 20:06 ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 11/21] hw/intc/arm_gicv3: Add external IRQ lines for NMI Jinjie Ruan via
2024-02-23 20:07 ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 12/21] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64() Jinjie Ruan via
2024-02-23 20:07 ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 13/21] hw/intc/arm_gicv3: Add irq superpriority information Jinjie Ruan via
2024-02-23 10:32 ` [RFC PATCH v3 14/21] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0 Jinjie Ruan via
2024-02-23 20:14 ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 15/21] hw/intc/arm_gicv3: Implement GICD_INMIR Jinjie Ruan via
2024-02-23 10:32 ` [RFC PATCH v3 16/21] hw/intc: Enable FEAT_GICv3_NMI Feature Jinjie Ruan via
2024-02-23 20:14 ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 17/21] hw/intc/arm_gicv3: Add NMI handling CPU interface registers Jinjie Ruan via
2024-02-23 20:52 ` Richard Henderson
2024-02-26 11:22 ` Jinjie Ruan via
2024-02-26 11:32 ` Peter Maydell
2024-02-23 10:32 ` [RFC PATCH v3 18/21] hw/intc/arm_gicv3: Implement NMI interrupt prioirty Jinjie Ruan via
2024-02-23 21:23 ` Richard Henderson [this message]
2024-02-23 10:32 ` [RFC PATCH v3 19/21] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update() Jinjie Ruan via
2024-02-23 21:48 ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 20/21] target/arm: Add FEAT_NMI to max Jinjie Ruan via
2024-02-23 10:32 ` [RFC PATCH v3 21/21] hw/arm/virt: Add FEAT_GICv3_NMI feature support in virt GIC Jinjie Ruan via
2024-02-23 21:50 ` Richard Henderson
2024-02-23 21:51 ` [RFC PATCH v3 00/21] target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI Richard Henderson
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