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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390daf7dbcsm63160665e9.30.2025.02.06.09.44.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Feb 2025 09:44:10 -0800 (PST) Message-ID: <60340d70-e307-44df-9f4f-fffdb6a440e6@linaro.org> Date: Thu, 6 Feb 2025 18:44:09 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 11/16] hw/microblaze: Support various endianness for s3adsp1800 machines To: Max Filippov Cc: =?UTF-8?Q?Daniel_P=2E_Berrang=C3=A9?= , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Anton Johansson , Jason Wang , Paolo Bonzini , Alistair Francis , Thomas Huth , Richard Henderson , Peter Maydell , "Edgar E. Iglesias" , Markus Armbruster , =?UTF-8?Q?Alex_Benn=C3=A9e?= References: <20250206131052.30207-1-philmd@linaro.org> <20250206131052.30207-12-philmd@linaro.org> <4624f149-76d0-4da5-8f13-8c015043c335@linaro.org> <3156dc3b-9553-4b5f-a934-f29ee0601887@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/2/25 18:34, Max Filippov wrote: > On Thu, Feb 6, 2025 at 7:04 AM Philippe Mathieu-Daudé wrote: >> On 6/2/25 15:31, Daniel P. Berrangé wrote: >>> We would pick an arbitrary endianness of our choosing >>> I guess. How does this work in physical machines ? Is >>> the choice of endianess a firmware setting, or a choice >>> by the vendor when manufacturing in some way ? >> >> Like MIPS*, SH4* and Xtensa*, it is a jumper on the board >> (wired to a CPU pin which is sampled once at cold reset). > > This is not exactly the case for xtensa. Each xtensa CPU is either > big- or little-endian and it's a static property of the CPU > configuration. On physical machines it's either fixed (e.g. if > the CPU is a part of an ASIC), or it's a part of a bitstream that > gets loaded into an FPGA and there may be a selector for one > of the bitstreams in the onboard FLASH. In either case there's > normally no board-level switch for the CPU endianness. Yes, this is what we meant in QEMU terms, "static property". > Also big- and little-endian instruction encodings are different on > otherwise identical xtensa CPUs. This is handled within the CPU decode logic, and doesn't have to be exposed. IOW, we don't need 2 distinct TCG frontends to decode the Xtensa ISA.