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Fri, 02 Jul 2021 07:46:31 -0700 (PDT) Received: from [192.168.1.11] ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id m14sm4122586pgu.84.2021.07.02.07.46.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 02 Jul 2021 07:46:31 -0700 (PDT) Subject: Re: [PATCH 07/20] target/loongarch: Add fixed point arithmetic instruction translation To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Song Gao References: <1624881885-31692-1-git-send-email-gaosong@loongson.cn> <1624881885-31692-8-git-send-email-gaosong@loongson.cn> <248d54fc-ebdd-09e9-22c2-e66307b22705@amsat.org> <2912e517-dba0-04f8-80e2-edc0a9b1a27d@amsat.org> From: Richard Henderson Message-ID: <6079cde9-f274-40e2-77ac-3a942455d58a@linaro.org> Date: Fri, 2 Jul 2021 07:46:29 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <2912e517-dba0-04f8-80e2-edc0a9b1a27d@amsat.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, thuth@redhat.com, qemu-devel@nongnu.org, maobibo@loongson.cn, laurent@vivier.eu, alistair.francis@wdc.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/2/21 1:51 AM, Philippe Mathieu-Daudé wrote: > static bool trans_mul_d(DisasContext *ctx, int rd, int rj, int rk) > { > TCGv t0, t1; > > check_loongarch_64(ctx); > > if (a->rd == 0) { > /* Treat as NOP. */ > return true; > } > > t0 = tcg_temp_new(); > t1 = tcg_temp_new(); > > gen_load_gpr(t0, a->rj); > gen_load_gpr(t1, a->rk); Another improvement over mips is possible, while we're at it: TCGv get_gpr(int regno) { if (regno == 0) { return tcg_constant_tl(0); } else { return cpu_gpr[regno]; } } t0 = get_gpr(a->rj); t1 = get_gpr(a->rk); > > tcg_gen_mul_i64(cpu_gpr[a->rd], t0, t1); > > tcg_temp_free(t0); > tcg_temp_free(t1); and now the frees are not necessary. You do have to be careful that you consume the input before you write back to cpu_gpr[a->rd]. Previously you had a copy, but now t0 and t1 reference the live register. And of course you cannot write to either t0 or t1, because one of them might be the constant 0. r~