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([2001:b07:6468:f312:c46c:2acb:d8d2:21d8]) by smtp.gmail.com with ESMTPSA id v6sm14485867wma.24.2019.09.19.07.54.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Sep 2019 07:54:36 -0700 (PDT) Subject: Re: [PATCH 6/7] target/i386: add VMX features To: Liran Alon References: <1568716480-9973-1-git-send-email-pbonzini@redhat.com> <1568716480-9973-7-git-send-email-pbonzini@redhat.com> From: Paolo Bonzini Openpgp: preference=signencrypt Message-ID: <60820b32-42df-dbc0-9fc7-81821b2e42cb@redhat.com> Date: Thu, 19 Sep 2019 16:54:36 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, ehabkost@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 19/09/19 16:32, Liran Alon wrote: >=20 >=20 >> On 17 Sep 2019, at 13:34, Paolo Bonzini wrote: >> >> Add code to convert the VMX feature words back into MSR values, >> allowing the user to enable/disable VMX features as they wish. The sa= me >> infrastructure enables support for limiting VMX features in named >> CPU models. >> >> Signed-off-by: Paolo Bonzini >> --- >> +static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features) >> +{ >> + uint32_t default1, can_be_one, can_be_zero; >> + uint32_t must_be_one; >> + >> + switch (index) { >> + case MSR_IA32_VMX_TRUE_PINBASED_CTLS: >> + default1 =3D 0x00000016; >> + break; >> + case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: >> + default1 =3D 0x0401e172; >> + break; >> + case MSR_IA32_VMX_TRUE_ENTRY_CTLS: >> + default1 =3D 0x000011ff; >> + break; >> + case MSR_IA32_VMX_TRUE_EXIT_CTLS: >> + default1 =3D 0x00036dff; >> + break; >> + case MSR_IA32_VMX_PROCBASED_CTLS2: >> + default1 =3D 0; >> + break; >> + default: >> + abort(); >> + } >> + >=20 > See below. >=20 >> + /* >> + * Bits 0-30, 32-44 and 50-53 come from the host. KVM should >> + * not change them for backwards compatibility. >> + */ >> + uint64_t fixed_vmx_basic =3D kvm_vmx_basic & 0x003c1fff7fffffffUL= L; >> + >> + /* >> + * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) ca= n >> + * change in the future but are always zero for now, clear them t= o be >> + * future proof. Bits 32-63 in theory could change, though KVM d= oes >> + * not support dual-monitor treatment and probably never will; ma= sk >> + * them out as well. >> + */ >> + uint64_t fixed_vmx_misc =3D kvm_vmx_misc & 0x0e00001f; >=20 > I haven=E2=80=99t yet read deeply entire patch-series but I=E2=80=99m d= efinitely against having > these hard-coded values in code instead of explicitly building proper b= itmap > with well-defined bit names. This is error-prone and less readable. > (E.g. Am I suppose as a reader to convert 0x0401e172 to which processor= -based controls it represents?) No, you're not. :) In fact, most of the bits that are set in these constants have no definition. Most "default1" reserved bits have remained reserved since forever, the only exceptions are DEBUGCTL and CR3 load/store controls. The hex constants here correspond simply to the bits that are listed in appendix A of the SDM: Default settings partition the various controls into the following classes: [...] * Default1. They are (or have been) reserved with a default setting of 1. [...] The default1 class of pin-based VM-execution controls contains bits 1, 2, and 4 [...] The default1 class of processor-based VM-execution controls contains bits 1, 4=E2=80=936, 8, 13=E2=80=9316, and 26 [...] The default1 class of VM-exit controls contains bits 0=E2=80=938, 10, 1= 1, 13, 14, 16, and 17 [...] The default1 class of VM-entry controls contains bits 0=E2=80=938 and 1= 2 I could add four #defines for these values, but they are used only here and shouldn't be used elsewhere since make_vmx_msr_value is there exactly to hide the existence of default1 reserved bits. I will add defines for fixed_vmx_basic, fixed_vmx_misc and fixed_vmx_ept_mask, though. Paolo