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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Joel Stanley" <joel@jms.id.au>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Andrew Jeffery" <andrew@aj.id.au>,
	qemu-arm@nongnu.org, "Cédric Le Goater" <clg@kaod.org>,
	"Alex Bennée" <alex.bennee@linaro.org>
Subject: Re: [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0
Date: Wed, 25 Oct 2023 11:17:28 +0200	[thread overview]
Message-ID: <608d8f04-5458-125c-3fa0-9296dfecc9fc@linaro.org> (raw)
In-Reply-To: <20231024162423.40206-1-philmd@linaro.org>

On 24/10/23 18:24, Philippe Mathieu-Daudé wrote:
> Hi,
> 
> This series is extracted for a bigger work.
> 
> Cortex-A MP clusters (TYPE_A15MPCORE_PRIV) should create
> the ARM cores in its own state. Unfortunately we don't do
> it that way, and this model calls qemu_get_cpu().
> 
> In order to remove the qemu_get_cpu() call there, we first
> need to rework some SoC users.
> 
> This series rework the Aspeed SoC state, so it is clear
> what fields are really used by a SoC type (2400 / 2600 /
> 10x0). It will then be easier to have the MP cluster create
> the core instances.

Being a bit more verbose, as I was trying to explain to Cédric
on IRC.

The fby35 machine creates 2 SoCs:

static void fby35_init(MachineState *machine)
{
     Fby35State *s = FBY35(machine);

     fby35_bmc_init(s);
     fby35_bic_init(s);
}

- bmc is Aspeed2600 (A7 MPCORE)
- bic is Aspeed10x0 (M7)

If we were to create the bic before the bmc, as:

static void fby35_init(MachineState *machine)
{
     Fby35State *s = FBY35(machine);

     fby35_bic_init(s);
     fby35_bmc_init(s);
}

then the MPCORE misbehave as it calls qemu_get_cpu(0) which
returns the M7 from the bic.


  parent reply	other threads:[~2023-10-25  9:18 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-24 16:24 [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0 Philippe Mathieu-Daudé
2023-10-24 16:24 ` [PATCH 01/11] hw/arm/aspeed: Extract code common to all boards to a common file Philippe Mathieu-Daudé
2023-10-25  7:06   ` Cédric Le Goater
2023-10-24 16:24 ` [PATCH 02/11] hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific Philippe Mathieu-Daudé
2023-10-25  7:06   ` Cédric Le Goater
2023-10-24 16:24 ` [PATCH 03/11] hw/arm/aspeed: Rename aspeed_soc_realize() " Philippe Mathieu-Daudé
2023-10-25  7:07   ` Cédric Le Goater
2023-10-24 16:24 ` [PATCH 04/11] hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field Philippe Mathieu-Daudé
2023-10-25  7:08   ` Cédric Le Goater
2023-10-24 16:24 ` [PATCH 05/11] hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC Philippe Mathieu-Daudé
2023-10-25  7:08   ` Cédric Le Goater
2023-10-24 16:24 ` [PATCH 06/11] hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC Philippe Mathieu-Daudé
2023-10-25  7:09   ` Cédric Le Goater
2023-10-24 16:24 ` [PATCH 07/11] hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC Philippe Mathieu-Daudé
2023-10-25  7:10   ` Cédric Le Goater
2023-10-24 16:24 ` [PATCH 08/11] hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize Philippe Mathieu-Daudé
2023-10-25  7:11   ` Cédric Le Goater
2023-10-24 16:24 ` [PATCH 09/11] hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState Philippe Mathieu-Daudé
2023-10-25  7:12   ` Cédric Le Goater
2023-10-24 16:24 ` [PATCH 10/11] hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState Philippe Mathieu-Daudé
2023-10-25  7:45   ` Cédric Le Goater
2023-10-24 16:24 ` [PATCH 11/11] hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState Philippe Mathieu-Daudé
2023-10-25  7:45   ` Cédric Le Goater
2023-10-25  9:17 ` Philippe Mathieu-Daudé [this message]
2023-10-25 13:01 ` [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0 Philippe Mathieu-Daudé

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