* [PATCH 01/11] hw/arm/aspeed: Extract code common to all boards to a common file
2023-10-24 16:24 [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0 Philippe Mathieu-Daudé
@ 2023-10-24 16:24 ` Philippe Mathieu-Daudé
2023-10-25 7:06 ` Cédric Le Goater
2023-10-24 16:24 ` [PATCH 02/11] hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific Philippe Mathieu-Daudé
` (11 subsequent siblings)
12 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-24 16:24 UTC (permalink / raw)
To: qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm,
Cédric Le Goater, Philippe Mathieu-Daudé
aspeed_soc.c contains definitions specific to the AST2400
and AST2500 SoCs, but also some definitions for other AST
SoCs: move them to a common file.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/aspeed_soc.c | 96 -------------------------------
hw/arm/aspeed_soc_common.c | 114 +++++++++++++++++++++++++++++++++++++
hw/arm/meson.build | 1 +
3 files changed, 115 insertions(+), 96 deletions(-)
create mode 100644 hw/arm/aspeed_soc_common.c
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index bf22258de9..f6c2ead4ac 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -585,99 +585,3 @@ static void aspeed_soc_register_types(void)
};
type_init(aspeed_soc_register_types);
-
-qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
-{
- return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
-}
-
-bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
-{
- AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- SerialMM *smm;
-
- for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
- smm = &s->uart[i];
-
- /* Chardev property is set by the machine. */
- qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
- qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
- qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
- qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
- if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
- return false;
- }
-
- sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
- aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
- }
-
- return true;
-}
-
-void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
-{
- AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- int i = dev - ASPEED_DEV_UART1;
-
- g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
- qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
-}
-
-/*
- * SDMC should be realized first to get correct RAM size and max size
- * values
- */
-bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
-{
- AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- ram_addr_t ram_size, max_ram_size;
-
- ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
- &error_abort);
- max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
- &error_abort);
-
- memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
- max_ram_size);
- memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
-
- /*
- * Add a memory region beyond the RAM region to let firmwares scan
- * the address space with load/store and guess how much RAM the
- * SoC has.
- */
- if (ram_size < max_ram_size) {
- DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
-
- qdev_prop_set_string(dev, "name", "ram-empty");
- qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size);
- if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
- return false;
- }
-
- memory_region_add_subregion_overlap(&s->dram_container, ram_size,
- sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
- }
-
- memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
- return true;
-}
-
-void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
-{
- memory_region_add_subregion(s->memory, addr,
- sysbus_mmio_get_region(dev, n));
-}
-
-void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
- const char *name, hwaddr addr, uint64_t size)
-{
- qdev_prop_set_string(DEVICE(dev), "name", name);
- qdev_prop_set_uint64(DEVICE(dev), "size", size);
- sysbus_realize(dev, &error_abort);
-
- memory_region_add_subregion_overlap(s->memory, addr,
- sysbus_mmio_get_region(dev, 0), -1000);
-}
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
new file mode 100644
index 0000000000..a43f5d2a6f
--- /dev/null
+++ b/hw/arm/aspeed_soc_common.c
@@ -0,0 +1,114 @@
+/*
+ * ASPEED SoC family
+ *
+ * Andrew Jeffery <andrew@aj.id.au>
+ * Jeremy Kerr <jk@ozlabs.org>
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/misc/unimp.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/char/serial.h"
+
+
+qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
+{
+ return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
+}
+
+bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
+{
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ SerialMM *smm;
+
+ for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
+ smm = &s->uart[i];
+
+ /* Chardev property is set by the machine. */
+ qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
+ qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
+ qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
+ qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
+ if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
+ return false;
+ }
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
+ }
+
+ return true;
+}
+
+void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
+{
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ int i = dev - ASPEED_DEV_UART1;
+
+ g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
+ qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
+}
+
+/*
+ * SDMC should be realized first to get correct RAM size and max size
+ * values
+ */
+bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
+{
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ ram_addr_t ram_size, max_ram_size;
+
+ ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
+ &error_abort);
+ max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
+ &error_abort);
+
+ memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
+ max_ram_size);
+ memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
+
+ /*
+ * Add a memory region beyond the RAM region to let firmwares scan
+ * the address space with load/store and guess how much RAM the
+ * SoC has.
+ */
+ if (ram_size < max_ram_size) {
+ DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
+
+ qdev_prop_set_string(dev, "name", "ram-empty");
+ qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size);
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
+ return false;
+ }
+
+ memory_region_add_subregion_overlap(&s->dram_container, ram_size,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
+ }
+
+ memory_region_add_subregion(s->memory,
+ sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
+ return true;
+}
+
+void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
+{
+ memory_region_add_subregion(s->memory, addr,
+ sysbus_mmio_get_region(dev, n));
+}
+
+void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
+ const char *name, hwaddr addr, uint64_t size)
+{
+ qdev_prop_set_string(DEVICE(dev), "name", name);
+ qdev_prop_set_uint64(DEVICE(dev), "size", size);
+ sysbus_realize(dev, &error_abort);
+
+ memory_region_add_subregion_overlap(s->memory, addr,
+ sysbus_mmio_get_region(dev, 0), -1000);
+}
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index a6feaf1af9..42e7aa36f3 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -50,6 +50,7 @@ arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_soc.c',
'aspeed.c',
+ 'aspeed_soc_common.c',
'aspeed_ast2600.c',
'aspeed_ast10x0.c',
'aspeed_eeprom.c',
--
2.41.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 01/11] hw/arm/aspeed: Extract code common to all boards to a common file
2023-10-24 16:24 ` [PATCH 01/11] hw/arm/aspeed: Extract code common to all boards to a common file Philippe Mathieu-Daudé
@ 2023-10-25 7:06 ` Cédric Le Goater
0 siblings, 0 replies; 25+ messages in thread
From: Cédric Le Goater @ 2023-10-25 7:06 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm
On 10/24/23 18:24, Philippe Mathieu-Daudé wrote:
> aspeed_soc.c contains definitions specific to the AST2400
> and AST2500 SoCs, but also some definitions for other AST
> SoCs: move them to a common file.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed_soc.c | 96 -------------------------------
> hw/arm/aspeed_soc_common.c | 114 +++++++++++++++++++++++++++++++++++++
> hw/arm/meson.build | 1 +
> 3 files changed, 115 insertions(+), 96 deletions(-)
> create mode 100644 hw/arm/aspeed_soc_common.c
>
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index bf22258de9..f6c2ead4ac 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -585,99 +585,3 @@ static void aspeed_soc_register_types(void)
> };
>
> type_init(aspeed_soc_register_types);
> -
> -qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
> -{
> - return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
> -}
> -
> -bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
> -{
> - AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> - SerialMM *smm;
> -
> - for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
> - smm = &s->uart[i];
> -
> - /* Chardev property is set by the machine. */
> - qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
> - qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
> - qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
> - qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
> - if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
> - return false;
> - }
> -
> - sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
> - aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
> - }
> -
> - return true;
> -}
> -
> -void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
> -{
> - AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> - int i = dev - ASPEED_DEV_UART1;
> -
> - g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
> - qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
> -}
> -
> -/*
> - * SDMC should be realized first to get correct RAM size and max size
> - * values
> - */
> -bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
> -{
> - AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> - ram_addr_t ram_size, max_ram_size;
> -
> - ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
> - &error_abort);
> - max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
> - &error_abort);
> -
> - memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
> - max_ram_size);
> - memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
> -
> - /*
> - * Add a memory region beyond the RAM region to let firmwares scan
> - * the address space with load/store and guess how much RAM the
> - * SoC has.
> - */
> - if (ram_size < max_ram_size) {
> - DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
> -
> - qdev_prop_set_string(dev, "name", "ram-empty");
> - qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size);
> - if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
> - return false;
> - }
> -
> - memory_region_add_subregion_overlap(&s->dram_container, ram_size,
> - sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
> - }
> -
> - memory_region_add_subregion(s->memory,
> - sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
> - return true;
> -}
> -
> -void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
> -{
> - memory_region_add_subregion(s->memory, addr,
> - sysbus_mmio_get_region(dev, n));
> -}
> -
> -void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
> - const char *name, hwaddr addr, uint64_t size)
> -{
> - qdev_prop_set_string(DEVICE(dev), "name", name);
> - qdev_prop_set_uint64(DEVICE(dev), "size", size);
> - sysbus_realize(dev, &error_abort);
> -
> - memory_region_add_subregion_overlap(s->memory, addr,
> - sysbus_mmio_get_region(dev, 0), -1000);
> -}
> diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
> new file mode 100644
> index 0000000000..a43f5d2a6f
> --- /dev/null
> +++ b/hw/arm/aspeed_soc_common.c
> @@ -0,0 +1,114 @@
> +/*
> + * ASPEED SoC family
> + *
> + * Andrew Jeffery <andrew@aj.id.au>
> + * Jeremy Kerr <jk@ozlabs.org>
> + *
> + * Copyright 2016 IBM Corp.
> + *
> + * This code is licensed under the GPL version 2 or later. See
> + * the COPYING file in the top-level directory.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "hw/misc/unimp.h"
> +#include "hw/arm/aspeed_soc.h"
> +#include "hw/char/serial.h"
> +
> +
> +qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
> +{
> + return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
> +}
> +
> +bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
> +{
> + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> + SerialMM *smm;
> +
> + for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
> + smm = &s->uart[i];
> +
> + /* Chardev property is set by the machine. */
> + qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
> + qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
> + qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
> + qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
> + if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
> + return false;
> + }
> +
> + sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
> + aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
> + }
> +
> + return true;
> +}
> +
> +void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
> +{
> + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> + int i = dev - ASPEED_DEV_UART1;
> +
> + g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
> + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
> +}
> +
> +/*
> + * SDMC should be realized first to get correct RAM size and max size
> + * values
> + */
> +bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
> +{
> + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> + ram_addr_t ram_size, max_ram_size;
> +
> + ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
> + &error_abort);
> + max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
> + &error_abort);
> +
> + memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
> + max_ram_size);
> + memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
> +
> + /*
> + * Add a memory region beyond the RAM region to let firmwares scan
> + * the address space with load/store and guess how much RAM the
> + * SoC has.
> + */
> + if (ram_size < max_ram_size) {
> + DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
> +
> + qdev_prop_set_string(dev, "name", "ram-empty");
> + qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size);
> + if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
> + return false;
> + }
> +
> + memory_region_add_subregion_overlap(&s->dram_container, ram_size,
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
> + }
> +
> + memory_region_add_subregion(s->memory,
> + sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
> + return true;
> +}
> +
> +void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
> +{
> + memory_region_add_subregion(s->memory, addr,
> + sysbus_mmio_get_region(dev, n));
> +}
> +
> +void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
> + const char *name, hwaddr addr, uint64_t size)
> +{
> + qdev_prop_set_string(DEVICE(dev), "name", name);
> + qdev_prop_set_uint64(DEVICE(dev), "size", size);
> + sysbus_realize(dev, &error_abort);
> +
> + memory_region_add_subregion_overlap(s->memory, addr,
> + sysbus_mmio_get_region(dev, 0), -1000);
> +}
> diff --git a/hw/arm/meson.build b/hw/arm/meson.build
> index a6feaf1af9..42e7aa36f3 100644
> --- a/hw/arm/meson.build
> +++ b/hw/arm/meson.build
> @@ -50,6 +50,7 @@ arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
> arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
> 'aspeed_soc.c',
> 'aspeed.c',
> + 'aspeed_soc_common.c',
> 'aspeed_ast2600.c',
> 'aspeed_ast10x0.c',
> 'aspeed_eeprom.c',
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 02/11] hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific
2023-10-24 16:24 [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0 Philippe Mathieu-Daudé
2023-10-24 16:24 ` [PATCH 01/11] hw/arm/aspeed: Extract code common to all boards to a common file Philippe Mathieu-Daudé
@ 2023-10-24 16:24 ` Philippe Mathieu-Daudé
2023-10-25 7:06 ` Cédric Le Goater
2023-10-24 16:24 ` [PATCH 03/11] hw/arm/aspeed: Rename aspeed_soc_realize() " Philippe Mathieu-Daudé
` (10 subsequent siblings)
12 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-24 16:24 UTC (permalink / raw)
To: qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm,
Cédric Le Goater, Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/aspeed_soc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index f6c2ead4ac..bb377e9e6e 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -140,7 +140,7 @@ static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]);
}
-static void aspeed_soc_init(Object *obj)
+static void aspeed_ast2400_soc_init(Object *obj)
{
AspeedSoCState *s = ASPEED_SOC(obj);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
@@ -546,7 +546,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
static const TypeInfo aspeed_soc_ast2400_type_info = {
.name = "ast2400-a1",
.parent = TYPE_ASPEED_SOC,
- .instance_init = aspeed_soc_init,
+ .instance_init = aspeed_ast2400_soc_init,
.instance_size = sizeof(AspeedSoCState),
.class_init = aspeed_soc_ast2400_class_init,
};
@@ -573,7 +573,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
static const TypeInfo aspeed_soc_ast2500_type_info = {
.name = "ast2500-a1",
.parent = TYPE_ASPEED_SOC,
- .instance_init = aspeed_soc_init,
+ .instance_init = aspeed_ast2400_soc_init,
.instance_size = sizeof(AspeedSoCState),
.class_init = aspeed_soc_ast2500_class_init,
};
--
2.41.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 02/11] hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific
2023-10-24 16:24 ` [PATCH 02/11] hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific Philippe Mathieu-Daudé
@ 2023-10-25 7:06 ` Cédric Le Goater
0 siblings, 0 replies; 25+ messages in thread
From: Cédric Le Goater @ 2023-10-25 7:06 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm
On 10/24/23 18:24, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed_soc.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index f6c2ead4ac..bb377e9e6e 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -140,7 +140,7 @@ static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
> return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]);
> }
>
> -static void aspeed_soc_init(Object *obj)
> +static void aspeed_ast2400_soc_init(Object *obj)
> {
> AspeedSoCState *s = ASPEED_SOC(obj);
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> @@ -546,7 +546,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
> static const TypeInfo aspeed_soc_ast2400_type_info = {
> .name = "ast2400-a1",
> .parent = TYPE_ASPEED_SOC,
> - .instance_init = aspeed_soc_init,
> + .instance_init = aspeed_ast2400_soc_init,
> .instance_size = sizeof(AspeedSoCState),
> .class_init = aspeed_soc_ast2400_class_init,
> };
> @@ -573,7 +573,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
> static const TypeInfo aspeed_soc_ast2500_type_info = {
> .name = "ast2500-a1",
> .parent = TYPE_ASPEED_SOC,
> - .instance_init = aspeed_soc_init,
> + .instance_init = aspeed_ast2400_soc_init,
> .instance_size = sizeof(AspeedSoCState),
> .class_init = aspeed_soc_ast2500_class_init,
> };
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 03/11] hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific
2023-10-24 16:24 [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0 Philippe Mathieu-Daudé
2023-10-24 16:24 ` [PATCH 01/11] hw/arm/aspeed: Extract code common to all boards to a common file Philippe Mathieu-Daudé
2023-10-24 16:24 ` [PATCH 02/11] hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific Philippe Mathieu-Daudé
@ 2023-10-24 16:24 ` Philippe Mathieu-Daudé
2023-10-25 7:07 ` Cédric Le Goater
2023-10-24 16:24 ` [PATCH 04/11] hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field Philippe Mathieu-Daudé
` (9 subsequent siblings)
12 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-24 16:24 UTC (permalink / raw)
To: qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm,
Cédric Le Goater, Philippe Mathieu-Daudé
Keep aspeed_soc_class_init() generic, set the realize handler
to aspeed_ast2400_soc_realize() in each 2400/2500 class_init.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/aspeed_soc.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index bb377e9e6e..191276a320 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -239,7 +239,7 @@ static void aspeed_ast2400_soc_init(Object *obj)
object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
}
-static void aspeed_soc_realize(DeviceState *dev, Error **errp)
+static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
{
int i;
AspeedSoCState *s = ASPEED_SOC(dev);
@@ -509,9 +509,6 @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
- dc->realize = aspeed_soc_realize;
- /* Reason: Uses serial_hds and nd_table in realize() directly */
- dc->user_creatable = false;
device_class_set_props(dc, aspeed_soc_properties);
}
@@ -527,6 +524,11 @@ static const TypeInfo aspeed_soc_type_info = {
static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
{
AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = aspeed_ast2400_soc_realize;
+ /* Reason: Uses serial_hds and nd_table in realize() directly */
+ dc->user_creatable = false;
sc->name = "ast2400-a1";
sc->cpu_type = ARM_CPU_TYPE_NAME("arm926");
@@ -554,6 +556,11 @@ static const TypeInfo aspeed_soc_ast2400_type_info = {
static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
{
AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = aspeed_ast2400_soc_realize;
+ /* Reason: Uses serial_hds and nd_table in realize() directly */
+ dc->user_creatable = false;
sc->name = "ast2500-a1";
sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
--
2.41.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 03/11] hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific
2023-10-24 16:24 ` [PATCH 03/11] hw/arm/aspeed: Rename aspeed_soc_realize() " Philippe Mathieu-Daudé
@ 2023-10-25 7:07 ` Cédric Le Goater
0 siblings, 0 replies; 25+ messages in thread
From: Cédric Le Goater @ 2023-10-25 7:07 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm
On 10/24/23 18:24, Philippe Mathieu-Daudé wrote:
> Keep aspeed_soc_class_init() generic, set the realize handler
> to aspeed_ast2400_soc_realize() in each 2400/2500 class_init.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed_soc.c | 15 +++++++++++----
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index bb377e9e6e..191276a320 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -239,7 +239,7 @@ static void aspeed_ast2400_soc_init(Object *obj)
> object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
> }
>
> -static void aspeed_soc_realize(DeviceState *dev, Error **errp)
> +static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
> {
> int i;
> AspeedSoCState *s = ASPEED_SOC(dev);
> @@ -509,9 +509,6 @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
>
> - dc->realize = aspeed_soc_realize;
> - /* Reason: Uses serial_hds and nd_table in realize() directly */
> - dc->user_creatable = false;
> device_class_set_props(dc, aspeed_soc_properties);
> }
>
> @@ -527,6 +524,11 @@ static const TypeInfo aspeed_soc_type_info = {
> static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
> {
> AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = aspeed_ast2400_soc_realize;
> + /* Reason: Uses serial_hds and nd_table in realize() directly */
> + dc->user_creatable = false;
>
> sc->name = "ast2400-a1";
> sc->cpu_type = ARM_CPU_TYPE_NAME("arm926");
> @@ -554,6 +556,11 @@ static const TypeInfo aspeed_soc_ast2400_type_info = {
> static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
> {
> AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = aspeed_ast2400_soc_realize;
> + /* Reason: Uses serial_hds and nd_table in realize() directly */
> + dc->user_creatable = false;
>
> sc->name = "ast2500-a1";
> sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 04/11] hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field
2023-10-24 16:24 [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0 Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2023-10-24 16:24 ` [PATCH 03/11] hw/arm/aspeed: Rename aspeed_soc_realize() " Philippe Mathieu-Daudé
@ 2023-10-24 16:24 ` Philippe Mathieu-Daudé
2023-10-25 7:08 ` Cédric Le Goater
2023-10-24 16:24 ` [PATCH 05/11] hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC Philippe Mathieu-Daudé
` (8 subsequent siblings)
12 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-24 16:24 UTC (permalink / raw)
To: qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm,
Cédric Le Goater, Philippe Mathieu-Daudé
We want to derivate the big AspeedSoCState object in some more
SoC-specific ones. Since the object size will vary, allocate it
dynamically.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/aspeed.c | 101 +++++++++++++++++++++++++-----------------------
1 file changed, 52 insertions(+), 49 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index f8ba67531a..cc59176563 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -40,7 +40,7 @@ struct AspeedMachineState {
MachineState parent_obj;
/* Public */
- AspeedSoCState soc;
+ AspeedSoCState *soc;
MemoryRegion boot_rom;
bool mmio_exec;
uint32_t uart_chosen;
@@ -288,7 +288,7 @@ static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
uint64_t rom_size)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
&error_abort);
@@ -337,7 +337,7 @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
{
AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
- AspeedSoCState *s = &bmc->soc;
+ AspeedSoCState *s = bmc->soc;
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
@@ -358,32 +358,33 @@ static void aspeed_machine_init(MachineState *machine)
int i;
NICInfo *nd = &nd_table[0];
- object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
-
- sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
+ bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
+ object_unref(OBJECT(bmc->soc));
+ sc = ASPEED_SOC_GET_CLASS(bmc->soc);
/*
* This will error out if the RAM size is not supported by the
* memory controller of the SoC.
*/
- object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
+ object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size,
&error_fatal);
for (i = 0; i < sc->macs_num; i++) {
if ((amc->macs_mask & (1 << i)) && nd->used) {
qemu_check_nic_model(nd, TYPE_FTGMAC100);
- qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
+ qdev_set_nic_properties(DEVICE(&bmc->soc->ftgmac100[i]), nd);
nd++;
}
}
- object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
+ object_property_set_int(OBJECT(bmc->soc), "hw-strap1", amc->hw_strap1,
&error_abort);
- object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
+ object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2,
&error_abort);
- object_property_set_link(OBJECT(&bmc->soc), "memory",
+ object_property_set_link(OBJECT(bmc->soc), "memory",
OBJECT(get_system_memory()), &error_abort);
- object_property_set_link(OBJECT(&bmc->soc), "dram",
+ object_property_set_link(OBJECT(bmc->soc), "dram",
OBJECT(machine->ram), &error_abort);
if (machine->kernel_filename) {
/*
@@ -391,17 +392,17 @@ static void aspeed_machine_init(MachineState *machine)
* that runs to unlock the SCU. In this case set the default to
* be unlocked as the kernel expects
*/
- object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
+ object_property_set_int(OBJECT(bmc->soc), "hw-prot-key",
ASPEED_SCU_PROT_KEY, &error_abort);
}
connect_serial_hds_to_uarts(bmc);
- qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
+ qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
if (defaults_enabled()) {
- aspeed_board_init_flashes(&bmc->soc.fmc,
+ aspeed_board_init_flashes(&bmc->soc->fmc,
bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
amc->num_cs, 0);
- aspeed_board_init_flashes(&bmc->soc.spi[0],
+ aspeed_board_init_flashes(&bmc->soc->spi[0],
bmc->spi_model ? bmc->spi_model : amc->spi_model,
1, amc->num_cs);
}
@@ -426,22 +427,22 @@ static void aspeed_machine_init(MachineState *machine)
amc->i2c_init(bmc);
}
- for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
- sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
+ for (i = 0; i < bmc->soc->sdhci.num_slots; i++) {
+ sdhci_attach_drive(&bmc->soc->sdhci.slots[i],
drive_get(IF_SD, 0, i));
}
- if (bmc->soc.emmc.num_slots) {
- sdhci_attach_drive(&bmc->soc.emmc.slots[0],
- drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
+ if (bmc->soc->emmc.num_slots) {
+ sdhci_attach_drive(&bmc->soc->emmc.slots[0],
+ drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots));
}
if (!bmc->mmio_exec) {
- DeviceState *dev = ssi_get_cs(bmc->soc.fmc.spi, 0);
+ DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0);
BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL;
if (fmc0) {
- uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
+ uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot);
aspeed_install_boot_rom(bmc, fmc0, rom_size);
}
}
@@ -451,7 +452,7 @@ static void aspeed_machine_init(MachineState *machine)
static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
DeviceState *dev;
uint8_t *eeprom_buf = g_malloc0(32 * 1024);
@@ -473,7 +474,7 @@ static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
/*
* The quanta-q71l platform expects tmp75s which are compatible with
@@ -505,7 +506,7 @@ static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
uint8_t *eeprom_buf = g_malloc0(8 * 1024);
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
@@ -518,7 +519,7 @@ static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
uint8_t *eeprom_buf = g_malloc0(8 * 1024);
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
@@ -531,7 +532,7 @@ static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
@@ -545,7 +546,7 @@ static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
/* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
* good enough */
@@ -554,7 +555,7 @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
@@ -573,7 +574,7 @@ static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
/* bus 2 : */
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
@@ -627,7 +628,7 @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
{14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
{15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
};
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
uint8_t *eeprom_buf = g_malloc0(8 * 1024);
DeviceState *dev;
LEDState *led;
@@ -672,7 +673,7 @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
DeviceState *dev;
dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
@@ -708,7 +709,7 @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
I2CSlave *i2c_mux;
/* The at24c256 */
@@ -735,7 +736,7 @@ static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
I2CSlave *i2c_mux;
at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
@@ -852,7 +853,7 @@ static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
I2CBus *i2c[144] = {};
for (int i = 0; i < 16; i++) {
@@ -930,7 +931,7 @@ static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
I2CBus *i2c[13] = {};
for (int i = 0; i < 13; i++) {
if ((i == 8) || (i == 11)) {
@@ -976,7 +977,7 @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
static void fby35_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
I2CBus *i2c[16];
for (int i = 0; i < 16; i++) {
@@ -1008,14 +1009,14 @@ static void fby35_i2c_init(AspeedMachineState *bmc)
static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
}
static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
I2CSlave *therm_mux, *cpuvr_mux;
/* Create the generic DC-SCM hardware */
@@ -1477,7 +1478,7 @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
static void fby35_reset(MachineState *state, ShutdownCause reason)
{
AspeedMachineState *bmc = ASPEED_MACHINE(state);
- AspeedGPIOState *gpio = &bmc->soc.gpio;
+ AspeedGPIOState *gpio = &bmc->soc->gpio;
qemu_devices_reset(reason);
@@ -1528,24 +1529,26 @@ static void aspeed_minibmc_machine_init(MachineState *machine)
sysclk = clock_new(OBJECT(machine), "SYSCLK");
clock_set_hz(sysclk, SYSCLK_FRQ);
- object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
- qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
+ bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
+ object_unref(OBJECT(bmc->soc));
+ qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
- object_property_set_link(OBJECT(&bmc->soc), "memory",
+ object_property_set_link(OBJECT(bmc->soc), "memory",
OBJECT(get_system_memory()), &error_abort);
connect_serial_hds_to_uarts(bmc);
- qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
+ qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
- aspeed_board_init_flashes(&bmc->soc.fmc,
+ aspeed_board_init_flashes(&bmc->soc->fmc,
bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
amc->num_cs,
0);
- aspeed_board_init_flashes(&bmc->soc.spi[0],
+ aspeed_board_init_flashes(&bmc->soc->spi[0],
bmc->spi_model ? bmc->spi_model : amc->spi_model,
amc->num_cs, amc->num_cs);
- aspeed_board_init_flashes(&bmc->soc.spi[1],
+ aspeed_board_init_flashes(&bmc->soc->spi[1],
bmc->spi_model ? bmc->spi_model : amc->spi_model,
amc->num_cs, (amc->num_cs * 2));
@@ -1561,7 +1564,7 @@ static void aspeed_minibmc_machine_init(MachineState *machine)
static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
/* U10 24C08 connects to SDA/SCL Group 1 by default */
uint8_t *eeprom_buf = g_malloc0(32 * 1024);
--
2.41.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 04/11] hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field
2023-10-24 16:24 ` [PATCH 04/11] hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field Philippe Mathieu-Daudé
@ 2023-10-25 7:08 ` Cédric Le Goater
0 siblings, 0 replies; 25+ messages in thread
From: Cédric Le Goater @ 2023-10-25 7:08 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm
On 10/24/23 18:24, Philippe Mathieu-Daudé wrote:
> We want to derivate the big AspeedSoCState object in some more
> SoC-specific ones. Since the object size will vary, allocate it
> dynamically.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed.c | 101 +++++++++++++++++++++++++-----------------------
> 1 file changed, 52 insertions(+), 49 deletions(-)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index f8ba67531a..cc59176563 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -40,7 +40,7 @@ struct AspeedMachineState {
> MachineState parent_obj;
> /* Public */
>
> - AspeedSoCState soc;
> + AspeedSoCState *soc;
> MemoryRegion boot_rom;
> bool mmio_exec;
> uint32_t uart_chosen;
> @@ -288,7 +288,7 @@ static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
> static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
> uint64_t rom_size)
> {
> - AspeedSoCState *soc = &bmc->soc;
> + AspeedSoCState *soc = bmc->soc;
>
> memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
> &error_abort);
> @@ -337,7 +337,7 @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
> static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
> {
> AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
> - AspeedSoCState *s = &bmc->soc;
> + AspeedSoCState *s = bmc->soc;
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
>
> @@ -358,32 +358,33 @@ static void aspeed_machine_init(MachineState *machine)
> int i;
> NICInfo *nd = &nd_table[0];
>
> - object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
> -
> - sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
> + bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
> + object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
> + object_unref(OBJECT(bmc->soc));
> + sc = ASPEED_SOC_GET_CLASS(bmc->soc);
>
> /*
> * This will error out if the RAM size is not supported by the
> * memory controller of the SoC.
> */
> - object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
> + object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size,
> &error_fatal);
>
> for (i = 0; i < sc->macs_num; i++) {
> if ((amc->macs_mask & (1 << i)) && nd->used) {
> qemu_check_nic_model(nd, TYPE_FTGMAC100);
> - qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
> + qdev_set_nic_properties(DEVICE(&bmc->soc->ftgmac100[i]), nd);
> nd++;
> }
> }
>
> - object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
> + object_property_set_int(OBJECT(bmc->soc), "hw-strap1", amc->hw_strap1,
> &error_abort);
> - object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
> + object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2,
> &error_abort);
> - object_property_set_link(OBJECT(&bmc->soc), "memory",
> + object_property_set_link(OBJECT(bmc->soc), "memory",
> OBJECT(get_system_memory()), &error_abort);
> - object_property_set_link(OBJECT(&bmc->soc), "dram",
> + object_property_set_link(OBJECT(bmc->soc), "dram",
> OBJECT(machine->ram), &error_abort);
> if (machine->kernel_filename) {
> /*
> @@ -391,17 +392,17 @@ static void aspeed_machine_init(MachineState *machine)
> * that runs to unlock the SCU. In this case set the default to
> * be unlocked as the kernel expects
> */
> - object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
> + object_property_set_int(OBJECT(bmc->soc), "hw-prot-key",
> ASPEED_SCU_PROT_KEY, &error_abort);
> }
> connect_serial_hds_to_uarts(bmc);
> - qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
> + qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
>
> if (defaults_enabled()) {
> - aspeed_board_init_flashes(&bmc->soc.fmc,
> + aspeed_board_init_flashes(&bmc->soc->fmc,
> bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
> amc->num_cs, 0);
> - aspeed_board_init_flashes(&bmc->soc.spi[0],
> + aspeed_board_init_flashes(&bmc->soc->spi[0],
> bmc->spi_model ? bmc->spi_model : amc->spi_model,
> 1, amc->num_cs);
> }
> @@ -426,22 +427,22 @@ static void aspeed_machine_init(MachineState *machine)
> amc->i2c_init(bmc);
> }
>
> - for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
> - sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
> + for (i = 0; i < bmc->soc->sdhci.num_slots; i++) {
> + sdhci_attach_drive(&bmc->soc->sdhci.slots[i],
> drive_get(IF_SD, 0, i));
> }
>
> - if (bmc->soc.emmc.num_slots) {
> - sdhci_attach_drive(&bmc->soc.emmc.slots[0],
> - drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
> + if (bmc->soc->emmc.num_slots) {
> + sdhci_attach_drive(&bmc->soc->emmc.slots[0],
> + drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots));
> }
>
> if (!bmc->mmio_exec) {
> - DeviceState *dev = ssi_get_cs(bmc->soc.fmc.spi, 0);
> + DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0);
> BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL;
>
> if (fmc0) {
> - uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
> + uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot);
> aspeed_install_boot_rom(bmc, fmc0, rom_size);
> }
> }
> @@ -451,7 +452,7 @@ static void aspeed_machine_init(MachineState *machine)
>
> static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
> {
> - AspeedSoCState *soc = &bmc->soc;
> + AspeedSoCState *soc = bmc->soc;
> DeviceState *dev;
> uint8_t *eeprom_buf = g_malloc0(32 * 1024);
>
> @@ -473,7 +474,7 @@ static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
>
> static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
> {
> - AspeedSoCState *soc = &bmc->soc;
> + AspeedSoCState *soc = bmc->soc;
>
> /*
> * The quanta-q71l platform expects tmp75s which are compatible with
> @@ -505,7 +506,7 @@ static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
>
> static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
> {
> - AspeedSoCState *soc = &bmc->soc;
> + AspeedSoCState *soc = bmc->soc;
> uint8_t *eeprom_buf = g_malloc0(8 * 1024);
>
> smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
> @@ -518,7 +519,7 @@ static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
>
> static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
> {
> - AspeedSoCState *soc = &bmc->soc;
> + AspeedSoCState *soc = bmc->soc;
> uint8_t *eeprom_buf = g_malloc0(8 * 1024);
>
> smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
> @@ -531,7 +532,7 @@ static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
>
> static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
> {
> - AspeedSoCState *soc = &bmc->soc;
> + AspeedSoCState *soc = bmc->soc;
>
> at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
> at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
> @@ -545,7 +546,7 @@ static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
>
> static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
> {
> - AspeedSoCState *soc = &bmc->soc;
> + AspeedSoCState *soc = bmc->soc;
>
> /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
> * good enough */
> @@ -554,7 +555,7 @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
>
> static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
> {
> - AspeedSoCState *soc = &bmc->soc;
> + AspeedSoCState *soc = bmc->soc;
>
> at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
> at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
> @@ -573,7 +574,7 @@ static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
>
> static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
> {
> - AspeedSoCState *soc = &bmc->soc;
> + AspeedSoCState *soc = bmc->soc;
>
> /* bus 2 : */
> i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
> @@ -627,7 +628,7 @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
> {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
> {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
> };
> - AspeedSoCState *soc = &bmc->soc;
> + AspeedSoCState *soc = bmc->soc;
> uint8_t *eeprom_buf = g_malloc0(8 * 1024);
> DeviceState *dev;
> LEDState *led;
> @@ -672,7 +673,7 @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
>
> static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
> {
> - AspeedSoCState *soc = &bmc->soc;
> + AspeedSoCState *soc = bmc->soc;
> DeviceState *dev;
>
> dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
> @@ -708,7 +709,7 @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
>
> static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
> {
> - AspeedSoCState *soc = &bmc->soc;
> + AspeedSoCState *soc = bmc->soc;
> I2CSlave *i2c_mux;
>
> /* The at24c256 */
> @@ -735,7 +736,7 @@ static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
>
> static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
> {
> - AspeedSoCState *soc = &bmc->soc;
> + AspeedSoCState *soc = bmc->soc;
> I2CSlave *i2c_mux;
>
> at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
> @@ -852,7 +853,7 @@ static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
>
> static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
> {
> - AspeedSoCState *soc = &bmc->soc;
> + AspeedSoCState *soc = bmc->soc;
> I2CBus *i2c[144] = {};
>
> for (int i = 0; i < 16; i++) {
> @@ -930,7 +931,7 @@ static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
>
> static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
> {
> - AspeedSoCState *soc = &bmc->soc;
> + AspeedSoCState *soc = bmc->soc;
> I2CBus *i2c[13] = {};
> for (int i = 0; i < 13; i++) {
> if ((i == 8) || (i == 11)) {
> @@ -976,7 +977,7 @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
>
> static void fby35_i2c_init(AspeedMachineState *bmc)
> {
> - AspeedSoCState *soc = &bmc->soc;
> + AspeedSoCState *soc = bmc->soc;
> I2CBus *i2c[16];
>
> for (int i = 0; i < 16; i++) {
> @@ -1008,14 +1009,14 @@ static void fby35_i2c_init(AspeedMachineState *bmc)
>
> static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
> {
> - AspeedSoCState *soc = &bmc->soc;
> + AspeedSoCState *soc = bmc->soc;
>
> i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
> }
>
> static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
> {
> - AspeedSoCState *soc = &bmc->soc;
> + AspeedSoCState *soc = bmc->soc;
> I2CSlave *therm_mux, *cpuvr_mux;
>
> /* Create the generic DC-SCM hardware */
> @@ -1477,7 +1478,7 @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
> static void fby35_reset(MachineState *state, ShutdownCause reason)
> {
> AspeedMachineState *bmc = ASPEED_MACHINE(state);
> - AspeedGPIOState *gpio = &bmc->soc.gpio;
> + AspeedGPIOState *gpio = &bmc->soc->gpio;
>
> qemu_devices_reset(reason);
>
> @@ -1528,24 +1529,26 @@ static void aspeed_minibmc_machine_init(MachineState *machine)
> sysclk = clock_new(OBJECT(machine), "SYSCLK");
> clock_set_hz(sysclk, SYSCLK_FRQ);
>
> - object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
> - qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
> + bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
> + object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
> + object_unref(OBJECT(bmc->soc));
> + qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
>
> - object_property_set_link(OBJECT(&bmc->soc), "memory",
> + object_property_set_link(OBJECT(bmc->soc), "memory",
> OBJECT(get_system_memory()), &error_abort);
> connect_serial_hds_to_uarts(bmc);
> - qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
> + qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
>
> - aspeed_board_init_flashes(&bmc->soc.fmc,
> + aspeed_board_init_flashes(&bmc->soc->fmc,
> bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
> amc->num_cs,
> 0);
>
> - aspeed_board_init_flashes(&bmc->soc.spi[0],
> + aspeed_board_init_flashes(&bmc->soc->spi[0],
> bmc->spi_model ? bmc->spi_model : amc->spi_model,
> amc->num_cs, amc->num_cs);
>
> - aspeed_board_init_flashes(&bmc->soc.spi[1],
> + aspeed_board_init_flashes(&bmc->soc->spi[1],
> bmc->spi_model ? bmc->spi_model : amc->spi_model,
> amc->num_cs, (amc->num_cs * 2));
>
> @@ -1561,7 +1564,7 @@ static void aspeed_minibmc_machine_init(MachineState *machine)
>
> static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
> {
> - AspeedSoCState *soc = &bmc->soc;
> + AspeedSoCState *soc = bmc->soc;
>
> /* U10 24C08 connects to SDA/SCL Group 1 by default */
> uint8_t *eeprom_buf = g_malloc0(32 * 1024);
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 05/11] hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC
2023-10-24 16:24 [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0 Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2023-10-24 16:24 ` [PATCH 04/11] hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field Philippe Mathieu-Daudé
@ 2023-10-24 16:24 ` Philippe Mathieu-Daudé
2023-10-25 7:08 ` Cédric Le Goater
2023-10-24 16:24 ` [PATCH 06/11] hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC Philippe Mathieu-Daudé
` (7 subsequent siblings)
12 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-24 16:24 UTC (permalink / raw)
To: qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm,
Cédric Le Goater, Philippe Mathieu-Daudé
TYPE_ASPEED10X0_SOC inherits from TYPE_ASPEED_SOC.
In few commits we'll add more fields, but to keep
review process simple, don't add any yet.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/arm/aspeed_soc.h | 7 +++++++
hw/arm/aspeed_ast10x0.c | 26 +++++++++++++-------------
2 files changed, 20 insertions(+), 13 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 8adff70072..dcb43a4ecd 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -101,6 +101,13 @@ struct AspeedSoCState {
#define TYPE_ASPEED_SOC "aspeed-soc"
OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
+struct Aspeed10x0SoCState {
+ AspeedSoCState parent;
+};
+
+#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
+
struct AspeedSoCClass {
DeviceClass parent_class;
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 649b3b13c1..1c15bf422f 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -435,18 +435,18 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
sc->get_irq = aspeed_soc_ast1030_get_irq;
}
-static const TypeInfo aspeed_soc_ast1030_type_info = {
- .name = "ast1030-a1",
- .parent = TYPE_ASPEED_SOC,
- .instance_size = sizeof(AspeedSoCState),
- .instance_init = aspeed_soc_ast1030_init,
- .class_init = aspeed_soc_ast1030_class_init,
- .class_size = sizeof(AspeedSoCClass),
+static const TypeInfo aspeed_soc_ast10x0_types[] = {
+ {
+ .name = TYPE_ASPEED10X0_SOC,
+ .parent = TYPE_ASPEED_SOC,
+ .instance_size = sizeof(Aspeed10x0SoCState),
+ .abstract = true,
+ }, {
+ .name = "ast1030-a1",
+ .parent = TYPE_ASPEED10X0_SOC,
+ .instance_init = aspeed_soc_ast1030_init,
+ .class_init = aspeed_soc_ast1030_class_init,
+ },
};
-static void aspeed_soc_register_types(void)
-{
- type_register_static(&aspeed_soc_ast1030_type_info);
-}
-
-type_init(aspeed_soc_register_types)
+DEFINE_TYPES(aspeed_soc_ast10x0_types)
--
2.41.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 05/11] hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC
2023-10-24 16:24 ` [PATCH 05/11] hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC Philippe Mathieu-Daudé
@ 2023-10-25 7:08 ` Cédric Le Goater
0 siblings, 0 replies; 25+ messages in thread
From: Cédric Le Goater @ 2023-10-25 7:08 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm
On 10/24/23 18:24, Philippe Mathieu-Daudé wrote:
> TYPE_ASPEED10X0_SOC inherits from TYPE_ASPEED_SOC.
> In few commits we'll add more fields, but to keep
> review process simple, don't add any yet.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> include/hw/arm/aspeed_soc.h | 7 +++++++
> hw/arm/aspeed_ast10x0.c | 26 +++++++++++++-------------
> 2 files changed, 20 insertions(+), 13 deletions(-)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 8adff70072..dcb43a4ecd 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -101,6 +101,13 @@ struct AspeedSoCState {
> #define TYPE_ASPEED_SOC "aspeed-soc"
> OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
>
> +struct Aspeed10x0SoCState {
> + AspeedSoCState parent;
> +};
> +
> +#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
> +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
> +
> struct AspeedSoCClass {
> DeviceClass parent_class;
>
> diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
> index 649b3b13c1..1c15bf422f 100644
> --- a/hw/arm/aspeed_ast10x0.c
> +++ b/hw/arm/aspeed_ast10x0.c
> @@ -435,18 +435,18 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
> sc->get_irq = aspeed_soc_ast1030_get_irq;
> }
>
> -static const TypeInfo aspeed_soc_ast1030_type_info = {
> - .name = "ast1030-a1",
> - .parent = TYPE_ASPEED_SOC,
> - .instance_size = sizeof(AspeedSoCState),
> - .instance_init = aspeed_soc_ast1030_init,
> - .class_init = aspeed_soc_ast1030_class_init,
> - .class_size = sizeof(AspeedSoCClass),
> +static const TypeInfo aspeed_soc_ast10x0_types[] = {
> + {
> + .name = TYPE_ASPEED10X0_SOC,
> + .parent = TYPE_ASPEED_SOC,
> + .instance_size = sizeof(Aspeed10x0SoCState),
> + .abstract = true,
> + }, {
> + .name = "ast1030-a1",
> + .parent = TYPE_ASPEED10X0_SOC,
> + .instance_init = aspeed_soc_ast1030_init,
> + .class_init = aspeed_soc_ast1030_class_init,
> + },
> };
>
> -static void aspeed_soc_register_types(void)
> -{
> - type_register_static(&aspeed_soc_ast1030_type_info);
> -}
> -
> -type_init(aspeed_soc_register_types)
> +DEFINE_TYPES(aspeed_soc_ast10x0_types)
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 06/11] hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC
2023-10-24 16:24 [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0 Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2023-10-24 16:24 ` [PATCH 05/11] hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC Philippe Mathieu-Daudé
@ 2023-10-24 16:24 ` Philippe Mathieu-Daudé
2023-10-25 7:09 ` Cédric Le Goater
2023-10-24 16:24 ` [PATCH 07/11] hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC Philippe Mathieu-Daudé
` (6 subsequent siblings)
12 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-24 16:24 UTC (permalink / raw)
To: qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm,
Cédric Le Goater, Philippe Mathieu-Daudé
TYPE_ASPEED2600_SOC inherits from TYPE_ASPEED_SOC.
In few commits we'll add more fields, but to keep
review process simple, don't add any yet.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/arm/aspeed_soc.h | 7 +++++++
hw/arm/aspeed_ast2600.c | 26 +++++++++++++-------------
2 files changed, 20 insertions(+), 13 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index dcb43a4ecd..103b1598f6 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -101,6 +101,13 @@ struct AspeedSoCState {
#define TYPE_ASPEED_SOC "aspeed-soc"
OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
+struct Aspeed2600SoCState {
+ AspeedSoCState parent;
+};
+
+#define TYPE_ASPEED2600_SOC "aspeed2600-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
+
struct Aspeed10x0SoCState {
AspeedSoCState parent;
};
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index e122e1c32d..1ee460e56c 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -646,18 +646,18 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
sc->get_irq = aspeed_soc_ast2600_get_irq;
}
-static const TypeInfo aspeed_soc_ast2600_type_info = {
- .name = "ast2600-a3",
- .parent = TYPE_ASPEED_SOC,
- .instance_size = sizeof(AspeedSoCState),
- .instance_init = aspeed_soc_ast2600_init,
- .class_init = aspeed_soc_ast2600_class_init,
- .class_size = sizeof(AspeedSoCClass),
+static const TypeInfo aspeed_soc_ast2600_types[] = {
+ {
+ .name = TYPE_ASPEED2600_SOC,
+ .parent = TYPE_ASPEED_SOC,
+ .instance_size = sizeof(Aspeed2600SoCState),
+ .abstract = true,
+ }, {
+ .name = "ast2600-a3",
+ .parent = TYPE_ASPEED2600_SOC,
+ .instance_init = aspeed_soc_ast2600_init,
+ .class_init = aspeed_soc_ast2600_class_init,
+ },
};
-static void aspeed_soc_register_types(void)
-{
- type_register_static(&aspeed_soc_ast2600_type_info);
-};
-
-type_init(aspeed_soc_register_types)
+DEFINE_TYPES(aspeed_soc_ast2600_types)
--
2.41.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 06/11] hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC
2023-10-24 16:24 ` [PATCH 06/11] hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC Philippe Mathieu-Daudé
@ 2023-10-25 7:09 ` Cédric Le Goater
0 siblings, 0 replies; 25+ messages in thread
From: Cédric Le Goater @ 2023-10-25 7:09 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm
On 10/24/23 18:24, Philippe Mathieu-Daudé wrote:
> TYPE_ASPEED2600_SOC inherits from TYPE_ASPEED_SOC.
> In few commits we'll add more fields, but to keep
> review process simple, don't add any yet.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> include/hw/arm/aspeed_soc.h | 7 +++++++
> hw/arm/aspeed_ast2600.c | 26 +++++++++++++-------------
> 2 files changed, 20 insertions(+), 13 deletions(-)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index dcb43a4ecd..103b1598f6 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -101,6 +101,13 @@ struct AspeedSoCState {
> #define TYPE_ASPEED_SOC "aspeed-soc"
> OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
>
> +struct Aspeed2600SoCState {
> + AspeedSoCState parent;
> +};
> +
> +#define TYPE_ASPEED2600_SOC "aspeed2600-soc"
> +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
> +
> struct Aspeed10x0SoCState {
> AspeedSoCState parent;
> };
> diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
> index e122e1c32d..1ee460e56c 100644
> --- a/hw/arm/aspeed_ast2600.c
> +++ b/hw/arm/aspeed_ast2600.c
> @@ -646,18 +646,18 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
> sc->get_irq = aspeed_soc_ast2600_get_irq;
> }
>
> -static const TypeInfo aspeed_soc_ast2600_type_info = {
> - .name = "ast2600-a3",
> - .parent = TYPE_ASPEED_SOC,
> - .instance_size = sizeof(AspeedSoCState),
> - .instance_init = aspeed_soc_ast2600_init,
> - .class_init = aspeed_soc_ast2600_class_init,
> - .class_size = sizeof(AspeedSoCClass),
> +static const TypeInfo aspeed_soc_ast2600_types[] = {
> + {
> + .name = TYPE_ASPEED2600_SOC,
> + .parent = TYPE_ASPEED_SOC,
> + .instance_size = sizeof(Aspeed2600SoCState),
> + .abstract = true,
> + }, {
> + .name = "ast2600-a3",
> + .parent = TYPE_ASPEED2600_SOC,
> + .instance_init = aspeed_soc_ast2600_init,
> + .class_init = aspeed_soc_ast2600_class_init,
> + },
> };
>
> -static void aspeed_soc_register_types(void)
> -{
> - type_register_static(&aspeed_soc_ast2600_type_info);
> -};
> -
> -type_init(aspeed_soc_register_types)
> +DEFINE_TYPES(aspeed_soc_ast2600_types)
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 07/11] hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC
2023-10-24 16:24 [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0 Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2023-10-24 16:24 ` [PATCH 06/11] hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC Philippe Mathieu-Daudé
@ 2023-10-24 16:24 ` Philippe Mathieu-Daudé
2023-10-25 7:10 ` Cédric Le Goater
2023-10-24 16:24 ` [PATCH 08/11] hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize Philippe Mathieu-Daudé
` (5 subsequent siblings)
12 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-24 16:24 UTC (permalink / raw)
To: qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm,
Cédric Le Goater, Philippe Mathieu-Daudé
TYPE_ASPEED2400_SOC inherits from TYPE_ASPEED_SOC.
In few commits we'll add more fields, but to keep
review process simple, don't add any yet.
TYPE_ASPEED_SOC is common to various Aspeed SoCs,
define it in aspeed_soc_common.c.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/arm/aspeed_soc.h | 7 +++++
hw/arm/aspeed_soc.c | 61 +++++++++++--------------------------
hw/arm/aspeed_soc_common.c | 29 ++++++++++++++++++
3 files changed, 53 insertions(+), 44 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 103b1598f6..ee7926b81c 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -101,6 +101,13 @@ struct AspeedSoCState {
#define TYPE_ASPEED_SOC "aspeed-soc"
OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
+struct Aspeed2400SoCState {
+ AspeedSoCState parent;
+};
+
+#define TYPE_ASPEED2400_SOC "aspeed2400-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
+
struct Aspeed2600SoCState {
AspeedSoCState parent;
};
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 191276a320..dfb97f6dbd 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -497,29 +497,6 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
}
-static Property aspeed_soc_properties[] = {
- DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
- MemoryRegion *),
- DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
- MemoryRegion *),
- DEFINE_PROP_END_OF_LIST(),
-};
-
-static void aspeed_soc_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- device_class_set_props(dc, aspeed_soc_properties);
-}
-
-static const TypeInfo aspeed_soc_type_info = {
- .name = TYPE_ASPEED_SOC,
- .parent = TYPE_DEVICE,
- .instance_size = sizeof(AspeedSoCState),
- .class_size = sizeof(AspeedSoCClass),
- .class_init = aspeed_soc_class_init,
- .abstract = true,
-};
static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
{
@@ -545,14 +522,6 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
sc->get_irq = aspeed_soc_ast2400_get_irq;
}
-static const TypeInfo aspeed_soc_ast2400_type_info = {
- .name = "ast2400-a1",
- .parent = TYPE_ASPEED_SOC,
- .instance_init = aspeed_ast2400_soc_init,
- .instance_size = sizeof(AspeedSoCState),
- .class_init = aspeed_soc_ast2400_class_init,
-};
-
static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
{
AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
@@ -577,18 +546,22 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
sc->get_irq = aspeed_soc_ast2400_get_irq;
}
-static const TypeInfo aspeed_soc_ast2500_type_info = {
- .name = "ast2500-a1",
- .parent = TYPE_ASPEED_SOC,
- .instance_init = aspeed_ast2400_soc_init,
- .instance_size = sizeof(AspeedSoCState),
- .class_init = aspeed_soc_ast2500_class_init,
-};
-static void aspeed_soc_register_types(void)
-{
- type_register_static(&aspeed_soc_type_info);
- type_register_static(&aspeed_soc_ast2400_type_info);
- type_register_static(&aspeed_soc_ast2500_type_info);
+static const TypeInfo aspeed_soc_ast2400_types[] = {
+ {
+ .name = TYPE_ASPEED2400_SOC,
+ .parent = TYPE_ASPEED_SOC,
+ .instance_init = aspeed_ast2400_soc_init,
+ .instance_size = sizeof(Aspeed2400SoCState),
+ .abstract = true,
+ }, {
+ .name = "ast2400-a1",
+ .parent = TYPE_ASPEED2400_SOC,
+ .class_init = aspeed_soc_ast2400_class_init,
+ }, {
+ .name = "ast2500-a1",
+ .parent = TYPE_ASPEED2400_SOC,
+ .class_init = aspeed_soc_ast2500_class_init,
+ },
};
-type_init(aspeed_soc_register_types);
+DEFINE_TYPES(aspeed_soc_ast2400_types)
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index a43f5d2a6f..b66f769d18 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -12,6 +12,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
+#include "hw/qdev-properties.h"
#include "hw/misc/unimp.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/char/serial.h"
@@ -112,3 +113,31 @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
memory_region_add_subregion_overlap(s->memory, addr,
sysbus_mmio_get_region(dev, 0), -1000);
}
+
+static Property aspeed_soc_properties[] = {
+ DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void aspeed_soc_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ device_class_set_props(dc, aspeed_soc_properties);
+}
+
+static const TypeInfo aspeed_soc_types[] = {
+ {
+ .name = TYPE_ASPEED_SOC,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(AspeedSoCState),
+ .class_size = sizeof(AspeedSoCClass),
+ .class_init = aspeed_soc_class_init,
+ .abstract = true,
+ },
+};
+
+DEFINE_TYPES(aspeed_soc_types)
--
2.41.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 07/11] hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC
2023-10-24 16:24 ` [PATCH 07/11] hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC Philippe Mathieu-Daudé
@ 2023-10-25 7:10 ` Cédric Le Goater
0 siblings, 0 replies; 25+ messages in thread
From: Cédric Le Goater @ 2023-10-25 7:10 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm
On 10/24/23 18:24, Philippe Mathieu-Daudé wrote:
> TYPE_ASPEED2400_SOC inherits from TYPE_ASPEED_SOC.
> In few commits we'll add more fields, but to keep
> review process simple, don't add any yet.
>
> TYPE_ASPEED_SOC is common to various Aspeed SoCs,
> define it in aspeed_soc_common.c.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> include/hw/arm/aspeed_soc.h | 7 +++++
> hw/arm/aspeed_soc.c | 61 +++++++++++--------------------------
> hw/arm/aspeed_soc_common.c | 29 ++++++++++++++++++
> 3 files changed, 53 insertions(+), 44 deletions(-)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 103b1598f6..ee7926b81c 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -101,6 +101,13 @@ struct AspeedSoCState {
> #define TYPE_ASPEED_SOC "aspeed-soc"
> OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
>
> +struct Aspeed2400SoCState {
> + AspeedSoCState parent;
> +};
> +
> +#define TYPE_ASPEED2400_SOC "aspeed2400-soc"
> +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
> +
> struct Aspeed2600SoCState {
> AspeedSoCState parent;
> };
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index 191276a320..dfb97f6dbd 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -497,29 +497,6 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
> aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
> }
> -static Property aspeed_soc_properties[] = {
> - DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
> - MemoryRegion *),
> - DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
> - MemoryRegion *),
> - DEFINE_PROP_END_OF_LIST(),
> -};
> -
> -static void aspeed_soc_class_init(ObjectClass *oc, void *data)
> -{
> - DeviceClass *dc = DEVICE_CLASS(oc);
> -
> - device_class_set_props(dc, aspeed_soc_properties);
> -}
> -
> -static const TypeInfo aspeed_soc_type_info = {
> - .name = TYPE_ASPEED_SOC,
> - .parent = TYPE_DEVICE,
> - .instance_size = sizeof(AspeedSoCState),
> - .class_size = sizeof(AspeedSoCClass),
> - .class_init = aspeed_soc_class_init,
> - .abstract = true,
> -};
>
> static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
> {
> @@ -545,14 +522,6 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
> sc->get_irq = aspeed_soc_ast2400_get_irq;
> }
>
> -static const TypeInfo aspeed_soc_ast2400_type_info = {
> - .name = "ast2400-a1",
> - .parent = TYPE_ASPEED_SOC,
> - .instance_init = aspeed_ast2400_soc_init,
> - .instance_size = sizeof(AspeedSoCState),
> - .class_init = aspeed_soc_ast2400_class_init,
> -};
> -
> static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
> {
> AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
> @@ -577,18 +546,22 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
> sc->get_irq = aspeed_soc_ast2400_get_irq;
> }
>
> -static const TypeInfo aspeed_soc_ast2500_type_info = {
> - .name = "ast2500-a1",
> - .parent = TYPE_ASPEED_SOC,
> - .instance_init = aspeed_ast2400_soc_init,
> - .instance_size = sizeof(AspeedSoCState),
> - .class_init = aspeed_soc_ast2500_class_init,
> -};
> -static void aspeed_soc_register_types(void)
> -{
> - type_register_static(&aspeed_soc_type_info);
> - type_register_static(&aspeed_soc_ast2400_type_info);
> - type_register_static(&aspeed_soc_ast2500_type_info);
> +static const TypeInfo aspeed_soc_ast2400_types[] = {
> + {
> + .name = TYPE_ASPEED2400_SOC,
> + .parent = TYPE_ASPEED_SOC,
> + .instance_init = aspeed_ast2400_soc_init,
> + .instance_size = sizeof(Aspeed2400SoCState),
> + .abstract = true,
> + }, {
> + .name = "ast2400-a1",
> + .parent = TYPE_ASPEED2400_SOC,
> + .class_init = aspeed_soc_ast2400_class_init,
> + }, {
> + .name = "ast2500-a1",
> + .parent = TYPE_ASPEED2400_SOC,
> + .class_init = aspeed_soc_ast2500_class_init,
> + },
> };
>
> -type_init(aspeed_soc_register_types);
> +DEFINE_TYPES(aspeed_soc_ast2400_types)
> diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
> index a43f5d2a6f..b66f769d18 100644
> --- a/hw/arm/aspeed_soc_common.c
> +++ b/hw/arm/aspeed_soc_common.c
> @@ -12,6 +12,7 @@
>
> #include "qemu/osdep.h"
> #include "qapi/error.h"
> +#include "hw/qdev-properties.h"
> #include "hw/misc/unimp.h"
> #include "hw/arm/aspeed_soc.h"
> #include "hw/char/serial.h"
> @@ -112,3 +113,31 @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
> memory_region_add_subregion_overlap(s->memory, addr,
> sysbus_mmio_get_region(dev, 0), -1000);
> }
> +
> +static Property aspeed_soc_properties[] = {
> + DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
> + MemoryRegion *),
> + DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
> + MemoryRegion *),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void aspeed_soc_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + device_class_set_props(dc, aspeed_soc_properties);
> +}
> +
> +static const TypeInfo aspeed_soc_types[] = {
> + {
> + .name = TYPE_ASPEED_SOC,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(AspeedSoCState),
> + .class_size = sizeof(AspeedSoCClass),
> + .class_init = aspeed_soc_class_init,
> + .abstract = true,
> + },
> +};
> +
> +DEFINE_TYPES(aspeed_soc_types)
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 08/11] hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize
2023-10-24 16:24 [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0 Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2023-10-24 16:24 ` [PATCH 07/11] hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC Philippe Mathieu-Daudé
@ 2023-10-24 16:24 ` Philippe Mathieu-Daudé
2023-10-25 7:11 ` Cédric Le Goater
2023-10-24 16:24 ` [PATCH 09/11] hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState Philippe Mathieu-Daudé
` (4 subsequent siblings)
12 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-24 16:24 UTC (permalink / raw)
To: qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm,
Cédric Le Goater, Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/aspeed_soc_common.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index b66f769d18..828f61093b 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -114,6 +114,16 @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
sysbus_mmio_get_region(dev, 0), -1000);
}
+static void aspeed_soc_realize(DeviceState *dev, Error **errp)
+{
+ AspeedSoCState *s = ASPEED_SOC(dev);
+
+ if (!s->memory) {
+ error_setg(errp, "'memory' link is not set");
+ return;
+ }
+}
+
static Property aspeed_soc_properties[] = {
DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *),
@@ -126,6 +136,7 @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
+ dc->realize = aspeed_soc_realize;
device_class_set_props(dc, aspeed_soc_properties);
}
--
2.41.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 08/11] hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize
2023-10-24 16:24 ` [PATCH 08/11] hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize Philippe Mathieu-Daudé
@ 2023-10-25 7:11 ` Cédric Le Goater
0 siblings, 0 replies; 25+ messages in thread
From: Cédric Le Goater @ 2023-10-25 7:11 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm
On 10/24/23 18:24, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed_soc_common.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
> index b66f769d18..828f61093b 100644
> --- a/hw/arm/aspeed_soc_common.c
> +++ b/hw/arm/aspeed_soc_common.c
> @@ -114,6 +114,16 @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
> sysbus_mmio_get_region(dev, 0), -1000);
> }
>
> +static void aspeed_soc_realize(DeviceState *dev, Error **errp)
> +{
> + AspeedSoCState *s = ASPEED_SOC(dev);
> +
> + if (!s->memory) {
> + error_setg(errp, "'memory' link is not set");
> + return;
> + }
> +}
> +
> static Property aspeed_soc_properties[] = {
> DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
> MemoryRegion *),
> @@ -126,6 +136,7 @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
>
> + dc->realize = aspeed_soc_realize;
> device_class_set_props(dc, aspeed_soc_properties);
> }
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 09/11] hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState
2023-10-24 16:24 [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0 Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2023-10-24 16:24 ` [PATCH 08/11] hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize Philippe Mathieu-Daudé
@ 2023-10-24 16:24 ` Philippe Mathieu-Daudé
2023-10-25 7:12 ` Cédric Le Goater
2023-10-24 16:24 ` [PATCH 10/11] hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState Philippe Mathieu-Daudé
` (3 subsequent siblings)
12 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-24 16:24 UTC (permalink / raw)
To: qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm,
Cédric Le Goater, Philippe Mathieu-Daudé
The v7-M core is specific to the Aspeed 10x0 series,
remove it from the common AspeedSoCState.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/arm/aspeed_soc.h | 5 ++---
hw/arm/aspeed_ast10x0.c | 27 +++++++++++++++------------
hw/arm/fby35.c | 13 ++++++++-----
3 files changed, 25 insertions(+), 20 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index ee7926b81c..2118a441f7 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -47,13 +47,10 @@
#define ASPEED_JTAG_NUM 2
struct AspeedSoCState {
- /*< private >*/
DeviceState parent;
- /*< public >*/
ARMCPU cpu[ASPEED_CPUS_NUM];
A15MPPrivState a7mpcore;
- ARMv7MState armv7m;
MemoryRegion *memory;
MemoryRegion *dram_mr;
MemoryRegion dram_container;
@@ -117,6 +114,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
struct Aspeed10x0SoCState {
AspeedSoCState parent;
+
+ ARMv7MState armv7m;
};
#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 1c15bf422f..8becb146a8 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -101,13 +101,15 @@ static const int aspeed_soc_ast1030_irqmap[] = {
static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
{
+ Aspeed10x0SoCState *a = ASPEED10X0_SOC(s);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]);
+ return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
}
static void aspeed_soc_ast1030_init(Object *obj)
{
+ Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj);
AspeedSoCState *s = ASPEED_SOC(obj);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
char socname[8];
@@ -118,7 +120,7 @@ static void aspeed_soc_ast1030_init(Object *obj)
g_assert_not_reached();
}
- object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
+ object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
@@ -185,6 +187,7 @@ static void aspeed_soc_ast1030_init(Object *obj)
static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
{
+ Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
AspeedSoCState *s = ASPEED_SOC(dev_soc);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
DeviceState *armv7m;
@@ -206,17 +209,17 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
0x40000);
/* AST1030 CPU Core */
- armv7m = DEVICE(&s->armv7m);
+ armv7m = DEVICE(&a->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 256);
qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
- object_property_set_link(OBJECT(&s->armv7m), "memory",
+ object_property_set_link(OBJECT(&a->armv7m), "memory",
OBJECT(s->memory), &error_abort);
- sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
/* Internal SRAM */
sram_name = g_strdup_printf("aspeed.sram.%d",
- CPU(s->armv7m.cpu)->cpu_index);
+ CPU(a->armv7m.cpu)->cpu_index);
memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
if (err != NULL) {
error_propagate(errp, err);
@@ -249,7 +252,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
}
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
- qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
sc->irqmap[ASPEED_DEV_I2C] + i);
/* The AST1030 I2C controller has one IRQ per bus. */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
@@ -261,7 +264,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
}
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
- qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
sc->irqmap[ASPEED_DEV_I3C] + i);
/* The AST1030 I3C controller has one IRQ per bus. */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
@@ -290,19 +293,19 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
* On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
*/
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
- qdev_get_gpio_in(DEVICE(&s->armv7m),
+ qdev_get_gpio_in(DEVICE(&a->armv7m),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
- qdev_get_gpio_in(DEVICE(&s->armv7m),
+ qdev_get_gpio_in(DEVICE(&a->armv7m),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
- qdev_get_gpio_in(DEVICE(&s->armv7m),
+ qdev_get_gpio_in(DEVICE(&a->armv7m),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
- qdev_get_gpio_in(DEVICE(&s->armv7m),
+ qdev_get_gpio_in(DEVICE(&a->armv7m),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
/* UART */
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index f2ff6c1abf..c8bc75d870 100644
--- a/hw/arm/fby35.c
+++ b/hw/arm/fby35.c
@@ -28,7 +28,7 @@ struct Fby35State {
Clock *bic_sysclk;
AspeedSoCState bmc;
- AspeedSoCState bic;
+ Aspeed10x0SoCState bic;
bool mmio_exec;
};
@@ -114,10 +114,13 @@ static void fby35_bmc_init(Fby35State *s)
static void fby35_bic_init(Fby35State *s)
{
+ AspeedSoCState *soc;
+
s->bic_sysclk = clock_new(OBJECT(s), "SYSCLK");
clock_set_hz(s->bic_sysclk, 200000000ULL);
object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1");
+ soc = ASPEED_SOC(&s->bic);
memory_region_init(&s->bic_memory, OBJECT(&s->bic), "bic-memory",
UINT64_MAX);
@@ -125,12 +128,12 @@ static void fby35_bic_init(Fby35State *s)
qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk);
object_property_set_link(OBJECT(&s->bic), "memory", OBJECT(&s->bic_memory),
&error_abort);
- aspeed_soc_uart_set_chr(&s->bic, ASPEED_DEV_UART5, serial_hd(1));
+ aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(1));
qdev_realize(DEVICE(&s->bic), NULL, &error_abort);
- aspeed_board_init_flashes(&s->bic.fmc, "sst25vf032b", 2, 2);
- aspeed_board_init_flashes(&s->bic.spi[0], "sst25vf032b", 2, 4);
- aspeed_board_init_flashes(&s->bic.spi[1], "sst25vf032b", 2, 6);
+ aspeed_board_init_flashes(&soc->fmc, "sst25vf032b", 2, 2);
+ aspeed_board_init_flashes(&soc->spi[0], "sst25vf032b", 2, 4);
+ aspeed_board_init_flashes(&soc->spi[1], "sst25vf032b", 2, 6);
}
static void fby35_init(MachineState *machine)
--
2.41.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 09/11] hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState
2023-10-24 16:24 ` [PATCH 09/11] hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState Philippe Mathieu-Daudé
@ 2023-10-25 7:12 ` Cédric Le Goater
0 siblings, 0 replies; 25+ messages in thread
From: Cédric Le Goater @ 2023-10-25 7:12 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm
On 10/24/23 18:24, Philippe Mathieu-Daudé wrote:
> The v7-M core is specific to the Aspeed 10x0 series,
> remove it from the common AspeedSoCState.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> include/hw/arm/aspeed_soc.h | 5 ++---
> hw/arm/aspeed_ast10x0.c | 27 +++++++++++++++------------
> hw/arm/fby35.c | 13 ++++++++-----
> 3 files changed, 25 insertions(+), 20 deletions(-)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index ee7926b81c..2118a441f7 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -47,13 +47,10 @@
> #define ASPEED_JTAG_NUM 2
>
> struct AspeedSoCState {
> - /*< private >*/
> DeviceState parent;
>
> - /*< public >*/
> ARMCPU cpu[ASPEED_CPUS_NUM];
> A15MPPrivState a7mpcore;
> - ARMv7MState armv7m;
> MemoryRegion *memory;
> MemoryRegion *dram_mr;
> MemoryRegion dram_container;
> @@ -117,6 +114,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
>
> struct Aspeed10x0SoCState {
> AspeedSoCState parent;
> +
> + ARMv7MState armv7m;
> };
>
> #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
> diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
> index 1c15bf422f..8becb146a8 100644
> --- a/hw/arm/aspeed_ast10x0.c
> +++ b/hw/arm/aspeed_ast10x0.c
> @@ -101,13 +101,15 @@ static const int aspeed_soc_ast1030_irqmap[] = {
>
> static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
> {
> + Aspeed10x0SoCState *a = ASPEED10X0_SOC(s);
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
>
> - return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]);
> + return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
> }
>
> static void aspeed_soc_ast1030_init(Object *obj)
> {
> + Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj);
> AspeedSoCState *s = ASPEED_SOC(obj);
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> char socname[8];
> @@ -118,7 +120,7 @@ static void aspeed_soc_ast1030_init(Object *obj)
> g_assert_not_reached();
> }
>
> - object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
> + object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
>
> s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
>
> @@ -185,6 +187,7 @@ static void aspeed_soc_ast1030_init(Object *obj)
>
> static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
> {
> + Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
> AspeedSoCState *s = ASPEED_SOC(dev_soc);
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> DeviceState *armv7m;
> @@ -206,17 +209,17 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
> 0x40000);
>
> /* AST1030 CPU Core */
> - armv7m = DEVICE(&s->armv7m);
> + armv7m = DEVICE(&a->armv7m);
> qdev_prop_set_uint32(armv7m, "num-irq", 256);
> qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
> qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
> - object_property_set_link(OBJECT(&s->armv7m), "memory",
> + object_property_set_link(OBJECT(&a->armv7m), "memory",
> OBJECT(s->memory), &error_abort);
> - sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
> + sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
>
> /* Internal SRAM */
> sram_name = g_strdup_printf("aspeed.sram.%d",
> - CPU(s->armv7m.cpu)->cpu_index);
> + CPU(a->armv7m.cpu)->cpu_index);
> memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
> if (err != NULL) {
> error_propagate(errp, err);
> @@ -249,7 +252,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
> }
> aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
> for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
> - qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
> + qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
> sc->irqmap[ASPEED_DEV_I2C] + i);
> /* The AST1030 I2C controller has one IRQ per bus. */
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
> @@ -261,7 +264,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
> }
> aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
> for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
> - qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
> + qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
> sc->irqmap[ASPEED_DEV_I3C] + i);
> /* The AST1030 I3C controller has one IRQ per bus. */
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
> @@ -290,19 +293,19 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
> * On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
> */
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
> - qdev_get_gpio_in(DEVICE(&s->armv7m),
> + qdev_get_gpio_in(DEVICE(&a->armv7m),
> sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
>
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
> - qdev_get_gpio_in(DEVICE(&s->armv7m),
> + qdev_get_gpio_in(DEVICE(&a->armv7m),
> sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
>
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
> - qdev_get_gpio_in(DEVICE(&s->armv7m),
> + qdev_get_gpio_in(DEVICE(&a->armv7m),
> sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
>
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
> - qdev_get_gpio_in(DEVICE(&s->armv7m),
> + qdev_get_gpio_in(DEVICE(&a->armv7m),
> sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
>
> /* UART */
> diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
> index f2ff6c1abf..c8bc75d870 100644
> --- a/hw/arm/fby35.c
> +++ b/hw/arm/fby35.c
> @@ -28,7 +28,7 @@ struct Fby35State {
> Clock *bic_sysclk;
>
> AspeedSoCState bmc;
> - AspeedSoCState bic;
> + Aspeed10x0SoCState bic;
>
> bool mmio_exec;
> };
> @@ -114,10 +114,13 @@ static void fby35_bmc_init(Fby35State *s)
>
> static void fby35_bic_init(Fby35State *s)
> {
> + AspeedSoCState *soc;
> +
> s->bic_sysclk = clock_new(OBJECT(s), "SYSCLK");
> clock_set_hz(s->bic_sysclk, 200000000ULL);
>
> object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1");
> + soc = ASPEED_SOC(&s->bic);
>
> memory_region_init(&s->bic_memory, OBJECT(&s->bic), "bic-memory",
> UINT64_MAX);
> @@ -125,12 +128,12 @@ static void fby35_bic_init(Fby35State *s)
> qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk);
> object_property_set_link(OBJECT(&s->bic), "memory", OBJECT(&s->bic_memory),
> &error_abort);
> - aspeed_soc_uart_set_chr(&s->bic, ASPEED_DEV_UART5, serial_hd(1));
> + aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(1));
> qdev_realize(DEVICE(&s->bic), NULL, &error_abort);
>
> - aspeed_board_init_flashes(&s->bic.fmc, "sst25vf032b", 2, 2);
> - aspeed_board_init_flashes(&s->bic.spi[0], "sst25vf032b", 2, 4);
> - aspeed_board_init_flashes(&s->bic.spi[1], "sst25vf032b", 2, 6);
> + aspeed_board_init_flashes(&soc->fmc, "sst25vf032b", 2, 2);
> + aspeed_board_init_flashes(&soc->spi[0], "sst25vf032b", 2, 4);
> + aspeed_board_init_flashes(&soc->spi[1], "sst25vf032b", 2, 6);
> }
>
> static void fby35_init(MachineState *machine)
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 10/11] hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState
2023-10-24 16:24 [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0 Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2023-10-24 16:24 ` [PATCH 09/11] hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState Philippe Mathieu-Daudé
@ 2023-10-24 16:24 ` Philippe Mathieu-Daudé
2023-10-25 7:45 ` Cédric Le Goater
2023-10-24 16:24 ` [PATCH 11/11] hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState Philippe Mathieu-Daudé
` (2 subsequent siblings)
12 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-24 16:24 UTC (permalink / raw)
To: qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm,
Cédric Le Goater, Philippe Mathieu-Daudé
The v7-A cluster is specific to the Aspeed 2600 series,
remove it from the common AspeedSoCState.
The ARM cores belong to the MP cluster, but the array
is currently used by TYPE_ASPEED2600_SOC. We'll clean
that soon, but for now keep it in Aspeed2600SoCState.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/arm/aspeed_soc.h | 4 ++-
hw/arm/aspeed_ast2600.c | 49 ++++++++++++++++++++-----------------
hw/arm/fby35.c | 14 ++++++-----
3 files changed, 37 insertions(+), 30 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 2118a441f7..6f783138e1 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -50,7 +50,6 @@ struct AspeedSoCState {
DeviceState parent;
ARMCPU cpu[ASPEED_CPUS_NUM];
- A15MPPrivState a7mpcore;
MemoryRegion *memory;
MemoryRegion *dram_mr;
MemoryRegion dram_container;
@@ -107,6 +106,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
struct Aspeed2600SoCState {
AspeedSoCState parent;
+
+ A15MPPrivState a7mpcore;
+ ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
};
#define TYPE_ASPEED2600_SOC "aspeed2600-soc"
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 1ee460e56c..b965fbab5e 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -137,13 +137,15 @@ static const int aspeed_soc_ast2600_irqmap[] = {
static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
{
+ Aspeed2600SoCState *a = ASPEED2600_SOC(s);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]);
+ return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]);
}
static void aspeed_soc_ast2600_init(Object *obj)
{
+ Aspeed2600SoCState *a = ASPEED2600_SOC(obj);
AspeedSoCState *s = ASPEED_SOC(obj);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
int i;
@@ -155,7 +157,7 @@ static void aspeed_soc_ast2600_init(Object *obj)
}
for (i = 0; i < sc->num_cpus; i++) {
- object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
+ object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
}
snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
@@ -169,7 +171,7 @@ static void aspeed_soc_ast2600_init(Object *obj)
object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
"hw-prot-key");
- object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
+ object_initialize_child(obj, "a7mpcore", &a->a7mpcore,
TYPE_A15MPCORE_PRIV);
object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
@@ -277,6 +279,7 @@ static uint64_t aspeed_calc_affinity(int cpu)
static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
{
int i;
+ Aspeed2600SoCState *a = ASPEED2600_SOC(dev);
AspeedSoCState *s = ASPEED_SOC(dev);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
Error *err = NULL;
@@ -306,39 +309,39 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
/* CPU */
for (i = 0; i < sc->num_cpus; i++) {
if (sc->num_cpus > 1) {
- object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
+ object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar",
ASPEED_A7MPCORE_ADDR, &error_abort);
}
- object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
+ object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
aspeed_calc_affinity(i), &error_abort);
- object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
+ object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000,
&error_abort);
- object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
+ object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false,
&error_abort);
- object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false,
+ object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false,
&error_abort);
- object_property_set_link(OBJECT(&s->cpu[i]), "memory",
+ object_property_set_link(OBJECT(&a->cpu[i]), "memory",
OBJECT(s->memory), &error_abort);
- if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
+ if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
return;
}
}
/* A7MPCORE */
- object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
+ object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus,
&error_abort);
- object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
+ object_property_set_int(OBJECT(&a->a7mpcore), "num-irq",
ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
&error_abort);
- sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
+ sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort);
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
for (i = 0; i < sc->num_cpus; i++) {
- SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
- DeviceState *d = DEVICE(&s->cpu[i]);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore);
+ DeviceState *d = DEVICE(&a->cpu[i]);
irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
sysbus_connect_irq(sbd, i, irq);
@@ -351,7 +354,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
}
/* SRAM */
- sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
+ sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
if (err) {
error_propagate(errp, err);
@@ -413,7 +416,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
}
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
sc->irqmap[ASPEED_DEV_I2C] + i);
/* The AST2600 I2C controller has one IRQ per bus. */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
@@ -579,19 +582,19 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
* offset 0.
*/
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ qdev_get_gpio_in(DEVICE(&a->a7mpcore),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ qdev_get_gpio_in(DEVICE(&a->a7mpcore),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ qdev_get_gpio_in(DEVICE(&a->a7mpcore),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ qdev_get_gpio_in(DEVICE(&a->a7mpcore),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
/* HACE */
@@ -611,7 +614,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
}
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
sc->irqmap[ASPEED_DEV_I3C] + i);
/* The AST2600 I3C controller has one IRQ per bus. */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index c8bc75d870..c9964bd283 100644
--- a/hw/arm/fby35.c
+++ b/hw/arm/fby35.c
@@ -27,7 +27,7 @@ struct Fby35State {
MemoryRegion bic_memory;
Clock *bic_sysclk;
- AspeedSoCState bmc;
+ Aspeed2600SoCState bmc;
Aspeed10x0SoCState bic;
bool mmio_exec;
@@ -70,7 +70,10 @@ static void fby35_bmc_write_boot_rom(DriveInfo *dinfo, MemoryRegion *mr,
static void fby35_bmc_init(Fby35State *s)
{
+ AspeedSoCState *soc;
+
object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3");
+ soc = ASPEED_SOC(&s->bmc);
memory_region_init(&s->bmc_memory, OBJECT(&s->bmc), "bmc-memory",
UINT64_MAX);
@@ -87,22 +90,21 @@ static void fby35_bmc_init(Fby35State *s)
&error_abort);
object_property_set_int(OBJECT(&s->bmc), "hw-strap2", 0x00000003,
&error_abort);
- aspeed_soc_uart_set_chr(&s->bmc, ASPEED_DEV_UART5, serial_hd(0));
+ aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(0));
qdev_realize(DEVICE(&s->bmc), NULL, &error_abort);
- aspeed_board_init_flashes(&s->bmc.fmc, "n25q00", 2, 0);
+ aspeed_board_init_flashes(&soc->fmc, "n25q00", 2, 0);
/* Install first FMC flash content as a boot rom. */
if (!s->mmio_exec) {
DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
if (mtd0) {
- AspeedSoCState *bmc = &s->bmc;
- uint64_t rom_size = memory_region_size(&bmc->spi_boot);
+ uint64_t rom_size = memory_region_size(&soc->spi_boot);
memory_region_init_rom(&s->bmc_boot_rom, NULL, "aspeed.boot_rom",
rom_size, &error_abort);
- memory_region_add_subregion_overlap(&bmc->spi_boot_container, 0,
+ memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
&s->bmc_boot_rom, 1);
fby35_bmc_write_boot_rom(mtd0, &s->bmc_boot_rom,
--
2.41.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 10/11] hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState
2023-10-24 16:24 ` [PATCH 10/11] hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState Philippe Mathieu-Daudé
@ 2023-10-25 7:45 ` Cédric Le Goater
0 siblings, 0 replies; 25+ messages in thread
From: Cédric Le Goater @ 2023-10-25 7:45 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm
On 10/24/23 18:24, Philippe Mathieu-Daudé wrote:
> The v7-A cluster is specific to the Aspeed 2600 series,
> remove it from the common AspeedSoCState.
>
> The ARM cores belong to the MP cluster, but the array
> is currently used by TYPE_ASPEED2600_SOC. We'll clean
> that soon, but for now keep it in Aspeed2600SoCState.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> include/hw/arm/aspeed_soc.h | 4 ++-
> hw/arm/aspeed_ast2600.c | 49 ++++++++++++++++++++-----------------
> hw/arm/fby35.c | 14 ++++++-----
> 3 files changed, 37 insertions(+), 30 deletions(-)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 2118a441f7..6f783138e1 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -50,7 +50,6 @@ struct AspeedSoCState {
> DeviceState parent;
>
> ARMCPU cpu[ASPEED_CPUS_NUM];
> - A15MPPrivState a7mpcore;
> MemoryRegion *memory;
> MemoryRegion *dram_mr;
> MemoryRegion dram_container;
> @@ -107,6 +106,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
>
> struct Aspeed2600SoCState {
> AspeedSoCState parent;
> +
> + A15MPPrivState a7mpcore;
> + ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
> };
>
> #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
> diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
> index 1ee460e56c..b965fbab5e 100644
> --- a/hw/arm/aspeed_ast2600.c
> +++ b/hw/arm/aspeed_ast2600.c
> @@ -137,13 +137,15 @@ static const int aspeed_soc_ast2600_irqmap[] = {
>
> static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
> {
> + Aspeed2600SoCState *a = ASPEED2600_SOC(s);
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
>
> - return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]);
> + return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]);
> }
>
> static void aspeed_soc_ast2600_init(Object *obj)
> {
> + Aspeed2600SoCState *a = ASPEED2600_SOC(obj);
> AspeedSoCState *s = ASPEED_SOC(obj);
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> int i;
> @@ -155,7 +157,7 @@ static void aspeed_soc_ast2600_init(Object *obj)
> }
>
> for (i = 0; i < sc->num_cpus; i++) {
> - object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
> + object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
> }
>
> snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
> @@ -169,7 +171,7 @@ static void aspeed_soc_ast2600_init(Object *obj)
> object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
> "hw-prot-key");
>
> - object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
> + object_initialize_child(obj, "a7mpcore", &a->a7mpcore,
> TYPE_A15MPCORE_PRIV);
>
> object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
> @@ -277,6 +279,7 @@ static uint64_t aspeed_calc_affinity(int cpu)
> static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
> {
> int i;
> + Aspeed2600SoCState *a = ASPEED2600_SOC(dev);
> AspeedSoCState *s = ASPEED_SOC(dev);
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> Error *err = NULL;
> @@ -306,39 +309,39 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
> /* CPU */
> for (i = 0; i < sc->num_cpus; i++) {
> if (sc->num_cpus > 1) {
> - object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
> + object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar",
> ASPEED_A7MPCORE_ADDR, &error_abort);
> }
> - object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
> + object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
> aspeed_calc_affinity(i), &error_abort);
>
> - object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
> + object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000,
> &error_abort);
> - object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
> + object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false,
> &error_abort);
> - object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false,
> + object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false,
> &error_abort);
> - object_property_set_link(OBJECT(&s->cpu[i]), "memory",
> + object_property_set_link(OBJECT(&a->cpu[i]), "memory",
> OBJECT(s->memory), &error_abort);
>
> - if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
> + if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
> return;
> }
> }
>
> /* A7MPCORE */
> - object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
> + object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus,
> &error_abort);
> - object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
> + object_property_set_int(OBJECT(&a->a7mpcore), "num-irq",
> ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
> &error_abort);
>
> - sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
> - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
> + sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort);
> + aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
>
> for (i = 0; i < sc->num_cpus; i++) {
> - SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
> - DeviceState *d = DEVICE(&s->cpu[i]);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore);
> + DeviceState *d = DEVICE(&a->cpu[i]);
>
> irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
> sysbus_connect_irq(sbd, i, irq);
> @@ -351,7 +354,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
> }
>
> /* SRAM */
> - sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
> + sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
> memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
> if (err) {
> error_propagate(errp, err);
> @@ -413,7 +416,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
> }
> aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
> for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
> - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
> + irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
> sc->irqmap[ASPEED_DEV_I2C] + i);
> /* The AST2600 I2C controller has one IRQ per bus. */
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
> @@ -579,19 +582,19 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
> * offset 0.
> */
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
> - qdev_get_gpio_in(DEVICE(&s->a7mpcore),
> + qdev_get_gpio_in(DEVICE(&a->a7mpcore),
> sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
>
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
> - qdev_get_gpio_in(DEVICE(&s->a7mpcore),
> + qdev_get_gpio_in(DEVICE(&a->a7mpcore),
> sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
>
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
> - qdev_get_gpio_in(DEVICE(&s->a7mpcore),
> + qdev_get_gpio_in(DEVICE(&a->a7mpcore),
> sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
>
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
> - qdev_get_gpio_in(DEVICE(&s->a7mpcore),
> + qdev_get_gpio_in(DEVICE(&a->a7mpcore),
> sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
>
> /* HACE */
> @@ -611,7 +614,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
> }
> aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
> for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
> - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
> + irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
> sc->irqmap[ASPEED_DEV_I3C] + i);
> /* The AST2600 I3C controller has one IRQ per bus. */
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
> diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
> index c8bc75d870..c9964bd283 100644
> --- a/hw/arm/fby35.c
> +++ b/hw/arm/fby35.c
> @@ -27,7 +27,7 @@ struct Fby35State {
> MemoryRegion bic_memory;
> Clock *bic_sysclk;
>
> - AspeedSoCState bmc;
> + Aspeed2600SoCState bmc;
> Aspeed10x0SoCState bic;
>
> bool mmio_exec;
> @@ -70,7 +70,10 @@ static void fby35_bmc_write_boot_rom(DriveInfo *dinfo, MemoryRegion *mr,
>
> static void fby35_bmc_init(Fby35State *s)
> {
> + AspeedSoCState *soc;
> +
> object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3");
> + soc = ASPEED_SOC(&s->bmc);
>
> memory_region_init(&s->bmc_memory, OBJECT(&s->bmc), "bmc-memory",
> UINT64_MAX);
> @@ -87,22 +90,21 @@ static void fby35_bmc_init(Fby35State *s)
> &error_abort);
> object_property_set_int(OBJECT(&s->bmc), "hw-strap2", 0x00000003,
> &error_abort);
> - aspeed_soc_uart_set_chr(&s->bmc, ASPEED_DEV_UART5, serial_hd(0));
> + aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(0));
> qdev_realize(DEVICE(&s->bmc), NULL, &error_abort);
>
> - aspeed_board_init_flashes(&s->bmc.fmc, "n25q00", 2, 0);
> + aspeed_board_init_flashes(&soc->fmc, "n25q00", 2, 0);
>
> /* Install first FMC flash content as a boot rom. */
> if (!s->mmio_exec) {
> DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
>
> if (mtd0) {
> - AspeedSoCState *bmc = &s->bmc;
> - uint64_t rom_size = memory_region_size(&bmc->spi_boot);
> + uint64_t rom_size = memory_region_size(&soc->spi_boot);
>
> memory_region_init_rom(&s->bmc_boot_rom, NULL, "aspeed.boot_rom",
> rom_size, &error_abort);
> - memory_region_add_subregion_overlap(&bmc->spi_boot_container, 0,
> + memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
> &s->bmc_boot_rom, 1);
>
> fby35_bmc_write_boot_rom(mtd0, &s->bmc_boot_rom,
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 11/11] hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState
2023-10-24 16:24 [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0 Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2023-10-24 16:24 ` [PATCH 10/11] hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState Philippe Mathieu-Daudé
@ 2023-10-24 16:24 ` Philippe Mathieu-Daudé
2023-10-25 7:45 ` Cédric Le Goater
2023-10-25 9:17 ` [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0 Philippe Mathieu-Daudé
2023-10-25 13:01 ` Philippe Mathieu-Daudé
12 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-24 16:24 UTC (permalink / raw)
To: qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm,
Cédric Le Goater, Philippe Mathieu-Daudé
The ARM array and VIC peripheral are only used by the
2400 series, remove them from the common AspeedSoCState.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/arm/aspeed_soc.h | 5 +++--
hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 27 +++++++++++++----------
hw/arm/meson.build | 2 +-
3 files changed, 19 insertions(+), 15 deletions(-)
rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (95%)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 6f783138e1..cb832bc1ee 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -49,14 +49,12 @@
struct AspeedSoCState {
DeviceState parent;
- ARMCPU cpu[ASPEED_CPUS_NUM];
MemoryRegion *memory;
MemoryRegion *dram_mr;
MemoryRegion dram_container;
MemoryRegion sram;
MemoryRegion spi_boot_container;
MemoryRegion spi_boot;
- AspeedVICState vic;
AspeedRtcState rtc;
AspeedTimerCtrlState timerctrl;
AspeedI2CState i2c;
@@ -99,6 +97,9 @@ OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
struct Aspeed2400SoCState {
AspeedSoCState parent;
+
+ ARMCPU cpu[ASPEED_CPUS_NUM];
+ AspeedVICState vic;
};
#define TYPE_ASPEED2400_SOC "aspeed2400-soc"
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_ast2400.c
similarity index 95%
rename from hw/arm/aspeed_soc.c
rename to hw/arm/aspeed_ast2400.c
index dfb97f6dbd..a4334c81b8 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -135,13 +135,15 @@ static const int aspeed_soc_ast2400_irqmap[] = {
static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
{
+ Aspeed2400SoCState *a = ASPEED2400_SOC(s);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]);
+ return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]);
}
static void aspeed_ast2400_soc_init(Object *obj)
{
+ Aspeed2400SoCState *a = ASPEED2400_SOC(obj);
AspeedSoCState *s = ASPEED_SOC(obj);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
int i;
@@ -153,7 +155,7 @@ static void aspeed_ast2400_soc_init(Object *obj)
}
for (i = 0; i < sc->num_cpus; i++) {
- object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
+ object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
}
snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
@@ -167,7 +169,7 @@ static void aspeed_ast2400_soc_init(Object *obj)
object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
"hw-prot-key");
- object_initialize_child(obj, "vic", &s->vic, TYPE_ASPEED_VIC);
+ object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC);
object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
@@ -242,6 +244,7 @@ static void aspeed_ast2400_soc_init(Object *obj)
static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
{
int i;
+ Aspeed2400SoCState *a = ASPEED2400_SOC(dev);
AspeedSoCState *s = ASPEED_SOC(dev);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
Error *err = NULL;
@@ -264,15 +267,15 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
/* CPU */
for (i = 0; i < sc->num_cpus; i++) {
- object_property_set_link(OBJECT(&s->cpu[i]), "memory",
+ object_property_set_link(OBJECT(&a->cpu[i]), "memory",
OBJECT(s->memory), &error_abort);
- if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
+ if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
return;
}
}
/* SRAM */
- sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
+ sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
if (err) {
error_propagate(errp, err);
@@ -288,14 +291,14 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
/* VIC */
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->vic), errp)) {
+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
- qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
- qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0,
+ qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1,
+ qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ));
/* RTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 42e7aa36f3..68245d3ad1 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -48,9 +48,9 @@ arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'
arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
- 'aspeed_soc.c',
'aspeed.c',
'aspeed_soc_common.c',
+ 'aspeed_ast2400.c',
'aspeed_ast2600.c',
'aspeed_ast10x0.c',
'aspeed_eeprom.c',
--
2.41.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 11/11] hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState
2023-10-24 16:24 ` [PATCH 11/11] hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState Philippe Mathieu-Daudé
@ 2023-10-25 7:45 ` Cédric Le Goater
0 siblings, 0 replies; 25+ messages in thread
From: Cédric Le Goater @ 2023-10-25 7:45 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm
On 10/24/23 18:24, Philippe Mathieu-Daudé wrote:
> The ARM array and VIC peripheral are only used by the
> 2400 series, remove them from the common AspeedSoCState.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> include/hw/arm/aspeed_soc.h | 5 +++--
> hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 27 +++++++++++++----------
> hw/arm/meson.build | 2 +-
> 3 files changed, 19 insertions(+), 15 deletions(-)
> rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (95%)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 6f783138e1..cb832bc1ee 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -49,14 +49,12 @@
> struct AspeedSoCState {
> DeviceState parent;
>
> - ARMCPU cpu[ASPEED_CPUS_NUM];
> MemoryRegion *memory;
> MemoryRegion *dram_mr;
> MemoryRegion dram_container;
> MemoryRegion sram;
> MemoryRegion spi_boot_container;
> MemoryRegion spi_boot;
> - AspeedVICState vic;
> AspeedRtcState rtc;
> AspeedTimerCtrlState timerctrl;
> AspeedI2CState i2c;
> @@ -99,6 +97,9 @@ OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
>
> struct Aspeed2400SoCState {
> AspeedSoCState parent;
> +
> + ARMCPU cpu[ASPEED_CPUS_NUM];
> + AspeedVICState vic;
> };
>
> #define TYPE_ASPEED2400_SOC "aspeed2400-soc"
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_ast2400.c
> similarity index 95%
> rename from hw/arm/aspeed_soc.c
> rename to hw/arm/aspeed_ast2400.c
> index dfb97f6dbd..a4334c81b8 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_ast2400.c
> @@ -135,13 +135,15 @@ static const int aspeed_soc_ast2400_irqmap[] = {
>
> static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
> {
> + Aspeed2400SoCState *a = ASPEED2400_SOC(s);
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
>
> - return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]);
> + return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]);
> }
>
> static void aspeed_ast2400_soc_init(Object *obj)
> {
> + Aspeed2400SoCState *a = ASPEED2400_SOC(obj);
> AspeedSoCState *s = ASPEED_SOC(obj);
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> int i;
> @@ -153,7 +155,7 @@ static void aspeed_ast2400_soc_init(Object *obj)
> }
>
> for (i = 0; i < sc->num_cpus; i++) {
> - object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
> + object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
> }
>
> snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
> @@ -167,7 +169,7 @@ static void aspeed_ast2400_soc_init(Object *obj)
> object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
> "hw-prot-key");
>
> - object_initialize_child(obj, "vic", &s->vic, TYPE_ASPEED_VIC);
> + object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC);
>
> object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
>
> @@ -242,6 +244,7 @@ static void aspeed_ast2400_soc_init(Object *obj)
> static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
> {
> int i;
> + Aspeed2400SoCState *a = ASPEED2400_SOC(dev);
> AspeedSoCState *s = ASPEED_SOC(dev);
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> Error *err = NULL;
> @@ -264,15 +267,15 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
>
> /* CPU */
> for (i = 0; i < sc->num_cpus; i++) {
> - object_property_set_link(OBJECT(&s->cpu[i]), "memory",
> + object_property_set_link(OBJECT(&a->cpu[i]), "memory",
> OBJECT(s->memory), &error_abort);
> - if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
> + if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
> return;
> }
> }
>
> /* SRAM */
> - sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
> + sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
> memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
> if (err) {
> error_propagate(errp, err);
> @@ -288,14 +291,14 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
> aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
>
> /* VIC */
> - if (!sysbus_realize(SYS_BUS_DEVICE(&s->vic), errp)) {
> + if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) {
> return;
> }
> - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
> - sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
> - qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
> - sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
> - qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
> + aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0,
> + qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ));
> + sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1,
> + qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ));
>
> /* RTC */
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
> diff --git a/hw/arm/meson.build b/hw/arm/meson.build
> index 42e7aa36f3..68245d3ad1 100644
> --- a/hw/arm/meson.build
> +++ b/hw/arm/meson.build
> @@ -48,9 +48,9 @@ arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'
> arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
> arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
> arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
> - 'aspeed_soc.c',
> 'aspeed.c',
> 'aspeed_soc_common.c',
> + 'aspeed_ast2400.c',
> 'aspeed_ast2600.c',
> 'aspeed_ast10x0.c',
> 'aspeed_eeprom.c',
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0
2023-10-24 16:24 [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0 Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2023-10-24 16:24 ` [PATCH 11/11] hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState Philippe Mathieu-Daudé
@ 2023-10-25 9:17 ` Philippe Mathieu-Daudé
2023-10-25 13:01 ` Philippe Mathieu-Daudé
12 siblings, 0 replies; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-25 9:17 UTC (permalink / raw)
To: qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm,
Cédric Le Goater, Alex Bennée
On 24/10/23 18:24, Philippe Mathieu-Daudé wrote:
> Hi,
>
> This series is extracted for a bigger work.
>
> Cortex-A MP clusters (TYPE_A15MPCORE_PRIV) should create
> the ARM cores in its own state. Unfortunately we don't do
> it that way, and this model calls qemu_get_cpu().
>
> In order to remove the qemu_get_cpu() call there, we first
> need to rework some SoC users.
>
> This series rework the Aspeed SoC state, so it is clear
> what fields are really used by a SoC type (2400 / 2600 /
> 10x0). It will then be easier to have the MP cluster create
> the core instances.
Being a bit more verbose, as I was trying to explain to Cédric
on IRC.
The fby35 machine creates 2 SoCs:
static void fby35_init(MachineState *machine)
{
Fby35State *s = FBY35(machine);
fby35_bmc_init(s);
fby35_bic_init(s);
}
- bmc is Aspeed2600 (A7 MPCORE)
- bic is Aspeed10x0 (M7)
If we were to create the bic before the bmc, as:
static void fby35_init(MachineState *machine)
{
Fby35State *s = FBY35(machine);
fby35_bic_init(s);
fby35_bmc_init(s);
}
then the MPCORE misbehave as it calls qemu_get_cpu(0) which
returns the M7 from the bic.
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0
2023-10-24 16:24 [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0 Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2023-10-25 9:17 ` [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0 Philippe Mathieu-Daudé
@ 2023-10-25 13:01 ` Philippe Mathieu-Daudé
12 siblings, 0 replies; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-25 13:01 UTC (permalink / raw)
To: qemu-devel
Cc: Joel Stanley, Peter Maydell, Andrew Jeffery, qemu-arm,
Cédric Le Goater
On 24/10/23 18:24, Philippe Mathieu-Daudé wrote:
> Philippe Mathieu-Daudé (11):
> hw/arm/aspeed: Extract code common to all boards to a common file
> hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific
> hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific
> hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field
> hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC
> hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC
> hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC
> hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize
> hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState
> hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState
> hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState
Updating other reviewers, this series has been queued in
Cédric's ASPEED queue.
^ permalink raw reply [flat|nested] 25+ messages in thread