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[97.90.106.114]) by smtp.gmail.com with ESMTPSA id 21-20020a170902c15500b00198ef76ce8dsm9013638plj.72.2023.03.21.09.10.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Mar 2023 09:10:56 -0700 (PDT) Message-ID: <609e4659-532f-0fe2-447a-f7deaa0824e5@linaro.org> Date: Tue, 21 Mar 2023 09:10:54 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change Content-Language: en-US To: fei2.wu@intel.com Cc: LIU Zhiwei , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , "open list:RISC-V TCG CPUs" , "open list:All patches CC here" References: <20230321063746.151107-1-fei2.wu@intel.com> From: Richard Henderson In-Reply-To: <20230321063746.151107-1-fei2.wu@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/20/23 23:37, fei2.wu@intel.com wrote: > From: Fei Wu > > Kernel needs to access user mode memory e.g. during syscalls, the window > is usually opened up for a very limited time through MSTATUS.SUM, the > overhead is too much if tlb_flush() gets called for every SUM change. > This patch saves addresses accessed when SUM=1, and flushs only these > pages when SUM changes to 0. If the buffer is not large enough to save > all the pages during SUM=1, it will fall back to tlb_flush when > necessary. > > The buffer size is set to 4 since in this MSTATUS.SUM open-up window, > most of the time kernel accesses 1 or 2 pages, it's very rare to see > more than 4 pages accessed. > > It's not necessary to save/restore these new added status, as > tlb_flush() is always called after restore. > > Result of 'pipe 10' from unixbench boosts from 223656 to 1327407. Many > other syscalls benefit a lot from this one too. This is not the correct approach. You should be making use of different softmmu indexes, similar to how ARM uses a separate index for PAN (privileged access never) mode. If I read the manual properly, PAN == !SUM. When you do this, you need no additional flushing. r~