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Tsirkin" Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Ani Sinha , Marcel Apfelbaum , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen References: <20230702094631.39111-1-akihiko.odaki@daynix.com> <20230702094631.39111-2-akihiko.odaki@daynix.com> <20230702064038-mutt-send-email-mst@kernel.org> From: Akihiko Odaki In-Reply-To: <20230702064038-mutt-send-email-mst@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: none client-ip=2001:4860:4864:20::2d; envelope-from=akihiko.odaki@daynix.com; helo=mail-oa1-x2d.google.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2023/07/02 19:40, Michael S. Tsirkin wrote: > On Sun, Jul 02, 2023 at 06:46:25PM +0900, Akihiko Odaki wrote: >> The ARI next function number field is undefined for VF so the PF should >> end the linked list formed with the field by specifying 0. >> >> This also changes the value of the field for VF; it seems to imply the >> value has some meaning if it differs from one of the PF, but it doesn't. >> >> Fixes: 2503461691 ("pcie: Add some SR/IOV API documentation in docs/pcie_sriov.txt") >> Signed-off-by: Akihiko Odaki >> --- >> docs/pcie_sriov.txt | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/docs/pcie_sriov.txt b/docs/pcie_sriov.txt >> index 7eff7f2703..2b7094dc47 100644 >> --- a/docs/pcie_sriov.txt >> +++ b/docs/pcie_sriov.txt >> @@ -48,7 +48,7 @@ setting up a BAR for a VF. >> ... >> int ret = pcie_endpoint_cap_init(d, 0x70); >> ... >> - pcie_ari_init(d, 0x100, 1); >> + pcie_ari_init(d, 0x100, 0); >> ... >> >> /* Add and initialize the SR/IOV capability */ >> @@ -78,7 +78,7 @@ setting up a BAR for a VF. >> ... >> int ret = pcie_endpoint_cap_init(d, 0x60); >> ... >> - pcie_ari_init(d, 0x100, 1); >> + pcie_ari_init(d, 0x100, 0); >> ... >> memory_region_init(mr, ... ) >> pcie_sriov_vf_register_bar(d, bar_nr, mr); > > > So now code does not match docs. Can you elaborate more?