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Mon, 14 Apr 2025 22:07:15 GMT Received: from smtprelay07.wdc07v.mail.ibm.com ([172.16.1.74]) by ppma11.dal12v.mail.ibm.com (PPS) with ESMTPS id 460571yv9n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 14 Apr 2025 22:07:15 +0000 Received: from smtpav03.wdc07v.mail.ibm.com (smtpav03.wdc07v.mail.ibm.com [10.39.53.230]) by smtprelay07.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 53EM7E7r32571950 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 14 Apr 2025 22:07:14 GMT Received: from smtpav03.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 08FAA5805A; Mon, 14 Apr 2025 22:07:14 +0000 (GMT) Received: from smtpav03.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C5DA258054; Mon, 14 Apr 2025 22:07:12 +0000 (GMT) Received: from [9.61.251.75] (unknown [9.61.251.75]) by smtpav03.wdc07v.mail.ibm.com (Postfix) with ESMTP; Mon, 14 Apr 2025 22:07:12 +0000 (GMT) Message-ID: <611df6cf-537e-40aa-b537-1797acb51ae0@linux.ibm.com> Date: Mon, 14 Apr 2025 15:07:07 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/3] include: Add a header to define host PCI MMIO functions To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, mjrosato@linux.ibm.com, schnelle@linux.ibm.com, stefanha@redhat.com, philmd@linaro.org, kwolf@redhat.com, hreitz@redhat.com, thuth@redhat.com, fam@euphon.net, alex.williamson@redhat.com References: <20250414213616.2675-1-alifm@linux.ibm.com> <20250414213616.2675-3-alifm@linux.ibm.com> Content-Language: en-US From: Farhan Ali In-Reply-To: <20250414213616.2675-3-alifm@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: yqDXUvZ4FTBlRp2tOJ2vvATWvCHKYVKY X-Proofpoint-ORIG-GUID: yqDXUvZ4FTBlRp2tOJ2vvATWvCHKYVKY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-14_08,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 clxscore=1015 mlxlogscore=999 adultscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 suspectscore=0 mlxscore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504140159 Received-SPF: pass client-ip=148.163.158.5; envelope-from=alifm@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/14/2025 2:36 PM, Farhan Ali wrote: > Add a generic API for host PCI MMIO reads/writes > (e.g. Linux VFIO BAR accesses). The functions access > little endian memory and returns the result in > host cpu endianness. > > Signed-off-by: Farhan Ali > --- > include/qemu/host-pci-mmio.h | 141 +++++++++++++++++++++++++++++++++++ > 1 file changed, 141 insertions(+) > create mode 100644 include/qemu/host-pci-mmio.h > > diff --git a/include/qemu/host-pci-mmio.h b/include/qemu/host-pci-mmio.h > new file mode 100644 > index 0000000000..de17d67e3a > --- /dev/null > +++ b/include/qemu/host-pci-mmio.h > @@ -0,0 +1,141 @@ > +/* > + * API for host PCI MMIO accesses (e.g. Linux VFIO BARs) > + * > + * Copyright 2025 IBM Corp. > + * Author(s): Farhan Ali > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#ifndef HOST_PCI_MMIO_H > +#define HOST_PCI_MMIO_H > + > +#include "qemu/bswap.h" > +#include "qemu/s390x_pci_mmio.h" > + > + > +static inline uint8_t host_pci_ldub_p(const void *ioaddr) > +{ > + uint8_t ret = 0; > +#ifdef __s390x__ > + ret = s390x_pci_mmio_read_8(ioaddr); > +#else Noticed a typo below, it should be ldub_p instead of ldub_he_p (didn't have any compiler errors). Will fix this, but will wait for some other feedback before sending a new revision. > + ret = ldub_he_p(ioaddr); > +#endif > + > + return ret; > +} > + > +static inline uint16_t host_pci_lduw_le_p(const void *ioaddr) > +{ > + uint16_t ret = 0; > +#ifdef __s390x__ > + ret = le16_to_cpu(s390x_pci_mmio_read_16(ioaddr)); > +#else > + ret = lduw_le_p(ioaddr); > +#endif > + > + return ret; > +} > + > +static inline uint32_t host_pci_ldl_le_p(const void *ioaddr) > +{ > + uint32_t ret = 0; > +#ifdef __s390x__ > + ret = le32_to_cpu(s390x_pci_mmio_read_32(ioaddr)); > +#else > + ret = (uint32_t)ldl_le_p(ioaddr); > +#endif > + > + return ret; > +} > + > +static inline uint64_t host_pci_ldq_le_p(const void *ioaddr) > +{ > + uint64_t ret = 0; > +#ifdef __s390x__ > + ret = le64_to_cpu(s390x_pci_mmio_read_64(ioaddr)); > +#else > + ret = ldq_le_p(ioaddr); > +#endif > + > + return ret; > +} > + > +static inline void host_pci_stb_le_p(void *ioaddr, uint8_t val) > +{ > + > +#ifdef __s390x__ > + s390x_pci_mmio_write_8(ioaddr, val); > +#else > + stb_p(ioaddr, val); > +#endif > +} > + > +static inline void host_pci_stw_le_p(void *ioaddr, uint16_t val) > +{ > + > +#ifdef __s390x__ > + s390x_pci_mmio_write_16(ioaddr, cpu_to_le16(val)); > +#else > + stw_le_p(ioaddr, val); > +#endif > +} > + > +static inline void host_pci_stl_le_p(void *ioaddr, uint32_t val) > +{ > + > +#ifdef __s390x__ > + s390x_pci_mmio_write_32(ioaddr, cpu_to_le32(val)); > +#else > + stl_le_p(ioaddr, val); > +#endif > +} > + > +static inline void host_pci_stq_le_p(void *ioaddr, uint64_t val) > +{ > + > +#ifdef __s390x__ > + s390x_pci_mmio_write_64(ioaddr, cpu_to_le64(val)); > +#else > + stq_le_p(ioaddr, val); > +#endif > +} > + > +static inline uint64_t host_pci_ldn_le_p(const void *ioaddr, int sz) > +{ > + switch (sz) { > + case 1: > + return host_pci_ldub_p(ioaddr); > + case 2: > + return host_pci_lduw_le_p(ioaddr); > + case 4: > + return host_pci_ldl_le_p(ioaddr); > + case 8: > + return host_pci_ldq_le_p(ioaddr); > + default: > + g_assert_not_reached(); > + } > +} > + > +static inline void host_pci_stn_le_p(void *ioaddr, int sz, uint64_t v) > +{ > + switch (sz) { > + case 1: > + host_pci_stb_le_p(ioaddr, v); > + break; > + case 2: > + host_pci_stw_le_p(ioaddr, v); > + break; > + case 4: > + host_pci_stl_le_p(ioaddr, v); > + break; > + case 8: > + host_pci_stq_le_p(ioaddr, v); > + break; > + default: > + g_assert_not_reached(); > + } > +} > + > +#endif