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[174.21.76.141]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac10e392asm16765105ad.78.2024.06.28.08.37.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 28 Jun 2024 08:37:23 -0700 (PDT) Message-ID: <61656f78-4f96-4212-b37e-3c77c937a3ea@linaro.org> Date: Fri, 28 Jun 2024 08:37:21 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/9] target/arm: Make vfp_get_fpscr() call vfp_get_{fpcr, fpsr} To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20240628142347.1283015-1-peter.maydell@linaro.org> <20240628142347.1283015-3-peter.maydell@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240628142347.1283015-3-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/28/24 07:23, Peter Maydell wrote: > In AArch32, the floating point control and status bits are all in a > single register, FPSCR. In AArch64, these were split into separate > FPCR and FPSR registers, but the bit layouts remained the same, with > no overlaps, so that you could construct an FPSCR value by ORing FPCR > and FPSR, or equivalently could produce FPSR and FPCR by masking an > FPSCR value. For QEMU's implementation, we opted to use masking to > produce FPSR and FPCR, because we started with an AArch32 > implementation of FPSCR. > > The addition of the (AArch64-only) FEAT_AFP adds new bits to the FPCR > which overlap with some bits in the FPSR. This means we'll no longer > be able to consider the FPSCR-encoded value as the primary one, but > instead need to treat FPSR/FPCR as the primary encoding and construct > the FPSCR from those. (This remains possible because the FEAT_AFP > bits in FPCR don't appear in the FPSCR.) > > As the first step in this refactoring, make vfp_get_fpscr() call > vfp_get_fpcr() and vfp_get_fpsr(), instead of the other way around. > > Note that vfp_get_fpcsr_from_host() returns only bits in the FPSR > (for the cumulative fp exception bits), so we can simply rename > it without needing to add a new function for getting FPCR bits. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 24 +++++++++++++++--------- > target/arm/vfp_helper.c | 34 ++++++++++++++++++++++------------ > 2 files changed, 37 insertions(+), 21 deletions(-) Reviewed-by: Richard Henderson r~