From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
QEMU Developers <qemu-devel@nongnu.org>,
"open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Bin Meng <bin.meng@windriver.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: Re: TCG op for 32 bit only cpu on qemu-riscv64
Date: Mon, 7 Jun 2021 08:52:46 -0700 [thread overview]
Message-ID: <618e9348-c420-b560-1f67-3608023985a7@linaro.org> (raw)
In-Reply-To: <97935519-42c8-71c8-3d87-30aa4cafc909@c-sky.com>
On 6/6/21 8:07 PM, LIU Zhiwei wrote:
> Hi Alistair,
>
> As I see, we are moving on to remove TARGET_RISCV64 macro.
>
> I have some questions:
>
> 1) Which tcg op should use when translate an instruction for 32bit cpu. The
> tcg_*_i64, tcg_*_i32 or tcg_*_tl?
You use *_tl, because that's the size of the field in CPURISCVState.
> 2) Do we should have a sign-extend 64 bit register(bit 31 as the sign bit) for
> 32 bit cpu?
If the value must be sign-extended for RV64, then leave it sign-extended for
RV32. There's no point in adding extra code to distinguish between them.
If the instruction does not exist for RV64, then you can probably leave the
high bits unspecified (sign, zero, or pure garbage).
r~
next prev parent reply other threads:[~2021-06-07 15:54 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-07 3:07 TCG op for 32 bit only cpu on qemu-riscv64 LIU Zhiwei
2021-06-07 6:22 ` Alistair Francis
2021-06-07 9:22 ` LIU Zhiwei
2021-06-07 15:59 ` Richard Henderson
2021-06-07 15:52 ` Richard Henderson [this message]
2021-06-10 1:43 ` LIU Zhiwei
2021-06-10 13:29 ` Richard Henderson
2021-06-11 2:33 ` LIU Zhiwei
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