qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Tao Tang <tangtao1634@phytium.com.cn>,
	qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Eric Auger <eric.auger@redhat.com>,
	Peter Maydell <peter.maydell@linaro.org>,
	Chen Baozi <chenbaozi@phytium.com.cn>
Subject: Re: [RFC 05/11] hw/arm/smmuv3: Support secure event queue and error handling
Date: Mon, 11 Aug 2025 12:41:03 +0200	[thread overview]
Message-ID: <61a78e65-4164-49a2-8ce4-d95730b10eaa@linaro.org> (raw)
In-Reply-To: <20250806151134.365755-6-tangtao1634@phytium.com.cn>

On 6/8/25 17:11, Tao Tang wrote:
> Following the implementation of the secure command queue, this commit
> introduces the infrastructure for reporting faults and events back to
> secure software.
> 
> The secure event queue is now enabled, serving as the primary mechanism
> for the SMMU to report translation faults and other architected events.
> 
> For more critical failures, such as an abort on an event queue write,
> the SMMU_S_GERROR registers are also added. Finally, SMMU_S_IRQ_CTRL
> is wired up to control interrupt notifications for both the event
> queue and these global errors.
> 
> Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn>
> ---
>   hw/arm/smmuv3-internal.h | 38 ++++++++++++++-----
>   hw/arm/smmuv3.c          | 82 +++++++++++++++++++++++++---------------
>   hw/arm/trace-events      |  2 +-
>   3 files changed, 81 insertions(+), 41 deletions(-)


> -static inline bool smmuv3_eventq_irq_enabled(SMMUv3State *s)
> +static inline bool smmuv3_eventq_irq_enabled(SMMUv3State *s, bool is_secure)
>   {
> -    return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, EVENTQ_IRQEN);
> +    if (is_secure) {
> +        return FIELD_EX32(s->secure_irq_ctrl, S_IRQ_CTRL, EVENTQ_IRQEN);
> +    } else {
> +        return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, EVENTQ_IRQEN);
> +    }
>   }

Or using bank as suggested in patch #1:

    static inline bool smmuv3_eventq_irq_enabled(SMMUv3State *s,
                                                 unsigned idx)
    {
        return FIELD_EX32(s->bank[idx].irq_ctrl, IRQ_CTRL, EVENTQ_IRQEN);
    }




  reply	other threads:[~2025-08-11 10:41 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-06 15:11 [RFC 00/11] hw/arm/smmuv3: Add initial support for Secure State Tao Tang
2025-08-06 15:11 ` [RFC 01/11] hw/arm/smmuv3: Introduce secure registers and commands Tao Tang
2025-08-11 10:22   ` Philippe Mathieu-Daudé
2025-08-11 10:43     ` Philippe Mathieu-Daudé
2025-08-18 21:21   ` Mostafa Saleh
2025-08-06 15:11 ` [RFC 02/11] hw/arm/smmuv3: Implement read/write logic for secure registers Tao Tang
2025-08-06 21:53   ` Pierrick Bouvier
2025-08-10 16:54     ` Tao Tang
2025-08-12 17:12       ` Pierrick Bouvier
2025-08-18 21:24   ` Mostafa Saleh
2025-08-20 15:21     ` Tao Tang
2025-08-23 10:41       ` Mostafa Saleh
2025-09-11 15:27         ` Tao Tang
2025-09-15  9:14           ` Mostafa Saleh
2025-09-15  9:34             ` Eric Auger
2025-08-06 15:11 ` [RFC 03/11] hw/arm/smmuv3: Implement S_INIT for secure initialization Tao Tang
2025-08-18 21:26   ` Mostafa Saleh
2025-08-20 16:01     ` Tao Tang
2025-08-06 15:11 ` [RFC 04/11] hw/arm/smmuv3: Enable command processing for the Secure state Tao Tang
2025-08-06 21:55   ` Pierrick Bouvier
2025-08-10 16:59     ` Tao Tang
2025-08-11 10:34       ` Philippe Mathieu-Daudé
2025-08-12 17:27         ` Pierrick Bouvier
2025-08-12 17:39           ` Philippe Mathieu-Daudé
2025-08-12 18:42         ` Peter Maydell
2025-08-15  6:02           ` Tao Tang
2025-08-15 14:53             ` Peter Maydell
2025-08-17  3:46               ` Tao Tang
2025-08-06 15:11 ` [RFC 05/11] hw/arm/smmuv3: Support secure event queue and error handling Tao Tang
2025-08-11 10:41   ` Philippe Mathieu-Daudé [this message]
2025-08-06 15:11 ` [RFC 06/11] hw/arm/smmuv3: Plumb security state through core functions Tao Tang
2025-08-18 21:28   ` Mostafa Saleh
2025-08-20 16:25     ` Tao Tang
2025-08-23 10:43       ` Mostafa Saleh
2025-08-06 15:11 ` [RFC 07/11] hw/arm/smmuv3: Add separate address space for secure SMMU accesses Tao Tang
2025-08-06 15:11 ` [RFC 08/11] hw/arm/smmuv3: Enable secure-side stage 2 TLB invalidations Tao Tang
2025-08-06 15:11 ` [RFC 09/11] hw/arm/smmuv3: Make the configuration cache security-state aware Tao Tang
2025-08-06 15:11 ` [RFC 10/11] hw/arm/smmuv3: Differentiate secure TLB entries via keying Tao Tang
2025-08-06 21:11 ` [RFC 00/11] hw/arm/smmuv3: Add initial support for Secure State Pierrick Bouvier
2025-08-06 21:28 ` Pierrick Bouvier
2025-08-10 16:11   ` Tao Tang
2025-08-11 10:26     ` Philippe Mathieu-Daudé
2025-08-12 17:50       ` Pierrick Bouvier
2025-08-12 18:04     ` Pierrick Bouvier
2025-08-15  5:49       ` Tao Tang
2025-09-30  4:04         ` Tao Tang
2025-08-18 21:52 ` Mostafa Saleh

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=61a78e65-4164-49a2-8ce4-d95730b10eaa@linaro.org \
    --to=philmd@linaro.org \
    --cc=chenbaozi@phytium.com.cn \
    --cc=eric.auger@redhat.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    --cc=tangtao1634@phytium.com.cn \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).