From: Richard Henderson <richard.henderson@linaro.org>
To: Artyom Tarasenko <atar4qemu@gmail.com>, qemu-devel@nongnu.org
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Subject: Re: [PATCH] target/sparc: fake UltraSPARC T1 PCR and PIC registers
Date: Sun, 2 Feb 2025 13:57:57 -0800 [thread overview]
Message-ID: <6208a701-0338-4e1f-b0e2-28bf50d81f86@linaro.org> (raw)
In-Reply-To: <99ea71e8-b978-41c6-8ba5-f056935ea39e@linaro.org>
On 2/2/25 13:46, Richard Henderson wrote:
> On 1/31/25 13:44, Artyom Tarasenko wrote:
>> fake access to
>> PCR Performance Control Register
>> and
>> PIC Performance Instrumentation Counter.
>>
>> Ignore writes in privileged mode, and return 0 on reads.
>>
>> This allows booting Tribblix, MilaX and v9os under Niagara target.
>>
>> Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
>> ---
>> target/sparc/insns.decode | 7 ++++++-
>> target/sparc/translate.c | 20 ++++++++++++++++++++
>> 2 files changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
>> index 989c20b44a..504147563c 100644
>> --- a/target/sparc/insns.decode
>> +++ b/target/sparc/insns.decode
>> @@ -96,7 +96,10 @@ CALL 01 i:s30
>> RDTICK 10 rd:5 101000 00100 0 0000000000000
>> RDPC 10 rd:5 101000 00101 0 0000000000000
>> RDFPRS 10 rd:5 101000 00110 0 0000000000000
>> - RDASR17 10 rd:5 101000 10001 0 0000000000000
>> + {
>> + RDASR17 10 rd:5 101000 10001 0 0000000000000
>> + RDPIC 10 rd:5 101000 10001 0 0000000000000
>> + }
>> RDGSR 10 rd:5 101000 10011 0 0000000000000
>> RDSOFTINT 10 rd:5 101000 10110 0 0000000000000
>> RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000
>> @@ -114,6 +117,8 @@ CALL 01 i:s30
>> WRCCR 10 00010 110000 ..... . ............. @n_r_ri
>> WRASI 10 00011 110000 ..... . ............. @n_r_ri
>> WRFPRS 10 00110 110000 ..... . ............. @n_r_ri
>> + WRPCR 10 10000 110000 01000 0 0000000000000
>> + WRPIC 10 10001 110000 01000 0 0000000000000
>> {
>> WRGSR 10 10011 110000 ..... . ............. @n_r_ri
>> WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri
>> diff --git a/target/sparc/translate.c b/target/sparc/translate.c
>> index 7e5c7351cb..285c9b0a59 100644
>> --- a/target/sparc/translate.c
>> +++ b/target/sparc/translate.c
>> @@ -2882,6 +2882,15 @@ static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst)
>> TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config)
>> +static TCGv do_rdpic(DisasContext *dc, TCGv dst)
>> +{
>> + tcg_gen_movi_tl(dst, 0UL);
>> + return dst;
>> +}
>
> return tcg_constant_tl(0);
>
>> +
>> +TRANS(RDPIC, HYPV, do_rd_special, true, a->rd, do_rdpic)
>
> Surely reads are not allowed in user mode.
You might as well implement RDPCR as well, which *is* privileged.
Since PCR=0, then RDPCR is allowed.
It might be worthwhile to implement PCR, or at least PCR.PRIV.
r~
r~
next prev parent reply other threads:[~2025-02-02 21:58 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-31 21:44 [PATCH] target/sparc: fake UltraSPARC T1 PCR and PIC registers Artyom Tarasenko
2025-02-02 21:46 ` Richard Henderson
2025-02-02 21:57 ` Richard Henderson [this message]
2025-02-09 21:12 ` [PATCH v2] " Artyom Tarasenko
2025-02-15 20:05 ` Richard Henderson
2025-02-09 21:16 ` [PATCH] " Artyom Tarasenko
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