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Tue, 02 Dec 2025 06:29:21 -0800 (PST) Received: from [192.168.0.102] ([177.139.2.175]) by smtp.gmail.com with ESMTPSA id ada2fe7eead31-5e24d9391f8sm6508592137.5.2025.12.02.06.29.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 02 Dec 2025 06:29:20 -0800 (PST) Message-ID: <622f85a3-c671-4a83-bf1b-83127a2fb282@linaro.org> Date: Tue, 2 Dec 2025 11:29:18 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V4 3/4] target/arm/tcg/cpu64.c: Enable ASID2 for cpu_max To: Jim MacArthur , qemu-devel@nongnu.org References: <20251202120250.763150-1-jim.macarthur@linaro.org> <20251202120250.763150-4-jim.macarthur@linaro.org> Content-Language: en-US From: Gustavo Romero In-Reply-To: <20251202120250.763150-4-jim.macarthur@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::e2b; envelope-from=gustavo.romero@linaro.org; helo=mail-vs1-xe2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Jim, On 12/2/25 09:00, Jim MacArthur wrote: > docs/system/arm/emulation.rst: Add ASID2 > > Signed-off-by: Jim MacArthur > --- > docs/system/arm/emulation.rst | 1 + > target/arm/tcg/cpu64.c | 4 ++++ > 2 files changed, 5 insertions(+) > > diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst > index 31a5878a8f..3f30ea5a30 100644 > --- a/docs/system/arm/emulation.rst > +++ b/docs/system/arm/emulation.rst > @@ -24,6 +24,7 @@ the following architecture extensions: > - FEAT_AIE (Memory Attribute Index Enhancement) > - FEAT_Armv9_Crypto (Armv9 Cryptographic Extension) > - FEAT_ASID16 (16 bit ASID) > +- FEAT_ASID2 (Concurrent use of two ASIDs) > - FEAT_ATS1A (Address Translation operations that ignore stage 1 permissions) > - FEAT_BBM at level 2 (Translation table break-before-make levels) > - FEAT_BF16 (AArch64 BFloat16 instructions) > diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c > index 6871956382..ef4c0c8d73 100644 > --- a/target/arm/tcg/cpu64.c > +++ b/target/arm/tcg/cpu64.c > @@ -1334,6 +1334,10 @@ void aarch64_max_tcg_initfn(Object *obj) > t = FIELD_DP64(t, ID_AA64MMFR3, AIE, 1); /* FEAT_AIE */ > SET_IDREG(isar, ID_AA64MMFR3, t); > > + t = GET_IDREG(isar, ID_AA64MMFR4); > + t = FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* FEAT_ASID2 */ > + SET_IDREG(isar, ID_AA64MMFR4, t); > + > t = GET_IDREG(isar, ID_AA64ZFR0); > t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* FEAT_SVE2p1 */ > t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ Reviewed-by: Gustavo Romero