[PATCH v3 00/16] target/mips: Convert nanoMIPS LSA opcode to decodetree

[PATCH v3 00/16] target/mips: Convert nanoMIPS LSA opcode to decodetree

[Philippe Mathieu-Daudé]

Since v2:
- Fix translator_ld() calls
- Add support for 48-bit nanoMIPS opcodes
- Convert Load Immediate opcode
---

Prepare buildsys to decode micro/nanoMIPS opcodes using
the decodetree script.
Simplify gen_lsa/dsa() and convert micro/nanoMIPS LSA
opcode to decodetree.

Philippe Mathieu-Daudé (16):
  target/mips: Extract gen_base_index_addr() helper
  target/mips: Extract generic gen_lx() helper
  target/mips: Convert Octeon LX instructions to decodetree
  target/mips: Call translator_ld() in translate_insn() callees
  target/mips: Have gen_[d]lsa() callers add 1 to shift amount argument
  target/mips: Decode LSA shift amount using decodetree function
  target/mips: Introduce decode tree bindings for MIPS16e ASE
  target/mips: Introduce decode tree bindings for microMIPS ISA
  scripts/decodetree: Add support for 48-bit instructions
  target/mips: Introduce decode tree bindings for nanoMIPS ISA
  target/mips: Convert microMIPS LSA opcode to decodetree
  target/mips: Convert nanoMIPS LSA opcode to decodetree
  target/mips: Add gen_li() helper
  target/mips: Convert microMIPS LI opcode to decodetree
  target/mips: Convert MIPS16e LI opcodes to decodetree
  target/mips: Convert nanoMIPS LI opcodes to decodetree

 target/mips/tcg/translate.h               | 10 +++
 target/mips/tcg/micromips16.decode        | 20 ++++++
 target/mips/tcg/micromips32.decode        | 19 +++++
 target/mips/tcg/mips16e_16.decode         | 17 +++++
 target/mips/tcg/mips16e_32.decode         | 18 +++++
 target/mips/tcg/msa.decode                |  3 +-
 target/mips/tcg/nanomips16.decode         | 16 +++++
 target/mips/tcg/nanomips32.decode         | 14 ++++
 target/mips/tcg/nanomips48.decode         | 16 +++++
 target/mips/tcg/octeon.decode             |  8 +++
 target/mips/tcg/rel6.decode               |  4 +-
 target/mips/tcg/comput_translate.c        | 21 ++++++
 target/mips/tcg/micromips_translate.c     | 43 ++++++++++++
 target/mips/tcg/mips16e_translate.c       | 28 ++++++++
 target/mips/tcg/nanomips_translate.c      | 43 ++++++++++++
 target/mips/tcg/octeon_translate.c        | 12 ++++
 target/mips/tcg/rel6_translate.c          |  5 ++
 target/mips/tcg/translate.c               | 84 +++++++++--------------
 target/mips/tcg/translate_addr_const.c    |  4 +-
 target/mips/tcg/micromips_translate.c.inc | 29 ++++----
 target/mips/tcg/mips16e_translate.c.inc   | 24 +++----
 target/mips/tcg/nanomips_translate.c.inc  | 54 +++++++--------
 scripts/decodetree.py                     |  4 ++
 target/mips/tcg/meson.build               | 11 +++
 24 files changed, 392 insertions(+), 115 deletions(-)
 create mode 100644 target/mips/tcg/micromips16.decode
 create mode 100644 target/mips/tcg/micromips32.decode
 create mode 100644 target/mips/tcg/mips16e_16.decode
 create mode 100644 target/mips/tcg/mips16e_32.decode
 create mode 100644 target/mips/tcg/nanomips16.decode
 create mode 100644 target/mips/tcg/nanomips32.decode
 create mode 100644 target/mips/tcg/nanomips48.decode
 create mode 100644 target/mips/tcg/comput_translate.c
 create mode 100644 target/mips/tcg/micromips_translate.c
 create mode 100644 target/mips/tcg/mips16e_translate.c
 create mode 100644 target/mips/tcg/nanomips_translate.c

-- 
2.45.2

[PATCH v3 01/16] target/mips: Extract gen_base_index_addr() helper

[Philippe Mathieu-Daudé]

Factor out gen_base_index_addr() which is used twice
but we'll use it more.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241111222936.59869-2-philmd@linaro.org>
---
 target/mips/tcg/translate.h |  1 +
 target/mips/tcg/translate.c | 27 +++++++++++++--------------
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 1bf153d1838..ed69ba15e58 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -153,6 +153,7 @@ void check_cp1_registers(DisasContext *ctx, int regs);
 void check_cop1x(DisasContext *ctx);
 
 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
+void gen_base_index_addr(DisasContext *ctx, TCGv addr, int base, int index);
 void gen_move_low32(TCGv ret, TCGv_i64 arg);
 void gen_move_high32(TCGv ret, TCGv_i64 arg);
 void gen_load_gpr(TCGv t, int reg);
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index de7045874dd..7152f5418e1 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1956,6 +1956,17 @@ void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset)
     }
 }
 
+void gen_base_index_addr(DisasContext *ctx, TCGv addr, int base, int index)
+{
+    if (base == 0) {
+        gen_load_gpr(addr, index);
+    } else if (index == 0) {
+        gen_load_gpr(addr, base);
+    } else {
+        gen_op_addr_add(ctx, addr, cpu_gpr[base], cpu_gpr[index]);
+    }
+}
+
 static target_ulong pc_relative_pc(DisasContext *ctx)
 {
     target_ulong pc = ctx->base.pc_next;
@@ -10545,13 +10556,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
 {
     TCGv t0 = tcg_temp_new();
 
-    if (base == 0) {
-        gen_load_gpr(t0, index);
-    } else if (index == 0) {
-        gen_load_gpr(t0, base);
-    } else {
-        gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
-    }
+    gen_base_index_addr(ctx, t0, base, index);
     /*
      * Don't do NOP if destination is zero: we must perform the actual
      * memory access.
@@ -11333,13 +11338,7 @@ static void gen_mips_lx(DisasContext *ctx, uint32_t opc,
     }
     t0 = tcg_temp_new();
 
-    if (base == 0) {
-        gen_load_gpr(t0, offset);
-    } else if (offset == 0) {
-        gen_load_gpr(t0, base);
-    } else {
-        gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]);
-    }
+    gen_base_index_addr(ctx, t0, base, offset);
 
     switch (opc) {
     case OPC_LBUX:
-- 
2.45.2

[PATCH v3 02/16] target/mips: Extract generic gen_lx() helper

[Philippe Mathieu-Daudé]

Extract gen_lx() from gen_mips_lx(); inline the Octeon
check in decode_opc_special3_legacy().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241111222936.59869-3-philmd@linaro.org>
---
 target/mips/tcg/translate.h |  1 +
 target/mips/tcg/translate.c | 55 +++++++++++++------------------------
 2 files changed, 20 insertions(+), 36 deletions(-)

diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index ed69ba15e58..a65ab4a747c 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -168,6 +168,7 @@ void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
 void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
 int get_fp_bit(int cc);
 
+void gen_lx(DisasContext *ctx, int rd, int base, int index, MemOp mop);
 void gen_ldxs(DisasContext *ctx, int base, int index, int rd);
 void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int bp);
 void gen_addiupc(DisasContext *ctx, int rx, int imm,
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 7152f5418e1..acadd3d8919 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -2035,6 +2035,15 @@ static void gen_lxr(DisasContext *ctx, TCGv reg, TCGv addr,
     tcg_gen_or_tl(reg, t0, t1);
 }
 
+void gen_lx(DisasContext *ctx, int rd, int base, int index, MemOp mop)
+{
+    TCGv t0 = tcg_temp_new();
+
+    gen_base_index_addr(ctx, t0, base, index);
+    tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | mop);
+    gen_store_gpr(t0, rd);
+}
+
 /* Load */
 static void gen_ld(DisasContext *ctx, uint32_t opc,
                    int rt, int base, int offset)
@@ -11327,41 +11336,6 @@ enum {
 
 /* MIPSDSP functions. */
 
-/* Indexed load is not for DSP only */
-static void gen_mips_lx(DisasContext *ctx, uint32_t opc,
-                        int rd, int base, int offset)
-{
-    TCGv t0;
-
-    if (!(ctx->insn_flags & INSN_OCTEON)) {
-        check_dsp(ctx);
-    }
-    t0 = tcg_temp_new();
-
-    gen_base_index_addr(ctx, t0, base, offset);
-
-    switch (opc) {
-    case OPC_LBUX:
-        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB);
-        gen_store_gpr(t0, rd);
-        break;
-    case OPC_LHX:
-        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW);
-        gen_store_gpr(t0, rd);
-        break;
-    case OPC_LWX:
-        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL);
-        gen_store_gpr(t0, rd);
-        break;
-#if defined(TARGET_MIPS64)
-    case OPC_LDX:
-        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
-        gen_store_gpr(t0, rd);
-        break;
-#endif
-    }
-}
-
 static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
                               int ret, int v1, int v2)
 {
@@ -13609,15 +13583,24 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
         }
         break;
     case OPC_LX_DSP:
+        if (!(ctx->insn_flags & INSN_OCTEON)) {
+            check_dsp(ctx);
+        }
         op2 = MASK_LX(ctx->opcode);
         switch (op2) {
 #if defined(TARGET_MIPS64)
         case OPC_LDX:
+            gen_lx(ctx, rd, rs, rt, MO_UQ);
+            break;
 #endif
         case OPC_LBUX:
+            gen_lx(ctx, rd, rs, rt, MO_UB);
+            break;
         case OPC_LHX:
+            gen_lx(ctx, rd, rs, rt, MO_SW);
+            break;
         case OPC_LWX:
-            gen_mips_lx(ctx, op2, rd, rs, rt);
+            gen_lx(ctx, rd, rs, rt, MO_SL);
             break;
         default:            /* Invalid */
             MIPS_INVAL("MASK LX");
-- 
2.45.2

[PATCH v3 03/16] target/mips: Convert Octeon LX instructions to decodetree

[Philippe Mathieu-Daudé]

Use Octeon decodetree to call gen_lx() for the LX instructions.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241111222936.59869-4-philmd@linaro.org>
---
 target/mips/tcg/octeon.decode      |  8 ++++++++
 target/mips/tcg/octeon_translate.c | 12 ++++++++++++
 target/mips/tcg/translate.c        |  4 +---
 3 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode
index 0c787cb498c..102a05860df 100644
--- a/target/mips/tcg/octeon.decode
+++ b/target/mips/tcg/octeon.decode
@@ -1,6 +1,7 @@
 # Octeon Architecture Module instruction set
 #
 # Copyright (C) 2022 Pavel Dovgalyuk
+# Copyright (C) 2024 Philippe Mathieu-Daudé
 #
 # SPDX-License-Identifier: LGPL-2.1-or-later
 #
@@ -39,3 +40,10 @@ CINS         011100 ..... ..... ..... ..... 11001 . @bitfield
 POP          011100 rs:5 00000 rd:5 00000 10110 dw:1
 SEQNE        011100 rs:5 rt:5 rd:5 00000 10101 ne:1
 SEQNEI       011100 rs:5 rt:5 imm:s10 10111 ne:1
+
+&lx          base index rd
+@lx          ...... base:5 index:5 rd:5 ...... ..... &lx
+LWX          011111 ..... ..... ..... 00000 001010 @lx
+LHX          011111 ..... ..... ..... 00100 001010 @lx
+LBUX         011111 ..... ..... ..... 00110 001010 @lx
+LDX          011111 ..... ..... ..... 01000 001010 @lx
diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
index e25c4cbaa06..0e0b00303a7 100644
--- a/target/mips/tcg/octeon_translate.c
+++ b/target/mips/tcg/octeon_translate.c
@@ -174,3 +174,15 @@ static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a)
     }
     return true;
 }
+
+static bool trans_lx(DisasContext *ctx, arg_lx *a, MemOp mop)
+{
+    gen_lx(ctx, a->rd, a->base, a->index, mop);
+
+    return true;
+}
+
+TRANS(LBUX, trans_lx, MO_UB);
+TRANS(LHX,  trans_lx, MO_SW);
+TRANS(LWX,  trans_lx, MO_SL);
+TRANS(LDX,  trans_lx, MO_UQ);
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index acadd3d8919..6fd5462a24f 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -13583,9 +13583,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
         }
         break;
     case OPC_LX_DSP:
-        if (!(ctx->insn_flags & INSN_OCTEON)) {
-            check_dsp(ctx);
-        }
+        check_dsp(ctx);
         op2 = MASK_LX(ctx->opcode);
         switch (op2) {
 #if defined(TARGET_MIPS64)
-- 
2.45.2

[PATCH v3 04/16] target/mips: Call translator_ld() in translate_insn() callees

[Philippe Mathieu-Daudé]

Historically we were only calling decode_opc() from the MIPS
translate_insn() handler. Then variable instruction length
ISAs were added, we kept using the same pattern but call
yet more translator_ld() in the callees when necessary.

This is cumbersome and bug prone, so better move all
translator_ld() calls to the callees where it is more
logical.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/tcg/translate.c               |  6 ++----
 target/mips/tcg/micromips_translate.c.inc |  3 +++
 target/mips/tcg/mips16e_translate.c.inc   |  5 +++--
 target/mips/tcg/nanomips_translate.c.inc  | 12 +++++++++---
 4 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 6fd5462a24f..0495fbe1dc6 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -15000,6 +15000,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
         gen_set_label(l1);
     }
 
+    ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
+
     /* Transition to the auto-generated decoder.  */
 
     /* Vendor specific extensions */
@@ -15120,17 +15122,13 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
 
     is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
     if (ctx->insn_flags & ISA_NANOMIPS32) {
-        ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
         insn_bytes = decode_isa_nanomips(env, ctx);
     } else if (!(ctx->hflags & MIPS_HFLAG_M16)) {
-        ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
         insn_bytes = 4;
         decode_opc(env, ctx);
     } else if (ctx->insn_flags & ASE_MICROMIPS) {
-        ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
         insn_bytes = decode_isa_micromips(env, ctx);
     } else if (ctx->insn_flags & ASE_MIPS16) {
-        ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
         insn_bytes = decode_ase_mips16e(env, ctx);
     } else {
         gen_reserved_instruction(ctx);
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index c479bec1081..98a00125520 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -2973,6 +2973,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
 
 static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx)
 {
+    uint32_t opcode;
     uint32_t op;
 
     /* make sure instructions are on a halfword boundary */
@@ -2982,6 +2983,8 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx)
         return 2;
     }
 
+    opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
+    ctx->opcode = opcode;
     op = (ctx->opcode >> 10) & 0x3f;
     /* Enforce properly-sized instructions in a delay slot */
     if (ctx->hflags & MIPS_HFLAG_BDS_STRICT) {
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
index a9af8f1e74a..defef3ce559 100644
--- a/target/mips/tcg/mips16e_translate.c.inc
+++ b/target/mips/tcg/mips16e_translate.c.inc
@@ -453,11 +453,9 @@ static void decode_i64_mips16(DisasContext *ctx,
 
 static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
 {
-    int extend = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
     int op, rx, ry, funct, sa;
     int16_t imm, offset;
 
-    ctx->opcode = (ctx->opcode << 16) | extend;
     op = (ctx->opcode >> 11) & 0x1f;
     sa = (ctx->opcode >> 22) & 0x1f;
     funct = (ctx->opcode >> 8) & 0x7;
@@ -658,6 +656,7 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx)
     int funct;
     int n_bytes;
 
+    ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
     op = (ctx->opcode >> 11) & 0x1f;
     sa = (ctx->opcode >> 2) & 0x7;
     sa = sa == 0 ? 8 : sa;
@@ -1103,6 +1102,8 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx)
         }
         break;
     case M16_OPC_EXTEND:
+        ctx->opcode <<= 16;
+        ctx->opcode |= translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
         decode_extended_mips16_opc(env, ctx);
         n_bytes = 4;
         break;
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index 1e274143bbd..6ee0c4fca3b 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -4467,10 +4467,11 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
 
 static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
 {
+    uint64_t opcode;
     uint32_t op;
-    int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode));
-    int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
-    int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD3(ctx->opcode));
+    int rt;
+    int rs;
+    int rd;
     int offset;
     int imm;
 
@@ -4482,6 +4483,11 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
         return 2;
     }
 
+    opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
+    ctx->opcode = opcode;
+    rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode));
+    rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
+    rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD3(ctx->opcode));
     op = extract32(ctx->opcode, 10, 6);
     switch (op) {
     case NM_P16_MV:
-- 
2.45.2

Re: [PATCH v3 04/16] target/mips: Call translator_ld() in translate_insn() callees

[Richard Henderson]

On 11/26/24 07:59, Philippe Mathieu-Daudé wrote:
> Historically we were only calling decode_opc() from the MIPS
> translate_insn() handler. Then variable instruction length
> ISAs were added, we kept using the same pattern but call
> yet more translator_ld() in the callees when necessary.
> 
> This is cumbersome and bug prone, so better move all
> translator_ld() calls to the callees where it is more
> logical.
> 
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
>   target/mips/tcg/translate.c               |  6 ++----
>   target/mips/tcg/micromips_translate.c.inc |  3 +++
>   target/mips/tcg/mips16e_translate.c.inc   |  5 +++--
>   target/mips/tcg/nanomips_translate.c.inc  | 12 +++++++++---
>   4 files changed, 17 insertions(+), 9 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[PATCH v3 05/16] target/mips: Have gen_[d]lsa() callers add 1 to shift amount argument

[Philippe Mathieu-Daudé]

Having the callee add 1 to shift amount is misleading (see the
NM_LSA case in decode_nanomips_32_48_opc() where we have to
manually substract 1). Rather have the callers pass a modified
$sa.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241112172022.88348-4-philmd@linaro.org>
---
 target/mips/tcg/msa_translate.c           | 4 ++--
 target/mips/tcg/rel6_translate.c          | 4 ++--
 target/mips/tcg/translate_addr_const.c    | 4 ++--
 target/mips/tcg/micromips_translate.c.inc | 2 +-
 target/mips/tcg/nanomips_translate.c.inc  | 7 +------
 5 files changed, 8 insertions(+), 13 deletions(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 75cf80a20ed..82b149922fa 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -780,7 +780,7 @@ TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st);
 
 static bool trans_LSA(DisasContext *ctx, arg_r *a)
 {
-    return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
+    return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
 }
 
 static bool trans_DLSA(DisasContext *ctx, arg_r *a)
@@ -788,5 +788,5 @@ static bool trans_DLSA(DisasContext *ctx, arg_r *a)
     if (TARGET_LONG_BITS != 64) {
         return false;
     }
-    return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa);
+    return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
 }
diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_translate.c
index 59f237ba3ba..363bc864912 100644
--- a/target/mips/tcg/rel6_translate.c
+++ b/target/mips/tcg/rel6_translate.c
@@ -23,7 +23,7 @@ bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a)
 
 static bool trans_LSA(DisasContext *ctx, arg_r *a)
 {
-    return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
+    return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
 }
 
 static bool trans_DLSA(DisasContext *ctx, arg_r *a)
@@ -31,5 +31,5 @@ static bool trans_DLSA(DisasContext *ctx, arg_r *a)
     if (TARGET_LONG_BITS != 64) {
         return false;
     }
-    return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa);
+    return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
 }
diff --git a/target/mips/tcg/translate_addr_const.c b/target/mips/tcg/translate_addr_const.c
index 6f4b39f715b..1d140e918da 100644
--- a/target/mips/tcg/translate_addr_const.c
+++ b/target/mips/tcg/translate_addr_const.c
@@ -26,7 +26,7 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
     t1 = tcg_temp_new();
     gen_load_gpr(t0, rs);
     gen_load_gpr(t1, rt);
-    tcg_gen_shli_tl(t0, t0, sa + 1);
+    tcg_gen_shli_tl(t0, t0, sa);
     tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
     tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
     return true;
@@ -47,7 +47,7 @@ bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
     t1 = tcg_temp_new();
     gen_load_gpr(t0, rs);
     gen_load_gpr(t1, rt);
-    tcg_gen_shli_tl(t0, t0, sa + 1);
+    tcg_gen_shli_tl(t0, t0, sa);
     tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
     return true;
 }
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index 98a00125520..26006f84df7 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -1795,7 +1795,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
             return;
         case LSA:
             check_insn(ctx, ISA_MIPS_R6);
-            gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2));
+            gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) + 1);
             break;
         case ALIGN:
             check_insn(ctx, ISA_MIPS_R6);
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index 6ee0c4fca3b..e0a920bdb3a 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -3626,12 +3626,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                 gen_p_lsx(ctx, rd, rs, rt);
                 break;
             case NM_LSA:
-                /*
-                 * In nanoMIPS, the shift field directly encodes the shift
-                 * amount, meaning that the supported shift values are in
-                 * the range 0 to 3 (instead of 1 to 4 in MIPSR6).
-                 */
-                gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) - 1);
+                gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2));
                 break;
             case NM_EXTW:
                 gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5));
-- 
2.45.2

[PATCH v3 06/16] target/mips: Decode LSA shift amount using decodetree function

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241112172022.88348-5-philmd@linaro.org>
---
 target/mips/tcg/msa.decode       | 3 ++-
 target/mips/tcg/rel6.decode      | 4 +++-
 target/mips/tcg/msa_translate.c  | 4 ++--
 target/mips/tcg/rel6_translate.c | 9 +++++++--
 4 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 4410e2a02e1..798e8c401ab 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -21,6 +21,7 @@
 &msa_elm_df         df  wd ws       n
 &msa_elm                wd ws
 
+%lsa_sa             6:2  !function=plus_1
 %elm_df             16:6 !function=elm_df
 %elm_n              16:6 !function=elm_n
 %bit_df             16:7 !function=bit_df
@@ -29,7 +30,7 @@
 %3r_df_h            21:1 !function=plus_1
 %3r_df_w            21:1 !function=plus_2
 
-@lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &r
+@lsa                ...... rs:5 rt:5 rd:5 ... .. ......     &r sa=%lsa_sa
 @ldst               ...... sa:s10 ws:5 wd:5 .... df:2       &msa_i
 @bz_v               ...... ... ..    wt:5 sa:s16            &msa_bz df=3
 @bz                 ...... ...  df:2 wt:5 sa:s16            &msa_bz
diff --git a/target/mips/tcg/rel6.decode b/target/mips/tcg/rel6.decode
index d6989cf56e8..a9031171b54 100644
--- a/target/mips/tcg/rel6.decode
+++ b/target/mips/tcg/rel6.decode
@@ -16,7 +16,9 @@
 
 &r                  rs rt rd sa
 
-@lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &r
+%lsa_sa             6:2  !function=plus_1
+
+@lsa                ...... rs:5 rt:5 rd:5 ... .. ......     &r sa=%lsa_sa
 
 LSA                 000000 ..... ..... ..... 000 .. 000101  @lsa
 DLSA                000000 ..... ..... ..... 000 .. 010101  @lsa
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 82b149922fa..75cf80a20ed 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -780,7 +780,7 @@ TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st);
 
 static bool trans_LSA(DisasContext *ctx, arg_r *a)
 {
-    return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
+    return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
 }
 
 static bool trans_DLSA(DisasContext *ctx, arg_r *a)
@@ -788,5 +788,5 @@ static bool trans_DLSA(DisasContext *ctx, arg_r *a)
     if (TARGET_LONG_BITS != 64) {
         return false;
     }
-    return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
+    return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa);
 }
diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_translate.c
index 363bc864912..2522ecae2ba 100644
--- a/target/mips/tcg/rel6_translate.c
+++ b/target/mips/tcg/rel6_translate.c
@@ -11,6 +11,11 @@
 #include "qemu/osdep.h"
 #include "translate.h"
 
+static inline int plus_1(DisasContext *ctx, int x)
+{
+    return x + 1;
+}
+
 /* Include the auto-generated decoders.  */
 #include "decode-rel6.c.inc"
 
@@ -23,7 +28,7 @@ bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a)
 
 static bool trans_LSA(DisasContext *ctx, arg_r *a)
 {
-    return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
+    return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
 }
 
 static bool trans_DLSA(DisasContext *ctx, arg_r *a)
@@ -31,5 +36,5 @@ static bool trans_DLSA(DisasContext *ctx, arg_r *a)
     if (TARGET_LONG_BITS != 64) {
         return false;
     }
-    return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
+    return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa);
 }
-- 
2.45.2

[PATCH v3 07/16] target/mips: Introduce decode tree bindings for MIPS16e ASE

[Philippe Mathieu-Daudé]

Introduce the MIPS16e decodetree configs for the 16-bit
and 32-bit instructions.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/tcg/translate.h             |  2 ++
 target/mips/tcg/mips16e_16.decode       |  9 +++++++++
 target/mips/tcg/mips16e_32.decode       |  9 +++++++++
 target/mips/tcg/mips16e_translate.c     | 14 ++++++++++++++
 target/mips/tcg/mips16e_translate.c.inc |  8 ++++++++
 target/mips/tcg/meson.build             |  3 +++
 6 files changed, 45 insertions(+)
 create mode 100644 target/mips/tcg/mips16e_16.decode
 create mode 100644 target/mips/tcg/mips16e_32.decode
 create mode 100644 target/mips/tcg/mips16e_translate.c

diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index a65ab4a747c..d1aa811cfa1 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -223,6 +223,8 @@ bool decode_64bit_enabled(DisasContext *ctx);
 
 /* decodetree generated */
 bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
+bool decode_ase_mips16e_16(DisasContext *ctx, uint16_t insn);
+bool decode_ase_mips16e_32(DisasContext *ctx, uint32_t insn);
 bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
 bool decode_ext_txx9(DisasContext *ctx, uint32_t insn);
 bool decode_ext_loongson(DisasContext *ctx, uint32_t insn);
diff --git a/target/mips/tcg/mips16e_16.decode b/target/mips/tcg/mips16e_16.decode
new file mode 100644
index 00000000000..82586493f68
--- /dev/null
+++ b/target/mips/tcg/mips16e_16.decode
@@ -0,0 +1,9 @@
+# MIPS16e 16-bit instruction set extensions
+#
+# Copyright (C) 2021  Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference: MIPS Architecture for Programmers, Volume IV-a
+#            The MIPS16e Application Specific Extension
+#            (Document Number: MD00076)
diff --git a/target/mips/tcg/mips16e_32.decode b/target/mips/tcg/mips16e_32.decode
new file mode 100644
index 00000000000..fc429049e18
--- /dev/null
+++ b/target/mips/tcg/mips16e_32.decode
@@ -0,0 +1,9 @@
+# MIPS16e 32-bit instruction set extensions
+#
+# Copyright (C) 2021  Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference: MIPS Architecture for Programmers, Volume IV-a
+#            The MIPS16e Application Specific Extension
+#            (Document Number: MD00076)
diff --git a/target/mips/tcg/mips16e_translate.c b/target/mips/tcg/mips16e_translate.c
new file mode 100644
index 00000000000..6de9928b37e
--- /dev/null
+++ b/target/mips/tcg/mips16e_translate.c
@@ -0,0 +1,14 @@
+/*
+ * MIPS emulation for QEMU - MIPS16e translation routines
+ *
+ * Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org>
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "translate.h"
+
+/* Include the auto-generated decoders.  */
+#include "decode-mips16e_16.c.inc"
+#include "decode-mips16e_32.c.inc"
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
index defef3ce559..a57ae4e95b1 100644
--- a/target/mips/tcg/mips16e_translate.c.inc
+++ b/target/mips/tcg/mips16e_translate.c.inc
@@ -657,6 +657,14 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx)
     int n_bytes;
 
     ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
+
+    if (decode_ase_mips16e_16(ctx, ctx->opcode)) {
+        return 2;
+    }
+    if (decode_ase_mips16e_32(ctx, ctx->opcode)) {
+        return 4;
+    }
+
     op = (ctx->opcode >> 11) & 0x1f;
     sa = (ctx->opcode >> 2) & 0x7;
     sa = sa == 0 ? 8 : sa;
diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build
index 7b18e6c4c8b..bcb64368be8 100644
--- a/target/mips/tcg/meson.build
+++ b/target/mips/tcg/meson.build
@@ -1,4 +1,6 @@
 gen = [
+  decodetree.process('mips16e_16.decode', extra_args: ['--decode=decode_ase_mips16e_16', '--insnwidth=16']),
+  decodetree.process('mips16e_32.decode', extra_args: ['--decode=decode_ase_mips16e_32']),
   decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']),
   decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'),
   decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
@@ -16,6 +18,7 @@ mips_ss.add(files(
   'fpu_helper.c',
   'ldst_helper.c',
   'lmmi_helper.c',
+  'mips16e_translate.c',
   'msa_helper.c',
   'msa_translate.c',
   'op_helper.c',
-- 
2.45.2

Re: [PATCH v3 07/16] target/mips: Introduce decode tree bindings for MIPS16e ASE

[Richard Henderson]

On 11/26/24 07:59, Philippe Mathieu-Daudé wrote:
> Introduce the MIPS16e decodetree configs for the 16-bit
> and 32-bit instructions.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/mips/tcg/translate.h             |  2 ++
>   target/mips/tcg/mips16e_16.decode       |  9 +++++++++
>   target/mips/tcg/mips16e_32.decode       |  9 +++++++++
>   target/mips/tcg/mips16e_translate.c     | 14 ++++++++++++++
>   target/mips/tcg/mips16e_translate.c.inc |  8 ++++++++
>   target/mips/tcg/meson.build             |  3 +++
>   6 files changed, 45 insertions(+)
>   create mode 100644 target/mips/tcg/mips16e_16.decode
>   create mode 100644 target/mips/tcg/mips16e_32.decode
>   create mode 100644 target/mips/tcg/mips16e_translate.c
> 
> diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
> index a65ab4a747c..d1aa811cfa1 100644
> --- a/target/mips/tcg/translate.h
> +++ b/target/mips/tcg/translate.h
> @@ -223,6 +223,8 @@ bool decode_64bit_enabled(DisasContext *ctx);
>   
>   /* decodetree generated */
>   bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
> +bool decode_ase_mips16e_16(DisasContext *ctx, uint16_t insn);
> +bool decode_ase_mips16e_32(DisasContext *ctx, uint32_t insn);
>   bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
>   bool decode_ext_txx9(DisasContext *ctx, uint32_t insn);
>   bool decode_ext_loongson(DisasContext *ctx, uint32_t insn);
> diff --git a/target/mips/tcg/mips16e_16.decode b/target/mips/tcg/mips16e_16.decode
> new file mode 100644
> index 00000000000..82586493f68
> --- /dev/null
> +++ b/target/mips/tcg/mips16e_16.decode
> @@ -0,0 +1,9 @@
> +# MIPS16e 16-bit instruction set extensions
> +#
> +# Copyright (C) 2021  Philippe Mathieu-Daudé
> +#
> +# SPDX-License-Identifier: LGPL-2.1-or-later
> +#
> +# Reference: MIPS Architecture for Programmers, Volume IV-a
> +#            The MIPS16e Application Specific Extension
> +#            (Document Number: MD00076)
> diff --git a/target/mips/tcg/mips16e_32.decode b/target/mips/tcg/mips16e_32.decode
> new file mode 100644
> index 00000000000..fc429049e18
> --- /dev/null
> +++ b/target/mips/tcg/mips16e_32.decode
> @@ -0,0 +1,9 @@
> +# MIPS16e 32-bit instruction set extensions
> +#
> +# Copyright (C) 2021  Philippe Mathieu-Daudé
> +#
> +# SPDX-License-Identifier: LGPL-2.1-or-later
> +#
> +# Reference: MIPS Architecture for Programmers, Volume IV-a
> +#            The MIPS16e Application Specific Extension
> +#            (Document Number: MD00076)
> diff --git a/target/mips/tcg/mips16e_translate.c b/target/mips/tcg/mips16e_translate.c
> new file mode 100644
> index 00000000000..6de9928b37e
> --- /dev/null
> +++ b/target/mips/tcg/mips16e_translate.c
> @@ -0,0 +1,14 @@
> +/*
> + * MIPS emulation for QEMU - MIPS16e translation routines
> + *
> + * Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org>
> + *
> + * SPDX-License-Identifier: LGPL-2.1-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "translate.h"
> +
> +/* Include the auto-generated decoders.  */
> +#include "decode-mips16e_16.c.inc"
> +#include "decode-mips16e_32.c.inc"
> diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
> index defef3ce559..a57ae4e95b1 100644
> --- a/target/mips/tcg/mips16e_translate.c.inc
> +++ b/target/mips/tcg/mips16e_translate.c.inc
> @@ -657,6 +657,14 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx)
>       int n_bytes;
>   
>       ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
> +
> +    if (decode_ase_mips16e_16(ctx, ctx->opcode)) {
> +        return 2;
> +    }
> +    if (decode_ase_mips16e_32(ctx, ctx->opcode)) {
> +        return 4;
> +    }

This is misplaced wrt loading 32-bits of opcode.  You have two options:

     opcode = lduw(...)
     if (extract32(opcode, 11, 5) == M16_OPC_EXTEND) {
         opcode <<= 16;
         opcode |= lduw(...);
         decode_ase_mips16e_32(...);
     } else {
         decode_ase_mips16e_16(...);
     }

Or, make use of the variable-length support in decodetree.  Given the trivial test above, 
the complexity and oddness of the variable-length stuff doesn't seem worth it.


r~

[PATCH v3 08/16] target/mips: Introduce decode tree bindings for microMIPS ISA

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Introduce the microMIPS decodetree configs for the 16-bit
and 32-bit instructions.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/tcg/translate.h               |  2 ++
 target/mips/tcg/micromips16.decode        | 11 +++++++++++
 target/mips/tcg/micromips32.decode        | 11 +++++++++++
 target/mips/tcg/micromips_translate.c     | 14 ++++++++++++++
 target/mips/tcg/micromips_translate.c.inc |  9 +++++++++
 target/mips/tcg/meson.build               |  3 +++
 6 files changed, 50 insertions(+)
 create mode 100644 target/mips/tcg/micromips16.decode
 create mode 100644 target/mips/tcg/micromips32.decode
 create mode 100644 target/mips/tcg/micromips_translate.c

diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index d1aa811cfa1..2a079cb28d9 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -222,6 +222,8 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn);
 bool decode_64bit_enabled(DisasContext *ctx);
 
 /* decodetree generated */
+bool decode_isa_micromips16(DisasContext *ctx, uint16_t insn);
+bool decode_isa_micromips32(DisasContext *ctx, uint32_t insn);
 bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
 bool decode_ase_mips16e_16(DisasContext *ctx, uint16_t insn);
 bool decode_ase_mips16e_32(DisasContext *ctx, uint32_t insn);
diff --git a/target/mips/tcg/micromips16.decode b/target/mips/tcg/micromips16.decode
new file mode 100644
index 00000000000..d341da16b04
--- /dev/null
+++ b/target/mips/tcg/micromips16.decode
@@ -0,0 +1,11 @@
+# microMIPS32 16-bit instruction set extensions
+#
+# Copyright (C) 2021  Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference: MIPS Architecture for Programmers, Volume II-B
+#            microMIPS32 Instruction Set
+#            (Document Number: MD00582)
+#            microMIPS64 Instruction Set
+#            (Document Number: MD00594)
diff --git a/target/mips/tcg/micromips32.decode b/target/mips/tcg/micromips32.decode
new file mode 100644
index 00000000000..333ab0969ca
--- /dev/null
+++ b/target/mips/tcg/micromips32.decode
@@ -0,0 +1,11 @@
+# microMIPS32 32-bit instruction set extensions
+#
+# Copyright (C) 2021  Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference: MIPS Architecture for Programmers, Volume II-B
+#            microMIPS32 Instruction Set
+#            (Document Number: MD00582)
+#            microMIPS64 Instruction Set
+#            (Document Number: MD00594)
diff --git a/target/mips/tcg/micromips_translate.c b/target/mips/tcg/micromips_translate.c
new file mode 100644
index 00000000000..49e90e7eca2
--- /dev/null
+++ b/target/mips/tcg/micromips_translate.c
@@ -0,0 +1,14 @@
+/*
+ * MIPS emulation for QEMU - microMIPS translation routines
+ *
+ * Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org>
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "translate.h"
+
+/* Include the auto-generated decoders.  */
+#include "decode-micromips16.c.inc"
+#include "decode-micromips32.c.inc"
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index 26006f84df7..7a884222eed 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -3018,6 +3018,15 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx)
         }
     }
 
+    if (decode_isa_micromips16(ctx, opcode)) {
+        return 2;
+    }
+    opcode <<= 16;
+    opcode |= translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
+    if (decode_isa_micromips32(ctx, opcode)) {
+        return 4;
+    }
+
     switch (op) {
     case POOL16A:
         {
diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build
index bcb64368be8..ca70769912c 100644
--- a/target/mips/tcg/meson.build
+++ b/target/mips/tcg/meson.build
@@ -1,6 +1,8 @@
 gen = [
   decodetree.process('mips16e_16.decode', extra_args: ['--decode=decode_ase_mips16e_16', '--insnwidth=16']),
   decodetree.process('mips16e_32.decode', extra_args: ['--decode=decode_ase_mips16e_32']),
+  decodetree.process('micromips16.decode', extra_args: ['--decode=decode_isa_micromips16', '--insnwidth=16']),
+  decodetree.process('micromips32.decode', extra_args: ['--decode=decode_isa_micromips32']),
   decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']),
   decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'),
   decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
@@ -18,6 +20,7 @@ mips_ss.add(files(
   'fpu_helper.c',
   'ldst_helper.c',
   'lmmi_helper.c',
+  'micromips_translate.c',
   'mips16e_translate.c',
   'msa_helper.c',
   'msa_translate.c',
-- 
2.45.2

Re: [PATCH v3 08/16] target/mips: Introduce decode tree bindings for microMIPS ISA

[Richard Henderson]

On 11/26/24 07:59, Philippe Mathieu-Daudé wrote:
> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
> 
> Introduce the microMIPS decodetree configs for the 16-bit
> and 32-bit instructions.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/mips/tcg/translate.h               |  2 ++
>   target/mips/tcg/micromips16.decode        | 11 +++++++++++
>   target/mips/tcg/micromips32.decode        | 11 +++++++++++
>   target/mips/tcg/micromips_translate.c     | 14 ++++++++++++++
>   target/mips/tcg/micromips_translate.c.inc |  9 +++++++++
>   target/mips/tcg/meson.build               |  3 +++
>   6 files changed, 50 insertions(+)
>   create mode 100644 target/mips/tcg/micromips16.decode
>   create mode 100644 target/mips/tcg/micromips32.decode
>   create mode 100644 target/mips/tcg/micromips_translate.c
> 
> diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
> index d1aa811cfa1..2a079cb28d9 100644
> --- a/target/mips/tcg/translate.h
> +++ b/target/mips/tcg/translate.h
> @@ -222,6 +222,8 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn);
>   bool decode_64bit_enabled(DisasContext *ctx);
>   
>   /* decodetree generated */
> +bool decode_isa_micromips16(DisasContext *ctx, uint16_t insn);
> +bool decode_isa_micromips32(DisasContext *ctx, uint32_t insn);
>   bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
>   bool decode_ase_mips16e_16(DisasContext *ctx, uint16_t insn);
>   bool decode_ase_mips16e_32(DisasContext *ctx, uint32_t insn);
> diff --git a/target/mips/tcg/micromips16.decode b/target/mips/tcg/micromips16.decode
> new file mode 100644
> index 00000000000..d341da16b04
> --- /dev/null
> +++ b/target/mips/tcg/micromips16.decode
> @@ -0,0 +1,11 @@
> +# microMIPS32 16-bit instruction set extensions
> +#
> +# Copyright (C) 2021  Philippe Mathieu-Daudé
> +#
> +# SPDX-License-Identifier: LGPL-2.1-or-later
> +#
> +# Reference: MIPS Architecture for Programmers, Volume II-B
> +#            microMIPS32 Instruction Set
> +#            (Document Number: MD00582)
> +#            microMIPS64 Instruction Set
> +#            (Document Number: MD00594)
> diff --git a/target/mips/tcg/micromips32.decode b/target/mips/tcg/micromips32.decode
> new file mode 100644
> index 00000000000..333ab0969ca
> --- /dev/null
> +++ b/target/mips/tcg/micromips32.decode
> @@ -0,0 +1,11 @@
> +# microMIPS32 32-bit instruction set extensions
> +#
> +# Copyright (C) 2021  Philippe Mathieu-Daudé
> +#
> +# SPDX-License-Identifier: LGPL-2.1-or-later
> +#
> +# Reference: MIPS Architecture for Programmers, Volume II-B
> +#            microMIPS32 Instruction Set
> +#            (Document Number: MD00582)
> +#            microMIPS64 Instruction Set
> +#            (Document Number: MD00594)
> diff --git a/target/mips/tcg/micromips_translate.c b/target/mips/tcg/micromips_translate.c
> new file mode 100644
> index 00000000000..49e90e7eca2
> --- /dev/null
> +++ b/target/mips/tcg/micromips_translate.c
> @@ -0,0 +1,14 @@
> +/*
> + * MIPS emulation for QEMU - microMIPS translation routines
> + *
> + * Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org>
> + *
> + * SPDX-License-Identifier: LGPL-2.1-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "translate.h"
> +
> +/* Include the auto-generated decoders.  */
> +#include "decode-micromips16.c.inc"
> +#include "decode-micromips32.c.inc"
> diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
> index 26006f84df7..7a884222eed 100644
> --- a/target/mips/tcg/micromips_translate.c.inc
> +++ b/target/mips/tcg/micromips_translate.c.inc
> @@ -3018,6 +3018,15 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx)
>           }
>       }
>   
> +    if (decode_isa_micromips16(ctx, opcode)) {
> +        return 2;
> +    }
> +    opcode <<= 16;
> +    opcode |= translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
> +    if (decode_isa_micromips32(ctx, opcode)) {
> +        return 4;
> +    }


In the switch just above, you have determined 16-bit vs 32-bit, have you not? I think you 
should make use of that and keep these two cases separate.


r~

[PATCH v3 09/16] scripts/decodetree: Add support for 48-bit instructions

[Philippe Mathieu-Daudé]

Some nanoMIPS instructions are encoded using 48-bit.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 scripts/decodetree.py | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index e8b72da3a97..88cd476d2d3 100644
--- a/scripts/decodetree.py
+++ b/scripts/decodetree.py
@@ -1543,6 +1543,10 @@ def main():
                 insntype = 'uint64_t'
                 insnmask = 0xffffffffffffffff
                 bitop_width = 64
+            elif insnwidth == 48:
+                insntype = 'uint64_t'
+                insnmask = 0xffffffffffff
+                bitop_width = 64
             elif insnwidth != 32:
                 error(0, 'cannot handle insns of width', insnwidth)
         elif o == '--test-for-error':
-- 
2.45.2

Re: [PATCH v3 09/16] scripts/decodetree: Add support for 48-bit instructions

[Richard Henderson]

On 11/26/24 07:59, Philippe Mathieu-Daudé wrote:
> Some nanoMIPS instructions are encoded using 48-bit.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   scripts/decodetree.py | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/scripts/decodetree.py b/scripts/decodetree.py
> index e8b72da3a97..88cd476d2d3 100644
> --- a/scripts/decodetree.py
> +++ b/scripts/decodetree.py
> @@ -1543,6 +1543,10 @@ def main():
>                   insntype = 'uint64_t'
>                   insnmask = 0xffffffffffffffff
>                   bitop_width = 64
> +            elif insnwidth == 48:
> +                insntype = 'uint64_t'
> +                insnmask = 0xffffffffffff
> +                bitop_width = 64
>               elif insnwidth != 32:
>                   error(0, 'cannot handle insns of width', insnwidth)
>           elif o == '--test-for-error':

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

This is probably simpler than falling back to the variable-length decodetree stuff.


r~

[PATCH v3 10/16] target/mips: Introduce decode tree bindings for nanoMIPS ISA

[Philippe Mathieu-Daudé]

Introduce the nanoMIPS decodetree configs for the 16-bit,
32-bit and 48-bit instructions.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/tcg/translate.h              |  3 +++
 target/mips/tcg/nanomips16.decode        |  8 ++++++++
 target/mips/tcg/nanomips32.decode        |  8 ++++++++
 target/mips/tcg/nanomips48.decode        |  8 ++++++++
 target/mips/tcg/nanomips_translate.c     | 15 +++++++++++++++
 target/mips/tcg/nanomips_translate.c.inc | 16 ++++++++++++++++
 target/mips/tcg/meson.build              |  4 ++++
 7 files changed, 62 insertions(+)
 create mode 100644 target/mips/tcg/nanomips16.decode
 create mode 100644 target/mips/tcg/nanomips32.decode
 create mode 100644 target/mips/tcg/nanomips48.decode
 create mode 100644 target/mips/tcg/nanomips_translate.c

diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 2a079cb28d9..7fe34a1d891 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -224,6 +224,9 @@ bool decode_64bit_enabled(DisasContext *ctx);
 /* decodetree generated */
 bool decode_isa_micromips16(DisasContext *ctx, uint16_t insn);
 bool decode_isa_micromips32(DisasContext *ctx, uint32_t insn);
+bool decode_isa_nanomips16(DisasContext *ctx, uint16_t insn);
+bool decode_isa_nanomips32(DisasContext *ctx, uint32_t insn);
+bool decode_isa_nanomips48(DisasContext *ctx, uint64_t insn);
 bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
 bool decode_ase_mips16e_16(DisasContext *ctx, uint16_t insn);
 bool decode_ase_mips16e_32(DisasContext *ctx, uint32_t insn);
diff --git a/target/mips/tcg/nanomips16.decode b/target/mips/tcg/nanomips16.decode
new file mode 100644
index 00000000000..81fdc68e98b
--- /dev/null
+++ b/target/mips/tcg/nanomips16.decode
@@ -0,0 +1,8 @@
+# nanoMIPS32 16-bit instruction set extensions
+#
+# Copyright (C) 2021  Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference: nanoMIPS32 Instruction Set Technical Reference Manual
+#            (Document Number: MD01247)
diff --git a/target/mips/tcg/nanomips32.decode b/target/mips/tcg/nanomips32.decode
new file mode 100644
index 00000000000..9cecf1e13d3
--- /dev/null
+++ b/target/mips/tcg/nanomips32.decode
@@ -0,0 +1,8 @@
+# nanoMIPS32 32-bit instruction set extensions
+#
+# Copyright (C) 2021  Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference: nanoMIPS32 Instruction Set Technical Reference Manual
+#            (Document Number: MD01247)
diff --git a/target/mips/tcg/nanomips48.decode b/target/mips/tcg/nanomips48.decode
new file mode 100644
index 00000000000..696cc15607a
--- /dev/null
+++ b/target/mips/tcg/nanomips48.decode
@@ -0,0 +1,8 @@
+# nanoMIPS32 48-bit instruction set extensions
+#
+# Copyright (C) 2021  Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference: nanoMIPS32 Instruction Set Technical Reference Manual
+#            (Document Number: MD01247)
diff --git a/target/mips/tcg/nanomips_translate.c b/target/mips/tcg/nanomips_translate.c
new file mode 100644
index 00000000000..335a32845ed
--- /dev/null
+++ b/target/mips/tcg/nanomips_translate.c
@@ -0,0 +1,15 @@
+/*
+ * MIPS emulation for QEMU - nanoMIPS translation routines
+ *
+ * Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org>
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "translate.h"
+
+/* Include the auto-generated decoders.  */
+#include "decode-nanomips16.c.inc"
+#include "decode-nanomips32.c.inc"
+#include "decode-nanomips48.c.inc"
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index e0a920bdb3a..5d021f01128 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -4480,6 +4480,22 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
 
     opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
     ctx->opcode = opcode;
+    if (decode_isa_nanomips16(ctx, opcode)) {
+        return 2;
+    }
+
+    opcode <<= 16;
+    opcode |= translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
+    if (decode_isa_nanomips32(ctx, opcode)) {
+        return 4;
+    }
+
+    opcode <<= 16;
+    opcode |= translator_lduw(env, &ctx->base, ctx->base.pc_next + 4);
+    if (decode_isa_nanomips48(ctx, opcode)) {
+        return 6;
+    }
+
     rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode));
     rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
     rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD3(ctx->opcode));
diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build
index ca70769912c..f674819e6a8 100644
--- a/target/mips/tcg/meson.build
+++ b/target/mips/tcg/meson.build
@@ -4,6 +4,9 @@ gen = [
   decodetree.process('micromips16.decode', extra_args: ['--decode=decode_isa_micromips16', '--insnwidth=16']),
   decodetree.process('micromips32.decode', extra_args: ['--decode=decode_isa_micromips32']),
   decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']),
+  decodetree.process('nanomips16.decode', extra_args: ['--decode=decode_isa_nanomips16', '--insnwidth=16']),
+  decodetree.process('nanomips32.decode', extra_args: ['--decode=decode_isa_nanomips32']),
+  decodetree.process('nanomips48.decode', extra_args: ['--decode=decode_isa_nanomips48', '--insnwidth=48']),
   decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'),
   decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
   decodetree.process('vr54xx.decode', extra_args: '--decode=decode_ext_vr54xx'),
@@ -24,6 +27,7 @@ mips_ss.add(files(
   'mips16e_translate.c',
   'msa_helper.c',
   'msa_translate.c',
+  'nanomips_translate.c',
   'op_helper.c',
   'rel6_translate.c',
   'translate.c',
-- 
2.45.2

Re: [PATCH v3 10/16] target/mips: Introduce decode tree bindings for nanoMIPS ISA

[Richard Henderson]

On 11/26/24 07:59, Philippe Mathieu-Daudé wrote:
> @@ -4480,6 +4480,22 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
>   
>       opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
>       ctx->opcode = opcode;
> +    if (decode_isa_nanomips16(ctx, opcode)) {
> +        return 2;
> +    }
> +
> +    opcode <<= 16;
> +    opcode |= translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
> +    if (decode_isa_nanomips32(ctx, opcode)) {
> +        return 4;
> +    }
> +
> +    opcode <<= 16;
> +    opcode |= translator_lduw(env, &ctx->base, ctx->base.pc_next + 4);
> +    if (decode_isa_nanomips48(ctx, opcode)) {
> +        return 6;
> +    }

Oof.  Trivial to determine 32 vs 48 bit (NM_P48I), but much harder for 16 vs 32 bit.

Maybe this *would* be easier with decodetree --varinsnwidth.


r~

[PATCH v3 11/16] target/mips: Convert microMIPS LSA opcode to decodetree

[Philippe Mathieu-Daudé]

Simply call the generic gen_lsa(), using the plus_1()
helper to add 1 to the shift amount.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241112172022.88348-6-philmd@linaro.org>
---
 target/mips/tcg/micromips32.decode        |  8 ++++++++
 target/mips/tcg/micromips_translate.c     | 10 ++++++++++
 target/mips/tcg/micromips_translate.c.inc |  5 -----
 3 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/target/mips/tcg/micromips32.decode b/target/mips/tcg/micromips32.decode
index 333ab0969ca..0df9f0c59ff 100644
--- a/target/mips/tcg/micromips32.decode
+++ b/target/mips/tcg/micromips32.decode
@@ -9,3 +9,11 @@
 #            (Document Number: MD00582)
 #            microMIPS64 Instruction Set
 #            (Document Number: MD00594)
+
+&r                  rs rt rd sa
+
+%lsa_sa             9:2  !function=plus_1
+
+@lsa                ...... rt:5  rs:5  rd:5  .. ... ......  &r sa=%lsa_sa
+
+LSA                 000000 ..... ..... ..... .. 000 001111  @lsa
diff --git a/target/mips/tcg/micromips_translate.c b/target/mips/tcg/micromips_translate.c
index 49e90e7eca2..f0b5dbf655d 100644
--- a/target/mips/tcg/micromips_translate.c
+++ b/target/mips/tcg/micromips_translate.c
@@ -9,6 +9,16 @@
 #include "qemu/osdep.h"
 #include "translate.h"
 
+static inline int plus_1(DisasContext *ctx, int x)
+{
+    return x + 1;
+}
+
 /* Include the auto-generated decoders.  */
 #include "decode-micromips16.c.inc"
 #include "decode-micromips32.c.inc"
+
+static bool trans_LSA(DisasContext *ctx, arg_r *a)
+{
+    return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
+}
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index 7a884222eed..73394554509 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -191,7 +191,6 @@ enum {
     /* The following can be distinguished by their lower 6 bits. */
     BREAK32 = 0x07,
     INS = 0x0c,
-    LSA = 0x0f,
     ALIGN = 0x1f,
     EXT = 0x2c,
     POOL32AXF = 0x3c,
@@ -1793,10 +1792,6 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
         case INS:
             gen_bitops(ctx, OPC_INS, rt, rs, rr, rd);
             return;
-        case LSA:
-            check_insn(ctx, ISA_MIPS_R6);
-            gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) + 1);
-            break;
         case ALIGN:
             check_insn(ctx, ISA_MIPS_R6);
             gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2));
-- 
2.45.2

[PATCH v3 12/16] target/mips: Convert nanoMIPS LSA opcode to decodetree

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Simply call the generic gen_lsa() helper.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241112172022.88348-7-philmd@linaro.org>
---
 target/mips/tcg/nanomips32.decode        | 6 ++++++
 target/mips/tcg/nanomips_translate.c     | 7 +++++++
 target/mips/tcg/nanomips_translate.c.inc | 4 ----
 3 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/target/mips/tcg/nanomips32.decode b/target/mips/tcg/nanomips32.decode
index 9cecf1e13d3..96d2299bfb0 100644
--- a/target/mips/tcg/nanomips32.decode
+++ b/target/mips/tcg/nanomips32.decode
@@ -6,3 +6,9 @@
 #
 # Reference: nanoMIPS32 Instruction Set Technical Reference Manual
 #            (Document Number: MD01247)
+
+&r                  rs rt rd sa
+
+@lsa                ...... rt:5 rs:5 rd:5 sa:2 --- ... ...  &r
+
+LSA                 001000 ..... ..... ..... .. ... 001 111 @lsa
diff --git a/target/mips/tcg/nanomips_translate.c b/target/mips/tcg/nanomips_translate.c
index 335a32845ed..3e77fcd23d3 100644
--- a/target/mips/tcg/nanomips_translate.c
+++ b/target/mips/tcg/nanomips_translate.c
@@ -13,3 +13,10 @@
 #include "decode-nanomips16.c.inc"
 #include "decode-nanomips32.c.inc"
 #include "decode-nanomips48.c.inc"
+
+static bool trans_LSA(DisasContext *ctx, arg_r *a)
+{
+    gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
+
+    return true;
+}
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index 5d021f01128..0627f01c19e 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -399,7 +399,6 @@ enum {
 /* POOL32A7 instruction pool */
 enum {
     NM_P_LSX        = 0x00,
-    NM_LSA          = 0x01,
     NM_EXTW         = 0x03,
     NM_POOL32AXF    = 0x07,
 };
@@ -3625,9 +3624,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
             case NM_P_LSX:
                 gen_p_lsx(ctx, rd, rs, rt);
                 break;
-            case NM_LSA:
-                gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2));
-                break;
             case NM_EXTW:
                 gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5));
                 break;
-- 
2.45.2

[PATCH v3 13/16] target/mips: Add gen_li() helper

[Philippe Mathieu-Daudé]

gen_li() is the trivial 'Load Immediate' instruction.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/tcg/translate.h        |  1 +
 target/mips/tcg/comput_translate.c | 21 +++++++++++++++++++++
 target/mips/tcg/meson.build        |  1 +
 3 files changed, 23 insertions(+)
 create mode 100644 target/mips/tcg/comput_translate.c

diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 7fe34a1d891..222fa9e1e8b 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -168,6 +168,7 @@ void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
 void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
 int get_fp_bit(int cc);
 
+void gen_li(DisasContext *ctx, int rd, int imm);
 void gen_lx(DisasContext *ctx, int rd, int base, int index, MemOp mop);
 void gen_ldxs(DisasContext *ctx, int base, int index, int rd);
 void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int bp);
diff --git a/target/mips/tcg/comput_translate.c b/target/mips/tcg/comput_translate.c
new file mode 100644
index 00000000000..3414cc079af
--- /dev/null
+++ b/target/mips/tcg/comput_translate.c
@@ -0,0 +1,21 @@
+/*
+ * MIPS emulation for QEMU - computational translation routines
+ *
+ * Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org>
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "translate.h"
+
+/* logical instructions */
+
+void gen_li(DisasContext *ctx, int rd, int imm)
+{
+    if (rd == 0) {
+        /* Treat as NOP. */
+        return;
+    }
+    tcg_gen_movi_tl(cpu_gpr[rd], imm);
+}
diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build
index f674819e6a8..a46c13f3e75 100644
--- a/target/mips/tcg/meson.build
+++ b/target/mips/tcg/meson.build
@@ -18,6 +18,7 @@ gen = [
 
 mips_ss.add(gen)
 mips_ss.add(files(
+  'comput_translate.c',
   'dsp_helper.c',
   'exception.c',
   'fpu_helper.c',
-- 
2.45.2

Re: [PATCH v3 13/16] target/mips: Add gen_li() helper

[Richard Henderson]

On 11/26/24 07:59, Philippe Mathieu-Daudé wrote:
> gen_li() is the trivial 'Load Immediate' instruction.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/mips/tcg/translate.h        |  1 +
>   target/mips/tcg/comput_translate.c | 21 +++++++++++++++++++++
>   target/mips/tcg/meson.build        |  1 +
>   3 files changed, 23 insertions(+)
>   create mode 100644 target/mips/tcg/comput_translate.c

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[PATCH v3 14/16] target/mips: Convert microMIPS LI opcode to decodetree

[Philippe Mathieu-Daudé]

Once the xlat() and simm7() helpers are added,
the decoding is trivial.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/tcg/micromips16.decode        |  9 +++++++++
 target/mips/tcg/micromips_translate.c     | 19 +++++++++++++++++++
 target/mips/tcg/micromips_translate.c.inc | 12 +-----------
 3 files changed, 29 insertions(+), 11 deletions(-)

diff --git a/target/mips/tcg/micromips16.decode b/target/mips/tcg/micromips16.decode
index d341da16b04..fdc3b131c9c 100644
--- a/target/mips/tcg/micromips16.decode
+++ b/target/mips/tcg/micromips16.decode
@@ -9,3 +9,12 @@
 #            (Document Number: MD00582)
 #            microMIPS64 Instruction Set
 #            (Document Number: MD00594)
+
+&rd_imm         rd imm
+
+%xlat_rd        7:3 !function=xlat
+%simm7          0:7 !function=simm7
+
+@rd_imm7        ...... ... .......          &rd_imm         rd=%xlat_rd imm=%simm7
+
+LI              111011 ... .......          @rd_imm7        # LI16
diff --git a/target/mips/tcg/micromips_translate.c b/target/mips/tcg/micromips_translate.c
index f0b5dbf655d..198eb466057 100644
--- a/target/mips/tcg/micromips_translate.c
+++ b/target/mips/tcg/micromips_translate.c
@@ -9,11 +9,23 @@
 #include "qemu/osdep.h"
 #include "translate.h"
 
+static int xlat(DisasContext *ctx, int x)
+{
+    static const int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
+
+    return map[x];
+}
+
 static inline int plus_1(DisasContext *ctx, int x)
 {
     return x + 1;
 }
 
+static inline int simm7(DisasContext *ctx, int x)
+{
+    return x == 0x7f ? -1 : x;
+}
+
 /* Include the auto-generated decoders.  */
 #include "decode-micromips16.c.inc"
 #include "decode-micromips32.c.inc"
@@ -22,3 +34,10 @@ static bool trans_LSA(DisasContext *ctx, arg_r *a)
 {
     return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
 }
+
+static bool trans_LI(DisasContext *ctx, arg_rd_imm *a)
+{
+    gen_li(ctx, a->rd, a->imm);
+
+    return true;
+}
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index 73394554509..cb98d6af7e4 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -113,7 +113,6 @@ enum {
     BLTZALC = 0x38,
     BLTUC = 0x38,
     SW16 = 0x3a,
-    LI16 = 0x3b,
     JALX32 = 0x3c,
     JAL32 = 0x3d,
     BLEZC = 0x3d,
@@ -3004,7 +3003,7 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx)
         case 2:
         /* LBU16, LHU16, LWSP16, LW16, SB16, SH16, SWSP16, SW16 */
         case 3:
-        /* MOVE16, ANDI16, POOL16D, POOL16E, BEQZ16, BNEZ16, B16, LI16 */
+        /* MOVE16, ANDI16, POOL16D, POOL16E, BEQZ16, BNEZ16, B16 */
             if (ctx->hflags & MIPS_HFLAG_BDS32) {
                 gen_reserved_instruction(ctx);
                 return 2;
@@ -3214,15 +3213,6 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx)
                            (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4);
 
         break;
-    case LI16:
-        {
-            int reg = mmreg(uMIPS_RD(ctx->opcode));
-            int imm = ZIMM(ctx->opcode, 0, 7);
-
-            imm = (imm == 0x7f ? -1 : imm);
-            tcg_gen_movi_tl(cpu_gpr[reg], imm);
-        }
-        break;
     case RES_29:
     case RES_31:
     case RES_39:
-- 
2.45.2

Re: [PATCH v3 14/16] target/mips: Convert microMIPS LI opcode to decodetree

[Richard Henderson]

On 11/26/24 08:00, Philippe Mathieu-Daudé wrote:
> Once the xlat() and simm7() helpers are added,
> the decoding is trivial.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/mips/tcg/micromips16.decode        |  9 +++++++++
>   target/mips/tcg/micromips_translate.c     | 19 +++++++++++++++++++
>   target/mips/tcg/micromips_translate.c.inc | 12 +-----------
>   3 files changed, 29 insertions(+), 11 deletions(-)
> 
> diff --git a/target/mips/tcg/micromips16.decode b/target/mips/tcg/micromips16.decode
> index d341da16b04..fdc3b131c9c 100644
> --- a/target/mips/tcg/micromips16.decode
> +++ b/target/mips/tcg/micromips16.decode
> @@ -9,3 +9,12 @@
>   #            (Document Number: MD00582)
>   #            microMIPS64 Instruction Set
>   #            (Document Number: MD00594)
> +
> +&rd_imm         rd imm
> +
> +%xlat_rd        7:3 !function=xlat
> +%simm7          0:7 !function=simm7

Hmm... simm7 sounds like sign-extended imm7, which this is not.
The encoding appears unique to LI16?  Perhaps just li16_imm7?

> +
> +@rd_imm7        ...... ... .......          &rd_imm         rd=%xlat_rd imm=%simm7

You need not define separate formats when they are one-off.

> +
> +LI              111011 ... .......          @rd_imm7        # LI16
> diff --git a/target/mips/tcg/micromips_translate.c b/target/mips/tcg/micromips_translate.c
> index f0b5dbf655d..198eb466057 100644
> --- a/target/mips/tcg/micromips_translate.c
> +++ b/target/mips/tcg/micromips_translate.c
> @@ -9,11 +9,23 @@
>   #include "qemu/osdep.h"
>   #include "translate.h"
>   
> +static int xlat(DisasContext *ctx, int x)
> +{
> +    static const int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
> +
> +    return map[x];
> +}
> +
>   static inline int plus_1(DisasContext *ctx, int x)
>   {
>       return x + 1;
>   }
>   
> +static inline int simm7(DisasContext *ctx, int x)
> +{
> +    return x == 0x7f ? -1 : x;
> +}

Don't mark inline.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

[PATCH v3 15/16] target/mips: Convert MIPS16e LI opcodes to decodetree

[Philippe Mathieu-Daudé]

Decode the destination register using the xlat() helper.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/tcg/mips16e_16.decode       |  8 ++++++++
 target/mips/tcg/mips16e_32.decode       |  9 +++++++++
 target/mips/tcg/mips16e_translate.c     | 14 ++++++++++++++
 target/mips/tcg/mips16e_translate.c.inc | 11 -----------
 4 files changed, 31 insertions(+), 11 deletions(-)

diff --git a/target/mips/tcg/mips16e_16.decode b/target/mips/tcg/mips16e_16.decode
index 82586493f68..bae7bfbb522 100644
--- a/target/mips/tcg/mips16e_16.decode
+++ b/target/mips/tcg/mips16e_16.decode
@@ -7,3 +7,11 @@
 # Reference: MIPS Architecture for Programmers, Volume IV-a
 #            The MIPS16e Application Specific Extension
 #            (Document Number: MD00076)
+
+&rd_imm         rd imm
+
+%xlat_rx8       8:3  !function=xlat
+
+@ri             ..... ... imm:8             &rd_imm   rd=%xlat_rx8
+
+LI              01101 ... ........          @ri
diff --git a/target/mips/tcg/mips16e_32.decode b/target/mips/tcg/mips16e_32.decode
index fc429049e18..248ee95706d 100644
--- a/target/mips/tcg/mips16e_32.decode
+++ b/target/mips/tcg/mips16e_32.decode
@@ -7,3 +7,12 @@
 # Reference: MIPS Architecture for Programmers, Volume IV-a
 #            The MIPS16e Application Specific Extension
 #            (Document Number: MD00076)
+
+&rd_imm         rd imm                                          !extern
+
+%immx           0:5 21:6 16:5
+%xlat_rx8       8:3  !function=xlat
+
+@ri             ..... ...... ..... ..... ... ... .....          &rd_imm rd=%xlat_rx8 imm=%immx
+
+LI              11110 ...... ..... 01101 ... 000 .....          @ri
diff --git a/target/mips/tcg/mips16e_translate.c b/target/mips/tcg/mips16e_translate.c
index 6de9928b37e..a66f49fe8ed 100644
--- a/target/mips/tcg/mips16e_translate.c
+++ b/target/mips/tcg/mips16e_translate.c
@@ -9,6 +9,20 @@
 #include "qemu/osdep.h"
 #include "translate.h"
 
+static inline int xlat(DisasContext *ctx, int x)
+{
+  static const int map[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
+
+  return map[x];
+}
+
 /* Include the auto-generated decoders.  */
 #include "decode-mips16e_16.c.inc"
 #include "decode-mips16e_32.c.inc"
+
+static bool trans_LI(DisasContext *ctx, arg_rd_imm *a)
+{
+    gen_li(ctx, a->rd, a->imm);
+
+    return true;
+}
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
index a57ae4e95b1..f3f09b164ae 100644
--- a/target/mips/tcg/mips16e_translate.c.inc
+++ b/target/mips/tcg/mips16e_translate.c.inc
@@ -24,7 +24,6 @@ enum {
   M16_OPC_SLTI = 0x0a,
   M16_OPC_SLTIU = 0x0b,
   M16_OPC_I8 = 0x0c,
-  M16_OPC_LI = 0x0d,
   M16_OPC_CMPI = 0x0e,
   M16_OPC_SD = 0x0f,
   M16_OPC_LB = 0x10,
@@ -582,9 +581,6 @@ static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
             break;
         }
         break;
-    case M16_OPC_LI:
-        tcg_gen_movi_tl(cpu_gpr[rx], (uint16_t) imm);
-        break;
     case M16_OPC_CMPI:
         tcg_gen_xori_tl(cpu_gpr[24], cpu_gpr[rx], (uint16_t) imm);
         break;
@@ -839,13 +835,6 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx)
             }
         }
         break;
-    case M16_OPC_LI:
-        {
-            int16_t imm = (uint8_t) ctx->opcode;
-
-            gen_arith_imm(ctx, OPC_ADDIU, rx, 0, imm);
-        }
-        break;
     case M16_OPC_CMPI:
         {
             int16_t imm = (uint8_t) ctx->opcode;
-- 
2.45.2

Re: [PATCH v3 15/16] target/mips: Convert MIPS16e LI opcodes to decodetree

[Richard Henderson]

On 11/26/24 08:00, Philippe Mathieu-Daudé wrote:
> Decode the destination register using the xlat() helper.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/mips/tcg/mips16e_16.decode       |  8 ++++++++
>   target/mips/tcg/mips16e_32.decode       |  9 +++++++++
>   target/mips/tcg/mips16e_translate.c     | 14 ++++++++++++++
>   target/mips/tcg/mips16e_translate.c.inc | 11 -----------
>   4 files changed, 31 insertions(+), 11 deletions(-)
> 
> diff --git a/target/mips/tcg/mips16e_16.decode b/target/mips/tcg/mips16e_16.decode
> index 82586493f68..bae7bfbb522 100644
> --- a/target/mips/tcg/mips16e_16.decode
> +++ b/target/mips/tcg/mips16e_16.decode
> @@ -7,3 +7,11 @@
>   # Reference: MIPS Architecture for Programmers, Volume IV-a
>   #            The MIPS16e Application Specific Extension
>   #            (Document Number: MD00076)
> +
> +&rd_imm         rd imm
> +
> +%xlat_rx8       8:3  !function=xlat
> +
> +@ri             ..... ... imm:8             &rd_imm   rd=%xlat_rx8

mips16e is decent enough to name its instruction formats -- this one is "I8".  You'd do 
well to use those names.


> +
> +LI              01101 ... ........          @ri
> diff --git a/target/mips/tcg/mips16e_32.decode b/target/mips/tcg/mips16e_32.decode
> index fc429049e18..248ee95706d 100644
> --- a/target/mips/tcg/mips16e_32.decode
> +++ b/target/mips/tcg/mips16e_32.decode
> @@ -7,3 +7,12 @@
>   # Reference: MIPS Architecture for Programmers, Volume IV-a
>   #            The MIPS16e Application Specific Extension
>   #            (Document Number: MD00076)
> +
> +&rd_imm         rd imm                                          !extern
> +
> +%immx           0:5 21:6 16:5

The bits are in reverse order.

> +%xlat_rx8       8:3  !function=xlat
> +
> +@ri             ..... ...... ..... ..... ... ... .....          &rd_imm rd=%xlat_rx8 imm=%immx

The format is "EXT-I8", though there appear to be variants where the immediate is signed 
(ADDIU) or unsigned (LI).

> @@ -9,6 +9,20 @@
>   #include "qemu/osdep.h"
>   #include "translate.h"
>   
> +static inline int xlat(DisasContext *ctx, int x)
> +{
> +  static const int map[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
> +
> +  return map[x];
> +}

Don't mark inline.

> +
>   /* Include the auto-generated decoders.  */
>   #include "decode-mips16e_16.c.inc"
>   #include "decode-mips16e_32.c.inc"
> +
> +static bool trans_LI(DisasContext *ctx, arg_rd_imm *a)
> +{
> +    gen_li(ctx, a->rd, a->imm);
> +
> +    return true;
> +}

We nearly have the right set of decodetree options to allow these trans_* functions to be 
shared:

     --translate=trans

which will drop the 'static'.  But we do not currently have an option to emit a separate 
header with all of the declarations.  That should be trivial.


r~

[PATCH v3 16/16] target/mips: Convert nanoMIPS LI opcodes to decodetree

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/tcg/nanomips16.decode        |  8 ++++++++
 target/mips/tcg/nanomips48.decode        |  8 ++++++++
 target/mips/tcg/nanomips_translate.c     | 21 +++++++++++++++++++++
 target/mips/tcg/nanomips_translate.c.inc | 17 -----------------
 4 files changed, 37 insertions(+), 17 deletions(-)

diff --git a/target/mips/tcg/nanomips16.decode b/target/mips/tcg/nanomips16.decode
index 81fdc68e98b..12815161d9c 100644
--- a/target/mips/tcg/nanomips16.decode
+++ b/target/mips/tcg/nanomips16.decode
@@ -6,3 +6,11 @@
 #
 # Reference: nanoMIPS32 Instruction Set Technical Reference Manual
 #            (Document Number: MD01247)
+
+&rd_imm             rd imm not_in_nms
+
+%s_eu               0:s7 !function=s_eu
+
+@rt3_s          ...... rd:3 .......         &rd_imm         imm=%s_eu
+
+LI              110100 ... .......          @rt3_s          not_in_nms=0        # LI[16]
diff --git a/target/mips/tcg/nanomips48.decode b/target/mips/tcg/nanomips48.decode
index 696cc15607a..778bff4ec06 100644
--- a/target/mips/tcg/nanomips48.decode
+++ b/target/mips/tcg/nanomips48.decode
@@ -6,3 +6,11 @@
 #
 # Reference: nanoMIPS32 Instruction Set Technical Reference Manual
 #            (Document Number: MD01247)
+
+&rd_imm     rd  imm not_in_nms                                       !extern
+
+%imm        16:16 0:s16
+
+@rd_imm     ...... rd:5  ..... ................ ................    &rd_imm imm=%imm
+
+LI          011000 ..... 00000 ................ ................    @rd_imm not_in_nms=1
diff --git a/target/mips/tcg/nanomips_translate.c b/target/mips/tcg/nanomips_translate.c
index 3e77fcd23d3..aee0606e4d4 100644
--- a/target/mips/tcg/nanomips_translate.c
+++ b/target/mips/tcg/nanomips_translate.c
@@ -9,14 +9,35 @@
 #include "qemu/osdep.h"
 #include "translate.h"
 
+static inline int s_eu(DisasContext *ctx, int x)
+{
+    return x == 0x7f ? -1 : x;
+}
+
 /* Include the auto-generated decoders.  */
 #include "decode-nanomips16.c.inc"
 #include "decode-nanomips32.c.inc"
 #include "decode-nanomips48.c.inc"
 
+static inline void check_nms(DisasContext *ctx, bool not_in_nms)
+{
+    if (not_in_nms && unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) {
+        gen_reserved_instruction(ctx);
+    }
+}
+
 static bool trans_LSA(DisasContext *ctx, arg_r *a)
 {
     gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
 
     return true;
 }
+
+static bool trans_LI(DisasContext *ctx, arg_rd_imm *a)
+{
+    check_nms(ctx, a->not_in_nms);
+
+    gen_li(ctx, a->rd, a->imm);
+
+    return true;
+}
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index 0627f01c19e..e3d81d9e15b 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -57,7 +57,6 @@ enum {
 
     NM_POOL32S      = 0x30,
     NM_P_BRI        = 0x32,
-    NM_LI16         = 0x34,
     NM_SWGP16       = 0x35,
     NM_P16_BR       = 0x36,
 
@@ -86,7 +85,6 @@ enum {
 
 /* P48I instruction pool */
 enum {
-    NM_LI48        = 0x00,
     NM_ADDIU48     = 0x01,
     NM_ADDIUGP48   = 0x02,
     NM_ADDIUPC48   = 0x03,
@@ -3664,12 +3662,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
             insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 4);
             target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16;
             switch (extract32(ctx->opcode, 16, 5)) {
-            case NM_LI48:
-                check_nms(ctx);
-                if (rt != 0) {
-                    tcg_gen_movi_tl(cpu_gpr[rt], addr_off);
-                }
-                break;
             case NM_ADDIU48:
                 check_nms(ctx);
                 if (rt != 0) {
@@ -4620,15 +4612,6 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
             break;
         }
         break;
-    case NM_LI16:
-        {
-            imm = extract32(ctx->opcode, 0, 7);
-            imm = (imm == 0x7f ? -1 : imm);
-            if (rt != 0) {
-                tcg_gen_movi_tl(cpu_gpr[rt], imm);
-            }
-        }
-        break;
     case NM_ANDI16:
         {
             uint32_t u = extract32(ctx->opcode, 0, 4);
-- 
2.45.2

Re: [PATCH v3 16/16] target/mips: Convert nanoMIPS LI opcodes to decodetree

[Richard Henderson]

On 11/26/24 08:00, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/mips/tcg/nanomips16.decode        |  8 ++++++++
>   target/mips/tcg/nanomips48.decode        |  8 ++++++++
>   target/mips/tcg/nanomips_translate.c     | 21 +++++++++++++++++++++
>   target/mips/tcg/nanomips_translate.c.inc | 17 -----------------
>   4 files changed, 37 insertions(+), 17 deletions(-)
> 
> diff --git a/target/mips/tcg/nanomips16.decode b/target/mips/tcg/nanomips16.decode
> index 81fdc68e98b..12815161d9c 100644
> --- a/target/mips/tcg/nanomips16.decode
> +++ b/target/mips/tcg/nanomips16.decode
> @@ -6,3 +6,11 @@
>   #
>   # Reference: nanoMIPS32 Instruction Set Technical Reference Manual
>   #            (Document Number: MD01247)
> +
> +&rd_imm             rd imm not_in_nms
> +
> +%s_eu               0:s7 !function=s_eu
> +
> +@rt3_s          ...... rd:3 .......         &rd_imm         imm=%s_eu
> +
> +LI              110100 ... .......          @rt3_s          not_in_nms=0        # LI[16]

I think probably it is a mistake to include not_in_nms in the argument set.
I think it would be better to have separate trans_LI and trans_LI_nnms.


> diff --git a/target/mips/tcg/nanomips48.decode b/target/mips/tcg/nanomips48.decode
> index 696cc15607a..778bff4ec06 100644
> --- a/target/mips/tcg/nanomips48.decode
> +++ b/target/mips/tcg/nanomips48.decode
> @@ -6,3 +6,11 @@
>   #
>   # Reference: nanoMIPS32 Instruction Set Technical Reference Manual
>   #            (Document Number: MD01247)
> +
> +&rd_imm     rd  imm not_in_nms                                       !extern
> +
> +%imm        16:16 0:s16

These subfields are swapped.

That said...  I will note that all 48-bit instructions are 16-bit plus a 32-bit immediate. 
There's a trick we used over in target/rx/ where we (ab)use !function to read immediate 
data. Using this would mean that we can treat all of these 48-bit insns as 16-bit insns.

%i48       !func=i48
@ri48      ...... rt:5  .....  &ri imm=%i48

LI_nnmi    011000 ..... 00000  @ri48


r~

Re: [PATCH v3 00/16] target/mips: Convert nanoMIPS LSA opcode to decodetree

[Philippe Mathieu-Daudé]

On 26/11/24 14:59, Philippe Mathieu-Daudé wrote:
> Since v2:
> - Fix translator_ld() calls
> - Add support for 48-bit nanoMIPS opcodes
> - Convert Load Immediate opcode
> ---
> 
> Prepare buildsys to decode micro/nanoMIPS opcodes using
> the decodetree script.
> Simplify gen_lsa/dsa() and convert micro/nanoMIPS LSA
> opcode to decodetree.
> 
> Philippe Mathieu-Daudé (16):
>    target/mips: Extract gen_base_index_addr() helper
>    target/mips: Extract generic gen_lx() helper
>    target/mips: Convert Octeon LX instructions to decodetree

>    target/mips: Have gen_[d]lsa() callers add 1 to shift amount argument

Patches 1-3 & 5 queued.