* [Qemu-devel] [PATCH v2 1/4] m68k: Add NeXTcube framebuffer device emulation
2019-06-28 18:15 [Qemu-devel] [PATCH v2 0/4] m68k: Add basic support for the NeXTcube machine Thomas Huth
@ 2019-06-28 18:15 ` Thomas Huth
2019-06-29 11:53 ` Philippe Mathieu-Daudé
2019-06-28 18:15 ` [Qemu-devel] [PATCH v2 2/4] m68k: Add NeXTcube keyboard device Thomas Huth
` (3 subsequent siblings)
4 siblings, 1 reply; 17+ messages in thread
From: Thomas Huth @ 2019-06-28 18:15 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Philippe Mathieu-Daudé, Laurent Vivier
The NeXTcube uses a linear framebuffer with 4 greyscale colors and
a fixed resolution of 1120 * 832.
This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at
https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-fb.c
and altered to fit the latest interface of the current QEMU (e.g.
the device has been "qdev"-ified etc.).
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
---
default-configs/m68k-softmmu.mak | 1 +
hw/display/Makefile.objs | 1 +
hw/display/next-fb.c | 157 +++++++++++++++++++++++++++++++
hw/m68k/Kconfig | 4 +
include/hw/m68k/next-cube.h | 8 ++
5 files changed, 171 insertions(+)
create mode 100644 hw/display/next-fb.c
create mode 100644 include/hw/m68k/next-cube.h
diff --git a/default-configs/m68k-softmmu.mak b/default-configs/m68k-softmmu.mak
index 4049a8f2ba..d67ab8b96d 100644
--- a/default-configs/m68k-softmmu.mak
+++ b/default-configs/m68k-softmmu.mak
@@ -6,3 +6,4 @@ CONFIG_SEMIHOSTING=y
#
CONFIG_AN5206=y
CONFIG_MCF5208=y
+CONFIG_NEXTCUBE=y
diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
index a64998fc7b..8d1c71026d 100644
--- a/hw/display/Makefile.objs
+++ b/hw/display/Makefile.objs
@@ -38,6 +38,7 @@ obj-$(CONFIG_RASPI) += bcm2835_fb.o
obj-$(CONFIG_SM501) += sm501.o
obj-$(CONFIG_TCX) += tcx.o
obj-$(CONFIG_CG3) += cg3.o
+obj-$(CONFIG_NEXTCUBE) += next-fb.o
obj-$(CONFIG_VGA) += vga.o
diff --git a/hw/display/next-fb.c b/hw/display/next-fb.c
new file mode 100644
index 0000000000..740102d7e9
--- /dev/null
+++ b/hw/display/next-fb.c
@@ -0,0 +1,157 @@
+/*
+ * NeXT Cube/Station Framebuffer Emulation
+ *
+ * Copyright (c) 2011 Bryce Lanham
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "ui/console.h"
+#include "hw/hw.h"
+#include "hw/boards.h"
+#include "hw/loader.h"
+#include "hw/display/framebuffer.h"
+#define BITS 8
+#include "ui/pixel_ops.h"
+#include "hw/m68k/next-cube.h"
+
+#define TYPE_NEXTFB "next-fb"
+#define NEXTFB(obj) OBJECT_CHECK(NeXTFbState, (obj), TYPE_NEXTFB)
+
+struct NeXTFbState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion fb_mr;
+ MemoryRegionSection fbsection;
+ QemuConsole *con;
+
+ uint32_t pitch;
+ uint32_t cols;
+ uint32_t rows;
+ int invalidate;
+};
+typedef struct NeXTFbState NeXTFbState;
+
+static void nextfb_draw_line(void *opaque, uint8_t *d, const uint8_t *s,
+ int width, int pitch)
+{
+ NeXTFbState *nfbstate = NEXTFB(opaque);
+ static const uint32_t pal[4] = {
+ 0xFFFFFFFF, 0xFFAAAAAA, 0xFF555555, 0xFF000000
+ };
+ uint32_t *buf = (uint32_t *)d;
+ int i = 0;
+
+ for (i = 0; i < nfbstate->cols / 4; i++) {
+ int j = i * 4;
+ uint8_t src = s[i];
+ buf[j + 3] = pal[src & 0x3];
+ src >>= 2;
+ buf[j + 2] = pal[src & 0x3];
+ src >>= 2;
+ buf[j + 1] = pal[src & 0x3];
+ src >>= 2;
+ buf[j + 0] = pal[src & 0x3];
+ }
+}
+
+static void nextfb_update(void *opaque)
+{
+ NeXTFbState *s = NEXTFB(opaque);
+ int dest_width = 4;
+ int src_width;
+ int first = 0;
+ int last = 0;
+ DisplaySurface *surface = qemu_console_surface(s->con);
+
+ src_width = s->cols / 4 + 8;
+ dest_width = s->cols * 4;
+
+ if (s->invalidate) {
+ framebuffer_update_memory_section(&s->fbsection, &s->fb_mr, 0,
+ s->cols, src_width);
+ s->invalidate = 0;
+ }
+
+ framebuffer_update_display(surface, &s->fbsection, 1120, 832,
+ src_width, dest_width, 0, 1, nextfb_draw_line,
+ s, &first, &last);
+
+ dpy_gfx_update(s->con, 0, 0, 1120, 832);
+}
+
+static void nextfb_invalidate(void *opaque)
+{
+ NeXTFbState *s = NEXTFB(opaque);
+ s->invalidate = 1;
+}
+
+static const GraphicHwOps nextfb_ops = {
+ .invalidate = nextfb_invalidate,
+ .gfx_update = nextfb_update,
+};
+
+static void nextfb_realize(DeviceState *dev, Error **errp)
+{
+ NeXTFbState *s = NEXTFB(dev);
+
+ memory_region_init_ram(&s->fb_mr, OBJECT(dev), "next-video", 0x1CB100,
+ &error_fatal);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->fb_mr);
+
+ s->invalidate = 1;
+ s->cols = 1120;
+ s->rows = 832;
+
+ s->con = graphic_console_init(dev, 0, &nextfb_ops, s);
+ qemu_console_resize(s->con, s->cols, s->rows);
+}
+
+static void nextfb_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
+ dc->realize = nextfb_realize;
+}
+
+static const TypeInfo nextfb_info = {
+ .name = TYPE_NEXTFB,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(NeXTFbState),
+ .class_init = nextfb_class_init,
+};
+
+static void nextfb_register_types(void)
+{
+ type_register_static(&nextfb_info);
+}
+
+type_init(nextfb_register_types)
+
+void nextfb_init(void)
+{
+ DeviceState *dev;
+
+ dev = qdev_create(NULL, TYPE_NEXTFB);
+ qdev_init_nofail(dev);
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xB000000);
+}
diff --git a/hw/m68k/Kconfig b/hw/m68k/Kconfig
index 49ef0b3f6d..ec58a2eb06 100644
--- a/hw/m68k/Kconfig
+++ b/hw/m68k/Kconfig
@@ -7,3 +7,7 @@ config MCF5208
bool
select COLDFIRE
select PTIMER
+
+config NEXTCUBE
+ bool
+ select FRAMEBUFFER
diff --git a/include/hw/m68k/next-cube.h b/include/hw/m68k/next-cube.h
new file mode 100644
index 0000000000..cf07243bda
--- /dev/null
+++ b/include/hw/m68k/next-cube.h
@@ -0,0 +1,8 @@
+
+#ifndef NEXT_CUBE_H
+#define NEXT_CUBE_H
+
+/* next-fb.c */
+void nextfb_init(void);
+
+#endif /* NEXT_CUBE_H */
--
2.21.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH v2 1/4] m68k: Add NeXTcube framebuffer device emulation
2019-06-28 18:15 ` [Qemu-devel] [PATCH v2 1/4] m68k: Add NeXTcube framebuffer device emulation Thomas Huth
@ 2019-06-29 11:53 ` Philippe Mathieu-Daudé
2019-06-29 17:45 ` Thomas Huth
0 siblings, 1 reply; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-06-29 11:53 UTC (permalink / raw)
To: Thomas Huth, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Laurent Vivier
Hi Thomas,
On 6/28/19 8:15 PM, Thomas Huth wrote:
> The NeXTcube uses a linear framebuffer with 4 greyscale colors and
> a fixed resolution of 1120 * 832.
> This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at
>
> https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-fb.c
Please use SHA1 for reference (unlikely case of Bryce pushing a new
version to his repo):
https://github.com/blanham/qemu-NeXT/blob/34f4323/hw/next-fb.c
>
> and altered to fit the latest interface of the current QEMU (e.g.
> the device has been "qdev"-ified etc.).
>
> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
> ---
> default-configs/m68k-softmmu.mak | 1 +
> hw/display/Makefile.objs | 1 +
> hw/display/next-fb.c | 157 +++++++++++++++++++++++++++++++
> hw/m68k/Kconfig | 4 +
> include/hw/m68k/next-cube.h | 8 ++
> 5 files changed, 171 insertions(+)
> create mode 100644 hw/display/next-fb.c
> create mode 100644 include/hw/m68k/next-cube.h
>
> diff --git a/default-configs/m68k-softmmu.mak b/default-configs/m68k-softmmu.mak
> index 4049a8f2ba..d67ab8b96d 100644
> --- a/default-configs/m68k-softmmu.mak
> +++ b/default-configs/m68k-softmmu.mak
> @@ -6,3 +6,4 @@ CONFIG_SEMIHOSTING=y
> #
> CONFIG_AN5206=y
> CONFIG_MCF5208=y
> +CONFIG_NEXTCUBE=y
> diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
> index a64998fc7b..8d1c71026d 100644
> --- a/hw/display/Makefile.objs
> +++ b/hw/display/Makefile.objs
> @@ -38,6 +38,7 @@ obj-$(CONFIG_RASPI) += bcm2835_fb.o
> obj-$(CONFIG_SM501) += sm501.o
> obj-$(CONFIG_TCX) += tcx.o
> obj-$(CONFIG_CG3) += cg3.o
> +obj-$(CONFIG_NEXTCUBE) += next-fb.o
>
> obj-$(CONFIG_VGA) += vga.o
>
> diff --git a/hw/display/next-fb.c b/hw/display/next-fb.c
> new file mode 100644
> index 0000000000..740102d7e9
> --- /dev/null
> +++ b/hw/display/next-fb.c
> @@ -0,0 +1,157 @@
> +/*
> + * NeXT Cube/Station Framebuffer Emulation
> + *
> + * Copyright (c) 2011 Bryce Lanham
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "ui/console.h"
> +#include "hw/hw.h"
> +#include "hw/boards.h"
> +#include "hw/loader.h"
> +#include "hw/display/framebuffer.h"
> +#define BITS 8
'BITS' is not used, remove?
> +#include "ui/pixel_ops.h"
> +#include "hw/m68k/next-cube.h"
> +
> +#define TYPE_NEXTFB "next-fb"
> +#define NEXTFB(obj) OBJECT_CHECK(NeXTFbState, (obj), TYPE_NEXTFB)
> +
> +struct NeXTFbState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion fb_mr;
> + MemoryRegionSection fbsection;
> + QemuConsole *con;
> +
> + uint32_t pitch;
> + uint32_t cols;
> + uint32_t rows;
> + int invalidate;
> +};
> +typedef struct NeXTFbState NeXTFbState;
> +
> +static void nextfb_draw_line(void *opaque, uint8_t *d, const uint8_t *s,
> + int width, int pitch)
> +{
> + NeXTFbState *nfbstate = NEXTFB(opaque);
> + static const uint32_t pal[4] = {
> + 0xFFFFFFFF, 0xFFAAAAAA, 0xFF555555, 0xFF000000
> + };
> + uint32_t *buf = (uint32_t *)d;
> + int i = 0;
> +
> + for (i = 0; i < nfbstate->cols / 4; i++) {
> + int j = i * 4;
> + uint8_t src = s[i];
> + buf[j + 3] = pal[src & 0x3];
0x3 -> 3?
or 0b11 :)
> + src >>= 2;
> + buf[j + 2] = pal[src & 0x3];
> + src >>= 2;
> + buf[j + 1] = pal[src & 0x3];
> + src >>= 2;
> + buf[j + 0] = pal[src & 0x3];
> + }
> +}
> +
> +static void nextfb_update(void *opaque)
> +{
> + NeXTFbState *s = NEXTFB(opaque);
> + int dest_width = 4;
> + int src_width;
> + int first = 0;
> + int last = 0;
> + DisplaySurface *surface = qemu_console_surface(s->con);
> +
> + src_width = s->cols / 4 + 8;
> + dest_width = s->cols * 4;
Since those are currently const, should we move them to NeXTFbState
and initialize them in nextfb_realize()?
> +
> + if (s->invalidate) {
> + framebuffer_update_memory_section(&s->fbsection, &s->fb_mr, 0,
> + s->cols, src_width);
> + s->invalidate = 0;
> + }
> +
> + framebuffer_update_display(surface, &s->fbsection, 1120, 832,
1120 -> s->cols?
832 -> s->rows?
> + src_width, dest_width, 0, 1, nextfb_draw_line,
> + s, &first, &last);
> +
> + dpy_gfx_update(s->con, 0, 0, 1120, 832);
Ditto.
> +}
> +
> +static void nextfb_invalidate(void *opaque)
> +{
> + NeXTFbState *s = NEXTFB(opaque);
> + s->invalidate = 1;
> +}
> +
> +static const GraphicHwOps nextfb_ops = {
> + .invalidate = nextfb_invalidate,
> + .gfx_update = nextfb_update,
> +};
> +
> +static void nextfb_realize(DeviceState *dev, Error **errp)
> +{
> + NeXTFbState *s = NEXTFB(dev);
> +
> + memory_region_init_ram(&s->fb_mr, OBJECT(dev), "next-video", 0x1CB100,
> + &error_fatal);
2 bits * cols * rows = 2 * 832 * 1120 = 0x1c7000
0x1cb100 - 0x1c7000 = 0x4100
Any idea what are these 16K + 256 extra bytes for?
Anyway we have 2MB of VRAM on the hardware here, right?
If so you should replace 0x1CB100 -> 2 * MiB.
> + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->fb_mr);
> +
> + s->invalidate = 1;
> + s->cols = 1120;
> + s->rows = 832;
> +
> + s->con = graphic_console_init(dev, 0, &nextfb_ops, s);
> + qemu_console_resize(s->con, s->cols, s->rows);
> +}
> +
> +static void nextfb_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
> + dc->realize = nextfb_realize;
> +}
> +
> +static const TypeInfo nextfb_info = {
> + .name = TYPE_NEXTFB,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(NeXTFbState),
> + .class_init = nextfb_class_init,
> +};
> +
> +static void nextfb_register_types(void)
> +{
> + type_register_static(&nextfb_info);
> +}
> +
> +type_init(nextfb_register_types)
> +
> +void nextfb_init(void)
> +{
> + DeviceState *dev;
> +
> + dev = qdev_create(NULL, TYPE_NEXTFB);
> + qdev_init_nofail(dev);
> +
> + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xB000000);
I'd appreciate this written as 0x0B000000 (32-bit address range).
Should you map the aliased VRAM regions here too?
for (int i = 0; i <= 4; i++) {
sysbus_mmio_map(SYS_BUS_DEVICE(dev), i,
0x0b000000 + 0x01000000 * i);
}
Anyway nextfb_init() content is this is board-specific code, not
related to the device. Can you move it there?
Thanks,
Phil.
> +}
> diff --git a/hw/m68k/Kconfig b/hw/m68k/Kconfig
> index 49ef0b3f6d..ec58a2eb06 100644
> --- a/hw/m68k/Kconfig
> +++ b/hw/m68k/Kconfig
> @@ -7,3 +7,7 @@ config MCF5208
> bool
> select COLDFIRE
> select PTIMER
> +
> +config NEXTCUBE
> + bool
> + select FRAMEBUFFER
> diff --git a/include/hw/m68k/next-cube.h b/include/hw/m68k/next-cube.h
> new file mode 100644
> index 0000000000..cf07243bda
> --- /dev/null
> +++ b/include/hw/m68k/next-cube.h
> @@ -0,0 +1,8 @@
> +
> +#ifndef NEXT_CUBE_H
> +#define NEXT_CUBE_H
> +
> +/* next-fb.c */
> +void nextfb_init(void);
> +
> +#endif /* NEXT_CUBE_H */
>
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH v2 1/4] m68k: Add NeXTcube framebuffer device emulation
2019-06-29 11:53 ` Philippe Mathieu-Daudé
@ 2019-06-29 17:45 ` Thomas Huth
2019-07-02 16:01 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 17+ messages in thread
From: Thomas Huth @ 2019-06-29 17:45 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Laurent Vivier
On 29/06/2019 13.53, Philippe Mathieu-Daudé wrote:
> Hi Thomas,
>
> On 6/28/19 8:15 PM, Thomas Huth wrote:
>> The NeXTcube uses a linear framebuffer with 4 greyscale colors and
>> a fixed resolution of 1120 * 832.
>> This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at
>>
>> https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-fb.c
>
> Please use SHA1 for reference (unlikely case of Bryce pushing a new
> version to his repo):
>
> https://github.com/blanham/qemu-NeXT/blob/34f4323/hw/next-fb.c
But if Bryce ever pushes a new version to his branch, the old SHA IDs
won't be part of a branch anymore, so they will be garbage collected
after a while and the links will become invalid. I think it's better to
refer to the "next-cube" branch.
>> and altered to fit the latest interface of the current QEMU (e.g.
>> the device has been "qdev"-ified etc.).
>>
>> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
>> ---
[...]
>> diff --git a/hw/display/next-fb.c b/hw/display/next-fb.c
>> new file mode 100644
>> index 0000000000..740102d7e9
>> --- /dev/null
>> +++ b/hw/display/next-fb.c
>> @@ -0,0 +1,157 @@
>> +/*
>> + * NeXT Cube/Station Framebuffer Emulation
>> + *
>> + * Copyright (c) 2011 Bryce Lanham
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a copy
>> + * of this software and associated documentation files (the "Software"), to deal
>> + * in the Software without restriction, including without limitation the rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +#include "qemu/osdep.h"
>> +#include "qapi/error.h"
>> +#include "ui/console.h"
>> +#include "hw/hw.h"
>> +#include "hw/boards.h"
>> +#include "hw/loader.h"
>> +#include "hw/display/framebuffer.h"
>> +#define BITS 8
>
> 'BITS' is not used, remove?
Seems unused, indeed. I'll remove it.
>> +static void nextfb_draw_line(void *opaque, uint8_t *d, const uint8_t *s,
>> + int width, int pitch)
>> +{
>> + NeXTFbState *nfbstate = NEXTFB(opaque);
>> + static const uint32_t pal[4] = {
>> + 0xFFFFFFFF, 0xFFAAAAAA, 0xFF555555, 0xFF000000
>> + };
>> + uint32_t *buf = (uint32_t *)d;
>> + int i = 0;
>> +
>> + for (i = 0; i < nfbstate->cols / 4; i++) {
>> + int j = i * 4;
>> + uint8_t src = s[i];
>> + buf[j + 3] = pal[src & 0x3];
>
> 0x3 -> 3?
I prefer the "0x" for bit-wise logical operations.
> or 0b11 :)
Hmm, does that work with all compiler versions that we currently
support? I remember it was not working with older versions of GCC...
Anyway, Bryce used 0x3 in his original code, so I'd like to keep it
close to his original code for the first commit. We can rework stuff
like this in later patches if we like, but for the initial commit, it
would be adequate that you can still recognize the original code, I think.
>> + src >>= 2;
>> + buf[j + 2] = pal[src & 0x3];
>> + src >>= 2;
>> + buf[j + 1] = pal[src & 0x3];
>> + src >>= 2;
>> + buf[j + 0] = pal[src & 0x3];
>> + }
>> +}
>> +
>> +static void nextfb_update(void *opaque)
>> +{
>> + NeXTFbState *s = NEXTFB(opaque);
>> + int dest_width = 4;
>> + int src_width;
>> + int first = 0;
>> + int last = 0;
>> + DisplaySurface *surface = qemu_console_surface(s->con);
>> +
>> + src_width = s->cols / 4 + 8;
>> + dest_width = s->cols * 4;
>
> Since those are currently const, should we move them to NeXTFbState
> and initialize them in nextfb_realize()?
Should not matter much ... I think I'll also keep the original code here
for now.
>> +
>> + if (s->invalidate) {
>> + framebuffer_update_memory_section(&s->fbsection, &s->fb_mr, 0,
>> + s->cols, src_width);
>> + s->invalidate = 0;
>> + }
>> +
>> + framebuffer_update_display(surface, &s->fbsection, 1120, 832,
>
> 1120 -> s->cols?
> 832 -> s->rows?
>
>> + src_width, dest_width, 0, 1, nextfb_draw_line,
>> + s, &first, &last);
>> +
>> + dpy_gfx_update(s->con, 0, 0, 1120, 832);
>
> Ditto.
Ok.
>> +}
>> +
>> +static void nextfb_invalidate(void *opaque)
>> +{
>> + NeXTFbState *s = NEXTFB(opaque);
>> + s->invalidate = 1;
>> +}
>> +
>> +static const GraphicHwOps nextfb_ops = {
>> + .invalidate = nextfb_invalidate,
>> + .gfx_update = nextfb_update,
>> +};
>> +
>> +static void nextfb_realize(DeviceState *dev, Error **errp)
>> +{
>> + NeXTFbState *s = NEXTFB(dev);
>> +
>> + memory_region_init_ram(&s->fb_mr, OBJECT(dev), "next-video", 0x1CB100,
>> + &error_fatal);
>
> 2 bits * cols * rows = 2 * 832 * 1120 = 0x1c7000
>
> 0x1cb100 - 0x1c7000 = 0x4100
>
> Any idea what are these 16K + 256 extra bytes for?
No clue. But as you can see in nextfb_update() ("src_width = s->cols / 4
+ 8"), a line is a little bit wider than the visible 1120 pixels.
> Anyway we have 2MB of VRAM on the hardware here, right?
> If so you should replace 0x1CB100 -> 2 * MiB.
I don't know the Cube hardware that well ... so let's keep the original
values for now, we can still tune it later if necessary.
>> + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->fb_mr);
>> +
>> + s->invalidate = 1;
>> + s->cols = 1120;
>> + s->rows = 832;
>> +
>> + s->con = graphic_console_init(dev, 0, &nextfb_ops, s);
>> + qemu_console_resize(s->con, s->cols, s->rows);
>> +}
>> +
>> +static void nextfb_class_init(ObjectClass *oc, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(oc);
>> +
>> + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
>> + dc->realize = nextfb_realize;
>> +}
>> +
>> +static const TypeInfo nextfb_info = {
>> + .name = TYPE_NEXTFB,
>> + .parent = TYPE_SYS_BUS_DEVICE,
>> + .instance_size = sizeof(NeXTFbState),
>> + .class_init = nextfb_class_init,
>> +};
>> +
>> +static void nextfb_register_types(void)
>> +{
>> + type_register_static(&nextfb_info);
>> +}
>> +
>> +type_init(nextfb_register_types)
>> +
>> +void nextfb_init(void)
>> +{
>> + DeviceState *dev;
>> +
>> + dev = qdev_create(NULL, TYPE_NEXTFB);
>> + qdev_init_nofail(dev);
>> +
>> + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xB000000);
>
> I'd appreciate this written as 0x0B000000 (32-bit address range).
>
> Should you map the aliased VRAM regions here too?
>
> for (int i = 0; i <= 4; i++) {
> sysbus_mmio_map(SYS_BUS_DEVICE(dev), i,
> 0x0b000000 + 0x01000000 * i);
> }
Where do you've got the information from that the VRAM region is aliased
a couple of times?
> Anyway nextfb_init() content is this is board-specific code, not
> related to the device. Can you move it there?
Ok, will do.
Thanks for the review!
Thomas
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH v2 1/4] m68k: Add NeXTcube framebuffer device emulation
2019-06-29 17:45 ` Thomas Huth
@ 2019-07-02 16:01 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-07-02 16:01 UTC (permalink / raw)
To: Thomas Huth, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Laurent Vivier
On 6/29/19 7:45 PM, Thomas Huth wrote:
> On 29/06/2019 13.53, Philippe Mathieu-Daudé wrote:
>> Hi Thomas,
>>
>> On 6/28/19 8:15 PM, Thomas Huth wrote:
>>> The NeXTcube uses a linear framebuffer with 4 greyscale colors and
>>> a fixed resolution of 1120 * 832.
>>> This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at
>>>
>>> https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-fb.c
>>
>> Please use SHA1 for reference (unlikely case of Bryce pushing a new
>> version to his repo):
>>
>> https://github.com/blanham/qemu-NeXT/blob/34f4323/hw/next-fb.c
>
> But if Bryce ever pushes a new version to his branch, the old SHA IDs
> won't be part of a branch anymore, so they will be garbage collected
> after a while and the links will become invalid. I think it's better to
> refer to the "next-cube" branch.
OK.
>>> and altered to fit the latest interface of the current QEMU (e.g.
>>> the device has been "qdev"-ified etc.).
>>>
>>> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
>>> ---
> [...]
>>> diff --git a/hw/display/next-fb.c b/hw/display/next-fb.c
>>> new file mode 100644
>>> index 0000000000..740102d7e9
>>> --- /dev/null
>>> +++ b/hw/display/next-fb.c
>>> @@ -0,0 +1,157 @@
>>> +/*
>>> + * NeXT Cube/Station Framebuffer Emulation
>>> + *
>>> + * Copyright (c) 2011 Bryce Lanham
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person obtaining a copy
>>> + * of this software and associated documentation files (the "Software"), to deal
>>> + * in the Software without restriction, including without limitation the rights
>>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>>> + * copies of the Software, and to permit persons to whom the Software is
>>> + * furnished to do so, subject to the following conditions:
>>> + *
>>> + * The above copyright notice and this permission notice shall be included in
>>> + * all copies or substantial portions of the Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
>>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>>> + * THE SOFTWARE.
>>> + */
>>> +#include "qemu/osdep.h"
>>> +#include "qapi/error.h"
>>> +#include "ui/console.h"
>>> +#include "hw/hw.h"
>>> +#include "hw/boards.h"
>>> +#include "hw/loader.h"
>>> +#include "hw/display/framebuffer.h"
>>> +#define BITS 8
>>
>> 'BITS' is not used, remove?
>
> Seems unused, indeed. I'll remove it.
>
>>> +static void nextfb_draw_line(void *opaque, uint8_t *d, const uint8_t *s,
>>> + int width, int pitch)
>>> +{
>>> + NeXTFbState *nfbstate = NEXTFB(opaque);
>>> + static const uint32_t pal[4] = {
>>> + 0xFFFFFFFF, 0xFFAAAAAA, 0xFF555555, 0xFF000000
>>> + };
>>> + uint32_t *buf = (uint32_t *)d;
>>> + int i = 0;
>>> +
>>> + for (i = 0; i < nfbstate->cols / 4; i++) {
>>> + int j = i * 4;
>>> + uint8_t src = s[i];
>>> + buf[j + 3] = pal[src & 0x3];
>>
>> 0x3 -> 3?
>
> I prefer the "0x" for bit-wise logical operations.
OK
>> or 0b11 :)
>
> Hmm, does that work with all compiler versions that we currently
> support? I remember it was not working with older versions of GCC...
$ git grep 0b
accel/tcg/user-exec.c:608: switch (((insn >> 0) & 0b11)) {
accel/tcg/user-exec.c:610: switch (((insn >> 2) & 0b11111)) {
...
It now certainly does :)
> Anyway, Bryce used 0x3 in his original code, so I'd like to keep it
> close to his original code for the first commit. We can rework stuff
> like this in later patches if we like, but for the initial commit, it
> would be adequate that you can still recognize the original code, I think.
Fair enough.
>>> + src >>= 2;
>>> + buf[j + 2] = pal[src & 0x3];
>>> + src >>= 2;
>>> + buf[j + 1] = pal[src & 0x3];
>>> + src >>= 2;
>>> + buf[j + 0] = pal[src & 0x3];
>>> + }
>>> +}
>>> +
>>> +static void nextfb_update(void *opaque)
>>> +{
>>> + NeXTFbState *s = NEXTFB(opaque);
>>> + int dest_width = 4;
>>> + int src_width;
>>> + int first = 0;
>>> + int last = 0;
>>> + DisplaySurface *surface = qemu_console_surface(s->con);
>>> +
>>> + src_width = s->cols / 4 + 8;
>>> + dest_width = s->cols * 4;
>>
>> Since those are currently const, should we move them to NeXTFbState
>> and initialize them in nextfb_realize()?
>
> Should not matter much ... I think I'll also keep the original code here
> for now.
>
>>> +
>>> + if (s->invalidate) {
>>> + framebuffer_update_memory_section(&s->fbsection, &s->fb_mr, 0,
>>> + s->cols, src_width);
>>> + s->invalidate = 0;
>>> + }
>>> +
>>> + framebuffer_update_display(surface, &s->fbsection, 1120, 832,
>>
>> 1120 -> s->cols?
>> 832 -> s->rows?
>>
>>> + src_width, dest_width, 0, 1, nextfb_draw_line,
>>> + s, &first, &last);
>>> +
>>> + dpy_gfx_update(s->con, 0, 0, 1120, 832);
>>
>> Ditto.
>
> Ok.
>
>>> +}
>>> +
>>> +static void nextfb_invalidate(void *opaque)
>>> +{
>>> + NeXTFbState *s = NEXTFB(opaque);
>>> + s->invalidate = 1;
>>> +}
>>> +
>>> +static const GraphicHwOps nextfb_ops = {
>>> + .invalidate = nextfb_invalidate,
>>> + .gfx_update = nextfb_update,
>>> +};
>>> +
>>> +static void nextfb_realize(DeviceState *dev, Error **errp)
>>> +{
>>> + NeXTFbState *s = NEXTFB(dev);
>>> +
>>> + memory_region_init_ram(&s->fb_mr, OBJECT(dev), "next-video", 0x1CB100,
>>> + &error_fatal);
>>
>> 2 bits * cols * rows = 2 * 832 * 1120 = 0x1c7000
>>
>> 0x1cb100 - 0x1c7000 = 0x4100
>>
>> Any idea what are these 16K + 256 extra bytes for?
>
> No clue. But as you can see in nextfb_update() ("src_width = s->cols / 4
> + 8"), a line is a little bit wider than the visible 1120 pixels.
Weird :)
>> Anyway we have 2MB of VRAM on the hardware here, right?
>> If so you should replace 0x1CB100 -> 2 * MiB.
>
> I don't know the Cube hardware that well ... so let's keep the original
> values for now, we can still tune it later if necessary.
>
>>> + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->fb_mr);
>>> +
>>> + s->invalidate = 1;
>>> + s->cols = 1120;
>>> + s->rows = 832;
>>> +
>>> + s->con = graphic_console_init(dev, 0, &nextfb_ops, s);
>>> + qemu_console_resize(s->con, s->cols, s->rows);
>>> +}
>>> +
>>> +static void nextfb_class_init(ObjectClass *oc, void *data)
>>> +{
>>> + DeviceClass *dc = DEVICE_CLASS(oc);
>>> +
>>> + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
>>> + dc->realize = nextfb_realize;
>>> +}
>>> +
>>> +static const TypeInfo nextfb_info = {
>>> + .name = TYPE_NEXTFB,
>>> + .parent = TYPE_SYS_BUS_DEVICE,
>>> + .instance_size = sizeof(NeXTFbState),
>>> + .class_init = nextfb_class_init,
>>> +};
>>> +
>>> +static void nextfb_register_types(void)
>>> +{
>>> + type_register_static(&nextfb_info);
>>> +}
>>> +
>>> +type_init(nextfb_register_types)
>>> +
>>> +void nextfb_init(void)
>>> +{
>>> + DeviceState *dev;
>>> +
>>> + dev = qdev_create(NULL, TYPE_NEXTFB);
>>> + qdev_init_nofail(dev);
>>> +
>>> + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xB000000);
>>
>> I'd appreciate this written as 0x0B000000 (32-bit address range).
>>
>> Should you map the aliased VRAM regions here too?
>>
>> for (int i = 0; i <= 4; i++) {
>> sysbus_mmio_map(SYS_BUS_DEVICE(dev), i,
>> 0x0b000000 + 0x01000000 * i);
>> }
>
> Where do you've got the information from that the VRAM region is aliased
> a couple of times?
I looked at Previous, the Next emulator:
https://sourceforge.net/p/previous/code/HEAD/tree/trunk/src/cpu/memory.c#l41
Than looked around the code.
>> Anyway nextfb_init() content is this is board-specific code, not
>> related to the device. Can you move it there?
>
> Ok, will do.
>
> Thanks for the review!
>
> Thomas
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH v2 2/4] m68k: Add NeXTcube keyboard device
2019-06-28 18:15 [Qemu-devel] [PATCH v2 0/4] m68k: Add basic support for the NeXTcube machine Thomas Huth
2019-06-28 18:15 ` [Qemu-devel] [PATCH v2 1/4] m68k: Add NeXTcube framebuffer device emulation Thomas Huth
@ 2019-06-28 18:15 ` Thomas Huth
2019-06-29 12:02 ` Philippe Mathieu-Daudé
2019-06-28 18:15 ` [Qemu-devel] [PATCH v2 3/4] m68k: Add NeXTcube machine Thomas Huth
` (2 subsequent siblings)
4 siblings, 1 reply; 17+ messages in thread
From: Thomas Huth @ 2019-06-28 18:15 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Philippe Mathieu-Daudé, Laurent Vivier
It is likely still quite incomplete (e.g. mouse and interrupts are not
implemented yet), but it is good enough for keyboard input at the firmware
monitor.
This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at
https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-kbd.c
and altered to fit the latest interface of the current QEMU (e.g. to use
memory_region_init_io() instead of cpu_register_physical_memory()).
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
---
hw/m68k/Makefile.objs | 1 +
hw/m68k/next-kbd.c | 320 ++++++++++++++++++++++++++++++++++++
include/hw/m68k/next-cube.h | 3 +
3 files changed, 324 insertions(+)
create mode 100644 hw/m68k/next-kbd.c
diff --git a/hw/m68k/Makefile.objs b/hw/m68k/Makefile.objs
index 482f8477b4..688002cac1 100644
--- a/hw/m68k/Makefile.objs
+++ b/hw/m68k/Makefile.objs
@@ -1,2 +1,3 @@
obj-$(CONFIG_AN5206) += an5206.o mcf5206.o
obj-$(CONFIG_MCF5208) += mcf5208.o mcf_intc.o
+obj-$(CONFIG_NEXTCUBE) += next-kbd.o
diff --git a/hw/m68k/next-kbd.c b/hw/m68k/next-kbd.c
new file mode 100644
index 0000000000..73e90f9b62
--- /dev/null
+++ b/hw/m68k/next-kbd.c
@@ -0,0 +1,320 @@
+/*
+ * QEMU NeXT Keyboard/Mouse emulation
+ *
+ * Copyright (c) 2011 Bryce Lanham
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/*
+ * This is admittedly hackish, but works well enough for basic input. Mouse
+ * support will be added once we can boot something that needs the mouse.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "exec/address-spaces.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "hw/m68k/next-cube.h"
+#include "ui/console.h"
+#include "sysemu/sysemu.h"
+
+#define TYPE_NEXTKBD "next-kbd"
+#define NEXTKBD(obj) OBJECT_CHECK(NextKBDState, (obj), TYPE_NEXTKBD)
+
+/* following defintions from next68k netbsd */
+#define CSR_INT 0x00800000
+#define CSR_DATA 0x00400000
+
+#define KD_KEYMASK 0x007f
+#define KD_DIRECTION 0x0080 /* pressed or released */
+#define KD_CNTL 0x0100
+#define KD_LSHIFT 0x0200
+#define KD_RSHIFT 0x0400
+#define KD_LCOMM 0x0800
+#define KD_RCOMM 0x1000
+#define KD_LALT 0x2000
+#define KD_RALT 0x4000
+#define KD_VALID 0x8000 /* only set for scancode keys ? */
+#define KD_MODS 0x4f00
+
+#define KBD_QUEUE_SIZE 256
+
+typedef struct {
+ uint8_t data[KBD_QUEUE_SIZE];
+ int rptr, wptr, count;
+} KBDQueue;
+
+
+typedef struct NextKBDState {
+ SysBusDevice sbd;
+ MemoryRegion mr;
+ KBDQueue queue;
+ uint16_t shift;
+} NextKBDState;
+
+static void queue_code(void *opaque, int code);
+
+/* lots of magic numbers here */
+static uint32_t kbd_read_byte(void *opaque, hwaddr addr)
+{
+ switch (addr & 0x3) {
+ case 0x0: /* 0xe000 */
+ return 0x80 | 0x20;
+
+ case 0x1: /* 0xe001 */
+ return 0x80 | 0x40 | 0x20 | 0x10;
+
+ case 0x2: /* 0xe002 */
+ /* returning 0x40 caused mach to hang */
+ return 0x10 | 0x2 | 0x1;
+
+ default:
+ qemu_log_mask(LOG_UNIMP, "NeXT kbd read byte %"HWADDR_PRIx"\n", addr);
+ }
+
+ return 0;
+}
+
+static uint32_t kbd_read_word(void *opaque, hwaddr addr)
+{
+ qemu_log_mask(LOG_UNIMP, "NeXT kbd read word %"HWADDR_PRIx"\n", addr);
+ return 0;
+}
+
+/* even more magic numbers */
+static uint32_t kbd_read_long(void *opaque, hwaddr addr)
+{
+ int key = 0;
+ NextKBDState *s = NEXTKBD(opaque);
+ KBDQueue *q = &s->queue;
+
+ switch (addr & 0xf) {
+ case 0x0: /* 0xe000 */
+ return 0xA0F09300;
+
+ case 0x8: /* 0xe008 */
+ /* get keycode from buffer */
+ if (q->count > 0) {
+ key = q->data[q->rptr];
+ if (++q->rptr == KBD_QUEUE_SIZE) {
+ q->rptr = 0;
+ }
+
+ q->count--;
+
+ if (s->shift) {
+ key |= s->shift;
+ }
+
+ if (key & 0x80) {
+ return 0;
+ } else {
+ return 0x10000000 | KD_VALID | key;
+ }
+ } else {
+ return 0;
+ }
+
+ default:
+ qemu_log_mask(LOG_UNIMP, "NeXT kbd read long %"HWADDR_PRIx"\n", addr);
+ return 0;
+ }
+}
+
+static void kbd_write_byte(void *opaque, hwaddr addr, uint32_t val)
+{
+ qemu_log_mask(LOG_UNIMP, "NeXT kbd write byte %"HWADDR_PRIx"\n", addr);
+}
+static void kbd_write_word(void *opaque, hwaddr addr, uint32_t val)
+{
+ qemu_log_mask(LOG_UNIMP, "NeXT kbd write addr %"HWADDR_PRIx"\n", addr);
+}
+static void kbd_write_long(void *opaque, hwaddr addr, uint32_t val)
+{
+ qemu_log_mask(LOG_UNIMP, "NeXT kbd write long %"HWADDR_PRIx"\n", addr);
+}
+
+static uint64_t kbd_readfn(void *opaque, hwaddr addr, unsigned size)
+{
+ switch (size) {
+ case 1:
+ return kbd_read_byte(opaque, addr);
+ case 2:
+ return kbd_read_word(opaque, addr);
+ case 4:
+ return kbd_read_long(opaque, addr);
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void kbd_writefn(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ switch (size) {
+ case 1:
+ kbd_write_byte(opaque, addr, value);
+ break;
+ case 2:
+ kbd_write_word(opaque, addr, value);
+ break;
+ case 4:
+ kbd_write_long(opaque, addr, value);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static const MemoryRegionOps kbd_ops = {
+ .read = kbd_readfn,
+ .write = kbd_writefn,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 4,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void nextkbd_event(void *opaque, int ch)
+{
+ /*
+ * Will want to set vars for caps/num lock
+ * if (ch & 0x80) -> key release
+ * there's also e0 escaped scancodes that might need to be handled
+ */
+ queue_code(opaque, ch);
+}
+
+static const unsigned char next_keycodes[128] = {
+ 0x00, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x50, 0x4F,
+ 0x4E, 0x1E, 0x1F, 0x20, 0x1D, 0x1C, 0x1B, 0x00,
+ 0x42, 0x43, 0x44, 0x45, 0x48, 0x47, 0x46, 0x06,
+ 0x07, 0x08, 0x00, 0x00, 0x2A, 0x00, 0x39, 0x3A,
+ 0x3B, 0x3C, 0x3D, 0x40, 0x3F, 0x3E, 0x2D, 0x2C,
+ 0x2B, 0x26, 0x00, 0x00, 0x31, 0x32, 0x33, 0x34,
+ 0x35, 0x37, 0x36, 0x2e, 0x2f, 0x30, 0x00, 0x00,
+ 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static void queue_code(void *opaque, int code)
+{
+ NextKBDState *s = NEXTKBD(opaque);
+ KBDQueue *q = &s->queue;
+ int key = code & 0x7F;
+ int release = code & 0x80;
+ static int ext;
+
+ if (code == 0xE0) {
+ ext = 1;
+ }
+
+ if (code == 0x2A || code == 0x1D || code == 0x36) {
+ if (code == 0x2A) {
+ s->shift = KD_LSHIFT;
+ } else if (code == 0x36) {
+ s->shift = KD_RSHIFT;
+ ext = 0;
+ } else if (code == 0x1D && !ext) {
+ s->shift = KD_LCOMM;
+ } else if (code == 0x1D && ext) {
+ ext = 0;
+ s->shift = KD_RCOMM;
+ }
+ return;
+ } else if (code == (0x2A | 0x80) || code == (0x1D | 0x80) ||
+ code == (0x36 | 0x80)) {
+ s->shift = 0;
+ return;
+ }
+
+ if (q->count >= KBD_QUEUE_SIZE) {
+ return;
+ }
+
+ q->data[q->wptr] = next_keycodes[key] | release;
+
+ if (++q->wptr == KBD_QUEUE_SIZE) {
+ q->wptr = 0;
+ }
+
+ q->count++;
+
+ /*
+ * might need to actually trigger the NeXT irq, but as the keyboard works
+ * at the moment, I'll worry about it later
+ */
+ /* s->update_irq(s->update_arg, 1); */
+}
+
+static void nextkbd_reset(DeviceState *dev)
+{
+ NextKBDState *nks = NEXTKBD(dev);
+
+ memset(&nks->queue, 0, sizeof(KBDQueue));
+ nks->shift = 0;
+}
+
+static void nextkbd_realize(DeviceState *dev, Error **errp)
+{
+ NextKBDState *s = NEXTKBD(dev);
+
+ memory_region_init_io(&s->mr, OBJECT(dev), &kbd_ops, s, "next.kbd", 0x1000);
+
+ qemu_add_kbd_event_handler(nextkbd_event, s);
+}
+
+static void nextkbd_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
+ dc->realize = nextkbd_realize;
+ dc->reset = nextkbd_reset;
+}
+
+static const TypeInfo nextkbd_info = {
+ .name = TYPE_NEXTKBD,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(NextKBDState),
+ .class_init = nextkbd_class_init,
+};
+
+static void nextkbd_register_types(void)
+{
+ type_register_static(&nextkbd_info);
+}
+
+type_init(nextkbd_register_types)
+
+void nextkbd_init(void)
+{
+ DeviceState *dev;
+ NextKBDState *nks;
+
+ dev = qdev_create(NULL, TYPE_NEXTKBD);
+ qdev_init_nofail(dev);
+
+ nks = NEXTKBD(dev);
+ memory_region_add_subregion(get_system_memory(), 0x200e000, &nks->mr);
+}
diff --git a/include/hw/m68k/next-cube.h b/include/hw/m68k/next-cube.h
index cf07243bda..88e94f6595 100644
--- a/include/hw/m68k/next-cube.h
+++ b/include/hw/m68k/next-cube.h
@@ -5,4 +5,7 @@
/* next-fb.c */
void nextfb_init(void);
+/* next-kbd.c */
+void nextkbd_init(void);
+
#endif /* NEXT_CUBE_H */
--
2.21.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH v2 2/4] m68k: Add NeXTcube keyboard device
2019-06-28 18:15 ` [Qemu-devel] [PATCH v2 2/4] m68k: Add NeXTcube keyboard device Thomas Huth
@ 2019-06-29 12:02 ` Philippe Mathieu-Daudé
2019-07-02 10:45 ` Thomas Huth
0 siblings, 1 reply; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-06-29 12:02 UTC (permalink / raw)
To: Thomas Huth, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Laurent Vivier
On 6/28/19 8:15 PM, Thomas Huth wrote:
> It is likely still quite incomplete (e.g. mouse and interrupts are not
> implemented yet), but it is good enough for keyboard input at the firmware
> monitor.
> This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at
>
> https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-kbd.c
Please use commit sha1 in link.
> and altered to fit the latest interface of the current QEMU (e.g. to use
> memory_region_init_io() instead of cpu_register_physical_memory()).
>
> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
> ---
> hw/m68k/Makefile.objs | 1 +
> hw/m68k/next-kbd.c | 320 ++++++++++++++++++++++++++++++++++++
> include/hw/m68k/next-cube.h | 3 +
> 3 files changed, 324 insertions(+)
> create mode 100644 hw/m68k/next-kbd.c
>
> diff --git a/hw/m68k/Makefile.objs b/hw/m68k/Makefile.objs
> index 482f8477b4..688002cac1 100644
> --- a/hw/m68k/Makefile.objs
> +++ b/hw/m68k/Makefile.objs
> @@ -1,2 +1,3 @@
> obj-$(CONFIG_AN5206) += an5206.o mcf5206.o
> obj-$(CONFIG_MCF5208) += mcf5208.o mcf_intc.o
> +obj-$(CONFIG_NEXTCUBE) += next-kbd.o
> diff --git a/hw/m68k/next-kbd.c b/hw/m68k/next-kbd.c
> new file mode 100644
> index 0000000000..73e90f9b62
> --- /dev/null
> +++ b/hw/m68k/next-kbd.c
> @@ -0,0 +1,320 @@
> +/*
> + * QEMU NeXT Keyboard/Mouse emulation
> + *
> + * Copyright (c) 2011 Bryce Lanham
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +/*
> + * This is admittedly hackish, but works well enough for basic input. Mouse
> + * support will be added once we can boot something that needs the mouse.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "exec/address-spaces.h"
> +#include "hw/hw.h"
> +#include "hw/sysbus.h"
> +#include "hw/m68k/next-cube.h"
> +#include "ui/console.h"
> +#include "sysemu/sysemu.h"
> +
> +#define TYPE_NEXTKBD "next-kbd"
> +#define NEXTKBD(obj) OBJECT_CHECK(NextKBDState, (obj), TYPE_NEXTKBD)
> +
> +/* following defintions from next68k netbsd */
> +#define CSR_INT 0x00800000
> +#define CSR_DATA 0x00400000
> +
> +#define KD_KEYMASK 0x007f
> +#define KD_DIRECTION 0x0080 /* pressed or released */
> +#define KD_CNTL 0x0100
> +#define KD_LSHIFT 0x0200
> +#define KD_RSHIFT 0x0400
> +#define KD_LCOMM 0x0800
> +#define KD_RCOMM 0x1000
> +#define KD_LALT 0x2000
> +#define KD_RALT 0x4000
> +#define KD_VALID 0x8000 /* only set for scancode keys ? */
> +#define KD_MODS 0x4f00
> +
> +#define KBD_QUEUE_SIZE 256
> +
> +typedef struct {
> + uint8_t data[KBD_QUEUE_SIZE];
> + int rptr, wptr, count;
> +} KBDQueue;
> +
> +
> +typedef struct NextKBDState {
> + SysBusDevice sbd;
> + MemoryRegion mr;
> + KBDQueue queue;
> + uint16_t shift;
> +} NextKBDState;
> +
> +static void queue_code(void *opaque, int code);
> +
> +/* lots of magic numbers here */
> +static uint32_t kbd_read_byte(void *opaque, hwaddr addr)
> +{
> + switch (addr & 0x3) {
> + case 0x0: /* 0xe000 */
> + return 0x80 | 0x20;
> +
> + case 0x1: /* 0xe001 */
> + return 0x80 | 0x40 | 0x20 | 0x10;
> +
> + case 0x2: /* 0xe002 */
> + /* returning 0x40 caused mach to hang */
> + return 0x10 | 0x2 | 0x1;
> +
> + default:
> + qemu_log_mask(LOG_UNIMP, "NeXT kbd read byte %"HWADDR_PRIx"\n", addr);
> + }
> +
> + return 0;
> +}
> +
> +static uint32_t kbd_read_word(void *opaque, hwaddr addr)
> +{
> + qemu_log_mask(LOG_UNIMP, "NeXT kbd read word %"HWADDR_PRIx"\n", addr);
This sounds odd... a bus working in 32-bit/8-bit but not 16...
> + return 0;
> +}
> +
> +/* even more magic numbers */
> +static uint32_t kbd_read_long(void *opaque, hwaddr addr)
> +{
> + int key = 0;
> + NextKBDState *s = NEXTKBD(opaque);
> + KBDQueue *q = &s->queue;
> +
> + switch (addr & 0xf) {
> + case 0x0: /* 0xe000 */
> + return 0xA0F09300;
> +
> + case 0x8: /* 0xe008 */
> + /* get keycode from buffer */
> + if (q->count > 0) {
> + key = q->data[q->rptr];
> + if (++q->rptr == KBD_QUEUE_SIZE) {
> + q->rptr = 0;
> + }
> +
> + q->count--;
> +
> + if (s->shift) {
> + key |= s->shift;
> + }
> +
> + if (key & 0x80) {
> + return 0;
> + } else {
> + return 0x10000000 | KD_VALID | key;
> + }
> + } else {
> + return 0;
> + }
> +
> + default:
> + qemu_log_mask(LOG_UNIMP, "NeXT kbd read long %"HWADDR_PRIx"\n", addr);
> + return 0;
> + }
> +}
> +
> +static void kbd_write_byte(void *opaque, hwaddr addr, uint32_t val)
> +{
> + qemu_log_mask(LOG_UNIMP, "NeXT kbd write byte %"HWADDR_PRIx"\n", addr);
> +}
> +static void kbd_write_word(void *opaque, hwaddr addr, uint32_t val)
> +{
> + qemu_log_mask(LOG_UNIMP, "NeXT kbd write addr %"HWADDR_PRIx"\n", addr);
> +}
> +static void kbd_write_long(void *opaque, hwaddr addr, uint32_t val)
> +{
> + qemu_log_mask(LOG_UNIMP, "NeXT kbd write long %"HWADDR_PRIx"\n", addr);
> +}
> +
> +static uint64_t kbd_readfn(void *opaque, hwaddr addr, unsigned size)
> +{
> + switch (size) {
> + case 1:
> + return kbd_read_byte(opaque, addr);
> + case 2:
> + return kbd_read_word(opaque, addr);
> + case 4:
> + return kbd_read_long(opaque, addr);
> + default:
> + g_assert_not_reached();
> + }
> +}
> +
> +static void kbd_writefn(void *opaque, hwaddr addr, uint64_t value,
> + unsigned size)
> +{
> + switch (size) {
> + case 1:
> + kbd_write_byte(opaque, addr, value);
> + break;
> + case 2:
> + kbd_write_word(opaque, addr, value);
> + break;
> + case 4:
> + kbd_write_long(opaque, addr, value);
> + break;
> + default:
> + g_assert_not_reached();
> + }
Well, you can replace this by:
qemu_log_mask(LOG_UNIMP,
"NeXT kbd write size:%u 0x%"HWADDR_PRIx"\n",
size, addr);
and kill the kbd_write_*() functions and the assert (never
reached since .valid.max_access_size = 4).
> +}
> +
> +static const MemoryRegionOps kbd_ops = {
> + .read = kbd_readfn,
> + .write = kbd_writefn,
> + .valid.min_access_size = 1,
> + .valid.max_access_size = 4,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +static void nextkbd_event(void *opaque, int ch)
> +{
> + /*
> + * Will want to set vars for caps/num lock
> + * if (ch & 0x80) -> key release
> + * there's also e0 escaped scancodes that might need to be handled
> + */
> + queue_code(opaque, ch);
> +}
> +
> +static const unsigned char next_keycodes[128] = {
> + 0x00, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x50, 0x4F,
> + 0x4E, 0x1E, 0x1F, 0x20, 0x1D, 0x1C, 0x1B, 0x00,
> + 0x42, 0x43, 0x44, 0x45, 0x48, 0x47, 0x46, 0x06,
> + 0x07, 0x08, 0x00, 0x00, 0x2A, 0x00, 0x39, 0x3A,
> + 0x3B, 0x3C, 0x3D, 0x40, 0x3F, 0x3E, 0x2D, 0x2C,
> + 0x2B, 0x26, 0x00, 0x00, 0x31, 0x32, 0x33, 0x34,
> + 0x35, 0x37, 0x36, 0x2e, 0x2f, 0x30, 0x00, 0x00,
> + 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
> +};
> +
> +static void queue_code(void *opaque, int code)
> +{
> + NextKBDState *s = NEXTKBD(opaque);
> + KBDQueue *q = &s->queue;
> + int key = code & 0x7F;
Here 0x7f is ARRAY_SIZE(next_keycodes) - 1, ok.
Isn't it the KD_KEYMASK definition from above then?
> + int release = code & 0x80;
> + static int ext;
> +
> + if (code == 0xE0) {
> + ext = 1;
> + }
> +
> + if (code == 0x2A || code == 0x1D || code == 0x36) {
> + if (code == 0x2A) {
> + s->shift = KD_LSHIFT;
> + } else if (code == 0x36) {
> + s->shift = KD_RSHIFT;
> + ext = 0;
> + } else if (code == 0x1D && !ext) {
> + s->shift = KD_LCOMM;
> + } else if (code == 0x1D && ext) {
> + ext = 0;
> + s->shift = KD_RCOMM;
> + }
> + return;
> + } else if (code == (0x2A | 0x80) || code == (0x1D | 0x80) ||
> + code == (0x36 | 0x80)) {
> + s->shift = 0;
> + return;
> + }
> +
> + if (q->count >= KBD_QUEUE_SIZE) {
> + return;
> + }
> +
> + q->data[q->wptr] = next_keycodes[key] | release;
> +
> + if (++q->wptr == KBD_QUEUE_SIZE) {
> + q->wptr = 0;
> + }
> +
> + q->count++;
> +
> + /*
> + * might need to actually trigger the NeXT irq, but as the keyboard works
> + * at the moment, I'll worry about it later
> + */
> + /* s->update_irq(s->update_arg, 1); */
> +}
> +
> +static void nextkbd_reset(DeviceState *dev)
> +{
> + NextKBDState *nks = NEXTKBD(dev);
> +
> + memset(&nks->queue, 0, sizeof(KBDQueue));
> + nks->shift = 0;
> +}
> +
> +static void nextkbd_realize(DeviceState *dev, Error **errp)
> +{
> + NextKBDState *s = NEXTKBD(dev);
> +
> + memory_region_init_io(&s->mr, OBJECT(dev), &kbd_ops, s, "next.kbd", 0x1000);
> +
> + qemu_add_kbd_event_handler(nextkbd_event, s);
> +}
> +
> +static void nextkbd_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
> + dc->realize = nextkbd_realize;
> + dc->reset = nextkbd_reset;
> +}
> +
> +static const TypeInfo nextkbd_info = {
> + .name = TYPE_NEXTKBD,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(NextKBDState),
> + .class_init = nextkbd_class_init,
> +};
> +
> +static void nextkbd_register_types(void)
> +{
> + type_register_static(&nextkbd_info);
> +}
> +
> +type_init(nextkbd_register_types)
> +
> +void nextkbd_init(void)
> +{
> + DeviceState *dev;
> + NextKBDState *nks;
> +
> + dev = qdev_create(NULL, TYPE_NEXTKBD);
> + qdev_init_nofail(dev);
> +
> + nks = NEXTKBD(dev);
> + memory_region_add_subregion(get_system_memory(), 0x200e000, &nks->mr);
0x200e000 -> 0x0200e000 :)
> +}
Again, nextkbd_init() is board-specific code.
Could you move this function there?
Thanks,
Phil.
> diff --git a/include/hw/m68k/next-cube.h b/include/hw/m68k/next-cube.h
> index cf07243bda..88e94f6595 100644
> --- a/include/hw/m68k/next-cube.h
> +++ b/include/hw/m68k/next-cube.h
> @@ -5,4 +5,7 @@
> /* next-fb.c */
> void nextfb_init(void);
>
> +/* next-kbd.c */
> +void nextkbd_init(void);
> +
> #endif /* NEXT_CUBE_H */
>
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH v2 2/4] m68k: Add NeXTcube keyboard device
2019-06-29 12:02 ` Philippe Mathieu-Daudé
@ 2019-07-02 10:45 ` Thomas Huth
0 siblings, 0 replies; 17+ messages in thread
From: Thomas Huth @ 2019-07-02 10:45 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Laurent Vivier
On 29/06/2019 14.02, Philippe Mathieu-Daudé wrote:
> On 6/28/19 8:15 PM, Thomas Huth wrote:
>> It is likely still quite incomplete (e.g. mouse and interrupts are not
>> implemented yet), but it is good enough for keyboard input at the firmware
>> monitor.
[...]
>> +
>> +static uint32_t kbd_read_word(void *opaque, hwaddr addr)
>> +{
>> + qemu_log_mask(LOG_UNIMP, "NeXT kbd read word %"HWADDR_PRIx"\n", addr);
>
> This sounds odd... a bus working in 32-bit/8-bit but not 16...
I guess the bus is working in 16-bit, too, it's just that the firmware
(and the OS) does not access it in that mode, so neither Bryce nor I
spent time implementing this. It's an "UNIMP" log entry ... so whenever
we see it during runtime, we still can add it.
>> + return 0;
>> +}
[...]
>> +static void kbd_write_byte(void *opaque, hwaddr addr, uint32_t val)
>> +{
>> + qemu_log_mask(LOG_UNIMP, "NeXT kbd write byte %"HWADDR_PRIx"\n", addr);
>> +}
>> +static void kbd_write_word(void *opaque, hwaddr addr, uint32_t val)
>> +{
>> + qemu_log_mask(LOG_UNIMP, "NeXT kbd write addr %"HWADDR_PRIx"\n", addr);
>> +}
>> +static void kbd_write_long(void *opaque, hwaddr addr, uint32_t val)
>> +{
>> + qemu_log_mask(LOG_UNIMP, "NeXT kbd write long %"HWADDR_PRIx"\n", addr);
>> +}
>> +
>> +static uint64_t kbd_readfn(void *opaque, hwaddr addr, unsigned size)
>> +{
>> + switch (size) {
>> + case 1:
>> + return kbd_read_byte(opaque, addr);
>> + case 2:
>> + return kbd_read_word(opaque, addr);
>> + case 4:
>> + return kbd_read_long(opaque, addr);
>> + default:
>> + g_assert_not_reached();
>> + }
>> +}
>> +
>> +static void kbd_writefn(void *opaque, hwaddr addr, uint64_t value,
>> + unsigned size)
>> +{
>> + switch (size) {
>> + case 1:
>> + kbd_write_byte(opaque, addr, value);
>> + break;
>> + case 2:
>> + kbd_write_word(opaque, addr, value);
>> + break;
>> + case 4:
>> + kbd_write_long(opaque, addr, value);
>> + break;
>> + default:
>> + g_assert_not_reached();
>> + }
>
> Well, you can replace this by:
>
> qemu_log_mask(LOG_UNIMP,
> "NeXT kbd write size:%u 0x%"HWADDR_PRIx"\n",
> size, addr);
>
> and kill the kbd_write_*() functions and the assert (never
> reached since .valid.max_access_size = 4).
Good idea, I'll do it in v3.
>> +}
>> +
>> +static const MemoryRegionOps kbd_ops = {
>> + .read = kbd_readfn,
>> + .write = kbd_writefn,
>> + .valid.min_access_size = 1,
>> + .valid.max_access_size = 4,
>> + .endianness = DEVICE_NATIVE_ENDIAN,
>> +};
>> +
>> +static void nextkbd_event(void *opaque, int ch)
>> +{
>> + /*
>> + * Will want to set vars for caps/num lock
>> + * if (ch & 0x80) -> key release
>> + * there's also e0 escaped scancodes that might need to be handled
>> + */
>> + queue_code(opaque, ch);
>> +}
>> +
>> +static const unsigned char next_keycodes[128] = {
>> + 0x00, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x50, 0x4F,
>> + 0x4E, 0x1E, 0x1F, 0x20, 0x1D, 0x1C, 0x1B, 0x00,
>> + 0x42, 0x43, 0x44, 0x45, 0x48, 0x47, 0x46, 0x06,
>> + 0x07, 0x08, 0x00, 0x00, 0x2A, 0x00, 0x39, 0x3A,
>> + 0x3B, 0x3C, 0x3D, 0x40, 0x3F, 0x3E, 0x2D, 0x2C,
>> + 0x2B, 0x26, 0x00, 0x00, 0x31, 0x32, 0x33, 0x34,
>> + 0x35, 0x37, 0x36, 0x2e, 0x2f, 0x30, 0x00, 0x00,
>> + 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>> + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
>> + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
>> + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
>> + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
>> +};
>> +
>> +static void queue_code(void *opaque, int code)
>> +{
>> + NextKBDState *s = NEXTKBD(opaque);
>> + KBDQueue *q = &s->queue;
>> + int key = code & 0x7F;
>
> Here 0x7f is ARRAY_SIZE(next_keycodes) - 1, ok.
> Isn't it the KD_KEYMASK definition from above then?
I guess so ... I'll use it in v3.
>> + int release = code & 0x80;
>> + static int ext;
>> +
>> + if (code == 0xE0) {
>> + ext = 1;
>> + }
>> +
>> + if (code == 0x2A || code == 0x1D || code == 0x36) {
>> + if (code == 0x2A) {
>> + s->shift = KD_LSHIFT;
>> + } else if (code == 0x36) {
>> + s->shift = KD_RSHIFT;
>> + ext = 0;
>> + } else if (code == 0x1D && !ext) {
>> + s->shift = KD_LCOMM;
>> + } else if (code == 0x1D && ext) {
>> + ext = 0;
>> + s->shift = KD_RCOMM;
>> + }
>> + return;
>> + } else if (code == (0x2A | 0x80) || code == (0x1D | 0x80) ||
>> + code == (0x36 | 0x80)) {
>> + s->shift = 0;
>> + return;
>> + }
>> +
>> + if (q->count >= KBD_QUEUE_SIZE) {
>> + return;
>> + }
>> +
>> + q->data[q->wptr] = next_keycodes[key] | release;
>> +
>> + if (++q->wptr == KBD_QUEUE_SIZE) {
>> + q->wptr = 0;
>> + }
>> +
>> + q->count++;
>> +
>> + /*
>> + * might need to actually trigger the NeXT irq, but as the keyboard works
>> + * at the moment, I'll worry about it later
>> + */
>> + /* s->update_irq(s->update_arg, 1); */
>> +}
>> +
>> +static void nextkbd_reset(DeviceState *dev)
>> +{
>> + NextKBDState *nks = NEXTKBD(dev);
>> +
>> + memset(&nks->queue, 0, sizeof(KBDQueue));
>> + nks->shift = 0;
>> +}
>> +
>> +static void nextkbd_realize(DeviceState *dev, Error **errp)
>> +{
>> + NextKBDState *s = NEXTKBD(dev);
>> +
>> + memory_region_init_io(&s->mr, OBJECT(dev), &kbd_ops, s, "next.kbd", 0x1000);
>> +
>> + qemu_add_kbd_event_handler(nextkbd_event, s);
>> +}
>> +
>> +static void nextkbd_class_init(ObjectClass *oc, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(oc);
>> +
>> + set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
>> + dc->realize = nextkbd_realize;
>> + dc->reset = nextkbd_reset;
>> +}
>> +
>> +static const TypeInfo nextkbd_info = {
>> + .name = TYPE_NEXTKBD,
>> + .parent = TYPE_SYS_BUS_DEVICE,
>> + .instance_size = sizeof(NextKBDState),
>> + .class_init = nextkbd_class_init,
>> +};
>> +
>> +static void nextkbd_register_types(void)
>> +{
>> + type_register_static(&nextkbd_info);
>> +}
>> +
>> +type_init(nextkbd_register_types)
>> +
>> +void nextkbd_init(void)
>> +{
>> + DeviceState *dev;
>> + NextKBDState *nks;
>> +
>> + dev = qdev_create(NULL, TYPE_NEXTKBD);
>> + qdev_init_nofail(dev);
>> +
>> + nks = NEXTKBD(dev);
>> + memory_region_add_subregion(get_system_memory(), 0x200e000, &nks->mr);
>
> 0x200e000 -> 0x0200e000 :)
Ok.
>> +}
>
> Again, nextkbd_init() is board-specific code.
> Could you move this function there?
Will do.
Thanks,
Thomas
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH v2 3/4] m68k: Add NeXTcube machine
2019-06-28 18:15 [Qemu-devel] [PATCH v2 0/4] m68k: Add basic support for the NeXTcube machine Thomas Huth
2019-06-28 18:15 ` [Qemu-devel] [PATCH v2 1/4] m68k: Add NeXTcube framebuffer device emulation Thomas Huth
2019-06-28 18:15 ` [Qemu-devel] [PATCH v2 2/4] m68k: Add NeXTcube keyboard device Thomas Huth
@ 2019-06-28 18:15 ` Thomas Huth
2019-06-29 12:26 ` Philippe Mathieu-Daudé
2019-06-28 18:15 ` [Qemu-devel] [PATCH v2 4/4] m68k: Add an entry for the NeXTcube machine to the MAINTAINERS file Thomas Huth
2019-06-29 14:40 ` [Qemu-devel] [PATCH v2 0/4] m68k: Add basic support for the NeXTcube machine Philippe Mathieu-Daudé
4 siblings, 1 reply; 17+ messages in thread
From: Thomas Huth @ 2019-06-28 18:15 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Philippe Mathieu-Daudé, Laurent Vivier
It is still quite incomplete (no SCSI, no floppy emulation, no network,
etc.), but the firmware already shows up the debug monitor prompt in the
framebuffer display, so at least the very basics are already working.
This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at
https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-cube.c
and altered quite a bit to fit the latest interface and coding conventions
of the current QEMU.
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
---
hw/m68k/Makefile.objs | 2 +-
hw/m68k/next-cube.c | 988 ++++++++++++++++++++++++++++++++++++
include/hw/m68k/next-cube.h | 38 ++
3 files changed, 1027 insertions(+), 1 deletion(-)
create mode 100644 hw/m68k/next-cube.c
diff --git a/hw/m68k/Makefile.objs b/hw/m68k/Makefile.objs
index 688002cac1..f25854730d 100644
--- a/hw/m68k/Makefile.objs
+++ b/hw/m68k/Makefile.objs
@@ -1,3 +1,3 @@
obj-$(CONFIG_AN5206) += an5206.o mcf5206.o
obj-$(CONFIG_MCF5208) += mcf5208.o mcf_intc.o
-obj-$(CONFIG_NEXTCUBE) += next-kbd.o
+obj-$(CONFIG_NEXTCUBE) += next-kbd.o next-cube.o
diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c
new file mode 100644
index 0000000000..700d386fb9
--- /dev/null
+++ b/hw/m68k/next-cube.c
@@ -0,0 +1,988 @@
+/*
+ * NeXT Cube System Driver
+ *
+ * Copyright (c) 2011 Bryce Lanham
+ *
+ * This code is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundation; either version 2 of the License,
+ * or (at your option) any later version.
+ */
+
+#include "qemu/osdep.h"
+#include "exec/hwaddr.h"
+#include "exec/address-spaces.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/qtest.h"
+#include "hw/hw.h"
+#include "hw/m68k/next-cube.h"
+#include "hw/boards.h"
+#include "hw/loader.h"
+#include "hw/scsi/esp.h"
+#include "hw/sysbus.h"
+#include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */
+#include "hw/block/fdc.h"
+#include "qapi/error.h"
+#include "ui/console.h"
+#include "target/m68k/cpu.h"
+
+/* #define DEBUG_NEXT */
+#ifdef DEBUG_NEXT
+#define DPRINTF(fmt, ...) \
+ do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...) do { } while (0)
+#endif
+
+#define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube")
+#define NEXT_MACHINE(obj) OBJECT_CHECK(NeXTState, (obj), TYPE_NEXT_MACHINE)
+
+#define ENTRY 0x0100001e
+#define RAM_SIZE 0x4000000
+#define ROM_FILE "rom66.bin"
+
+typedef struct next_dma {
+ uint32_t csr;
+
+ uint32_t saved_next;
+ uint32_t saved_limit;
+ uint32_t saved_start;
+ uint32_t saved_stop;
+
+ uint32_t next;
+ uint32_t limit;
+ uint32_t start;
+ uint32_t stop;
+
+ uint32_t next_initbuf;
+ uint32_t size;
+} next_dma;
+
+typedef struct {
+ MachineState parent;
+
+ uint32_t int_mask;
+ uint32_t int_status;
+
+ uint8_t scsi_csr_1;
+ uint8_t scsi_csr_2;
+ next_dma dma[10];
+ qemu_irq *scsi_irq;
+ qemu_irq scsi_dma;
+ qemu_irq scsi_reset;
+ qemu_irq *fd_irq;
+
+ uint32_t scr1;
+ uint32_t scr2;
+
+ uint8_t rtc_ram[32];
+} NeXTState;
+
+/* Thanks to NeXT forums for this */
+/*
+static const uint8_t rtc_ram3[32] = {
+ 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00,
+ 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13
+};
+*/
+static const uint8_t rtc_ram2[32] = {
+ 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00,
+ 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e,
+};
+
+#define SCR2_RTCLK 0x2
+#define SCR2_RTDATA 0x4
+#define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10))
+
+static void nextscr2_write(NeXTState *s, uint32_t val, int size)
+{
+ static int led;
+ static int phase;
+ static uint8_t old_scr2;
+ static uint8_t rtc_command;
+ static uint8_t rtc_value;
+ static uint8_t rtc_status = 0x90;
+ static uint8_t rtc_return;
+ uint8_t scr2_2;
+
+ if (size == 4) {
+ scr2_2 = (val >> 8) & 0xFF;
+ } else {
+ scr2_2 = val & 0xFF;
+ }
+
+ if (val & 0x1) {
+ DPRINTF("fault!\n");
+ led++;
+ if (led == 10) {
+ DPRINTF("LED flashing, possible fault!\n");
+ led = 0;
+ }
+ }
+
+ if (scr2_2 & 0x1) {
+ /* DPRINTF("RTC %x phase %i\n", scr2_2, phase); */
+ if (phase == -1) {
+ phase = 0;
+ }
+ /* If we are in going down clock... do something */
+ if (((old_scr2 & SCR2_RTCLK) != (scr2_2 & SCR2_RTCLK)) &&
+ ((scr2_2 & SCR2_RTCLK) == 0)) {
+ if (phase < 8) {
+ rtc_command = (rtc_command << 1) |
+ ((scr2_2 & SCR2_RTDATA) ? 1 : 0);
+ }
+ if (phase >= 8 && phase < 16) {
+ rtc_value = (rtc_value << 1) | ((scr2_2 & SCR2_RTDATA) ? 1 : 0);
+
+ /* if we read RAM register, output RT_DATA bit */
+ if (rtc_command <= 0x1F) {
+ scr2_2 = scr2_2 & (~SCR2_RTDATA);
+ if (s->rtc_ram[rtc_command] & (0x80 >> (phase - 8))) {
+ scr2_2 |= SCR2_RTDATA;
+ }
+
+ rtc_return = (rtc_return << 1) |
+ ((scr2_2 & SCR2_RTDATA) ? 1 : 0);
+ }
+ /* read the status 0x30 */
+ if (rtc_command == 0x30) {
+ scr2_2 = scr2_2 & (~SCR2_RTDATA);
+ /* for now status = 0x98 (new rtc + FTU) */
+ if (rtc_status & (0x80 >> (phase - 8))) {
+ scr2_2 |= SCR2_RTDATA;
+ }
+
+ rtc_return = (rtc_return << 1) |
+ ((scr2_2 & SCR2_RTDATA) ? 1 : 0);
+ }
+ /* read the status 0x31 */
+ if (rtc_command == 0x31) {
+ scr2_2 = scr2_2 & (~SCR2_RTDATA);
+ /* for now 0x00 */
+ if (0x00 & (0x80 >> (phase - 8))) {
+ scr2_2 |= SCR2_RTDATA;
+ }
+ rtc_return = (rtc_return << 1) |
+ ((scr2_2 & SCR2_RTDATA) ? 1 : 0);
+ }
+
+ if ((rtc_command >= 0x20) && (rtc_command <= 0x2F)) {
+ scr2_2 = scr2_2 & (~SCR2_RTDATA);
+ /* for now 0x00 */
+ time_t time_h = time(NULL);
+ struct tm *info = localtime(&time_h);
+ int ret = 0;
+
+ switch (rtc_command) {
+ case 0x20:
+ ret = SCR2_TOBCD(info->tm_sec);
+ break;
+ case 0x21:
+ ret = SCR2_TOBCD(info->tm_min);
+ break;
+ case 0x22:
+ ret = SCR2_TOBCD(info->tm_hour);
+ break;
+ case 0x24:
+ ret = SCR2_TOBCD(info->tm_mday);
+ break;
+ case 0x25:
+ ret = SCR2_TOBCD((info->tm_mon + 1));
+ break;
+ case 0x26:
+ ret = SCR2_TOBCD((info->tm_year - 100));
+ break;
+
+ }
+
+ if (ret & (0x80 >> (phase - 8))) {
+ scr2_2 |= SCR2_RTDATA;
+ }
+ rtc_return = (rtc_return << 1) |
+ ((scr2_2 & SCR2_RTDATA) ? 1 : 0);
+ }
+
+ }
+
+ phase++;
+ if (phase == 16) {
+ if (rtc_command >= 0x80 && rtc_command <= 0x9F) {
+ s->rtc_ram[rtc_command - 0x80] = rtc_value;
+#ifdef READ_RTC
+ FILE *fp = fopen("rtc.ram", "wb+");
+ int ret = fwrite(s->rtc_ram, 1, 32, fp);
+ if (ret != 32) {
+ abort();
+ }
+ fclose(fp);
+#endif
+ }
+ /* write to x30 register */
+ if (rtc_command == 0xB1) {
+ /* clear FTU */
+ if (rtc_value & 0x04) {
+ rtc_status = rtc_status & (~0x18);
+ s->int_status = s->int_status & (~0x04);
+ }
+ }
+ }
+ }
+ } else {
+ /* else end or abort */
+ phase = -1;
+ rtc_command = 0;
+ rtc_value = 0;
+ }
+ s->scr2 = val & 0xFFFF00FF;
+ s->scr2 |= scr2_2 << 8;
+ old_scr2 = scr2_2;
+}
+
+
+static uint32_t mmio_readb(NeXTState *s, hwaddr addr)
+{
+ switch (addr) {
+ case 0xc000:
+ return (s->scr1 >> 24) & 0xFF;
+ case 0xc001:
+ return (s->scr1 >> 16) & 0xFF;
+ case 0xc002:
+ return (s->scr1 >> 8) & 0xFF;
+ case 0xc003:
+ return (s->scr1 >> 0) & 0xFF;
+
+ case 0xd000:
+ return (s->scr2 >> 24) & 0xFF;
+ case 0xd001:
+ return (s->scr2 >> 16) & 0xFF;
+ case 0xd002:
+ return (s->scr2 >> 8) & 0xFF;
+ case 0xd003:
+ return (s->scr2 >> 0) & 0xFF;
+ case 0x14020:
+ DPRINTF("MMIO Read 0x4020\n");
+ return 0x7f;
+
+ default:
+ DPRINTF("MMIO Read B @ %"HWADDR_PRIx"\n", addr);
+ return 0x0;
+ }
+}
+static uint32_t mmio_readw(NeXTState *s, hwaddr addr)
+{
+ switch (addr) {
+ default:
+ DPRINTF("MMIO Read W @ %"HWADDR_PRIx"\n", addr);
+ return 0x0;
+ }
+}
+
+static uint32_t mmio_readl(NeXTState *s, hwaddr addr)
+{
+ switch (addr) {
+ case 0x7000:
+ DPRINTF("Read INT status: %x\n", s->int_status);
+ return s->int_status;
+
+ case 0x7800:
+ DPRINTF("MMIO Read INT mask: %x\n", s->int_mask);
+ return s->int_mask;
+
+ case 0xc000:
+ return s->scr1;
+
+ /*
+ * case 0xc800:
+ * return 0x01000000;
+ */
+
+ case 0xd000:
+ return s->scr2;
+
+ default:
+ DPRINTF("MMIO Read L @ %"HWADDR_PRIx"\n", addr);
+ return 0x0;
+ }
+}
+
+static void mmio_writeb(NeXTState *s, hwaddr addr, uint32_t val)
+{
+ switch (addr) {
+ case 0xd003:
+ nextscr2_write(s, val, 1);
+ break;
+ default:
+ DPRINTF("MMIO Write B @ %x with %x\n", (unsigned int)addr, val);
+ }
+
+}
+static void mmio_writew(NeXTState *s, hwaddr addr, uint32_t val)
+{
+ DPRINTF("MMIO Write W\n");
+}
+
+static void mmio_writel(NeXTState *s, hwaddr addr, uint32_t val)
+{
+ switch (addr) {
+ case 0x7000:
+ DPRINTF("INT Status old: %x new: %x\n", s->int_status, val);
+ s->int_status = val;
+ break;
+ case 0x7800:
+ DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, val);
+ s->int_mask = val;
+ break;
+ case 0xc000:
+ DPRINTF("SCR1 Write: %x\n", val);
+ break;
+ case 0xd000:
+ nextscr2_write(s, val, 4);
+ break;
+
+ default:
+ DPRINTF("MMIO Write l @ %x with %x\n", (unsigned int)addr, val);
+ }
+}
+
+static uint64_t mmio_readfn(void *opaque, hwaddr addr, unsigned size)
+{
+ NeXTState *ns = NEXT_MACHINE(opaque);
+
+ switch (size) {
+ case 1:
+ return mmio_readb(ns, addr);
+ case 2:
+ return mmio_readw(ns, addr);
+ case 4:
+ return mmio_readl(ns, addr);
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void mmio_writefn(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ NeXTState *ns = NEXT_MACHINE(opaque);
+
+ switch (size) {
+ case 1:
+ mmio_writeb(ns, addr, value);
+ break;
+ case 2:
+ mmio_writew(ns, addr, value);
+ break;
+ case 4:
+ mmio_writel(ns, addr, value);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static const MemoryRegionOps mmio_ops = {
+ .read = mmio_readfn,
+ .write = mmio_writefn,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 4,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static uint32_t scr_readb(NeXTState *s, hwaddr addr)
+{
+ switch (addr) {
+ case 0x14108:
+ DPRINTF("FD read @ %x\n", (unsigned int)addr);
+ return 0x40 | 0x04 | 0x2 | 0x1;
+ case 0x14020:
+ DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1);
+ return s->scsi_csr_1;
+
+ case 0x14021:
+ DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2);
+ return 0x40;
+
+ /*
+ * These 4 registers are the hardware timer, not sure which register
+ * is the latch instead of data, but no problems so far
+ */
+ case 0x1a000:
+ return 0xff & (clock() >> 24);
+ case 0x1a001:
+ return 0xff & (clock() >> 16);
+ case 0x1a002:
+ return 0xff & (clock() >> 8);
+ case 0x1a003:
+ /* Hack: We need to have this change consistently to make it work */
+ return 0xFF & clock();
+
+ default:
+ DPRINTF("BMAP Read B @ %x\n", (unsigned int)addr);
+ return 0;
+ }
+}
+
+static uint32_t scr_readw(NeXTState *s, hwaddr addr)
+{
+ DPRINTF("BMAP Read W @ %x\n", (unsigned int)addr);
+ return 0;
+}
+
+static uint32_t scr_readl(NeXTState *s, hwaddr addr)
+{
+ DPRINTF("BMAP Read L @ %x\n", (unsigned int)addr);
+ return 0;
+}
+
+#define SCSICSR_ENABLE 0x01
+#define SCSICSR_RESET 0x02 /* reset scsi dma */
+#define SCSICSR_FIFOFL 0x04
+#define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */
+#define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */
+#define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */
+
+static void scr_writeb(NeXTState *s, hwaddr addr, uint32_t value)
+{
+ switch (addr) {
+ case 0x14108:
+ DPRINTF("FDCSR Write: %x\n", value);
+
+ if (value == 0x0) {
+ /* qemu_irq_raise(s->fd_irq[0]); */
+ }
+ break;
+ case 0x14020: /* SCSI Control Register */
+ if (value & SCSICSR_FIFOFL) {
+ DPRINTF("SCSICSR FIFO Flush\n");
+ /* will have to add another irq to the esp if this is needed */
+ /* esp_puflush_fifo(esp_g); */
+ /* qemu_irq_pulse(s->scsi_dma); */
+ }
+
+ if (value & SCSICSR_ENABLE) {
+ DPRINTF("SCSICSR Enable\n");
+ /*
+ * qemu_irq_raise(s->scsi_dma);
+ * s->scsi_csr_1 = 0xc0;
+ * s->scsi_csr_1 |= 0x1;
+ * qemu_irq_pulse(s->scsi_dma);
+ */
+ }
+ /*
+ * else
+ * s->scsi_csr_1 &= ~SCSICSR_ENABLE;
+ */
+
+ if (value & SCSICSR_RESET) {
+ DPRINTF("SCSICSR Reset\n");
+ /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */
+ /* qemu_irq_raise(s->scsi_reset); */
+ /* s->scsi_csr_1 &= ~(SCSICSR_INTMASK |0x80|0x1); */
+
+ }
+ if (value & SCSICSR_DMADIR) {
+ DPRINTF("SCSICSR DMAdir\n");
+ }
+ if (value & SCSICSR_CPUDMA) {
+ DPRINTF("SCSICSR CPUDMA\n");
+ /* qemu_irq_raise(s->scsi_dma); */
+
+ s->int_status |= 0x4000000;
+ } else {
+ s->int_status &= ~(0x4000000);
+ }
+ if (value & SCSICSR_INTMASK) {
+ DPRINTF("SCSICSR INTMASK\n");
+ /*
+ * int_mask &= ~0x1000;
+ * s->scsi_csr_1 |= value;
+ * s->scsi_csr_1 &= ~SCSICSR_INTMASK;
+ * if (s->scsi_queued) {
+ * s->scsi_queued = 0;
+ * next_irq(s, NEXT_SCSI_I, level);
+ * }
+ */
+ } else {
+ /* int_mask |= 0x1000; */
+ }
+ if (value & 0x80) {
+ /* int_mask |= 0x1000; */
+ /* s->scsi_csr_1 |= 0x80; */
+ }
+ DPRINTF("SCSICSR Write: %x\n", value);
+ /* s->scsi_csr_1 = value; */
+ return;
+ /* Hardware timer latch - not implemented yet */
+ case 0x1a000:
+ default:
+ DPRINTF("BMAP Write B @ %x with %x\n", (unsigned int)addr, value);
+ }
+}
+
+static void scr_writew(NeXTState *s, hwaddr addr, uint32_t value)
+{
+ DPRINTF("BMAP Write W @ %x with %x\n", (unsigned int)addr, value);
+}
+
+static void scr_writel(NeXTState *s, hwaddr addr, uint32_t value)
+{
+ DPRINTF("BMAP Write L @ %x with %x\n", (unsigned int)addr, value);
+}
+
+static uint64_t scr_readfn(void *opaque, hwaddr addr, unsigned size)
+{
+ NeXTState *ns = NEXT_MACHINE(opaque);
+
+ switch (size) {
+ case 1:
+ return scr_readb(ns, addr);
+ case 2:
+ return scr_readw(ns, addr);
+ case 4:
+ return scr_readl(ns, addr);
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void scr_writefn(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ NeXTState *ns = NEXT_MACHINE(opaque);
+
+ switch (size) {
+ case 1:
+ scr_writeb(ns, addr, value);
+ break;
+ case 2:
+ scr_writew(ns, addr, value);
+ break;
+ case 4:
+ scr_writel(ns, addr, value);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static const MemoryRegionOps scr_ops = {
+ .read = scr_readfn,
+ .write = scr_writefn,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 4,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+#define NEXTDMA_SCSI(x) (0x10 + x)
+#define NEXTDMA_FD(x) (0x10 + x)
+#define NEXTDMA_ENTX(x) (0x110 + x)
+#define NEXTDMA_ENRX(x) (0x150 + x)
+#define NEXTDMA_CSR 0x0
+#define NEXTDMA_SAVED_NEXT 0x3FF0
+#define NEXTDMA_SAVED_LIMIT 0x3FF4
+#define NEXTDMA_SAVED_START 0x3FF8
+#define NEXTDMA_SAVED_STOP 0x3FFc
+#define NEXTDMA_NEXT 0x4000
+#define NEXTDMA_LIMIT 0x4004
+#define NEXTDMA_START 0x4008
+#define NEXTDMA_STOP 0x400c
+#define NEXTDMA_NEXT_INIT 0x4200
+#define NEXTDMA_SIZE 0x4204
+
+static void dma_writel(NeXTState *next_state, hwaddr addr, uint32_t value)
+{
+ /*
+ * uint16_t reg = addr;
+ * int channel = 0;
+ * switch (reg) {
+ * case SCSI"all registers:
+ * channel = NEXTDMA_SCSI;
+ * addr = addr - NEXTDMA_SCSI(0);
+ * }
+ */
+
+ switch (addr) {
+ case NEXTDMA_ENRX(NEXTDMA_CSR):
+ if (value & DMA_DEV2M) {
+ next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M;
+ }
+
+ if (value & DMA_SETENABLE) {
+ /* DPRINTF("SCSI DMA ENABLE\n"); */
+ next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE;
+ /*
+ * if (!(next_state->dma[NEXTDMA_ENRX].csr & DMA_DEV2M))
+ * DPRINTF("DMA TO DEVICE\n");
+ * else
+ * DPRINTF("DMA TO CPU\n");
+ * if (next_state->scsi_csr_1 & 1<<3)
+ * DPRINTF("SCSI DIR\n");
+ */
+ }
+ if (value & DMA_SETSUPDATE) {
+ next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE;
+ }
+ if (value & DMA_CLRCOMPLETE) {
+ next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE;
+ }
+
+ if (value & DMA_RESET) {
+ next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE |
+ DMA_ENABLE | DMA_DEV2M);
+ }
+ /* DPRINTF("RXCSR \tWrite: %x\n",value); */
+ break;
+ case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT):
+ next_state->dma[NEXTDMA_ENRX].next_initbuf = value;
+ break;
+ case NEXTDMA_ENRX(NEXTDMA_NEXT):
+ next_state->dma[NEXTDMA_ENRX].next = value;
+ break;
+ case NEXTDMA_ENRX(NEXTDMA_LIMIT):
+ next_state->dma[NEXTDMA_ENRX].limit = value;
+ break;
+ case NEXTDMA_SCSI(NEXTDMA_CSR):
+ if (value & DMA_DEV2M) {
+ next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M;
+ }
+ if (value & DMA_SETENABLE) {
+ /* DPRINTF("SCSI DMA ENABLE\n"); */
+ next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE;
+ /*
+ * if (!(next_state->dma[NEXTDMA_SCSI].csr & DMA_DEV2M)) {
+ * DPRINTF("DMA TO DEVICE\n");
+ * } else {
+ * DPRINTF("DMA TO CPU\n");
+ * }
+ * if (next_state->scsi_csr_1 & 1<<3) {
+ * DPRINTF("SCSI DIR\n");
+ * }
+ */
+ }
+ if (value & DMA_SETSUPDATE) {
+ next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE;
+ }
+ if (value & DMA_CLRCOMPLETE) {
+ next_state->dma[NEXTDMA_SCSI].csr &= ~DMA_COMPLETE;
+ }
+
+ if (value & DMA_RESET) {
+ next_state->dma[NEXTDMA_SCSI].csr &= ~(DMA_COMPLETE | DMA_SUPDATE |
+ DMA_ENABLE | DMA_DEV2M);
+ /* DPRINTF("SCSI DMA RESET\n"); */
+ }
+ /* DPRINTF("RXCSR \tWrite: %x\n",value); */
+ break;
+
+ case NEXTDMA_SCSI(NEXTDMA_NEXT):
+ next_state->dma[NEXTDMA_SCSI].next = value;
+ break;
+
+ case NEXTDMA_SCSI(NEXTDMA_LIMIT):
+ next_state->dma[NEXTDMA_SCSI].limit = value;
+ break;
+
+ case NEXTDMA_SCSI(NEXTDMA_START):
+ next_state->dma[NEXTDMA_SCSI].start = value;
+ break;
+
+ case NEXTDMA_SCSI(NEXTDMA_STOP):
+ next_state->dma[NEXTDMA_SCSI].stop = value;
+ break;
+
+ case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT):
+ next_state->dma[NEXTDMA_SCSI].next_initbuf = value;
+ break;
+
+ default:
+ DPRINTF("DMA write @ %x w/ %x\n", (unsigned int)addr, value);
+ }
+}
+
+static uint32_t dma_readl(NeXTState *next_state, hwaddr addr)
+{
+ switch (addr) {
+ case NEXTDMA_SCSI(NEXTDMA_CSR):
+ DPRINTF("SCSI DMA CSR READ\n");
+ return next_state->dma[NEXTDMA_SCSI].csr;
+ case NEXTDMA_ENRX(NEXTDMA_CSR):
+ return next_state->dma[NEXTDMA_ENRX].csr;
+ case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT):
+ return next_state->dma[NEXTDMA_ENRX].next_initbuf;
+ case NEXTDMA_ENRX(NEXTDMA_NEXT):
+ return next_state->dma[NEXTDMA_ENRX].next;
+ case NEXTDMA_ENRX(NEXTDMA_LIMIT):
+ return next_state->dma[NEXTDMA_ENRX].limit;
+
+ case NEXTDMA_SCSI(NEXTDMA_NEXT):
+ return next_state->dma[NEXTDMA_SCSI].next;
+ case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT):
+ return next_state->dma[NEXTDMA_SCSI].next_initbuf;
+ case NEXTDMA_SCSI(NEXTDMA_LIMIT):
+ return next_state->dma[NEXTDMA_SCSI].limit;
+ case NEXTDMA_SCSI(NEXTDMA_START):
+ return next_state->dma[NEXTDMA_SCSI].start;
+ case NEXTDMA_SCSI(NEXTDMA_STOP):
+ return next_state->dma[NEXTDMA_SCSI].stop;
+
+ default:
+ DPRINTF("DMA read @ %x\n", (unsigned int)addr);
+ return 0;
+ }
+
+ /*
+ * once the csr's are done, subtract 0x3FEC from the addr, and that will
+ * normalize the upper registers
+ */
+}
+
+static uint64_t dma_readfn(void *opaque, hwaddr addr, unsigned size)
+{
+ NeXTState *ns = NEXT_MACHINE(opaque);
+
+ switch (size) {
+ case 4:
+ return dma_readl(ns, addr);
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void dma_writefn(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ NeXTState *ns = NEXT_MACHINE(opaque);
+
+ switch (size) {
+ case 4:
+ dma_writel(ns, addr, value);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static const MemoryRegionOps dma_ops = {
+ .read = dma_readfn,
+ .write = dma_writefn,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 4,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+/*
+ * TODO: set the shift numbers as values in the enum, so the first switch
+ * will not be needed
+ */
+void next_irq(void *opaque, int number, int level)
+{
+ M68kCPU *cpu = opaque;
+ int shift = 0;
+ NeXTState *ns = NEXT_MACHINE(qdev_get_machine());
+
+ /* first switch sets interupt status */
+ /* DPRINTF("IRQ %i\n",number); */
+ switch (number) {
+ /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */
+ case NEXT_FD_I:
+ shift = 7;;
+ break;
+ case NEXT_KBD_I:
+ shift = 3;
+ break;
+ case NEXT_PWR_I:
+ shift = 2;
+ break;
+ case NEXT_ENRX_I:
+ shift = 9;
+ break;
+ case NEXT_ENTX_I:
+ shift = 10;
+ break;
+ case NEXT_SCSI_I:
+ shift = 12;
+ break;
+ case NEXT_CLK_I:
+ shift = 5;
+ break;
+
+ /* level 5 - scc (serial) */
+ case NEXT_SCC_I:
+ shift = 17;
+ break;
+
+ /* level 6 - audio etherrx/tx dma */
+ case NEXT_ENTX_DMA_I:
+ shift = 28;
+ break;
+ case NEXT_ENRX_DMA_I:
+ shift = 27;
+ break;
+ case NEXT_SCSI_DMA_I:
+ shift = 26;
+ break;
+ case NEXT_SND_I:
+ shift = 23;
+ break;
+ case NEXT_SCC_DMA_I:
+ shift = 21;
+ break;
+
+ }
+ /*
+ * this HAS to be wrong, the interrupt handlers in mach and together
+ * int_status and int_mask and return if there is a hit
+ */
+ if (ns->int_mask & (1 << shift)) {
+ DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc);
+ /* return; */
+ }
+
+ /* second switch triggers the correct interrupt */
+ if (level) {
+ ns->int_status |= 1 << shift;
+
+ switch (number) {
+ /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */
+ case NEXT_FD_I:
+ case NEXT_KBD_I:
+ case NEXT_PWR_I:
+ case NEXT_ENRX_I:
+ case NEXT_ENTX_I:
+ case NEXT_SCSI_I:
+ case NEXT_CLK_I:
+ m68k_set_irq_level(cpu, 3, 27);
+ break;
+
+ /* level 5 - scc (serial) */
+ case NEXT_SCC_I:
+ m68k_set_irq_level(cpu, 5, 29);
+ break;
+
+ /* level 6 - audio etherrx/tx dma */
+ case NEXT_ENTX_DMA_I:
+ case NEXT_ENRX_DMA_I:
+ case NEXT_SCSI_DMA_I:
+ case NEXT_SND_I:
+ case NEXT_SCC_DMA_I:
+ m68k_set_irq_level(cpu, 6, 30);
+ break;
+ }
+ } else {
+ ns->int_status &= ~(1 << shift);
+ cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
+ }
+}
+
+static void next_cube_init(MachineState *machine)
+{
+ M68kCPU *cpu;
+ CPUM68KState *env;
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
+ MemoryRegion *rom = g_new(MemoryRegion, 1);
+ MemoryRegion *mmiomem = g_new(MemoryRegion, 1);
+ MemoryRegion *scrmem = g_new(MemoryRegion, 1);
+ MemoryRegion *dmamem = g_new(MemoryRegion, 1);
+ MemoryRegion *unknownmem = g_new(MemoryRegion, 1);
+ MemoryRegion *sysmem = get_system_memory();
+ NeXTState *ns = NEXT_MACHINE(machine);
+
+ /* Initialize the cpu core */
+ cpu = M68K_CPU(cpu_create(machine->cpu_type));
+ if (!cpu) {
+ error_report("Unable to find m68k CPU definition");
+ exit(1);
+ }
+ env = &cpu->env;
+
+ /* Initialize CPU registers. */
+ env->vbr = 0;
+ env->pc = 0x100001e; /* technically should read vector */
+ env->sr = 0x2700;
+
+ /* Set internal registers to initial values */
+ /* 0x0000XX00 << vital bits */
+ ns->scr1 = 0x00011102;
+ ns->scr2 = 0x00ff0c80;
+
+ ns->int_mask = 0x0; /* 88027640; */
+ ns->int_status = 0x0; /* 200; */
+
+ /* Load RTC RAM - TODO: provide possibility to load contents from file */
+ memcpy(ns->rtc_ram, rtc_ram2, 32);
+
+ /* 64MB RAM starting at 0x4000000 */
+ memory_region_allocate_system_memory(ram, NULL, "next.ram", ram_size);
+ memory_region_add_subregion(sysmem, 0x4000000, ram);
+
+ /* Framebuffer */
+ nextfb_init();
+
+ /* MMIO */
+ memory_region_init_io(mmiomem, NULL, &mmio_ops, machine, "next.mmio",
+ 0xD0000);
+ memory_region_add_subregion(sysmem, 0x2000000, mmiomem);
+
+ /* BMAP - acts as a catch-all for now */
+ memory_region_init_io(scrmem, NULL, &scr_ops, machine, "next.scr",
+ 0x3A7FF);
+ memory_region_add_subregion(sysmem, 0x2100000, scrmem);
+
+ /* KBD */
+ nextkbd_init();
+
+ /* Load ROM here */
+ if (bios_name == NULL) {
+ bios_name = ROM_FILE;
+ }
+ /* still not sure if the rom should also be mapped at 0x0*/
+ memory_region_init_rom(rom, NULL, "next.rom", 0x20000, &error_fatal);
+ memory_region_add_subregion(sysmem, 0x1000000, rom);
+ if (load_image_targphys(bios_name, 0x1000000, 0x20000) < 0) {
+ if (!qtest_enabled()) {
+ error_report("Failed to load firmware '%s'", bios_name);
+ }
+ }
+
+ /* TODO: */
+ /* Serial */
+ /* Network */
+ /* SCSI */
+
+ /* DMA */
+ memory_region_init_io(dmamem, NULL, &dma_ops, machine, "next.dma", 0x5000);
+ memory_region_add_subregion(sysmem, 0x2000000, dmamem);
+
+ /* FIXME: Why does the bios access this memory area? */
+ memory_region_allocate_system_memory(unknownmem, NULL, "next.unknown", 16);
+ memory_region_add_subregion(sysmem, 0x820c0020, unknownmem);
+}
+
+static void next_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "NeXT Cube";
+ mc->init = next_cube_init;
+ mc->default_ram_size = RAM_SIZE;
+ mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040");
+}
+
+static const TypeInfo next_typeinfo = {
+ .name = TYPE_NEXT_MACHINE,
+ .parent = TYPE_MACHINE,
+ .class_init = next_machine_class_init,
+ .instance_size = sizeof(NeXTState),
+};
+
+static void next_register_type(void)
+{
+ type_register_static(&next_typeinfo);
+}
+
+type_init(next_register_type)
diff --git a/include/hw/m68k/next-cube.h b/include/hw/m68k/next-cube.h
index 88e94f6595..d7df6a223b 100644
--- a/include/hw/m68k/next-cube.h
+++ b/include/hw/m68k/next-cube.h
@@ -2,6 +2,44 @@
#ifndef NEXT_CUBE_H
#define NEXT_CUBE_H
+enum next_dma_chan {
+ NEXTDMA_FD,
+ NEXTDMA_ENRX,
+ NEXTDMA_ENTX,
+ NEXTDMA_SCSI,
+ NEXTDMA_SCC,
+ NEXTDMA_SND
+};
+
+#define DMA_ENABLE 0x01000000
+#define DMA_SUPDATE 0x02000000
+#define DMA_COMPLETE 0x08000000
+
+#define DMA_M2DEV 0x0
+#define DMA_SETENABLE 0x00010000
+#define DMA_SETSUPDATE 0x00020000
+#define DMA_DEV2M 0x00040000
+#define DMA_CLRCOMPLETE 0x00080000
+#define DMA_RESET 0x00100000
+
+enum next_irqs {
+ NEXT_FD_I,
+ NEXT_KBD_I,
+ NEXT_PWR_I,
+ NEXT_ENRX_I,
+ NEXT_ENTX_I,
+ NEXT_SCSI_I,
+ NEXT_CLK_I,
+ NEXT_SCC_I,
+ NEXT_ENTX_DMA_I,
+ NEXT_ENRX_DMA_I,
+ NEXT_SCSI_DMA_I,
+ NEXT_SCC_DMA_I,
+ NEXT_SND_I
+};
+
+void next_irq(void *opaque, int number, int level);
+
/* next-fb.c */
void nextfb_init(void);
--
2.21.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH v2 3/4] m68k: Add NeXTcube machine
2019-06-28 18:15 ` [Qemu-devel] [PATCH v2 3/4] m68k: Add NeXTcube machine Thomas Huth
@ 2019-06-29 12:26 ` Philippe Mathieu-Daudé
2019-06-29 12:36 ` Philippe Mathieu-Daudé
2019-07-02 17:43 ` Thomas Huth
0 siblings, 2 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-06-29 12:26 UTC (permalink / raw)
To: Thomas Huth, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Laurent Vivier
On 6/28/19 8:15 PM, Thomas Huth wrote:
> It is still quite incomplete (no SCSI, no floppy emulation, no network,
> etc.), but the firmware already shows up the debug monitor prompt in the
> framebuffer display, so at least the very basics are already working.
>
> This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at
>
> https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-cube.c
>
> and altered quite a bit to fit the latest interface and coding conventions
> of the current QEMU.
>
> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
> ---
> hw/m68k/Makefile.objs | 2 +-
> hw/m68k/next-cube.c | 988 ++++++++++++++++++++++++++++++++++++
> include/hw/m68k/next-cube.h | 38 ++
> 3 files changed, 1027 insertions(+), 1 deletion(-)
> create mode 100644 hw/m68k/next-cube.c
>
> diff --git a/hw/m68k/Makefile.objs b/hw/m68k/Makefile.objs
> index 688002cac1..f25854730d 100644
> --- a/hw/m68k/Makefile.objs
> +++ b/hw/m68k/Makefile.objs
> @@ -1,3 +1,3 @@
> obj-$(CONFIG_AN5206) += an5206.o mcf5206.o
> obj-$(CONFIG_MCF5208) += mcf5208.o mcf_intc.o
> -obj-$(CONFIG_NEXTCUBE) += next-kbd.o
> +obj-$(CONFIG_NEXTCUBE) += next-kbd.o next-cube.o
> diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c
> new file mode 100644
> index 0000000000..700d386fb9
> --- /dev/null
> +++ b/hw/m68k/next-cube.c
> @@ -0,0 +1,988 @@
> +/*
> + * NeXT Cube System Driver
> + *
> + * Copyright (c) 2011 Bryce Lanham
> + *
> + * This code is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published
> + * by the Free Software Foundation; either version 2 of the License,
> + * or (at your option) any later version.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "exec/hwaddr.h"
> +#include "exec/address-spaces.h"
> +#include "sysemu/sysemu.h"
> +#include "sysemu/qtest.h"
> +#include "hw/hw.h"
> +#include "hw/m68k/next-cube.h"
> +#include "hw/boards.h"
> +#include "hw/loader.h"
> +#include "hw/scsi/esp.h"
> +#include "hw/sysbus.h"
> +#include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */
> +#include "hw/block/fdc.h"
> +#include "qapi/error.h"
> +#include "ui/console.h"
> +#include "target/m68k/cpu.h"
> +
> +/* #define DEBUG_NEXT */
> +#ifdef DEBUG_NEXT
> +#define DPRINTF(fmt, ...) \
> + do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0)
> +#else
> +#define DPRINTF(fmt, ...) do { } while (0)
> +#endif
> +
> +#define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube")
> +#define NEXT_MACHINE(obj) OBJECT_CHECK(NeXTState, (obj), TYPE_NEXT_MACHINE)
> +
> +#define ENTRY 0x0100001e
> +#define RAM_SIZE 0x4000000
> +#define ROM_FILE "rom66.bin"
Where can we find this file to test your work?
> +
> +typedef struct next_dma {
> + uint32_t csr;
> +
> + uint32_t saved_next;
> + uint32_t saved_limit;
> + uint32_t saved_start;
> + uint32_t saved_stop;
> +
> + uint32_t next;
> + uint32_t limit;
> + uint32_t start;
> + uint32_t stop;
> +
> + uint32_t next_initbuf;
> + uint32_t size;
> +} next_dma;
> +
> +typedef struct {
> + MachineState parent;
> +
> + uint32_t int_mask;
> + uint32_t int_status;
> +
> + uint8_t scsi_csr_1;
> + uint8_t scsi_csr_2;
> + next_dma dma[10];
> + qemu_irq *scsi_irq;
> + qemu_irq scsi_dma;
> + qemu_irq scsi_reset;
> + qemu_irq *fd_irq;
> +
> + uint32_t scr1;
> + uint32_t scr2;
> +
> + uint8_t rtc_ram[32];
> +} NeXTState;
> +
> +/* Thanks to NeXT forums for this */
> +/*
> +static const uint8_t rtc_ram3[32] = {
> + 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00,
> + 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13
> +};
> +*/
> +static const uint8_t rtc_ram2[32] = {
> + 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00,
> + 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e,
> +};
> +
> +#define SCR2_RTCLK 0x2
> +#define SCR2_RTDATA 0x4
> +#define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10))
> +
> +static void nextscr2_write(NeXTState *s, uint32_t val, int size)
> +{
> + static int led;
> + static int phase;
> + static uint8_t old_scr2;
> + static uint8_t rtc_command;
> + static uint8_t rtc_value;
> + static uint8_t rtc_status = 0x90;
> + static uint8_t rtc_return;
> + uint8_t scr2_2;
> +
> + if (size == 4) {
> + scr2_2 = (val >> 8) & 0xFF;
> + } else {
> + scr2_2 = val & 0xFF;
> + }
> +
> + if (val & 0x1) {
> + DPRINTF("fault!\n");
> + led++;
> + if (led == 10) {
> + DPRINTF("LED flashing, possible fault!\n");
> + led = 0;
> + }
> + }
> +
> + if (scr2_2 & 0x1) {
> + /* DPRINTF("RTC %x phase %i\n", scr2_2, phase); */
> + if (phase == -1) {
> + phase = 0;
> + }
> + /* If we are in going down clock... do something */
> + if (((old_scr2 & SCR2_RTCLK) != (scr2_2 & SCR2_RTCLK)) &&
> + ((scr2_2 & SCR2_RTCLK) == 0)) {
> + if (phase < 8) {
> + rtc_command = (rtc_command << 1) |
> + ((scr2_2 & SCR2_RTDATA) ? 1 : 0);
> + }
> + if (phase >= 8 && phase < 16) {
> + rtc_value = (rtc_value << 1) | ((scr2_2 & SCR2_RTDATA) ? 1 : 0);
> +
> + /* if we read RAM register, output RT_DATA bit */
> + if (rtc_command <= 0x1F) {
> + scr2_2 = scr2_2 & (~SCR2_RTDATA);
> + if (s->rtc_ram[rtc_command] & (0x80 >> (phase - 8))) {
> + scr2_2 |= SCR2_RTDATA;
> + }
> +
> + rtc_return = (rtc_return << 1) |
> + ((scr2_2 & SCR2_RTDATA) ? 1 : 0);
> + }
> + /* read the status 0x30 */
> + if (rtc_command == 0x30) {
> + scr2_2 = scr2_2 & (~SCR2_RTDATA);
> + /* for now status = 0x98 (new rtc + FTU) */
> + if (rtc_status & (0x80 >> (phase - 8))) {
> + scr2_2 |= SCR2_RTDATA;
> + }
> +
> + rtc_return = (rtc_return << 1) |
> + ((scr2_2 & SCR2_RTDATA) ? 1 : 0);
> + }
> + /* read the status 0x31 */
> + if (rtc_command == 0x31) {
> + scr2_2 = scr2_2 & (~SCR2_RTDATA);
> + /* for now 0x00 */
> + if (0x00 & (0x80 >> (phase - 8))) {
> + scr2_2 |= SCR2_RTDATA;
> + }
> + rtc_return = (rtc_return << 1) |
> + ((scr2_2 & SCR2_RTDATA) ? 1 : 0);
> + }
> +
> + if ((rtc_command >= 0x20) && (rtc_command <= 0x2F)) {
> + scr2_2 = scr2_2 & (~SCR2_RTDATA);
> + /* for now 0x00 */
> + time_t time_h = time(NULL);
> + struct tm *info = localtime(&time_h);
> + int ret = 0;
> +
> + switch (rtc_command) {
> + case 0x20:
> + ret = SCR2_TOBCD(info->tm_sec);
> + break;
> + case 0x21:
> + ret = SCR2_TOBCD(info->tm_min);
> + break;
> + case 0x22:
> + ret = SCR2_TOBCD(info->tm_hour);
> + break;
> + case 0x24:
> + ret = SCR2_TOBCD(info->tm_mday);
> + break;
> + case 0x25:
> + ret = SCR2_TOBCD((info->tm_mon + 1));
> + break;
> + case 0x26:
> + ret = SCR2_TOBCD((info->tm_year - 100));
> + break;
> +
> + }
> +
> + if (ret & (0x80 >> (phase - 8))) {
> + scr2_2 |= SCR2_RTDATA;
> + }
> + rtc_return = (rtc_return << 1) |
> + ((scr2_2 & SCR2_RTDATA) ? 1 : 0);
> + }
> +
> + }
> +
> + phase++;
> + if (phase == 16) {
> + if (rtc_command >= 0x80 && rtc_command <= 0x9F) {
> + s->rtc_ram[rtc_command - 0x80] = rtc_value;
> +#ifdef READ_RTC
> + FILE *fp = fopen("rtc.ram", "wb+");
> + int ret = fwrite(s->rtc_ram, 1, 32, fp);
> + if (ret != 32) {
> + abort();
> + }
> + fclose(fp);
> +#endif
> + }
> + /* write to x30 register */
> + if (rtc_command == 0xB1) {
> + /* clear FTU */
> + if (rtc_value & 0x04) {
> + rtc_status = rtc_status & (~0x18);
> + s->int_status = s->int_status & (~0x04);
> + }
> + }
> + }
> + }
> + } else {
> + /* else end or abort */
> + phase = -1;
> + rtc_command = 0;
> + rtc_value = 0;
> + }
> + s->scr2 = val & 0xFFFF00FF;
> + s->scr2 |= scr2_2 << 8;
> + old_scr2 = scr2_2;
> +}
> +
> +
> +static uint32_t mmio_readb(NeXTState *s, hwaddr addr)
> +{
> + switch (addr) {
> + case 0xc000:
> + return (s->scr1 >> 24) & 0xFF;
> + case 0xc001:
> + return (s->scr1 >> 16) & 0xFF;
> + case 0xc002:
> + return (s->scr1 >> 8) & 0xFF;
> + case 0xc003:
> + return (s->scr1 >> 0) & 0xFF;
So you have a 32-bit implementation (DMA accessed device?).
memory::access_with_adjusted_size() already does this work
for you if you use:
.impl.min_access_size = 4,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
> +
> + case 0xd000:
> + return (s->scr2 >> 24) & 0xFF;
> + case 0xd001:
> + return (s->scr2 >> 16) & 0xFF;
> + case 0xd002:
> + return (s->scr2 >> 8) & 0xFF;
> + case 0xd003:
> + return (s->scr2 >> 0) & 0xFF;
> + case 0x14020:
> + DPRINTF("MMIO Read 0x4020\n");
> + return 0x7f;
> +
> + default:
> + DPRINTF("MMIO Read B @ %"HWADDR_PRIx"\n", addr);
> + return 0x0;
> + }
> +}
> +static uint32_t mmio_readw(NeXTState *s, hwaddr addr)
> +{
> + switch (addr) {
> + default:
> + DPRINTF("MMIO Read W @ %"HWADDR_PRIx"\n", addr);
> + return 0x0;
Hmmm again the weird 16-bit case...
> + }
> +}
> +
> +static uint32_t mmio_readl(NeXTState *s, hwaddr addr)
> +{
> + switch (addr) {
> + case 0x7000:
> + DPRINTF("Read INT status: %x\n", s->int_status);
> + return s->int_status;
> +
> + case 0x7800:
> + DPRINTF("MMIO Read INT mask: %x\n", s->int_mask);
> + return s->int_mask;
> +
> + case 0xc000:
> + return s->scr1;
> +
> + /*
> + * case 0xc800:
> + * return 0x01000000;
> + */
> +
> + case 0xd000:
> + return s->scr2;
> +
> + default:
> + DPRINTF("MMIO Read L @ %"HWADDR_PRIx"\n", addr);
> + return 0x0;
> + }
> +}
> +
> +static void mmio_writeb(NeXTState *s, hwaddr addr, uint32_t val)
> +{
> + switch (addr) {
> + case 0xd003:
> + nextscr2_write(s, val, 1);
> + break;
> + default:
> + DPRINTF("MMIO Write B @ %x with %x\n", (unsigned int)addr, val);
> + }
> +
> +}
> +static void mmio_writew(NeXTState *s, hwaddr addr, uint32_t val)
> +{
> + DPRINTF("MMIO Write W\n");
> +}
> +
> +static void mmio_writel(NeXTState *s, hwaddr addr, uint32_t val)
> +{
> + switch (addr) {
> + case 0x7000:
> + DPRINTF("INT Status old: %x new: %x\n", s->int_status, val);
> + s->int_status = val;
> + break;
> + case 0x7800:
> + DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, val);
> + s->int_mask = val;
> + break;
> + case 0xc000:
> + DPRINTF("SCR1 Write: %x\n", val);
> + break;
> + case 0xd000:
> + nextscr2_write(s, val, 4);
> + break;
> +
> + default:
> + DPRINTF("MMIO Write l @ %x with %x\n", (unsigned int)addr, val);
> + }
> +}
> +
> +static uint64_t mmio_readfn(void *opaque, hwaddr addr, unsigned size)
> +{
> + NeXTState *ns = NEXT_MACHINE(opaque);
> +
> + switch (size) {
> + case 1:
> + return mmio_readb(ns, addr);
> + case 2:
> + return mmio_readw(ns, addr);
> + case 4:
> + return mmio_readl(ns, addr);
> + default:
> + g_assert_not_reached();
> + }
> +}
> +
> +static void mmio_writefn(void *opaque, hwaddr addr, uint64_t value,
> + unsigned size)
> +{
> + NeXTState *ns = NEXT_MACHINE(opaque);
> +
> + switch (size) {
> + case 1:
> + mmio_writeb(ns, addr, value);
> + break;
> + case 2:
> + mmio_writew(ns, addr, value);
> + break;
> + case 4:
> + mmio_writel(ns, addr, value);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> +}
> +
> +static const MemoryRegionOps mmio_ops = {
> + .read = mmio_readfn,
> + .write = mmio_writefn,
> + .valid.min_access_size = 1,
> + .valid.max_access_size = 4,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +static uint32_t scr_readb(NeXTState *s, hwaddr addr)
> +{
> + switch (addr) {
> + case 0x14108:
> + DPRINTF("FD read @ %x\n", (unsigned int)addr);
> + return 0x40 | 0x04 | 0x2 | 0x1;
> + case 0x14020:
> + DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1);
> + return s->scsi_csr_1;
> +
> + case 0x14021:
> + DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2);
> + return 0x40;
> +
> + /*
> + * These 4 registers are the hardware timer, not sure which register
> + * is the latch instead of data, but no problems so far
> + */
> + case 0x1a000:
> + return 0xff & (clock() >> 24);
> + case 0x1a001:
> + return 0xff & (clock() >> 16);
> + case 0x1a002:
> + return 0xff & (clock() >> 8);
> + case 0x1a003:
> + /* Hack: We need to have this change consistently to make it work */
> + return 0xFF & clock();
> +
> + default:
> + DPRINTF("BMAP Read B @ %x\n", (unsigned int)addr);
> + return 0;
> + }
> +}
> +
> +static uint32_t scr_readw(NeXTState *s, hwaddr addr)
> +{
> + DPRINTF("BMAP Read W @ %x\n", (unsigned int)addr);
> + return 0;
> +}
> +
> +static uint32_t scr_readl(NeXTState *s, hwaddr addr)
> +{
> + DPRINTF("BMAP Read L @ %x\n", (unsigned int)addr);
> + return 0;
> +}
> +
> +#define SCSICSR_ENABLE 0x01
> +#define SCSICSR_RESET 0x02 /* reset scsi dma */
> +#define SCSICSR_FIFOFL 0x04
> +#define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */
> +#define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */
> +#define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */
> +
> +static void scr_writeb(NeXTState *s, hwaddr addr, uint32_t value)
> +{
> + switch (addr) {
> + case 0x14108:
> + DPRINTF("FDCSR Write: %x\n", value);
> +
> + if (value == 0x0) {
> + /* qemu_irq_raise(s->fd_irq[0]); */
> + }
> + break;
> + case 0x14020: /* SCSI Control Register */
> + if (value & SCSICSR_FIFOFL) {
> + DPRINTF("SCSICSR FIFO Flush\n");
> + /* will have to add another irq to the esp if this is needed */
> + /* esp_puflush_fifo(esp_g); */
> + /* qemu_irq_pulse(s->scsi_dma); */
> + }
> +
> + if (value & SCSICSR_ENABLE) {
> + DPRINTF("SCSICSR Enable\n");
> + /*
> + * qemu_irq_raise(s->scsi_dma);
> + * s->scsi_csr_1 = 0xc0;
> + * s->scsi_csr_1 |= 0x1;
> + * qemu_irq_pulse(s->scsi_dma);
> + */
> + }
> + /*
> + * else
> + * s->scsi_csr_1 &= ~SCSICSR_ENABLE;
> + */
> +
> + if (value & SCSICSR_RESET) {
> + DPRINTF("SCSICSR Reset\n");
> + /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */
> + /* qemu_irq_raise(s->scsi_reset); */
> + /* s->scsi_csr_1 &= ~(SCSICSR_INTMASK |0x80|0x1); */
> +
> + }
> + if (value & SCSICSR_DMADIR) {
> + DPRINTF("SCSICSR DMAdir\n");
> + }
> + if (value & SCSICSR_CPUDMA) {
> + DPRINTF("SCSICSR CPUDMA\n");
> + /* qemu_irq_raise(s->scsi_dma); */
> +
> + s->int_status |= 0x4000000;
> + } else {
> + s->int_status &= ~(0x4000000);
> + }
> + if (value & SCSICSR_INTMASK) {
> + DPRINTF("SCSICSR INTMASK\n");
> + /*
> + * int_mask &= ~0x1000;
> + * s->scsi_csr_1 |= value;
> + * s->scsi_csr_1 &= ~SCSICSR_INTMASK;
> + * if (s->scsi_queued) {
> + * s->scsi_queued = 0;
> + * next_irq(s, NEXT_SCSI_I, level);
> + * }
> + */
> + } else {
> + /* int_mask |= 0x1000; */
> + }
> + if (value & 0x80) {
> + /* int_mask |= 0x1000; */
> + /* s->scsi_csr_1 |= 0x80; */
> + }
> + DPRINTF("SCSICSR Write: %x\n", value);
> + /* s->scsi_csr_1 = value; */
> + return;
> + /* Hardware timer latch - not implemented yet */
> + case 0x1a000:
> + default:
> + DPRINTF("BMAP Write B @ %x with %x\n", (unsigned int)addr, value);
> + }
> +}
> +
> +static void scr_writew(NeXTState *s, hwaddr addr, uint32_t value)
> +{
> + DPRINTF("BMAP Write W @ %x with %x\n", (unsigned int)addr, value);
So it seems we have .valid.max_access_size = 1, and you can simplify
a lot of code.
> +}
> +
> +static void scr_writel(NeXTState *s, hwaddr addr, uint32_t value)
> +{
> + DPRINTF("BMAP Write L @ %x with %x\n", (unsigned int)addr, value);
> +}
> +
> +static uint64_t scr_readfn(void *opaque, hwaddr addr, unsigned size)
> +{
> + NeXTState *ns = NEXT_MACHINE(opaque);
> +
> + switch (size) {
> + case 1:
> + return scr_readb(ns, addr);
> + case 2:
> + return scr_readw(ns, addr);
> + case 4:
> + return scr_readl(ns, addr);
> + default:
> + g_assert_not_reached();
> + }
> +}
> +
> +static void scr_writefn(void *opaque, hwaddr addr, uint64_t value,
> + unsigned size)
> +{
> + NeXTState *ns = NEXT_MACHINE(opaque);
> +
> + switch (size) {
> + case 1:
> + scr_writeb(ns, addr, value);
> + break;
> + case 2:
> + scr_writew(ns, addr, value);
> + break;
> + case 4:
> + scr_writel(ns, addr, value);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> +}
> +
> +static const MemoryRegionOps scr_ops = {
> + .read = scr_readfn,
> + .write = scr_writefn,
> + .valid.min_access_size = 1,
> + .valid.max_access_size = 4,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +#define NEXTDMA_SCSI(x) (0x10 + x)
> +#define NEXTDMA_FD(x) (0x10 + x)
> +#define NEXTDMA_ENTX(x) (0x110 + x)
> +#define NEXTDMA_ENRX(x) (0x150 + x)
> +#define NEXTDMA_CSR 0x0
> +#define NEXTDMA_SAVED_NEXT 0x3FF0
> +#define NEXTDMA_SAVED_LIMIT 0x3FF4
> +#define NEXTDMA_SAVED_START 0x3FF8
> +#define NEXTDMA_SAVED_STOP 0x3FFc
> +#define NEXTDMA_NEXT 0x4000
> +#define NEXTDMA_LIMIT 0x4004
> +#define NEXTDMA_START 0x4008
> +#define NEXTDMA_STOP 0x400c
> +#define NEXTDMA_NEXT_INIT 0x4200
> +#define NEXTDMA_SIZE 0x4204
> +
> +static void dma_writel(NeXTState *next_state, hwaddr addr, uint32_t value)
> +{
> + /*
> + * uint16_t reg = addr;
> + * int channel = 0;
> + * switch (reg) {
> + * case SCSI"all registers:
> + * channel = NEXTDMA_SCSI;
> + * addr = addr - NEXTDMA_SCSI(0);
> + * }
> + */
> +
> + switch (addr) {
> + case NEXTDMA_ENRX(NEXTDMA_CSR):
> + if (value & DMA_DEV2M) {
> + next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M;
> + }
> +
> + if (value & DMA_SETENABLE) {
> + /* DPRINTF("SCSI DMA ENABLE\n"); */
> + next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE;
> + /*
> + * if (!(next_state->dma[NEXTDMA_ENRX].csr & DMA_DEV2M))
> + * DPRINTF("DMA TO DEVICE\n");
> + * else
> + * DPRINTF("DMA TO CPU\n");
> + * if (next_state->scsi_csr_1 & 1<<3)
> + * DPRINTF("SCSI DIR\n");
> + */
> + }
> + if (value & DMA_SETSUPDATE) {
> + next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE;
> + }
> + if (value & DMA_CLRCOMPLETE) {
> + next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE;
> + }
> +
> + if (value & DMA_RESET) {
> + next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE |
> + DMA_ENABLE | DMA_DEV2M);
> + }
> + /* DPRINTF("RXCSR \tWrite: %x\n",value); */
> + break;
> + case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT):
> + next_state->dma[NEXTDMA_ENRX].next_initbuf = value;
> + break;
> + case NEXTDMA_ENRX(NEXTDMA_NEXT):
> + next_state->dma[NEXTDMA_ENRX].next = value;
> + break;
> + case NEXTDMA_ENRX(NEXTDMA_LIMIT):
> + next_state->dma[NEXTDMA_ENRX].limit = value;
> + break;
> + case NEXTDMA_SCSI(NEXTDMA_CSR):
> + if (value & DMA_DEV2M) {
> + next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M;
> + }
> + if (value & DMA_SETENABLE) {
> + /* DPRINTF("SCSI DMA ENABLE\n"); */
> + next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE;
> + /*
> + * if (!(next_state->dma[NEXTDMA_SCSI].csr & DMA_DEV2M)) {
> + * DPRINTF("DMA TO DEVICE\n");
> + * } else {
> + * DPRINTF("DMA TO CPU\n");
> + * }
> + * if (next_state->scsi_csr_1 & 1<<3) {
> + * DPRINTF("SCSI DIR\n");
> + * }
> + */
> + }
> + if (value & DMA_SETSUPDATE) {
> + next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE;
> + }
> + if (value & DMA_CLRCOMPLETE) {
> + next_state->dma[NEXTDMA_SCSI].csr &= ~DMA_COMPLETE;
> + }
> +
> + if (value & DMA_RESET) {
> + next_state->dma[NEXTDMA_SCSI].csr &= ~(DMA_COMPLETE | DMA_SUPDATE |
> + DMA_ENABLE | DMA_DEV2M);
> + /* DPRINTF("SCSI DMA RESET\n"); */
> + }
> + /* DPRINTF("RXCSR \tWrite: %x\n",value); */
> + break;
> +
> + case NEXTDMA_SCSI(NEXTDMA_NEXT):
> + next_state->dma[NEXTDMA_SCSI].next = value;
> + break;
> +
> + case NEXTDMA_SCSI(NEXTDMA_LIMIT):
> + next_state->dma[NEXTDMA_SCSI].limit = value;
> + break;
> +
> + case NEXTDMA_SCSI(NEXTDMA_START):
> + next_state->dma[NEXTDMA_SCSI].start = value;
> + break;
> +
> + case NEXTDMA_SCSI(NEXTDMA_STOP):
> + next_state->dma[NEXTDMA_SCSI].stop = value;
> + break;
> +
> + case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT):
> + next_state->dma[NEXTDMA_SCSI].next_initbuf = value;
> + break;
> +
> + default:
> + DPRINTF("DMA write @ %x w/ %x\n", (unsigned int)addr, value);
> + }
> +}
> +
> +static uint32_t dma_readl(NeXTState *next_state, hwaddr addr)
> +{
> + switch (addr) {
> + case NEXTDMA_SCSI(NEXTDMA_CSR):
> + DPRINTF("SCSI DMA CSR READ\n");
> + return next_state->dma[NEXTDMA_SCSI].csr;
> + case NEXTDMA_ENRX(NEXTDMA_CSR):
> + return next_state->dma[NEXTDMA_ENRX].csr;
> + case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT):
> + return next_state->dma[NEXTDMA_ENRX].next_initbuf;
> + case NEXTDMA_ENRX(NEXTDMA_NEXT):
> + return next_state->dma[NEXTDMA_ENRX].next;
> + case NEXTDMA_ENRX(NEXTDMA_LIMIT):
> + return next_state->dma[NEXTDMA_ENRX].limit;
> +
> + case NEXTDMA_SCSI(NEXTDMA_NEXT):
> + return next_state->dma[NEXTDMA_SCSI].next;
> + case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT):
> + return next_state->dma[NEXTDMA_SCSI].next_initbuf;
> + case NEXTDMA_SCSI(NEXTDMA_LIMIT):
> + return next_state->dma[NEXTDMA_SCSI].limit;
> + case NEXTDMA_SCSI(NEXTDMA_START):
> + return next_state->dma[NEXTDMA_SCSI].start;
> + case NEXTDMA_SCSI(NEXTDMA_STOP):
> + return next_state->dma[NEXTDMA_SCSI].stop;
> +
> + default:
> + DPRINTF("DMA read @ %x\n", (unsigned int)addr);
> + return 0;
> + }
> +
> + /*
> + * once the csr's are done, subtract 0x3FEC from the addr, and that will
> + * normalize the upper registers
> + */
> +}
> +
> +static uint64_t dma_readfn(void *opaque, hwaddr addr, unsigned size)
> +{
> + NeXTState *ns = NEXT_MACHINE(opaque);
> +
> + switch (size) {
> + case 4:
> + return dma_readl(ns, addr);
Well, maybe you can directly use dma_readfn prototype for dma_readl, and
remove this function and dma_writefn (you know we'll ever get 32-bit
accesses here due to .valid.min/max_access_size = 4).
> + default:
> + g_assert_not_reached();
> + }
> +}
> +
> +static void dma_writefn(void *opaque, hwaddr addr, uint64_t value,
> + unsigned size)
> +{
> + NeXTState *ns = NEXT_MACHINE(opaque);
> +
> + switch (size) {
> + case 4:
> + dma_writel(ns, addr, value);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> +}
> +
> +static const MemoryRegionOps dma_ops = {
> + .read = dma_readfn,
> + .write = dma_writefn,
> + .valid.min_access_size = 4,
> + .valid.max_access_size = 4,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +/*
> + * TODO: set the shift numbers as values in the enum, so the first switch
> + * will not be needed
> + */
> +void next_irq(void *opaque, int number, int level)
> +{
> + M68kCPU *cpu = opaque;
> + int shift = 0;
> + NeXTState *ns = NEXT_MACHINE(qdev_get_machine());
> +
> + /* first switch sets interupt status */
> + /* DPRINTF("IRQ %i\n",number); */
> + switch (number) {
> + /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */
> + case NEXT_FD_I:
> + shift = 7;;
> + break;
> + case NEXT_KBD_I:
> + shift = 3;
> + break;
> + case NEXT_PWR_I:
> + shift = 2;
> + break;
> + case NEXT_ENRX_I:
> + shift = 9;
> + break;
> + case NEXT_ENTX_I:
> + shift = 10;
> + break;
> + case NEXT_SCSI_I:
> + shift = 12;
> + break;
> + case NEXT_CLK_I:
> + shift = 5;
> + break;
> +
> + /* level 5 - scc (serial) */
> + case NEXT_SCC_I:
> + shift = 17;
> + break;
> +
> + /* level 6 - audio etherrx/tx dma */
> + case NEXT_ENTX_DMA_I:
> + shift = 28;
> + break;
> + case NEXT_ENRX_DMA_I:
> + shift = 27;
> + break;
> + case NEXT_SCSI_DMA_I:
> + shift = 26;
> + break;
> + case NEXT_SND_I:
> + shift = 23;
> + break;
> + case NEXT_SCC_DMA_I:
> + shift = 21;
> + break;
> +
> + }
> + /*
> + * this HAS to be wrong, the interrupt handlers in mach and together
> + * int_status and int_mask and return if there is a hit
> + */
> + if (ns->int_mask & (1 << shift)) {
> + DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc);
> + /* return; */
> + }
> +
> + /* second switch triggers the correct interrupt */
> + if (level) {
> + ns->int_status |= 1 << shift;
> +
> + switch (number) {
> + /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */
> + case NEXT_FD_I:
> + case NEXT_KBD_I:
> + case NEXT_PWR_I:
> + case NEXT_ENRX_I:
> + case NEXT_ENTX_I:
> + case NEXT_SCSI_I:
> + case NEXT_CLK_I:
> + m68k_set_irq_level(cpu, 3, 27);
> + break;
> +
> + /* level 5 - scc (serial) */
> + case NEXT_SCC_I:
> + m68k_set_irq_level(cpu, 5, 29);
> + break;
> +
> + /* level 6 - audio etherrx/tx dma */
> + case NEXT_ENTX_DMA_I:
> + case NEXT_ENRX_DMA_I:
> + case NEXT_SCSI_DMA_I:
> + case NEXT_SND_I:
> + case NEXT_SCC_DMA_I:
> + m68k_set_irq_level(cpu, 6, 30);
> + break;
> + }
> + } else {
> + ns->int_status &= ~(1 << shift);
> + cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> + }
> +}
> +
> +static void next_cube_init(MachineState *machine)
> +{
> + M68kCPU *cpu;
> + CPUM68KState *env;
> + MemoryRegion *ram = g_new(MemoryRegion, 1);
> + MemoryRegion *rom = g_new(MemoryRegion, 1);
> + MemoryRegion *mmiomem = g_new(MemoryRegion, 1);
> + MemoryRegion *scrmem = g_new(MemoryRegion, 1);
> + MemoryRegion *dmamem = g_new(MemoryRegion, 1);
> + MemoryRegion *unknownmem = g_new(MemoryRegion, 1);
> + MemoryRegion *sysmem = get_system_memory();
> + NeXTState *ns = NEXT_MACHINE(machine);
> +
> + /* Initialize the cpu core */
> + cpu = M68K_CPU(cpu_create(machine->cpu_type));
> + if (!cpu) {
> + error_report("Unable to find m68k CPU definition");
> + exit(1);
> + }
> + env = &cpu->env;
> +
> + /* Initialize CPU registers. */
> + env->vbr = 0;
> + env->pc = 0x100001e; /* technically should read vector */
> + env->sr = 0x2700;
> +
> + /* Set internal registers to initial values */
> + /* 0x0000XX00 << vital bits */
> + ns->scr1 = 0x00011102;
> + ns->scr2 = 0x00ff0c80;
> +
> + ns->int_mask = 0x0; /* 88027640; */
> + ns->int_status = 0x0; /* 200; */
What mean those comments?
> +
> + /* Load RTC RAM - TODO: provide possibility to load contents from file */
> + memcpy(ns->rtc_ram, rtc_ram2, 32);
> +
> + /* 64MB RAM starting at 0x4000000 */
> + memory_region_allocate_system_memory(ram, NULL, "next.ram", ram_size);
> + memory_region_add_subregion(sysmem, 0x4000000, ram);
0x04000000
> +
> + /* Framebuffer */
> + nextfb_init();
Todays QEMU style seems to create device in place (here).
> +
> + /* MMIO */
> + memory_region_init_io(mmiomem, NULL, &mmio_ops, machine, "next.mmio",
> + 0xD0000);
> + memory_region_add_subregion(sysmem, 0x2000000, mmiomem);
0x02000000
> +
> + /* BMAP - acts as a catch-all for now */
> + memory_region_init_io(scrmem, NULL, &scr_ops, machine, "next.scr",
> + 0x3A7FF);
0x3A7FF? 0x3a800 at least, but why not use a 256 * KiB full range?
Wait... Isn't this I/O range of 128KB?
> + memory_region_add_subregion(sysmem, 0x2100000, scrmem);
0x02100000
> +
> + /* KBD */
> + nextkbd_init();
Ditto (create in place).
> +
> + /* Load ROM here */
> + if (bios_name == NULL) {
> + bios_name = ROM_FILE;
> + }
> + /* still not sure if the rom should also be mapped at 0x0*/
> + memory_region_init_rom(rom, NULL, "next.rom", 0x20000, &error_fatal);
> + memory_region_add_subregion(sysmem, 0x1000000, rom);
0x01000000
> + if (load_image_targphys(bios_name, 0x1000000, 0x20000) < 0) {
> + if (!qtest_enabled()) {
> + error_report("Failed to load firmware '%s'", bios_name);
> + }
> + }
> +
> + /* TODO: */
> + /* Serial */
> + /* Network */
> + /* SCSI */
Can you use create_unimplemented_device() here?
> +
> + /* DMA */
> + memory_region_init_io(dmamem, NULL, &dma_ops, machine, "next.dma", 0x5000);
> + memory_region_add_subregion(sysmem, 0x2000000, dmamem);
0x02000000
> +
> + /* FIXME: Why does the bios access this memory area? */
> + memory_region_allocate_system_memory(unknownmem, NULL, "next.unknown", 16);
> + memory_region_add_subregion(sysmem, 0x820c0020, unknownmem);
Isn't this uncached access to 0x020c0000?
> +}
> +
> +static void next_machine_class_init(ObjectClass *oc, void *data)
> +{
> + MachineClass *mc = MACHINE_CLASS(oc);
> +
> + mc->desc = "NeXT Cube";
> + mc->init = next_cube_init;
> + mc->default_ram_size = RAM_SIZE;
> + mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040");
> +}
> +
> +static const TypeInfo next_typeinfo = {
> + .name = TYPE_NEXT_MACHINE,
> + .parent = TYPE_MACHINE,
> + .class_init = next_machine_class_init,
> + .instance_size = sizeof(NeXTState),
> +};
> +
> +static void next_register_type(void)
> +{
> + type_register_static(&next_typeinfo);
> +}
> +
> +type_init(next_register_type)
> diff --git a/include/hw/m68k/next-cube.h b/include/hw/m68k/next-cube.h
> index 88e94f6595..d7df6a223b 100644
> --- a/include/hw/m68k/next-cube.h
> +++ b/include/hw/m68k/next-cube.h
> @@ -2,6 +2,44 @@
> #ifndef NEXT_CUBE_H
> #define NEXT_CUBE_H
>
> +enum next_dma_chan {
> + NEXTDMA_FD,
> + NEXTDMA_ENRX,
> + NEXTDMA_ENTX,
> + NEXTDMA_SCSI,
> + NEXTDMA_SCC,
> + NEXTDMA_SND
> +};
> +
> +#define DMA_ENABLE 0x01000000
> +#define DMA_SUPDATE 0x02000000
> +#define DMA_COMPLETE 0x08000000
> +
> +#define DMA_M2DEV 0x0
> +#define DMA_SETENABLE 0x00010000
> +#define DMA_SETSUPDATE 0x00020000
> +#define DMA_DEV2M 0x00040000
> +#define DMA_CLRCOMPLETE 0x00080000
> +#define DMA_RESET 0x00100000
The DMA code is consequent enough to deserve its own file IMO.
Regards,
Phil.
> +
> +enum next_irqs {
> + NEXT_FD_I,
> + NEXT_KBD_I,
> + NEXT_PWR_I,
> + NEXT_ENRX_I,
> + NEXT_ENTX_I,
> + NEXT_SCSI_I,
> + NEXT_CLK_I,
> + NEXT_SCC_I,
> + NEXT_ENTX_DMA_I,
> + NEXT_ENRX_DMA_I,
> + NEXT_SCSI_DMA_I,
> + NEXT_SCC_DMA_I,
> + NEXT_SND_I
> +};
> +
> +void next_irq(void *opaque, int number, int level);
> +
> /* next-fb.c */
> void nextfb_init(void);
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH v2 3/4] m68k: Add NeXTcube machine
2019-06-29 12:26 ` Philippe Mathieu-Daudé
@ 2019-06-29 12:36 ` Philippe Mathieu-Daudé
2019-07-02 17:43 ` Thomas Huth
1 sibling, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-06-29 12:36 UTC (permalink / raw)
To: Thomas Huth, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Laurent Vivier
On 6/29/19 2:26 PM, Philippe Mathieu-Daudé wrote:
> On 6/28/19 8:15 PM, Thomas Huth wrote:
>> It is still quite incomplete (no SCSI, no floppy emulation, no network,
>> etc.), but the firmware already shows up the debug monitor prompt in the
>> framebuffer display, so at least the very basics are already working.
>>
>> This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at
>>
>> https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-cube.c
>>
>> and altered quite a bit to fit the latest interface and coding conventions
>> of the current QEMU.
>>
>> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
>> ---
>> hw/m68k/Makefile.objs | 2 +-
>> hw/m68k/next-cube.c | 988 ++++++++++++++++++++++++++++++++++++
>> include/hw/m68k/next-cube.h | 38 ++
>> 3 files changed, 1027 insertions(+), 1 deletion(-)
>> create mode 100644 hw/m68k/next-cube.c
>>
>> diff --git a/hw/m68k/Makefile.objs b/hw/m68k/Makefile.objs
>> index 688002cac1..f25854730d 100644
>> --- a/hw/m68k/Makefile.objs
>> +++ b/hw/m68k/Makefile.objs
>> @@ -1,3 +1,3 @@
>> obj-$(CONFIG_AN5206) += an5206.o mcf5206.o
>> obj-$(CONFIG_MCF5208) += mcf5208.o mcf_intc.o
>> -obj-$(CONFIG_NEXTCUBE) += next-kbd.o
>> +obj-$(CONFIG_NEXTCUBE) += next-kbd.o next-cube.o
>> diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c
>> new file mode 100644
>> index 0000000000..700d386fb9
>> --- /dev/null
>> +++ b/hw/m68k/next-cube.c
>> @@ -0,0 +1,988 @@
>> +/*
>> + * NeXT Cube System Driver
>> + *
>> + * Copyright (c) 2011 Bryce Lanham
>> + *
>> + * This code is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published
>> + * by the Free Software Foundation; either version 2 of the License,
>> + * or (at your option) any later version.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "exec/hwaddr.h"
>> +#include "exec/address-spaces.h"
>> +#include "sysemu/sysemu.h"
>> +#include "sysemu/qtest.h"
>> +#include "hw/hw.h"
>> +#include "hw/m68k/next-cube.h"
>> +#include "hw/boards.h"
>> +#include "hw/loader.h"
>> +#include "hw/scsi/esp.h"
>> +#include "hw/sysbus.h"
>> +#include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */
>> +#include "hw/block/fdc.h"
>> +#include "qapi/error.h"
>> +#include "ui/console.h"
>> +#include "target/m68k/cpu.h"
>> +
>> +/* #define DEBUG_NEXT */
>> +#ifdef DEBUG_NEXT
>> +#define DPRINTF(fmt, ...) \
>> + do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0)
>> +#else
>> +#define DPRINTF(fmt, ...) do { } while (0)
>> +#endif
>> +
>> +#define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube")
>> +#define NEXT_MACHINE(obj) OBJECT_CHECK(NeXTState, (obj), TYPE_NEXT_MACHINE)
>> +
>> +#define ENTRY 0x0100001e
>> +#define RAM_SIZE 0x4000000
>> +#define ROM_FILE "rom66.bin"
>
> Where can we find this file to test your work?
I found one:
http://www.nextcomputers.org/NeXTfiles/Software/ROM_Files/68040_Non-Turbo_Chipset/
I have to say I'm impressed :)
Let me share this comment from
http://old-computers.com/museum/computer.asp?c=277
"did you know the 040 nextcube was actually used for graphics design at
id software at the time doom was made?"
=)
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH v2 3/4] m68k: Add NeXTcube machine
2019-06-29 12:26 ` Philippe Mathieu-Daudé
2019-06-29 12:36 ` Philippe Mathieu-Daudé
@ 2019-07-02 17:43 ` Thomas Huth
2019-07-03 17:00 ` Thomas Huth
1 sibling, 1 reply; 17+ messages in thread
From: Thomas Huth @ 2019-07-02 17:43 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Thomas Huth, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Laurent Vivier
On 29/06/2019 14.26, Philippe Mathieu-Daudé wrote:
> On 6/28/19 8:15 PM, Thomas Huth wrote:
>> It is still quite incomplete (no SCSI, no floppy emulation, no network,
>> etc.), but the firmware already shows up the debug monitor prompt in the
>> framebuffer display, so at least the very basics are already working.
>>
>> This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at
>>
>> https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-cube.c
>>
>> and altered quite a bit to fit the latest interface and coding conventions
>> of the current QEMU.
>>
>> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
>> ---
>> hw/m68k/Makefile.objs | 2 +-
>> hw/m68k/next-cube.c | 988 ++++++++++++++++++++++++++++++++++++
>> include/hw/m68k/next-cube.h | 38 ++
>> 3 files changed, 1027 insertions(+), 1 deletion(-)
>> create mode 100644 hw/m68k/next-cube.c
>>
>> diff --git a/hw/m68k/Makefile.objs b/hw/m68k/Makefile.objs
>> index 688002cac1..f25854730d 100644
>> --- a/hw/m68k/Makefile.objs
>> +++ b/hw/m68k/Makefile.objs
>> @@ -1,3 +1,3 @@
>> obj-$(CONFIG_AN5206) += an5206.o mcf5206.o
>> obj-$(CONFIG_MCF5208) += mcf5208.o mcf_intc.o
>> -obj-$(CONFIG_NEXTCUBE) += next-kbd.o
>> +obj-$(CONFIG_NEXTCUBE) += next-kbd.o next-cube.o
>> diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c
>> new file mode 100644
>> index 0000000000..700d386fb9
>> --- /dev/null
>> +++ b/hw/m68k/next-cube.c
>> @@ -0,0 +1,988 @@
>> +/*
>> + * NeXT Cube System Driver
>> + *
>> + * Copyright (c) 2011 Bryce Lanham
>> + *
>> + * This code is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published
>> + * by the Free Software Foundation; either version 2 of the License,
>> + * or (at your option) any later version.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "exec/hwaddr.h"
>> +#include "exec/address-spaces.h"
>> +#include "sysemu/sysemu.h"
>> +#include "sysemu/qtest.h"
>> +#include "hw/hw.h"
>> +#include "hw/m68k/next-cube.h"
>> +#include "hw/boards.h"
>> +#include "hw/loader.h"
>> +#include "hw/scsi/esp.h"
>> +#include "hw/sysbus.h"
>> +#include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */
>> +#include "hw/block/fdc.h"
>> +#include "qapi/error.h"
>> +#include "ui/console.h"
>> +#include "target/m68k/cpu.h"
>> +
>> +/* #define DEBUG_NEXT */
>> +#ifdef DEBUG_NEXT
>> +#define DPRINTF(fmt, ...) \
>> + do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0)
>> +#else
>> +#define DPRINTF(fmt, ...) do { } while (0)
>> +#endif
>> +
>> +#define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube")
>> +#define NEXT_MACHINE(obj) OBJECT_CHECK(NeXTState, (obj), TYPE_NEXT_MACHINE)
>> +
>> +#define ENTRY 0x0100001e
>> +#define RAM_SIZE 0x4000000
>> +#define ROM_FILE "rom66.bin"
>
> Where can we find this file to test your work?
Bryce added that file to his repository ... but the one from the
location that you've mentioned in your other mail seems to work fine, too.
[...]
>> +static uint32_t mmio_readb(NeXTState *s, hwaddr addr)
>> +{
>> + switch (addr) {
>> + case 0xc000:
>> + return (s->scr1 >> 24) & 0xFF;
>> + case 0xc001:
>> + return (s->scr1 >> 16) & 0xFF;
>> + case 0xc002:
>> + return (s->scr1 >> 8) & 0xFF;
>> + case 0xc003:
>> + return (s->scr1 >> 0) & 0xFF;
>
> So you have a 32-bit implementation (DMA accessed device?).
>
> memory::access_with_adjusted_size() already does this work
> for you if you use:
>
> .impl.min_access_size = 4,
> .valid.min_access_size = 1,
> .valid.max_access_size = 4,
Yeah, it's old code from 2011 ... I'll try to rework it as you suggested.
>> +
>> + case 0xd000:
>> + return (s->scr2 >> 24) & 0xFF;
>> + case 0xd001:
>> + return (s->scr2 >> 16) & 0xFF;
>> + case 0xd002:
>> + return (s->scr2 >> 8) & 0xFF;
>> + case 0xd003:
>> + return (s->scr2 >> 0) & 0xFF;
>> + case 0x14020:
>> + DPRINTF("MMIO Read 0x4020\n");
>> + return 0x7f;
>> +
>> + default:
>> + DPRINTF("MMIO Read B @ %"HWADDR_PRIx"\n", addr);
>> + return 0x0;
>> + }
[...]
>> +static uint64_t dma_readfn(void *opaque, hwaddr addr, unsigned size)
>> +{
>> + NeXTState *ns = NEXT_MACHINE(opaque);
>> +
>> + switch (size) {
>> + case 4:
>> + return dma_readl(ns, addr);
>
> Well, maybe you can directly use dma_readfn prototype for dma_readl, and
> remove this function and dma_writefn (you know we'll ever get 32-bit
> accesses here due to .valid.min/max_access_size = 4).
Funny, bit this function is still triggered with size = 1 when you use
the Rev_2.1_v59.bin firmware file... looks like I need an additional
.impl.min_access_size = 4 to get it right.
>> + default:
>> + g_assert_not_reached();
>> + }
>> +}
[...]
>> +static void next_cube_init(MachineState *machine)
>> +{
>> + M68kCPU *cpu;
>> + CPUM68KState *env;
>> + MemoryRegion *ram = g_new(MemoryRegion, 1);
>> + MemoryRegion *rom = g_new(MemoryRegion, 1);
>> + MemoryRegion *mmiomem = g_new(MemoryRegion, 1);
>> + MemoryRegion *scrmem = g_new(MemoryRegion, 1);
>> + MemoryRegion *dmamem = g_new(MemoryRegion, 1);
>> + MemoryRegion *unknownmem = g_new(MemoryRegion, 1);
>> + MemoryRegion *sysmem = get_system_memory();
>> + NeXTState *ns = NEXT_MACHINE(machine);
>> +
>> + /* Initialize the cpu core */
>> + cpu = M68K_CPU(cpu_create(machine->cpu_type));
>> + if (!cpu) {
>> + error_report("Unable to find m68k CPU definition");
>> + exit(1);
>> + }
>> + env = &cpu->env;
>> +
>> + /* Initialize CPU registers. */
>> + env->vbr = 0;
>> + env->pc = 0x100001e; /* technically should read vector */
>> + env->sr = 0x2700;
>> +
>> + /* Set internal registers to initial values */
>> + /* 0x0000XX00 << vital bits */
>> + ns->scr1 = 0x00011102;
>> + ns->scr2 = 0x00ff0c80;
>> +
>> + ns->int_mask = 0x0; /* 88027640; */
>> + ns->int_status = 0x0; /* 200; */
>
> What mean those comments?
No clue, they were part of Bryce code. Maybe I should simply remove them.
>> +
>> + /* Load RTC RAM - TODO: provide possibility to load contents from file */
>> + memcpy(ns->rtc_ram, rtc_ram2, 32);
>> +
>> + /* 64MB RAM starting at 0x4000000 */
>> + memory_region_allocate_system_memory(ram, NULL, "next.ram", ram_size);
>> + memory_region_add_subregion(sysmem, 0x4000000, ram);
>
> 0x04000000
>
>> +
>> + /* Framebuffer */
>> + nextfb_init();
>
> Todays QEMU style seems to create device in place (here).
>
>> +
>> + /* MMIO */
>> + memory_region_init_io(mmiomem, NULL, &mmio_ops, machine, "next.mmio",
>> + 0xD0000);
>> + memory_region_add_subregion(sysmem, 0x2000000, mmiomem);
>
> 0x02000000
Ok.
>> +
>> + /* BMAP - acts as a catch-all for now */
>> + memory_region_init_io(scrmem, NULL, &scr_ops, machine, "next.scr",
>> + 0x3A7FF);
>
> 0x3A7FF? 0x3a800 at least, but why not use a 256 * KiB full range?
Ok.
> Wait... Isn't this I/O range of 128KB?
Hmm, yes, according to the Previous sources, it's 128kB only... I'll
have a try with 0x20000, and if there are no regressions, I'll use that
value instead.
>> + /* TODO: */
>> + /* Serial */
>> + /* Network */
>> + /* SCSI */
>
> Can you use create_unimplemented_device() here?
There are already patches for these devices available (just not working
yet), so I don't think it's worth the effort to take the detour via the
unimplemented device here.
>> + /* FIXME: Why does the bios access this memory area? */
>> + memory_region_allocate_system_memory(unknownmem, NULL, "next.unknown", 16);
>> + memory_region_add_subregion(sysmem, 0x820c0020, unknownmem);
>
> Isn't this uncached access to 0x020c0000?
No clue, but looking at the Previous sources, this seems to be a mirror
of 0x020c0000 indeed. I'll change that accordingly.
[...]
>> diff --git a/include/hw/m68k/next-cube.h b/include/hw/m68k/next-cube.h
>> index 88e94f6595..d7df6a223b 100644
>> --- a/include/hw/m68k/next-cube.h
>> +++ b/include/hw/m68k/next-cube.h
>> @@ -2,6 +2,44 @@
>> #ifndef NEXT_CUBE_H
>> #define NEXT_CUBE_H
>>
>> +enum next_dma_chan {
>> + NEXTDMA_FD,
>> + NEXTDMA_ENRX,
>> + NEXTDMA_ENTX,
>> + NEXTDMA_SCSI,
>> + NEXTDMA_SCC,
>> + NEXTDMA_SND
>> +};
>> +
>> +#define DMA_ENABLE 0x01000000
>> +#define DMA_SUPDATE 0x02000000
>> +#define DMA_COMPLETE 0x08000000
>> +
>> +#define DMA_M2DEV 0x0
>> +#define DMA_SETENABLE 0x00010000
>> +#define DMA_SETSUPDATE 0x00020000
>> +#define DMA_DEV2M 0x00040000
>> +#define DMA_CLRCOMPLETE 0x00080000
>> +#define DMA_RESET 0x00100000
>
> The DMA code is consequent enough to deserve its own file IMO.
Maybe later ... I'd like to keep the initial patches close to the code
from Bryce if possible.
Thanks for the review,
Thomas
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH v2 3/4] m68k: Add NeXTcube machine
2019-07-02 17:43 ` Thomas Huth
@ 2019-07-03 17:00 ` Thomas Huth
2019-07-03 17:36 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 17+ messages in thread
From: Thomas Huth @ 2019-07-03 17:00 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Laurent Vivier
On 02/07/2019 19.43, Thomas Huth wrote:
> On 29/06/2019 14.26, Philippe Mathieu-Daudé wrote:
>> On 6/28/19 8:15 PM, Thomas Huth wrote:
[...]
>>> +static uint32_t mmio_readb(NeXTState *s, hwaddr addr)
>>> +{
>>> + switch (addr) {
>>> + case 0xc000:
>>> + return (s->scr1 >> 24) & 0xFF;
>>> + case 0xc001:
>>> + return (s->scr1 >> 16) & 0xFF;
>>> + case 0xc002:
>>> + return (s->scr1 >> 8) & 0xFF;
>>> + case 0xc003:
>>> + return (s->scr1 >> 0) & 0xFF;
>>
>> So you have a 32-bit implementation (DMA accessed device?).
>>
>> memory::access_with_adjusted_size() already does this work
>> for you if you use:
>>
>> .impl.min_access_size = 4,
>> .valid.min_access_size = 1,
>> .valid.max_access_size = 4,
>
> Yeah, it's old code from 2011 ... I'll try to rework it as you suggested.
That does not really seem to work. I'm then still seeing accesses to
0xc002 in my "readl" handler. Looks like access_with_adjusted_size() is
not really ready for that yet (see the FIXME in that function - it does
not take care of unaligned accesses yet).
Thomas
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH v2 3/4] m68k: Add NeXTcube machine
2019-07-03 17:00 ` Thomas Huth
@ 2019-07-03 17:36 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-07-03 17:36 UTC (permalink / raw)
To: Thomas Huth, qemu-devel
Cc: Peter Maydell, Paolo Bonzini, Philippe Mathieu-Daudé,
Laurent Vivier
On 7/3/19 7:00 PM, Thomas Huth wrote:
> On 02/07/2019 19.43, Thomas Huth wrote:
>> On 29/06/2019 14.26, Philippe Mathieu-Daudé wrote:
>>> On 6/28/19 8:15 PM, Thomas Huth wrote:
> [...]
>>>> +static uint32_t mmio_readb(NeXTState *s, hwaddr addr)
>>>> +{
>>>> + switch (addr) {
>>>> + case 0xc000:
>>>> + return (s->scr1 >> 24) & 0xFF;
>>>> + case 0xc001:
>>>> + return (s->scr1 >> 16) & 0xFF;
>>>> + case 0xc002:
>>>> + return (s->scr1 >> 8) & 0xFF;
>>>> + case 0xc003:
>>>> + return (s->scr1 >> 0) & 0xFF;
>>>
>>> So you have a 32-bit implementation (DMA accessed device?).
>>>
>>> memory::access_with_adjusted_size() already does this work
>>> for you if you use:
>>>
>>> .impl.min_access_size = 4,
>>> .valid.min_access_size = 1,
>>> .valid.max_access_size = 4,
>>
>> Yeah, it's old code from 2011 ... I'll try to rework it as you suggested.
>
> That does not really seem to work. I'm then still seeing accesses to
> 0xc002 in my "readl" handler. Looks like access_with_adjusted_size() is
> not really ready for that yet (see the FIXME in that function - it does
> not take care of unaligned accesses yet).
I was convinced the unaligned series [*] was already merged. Anyway you
give me a good news, we have new a test for it :)
[*] https://lists.gnu.org/archive/html/qemu-devel/2017-06/msg06957.html
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH v2 4/4] m68k: Add an entry for the NeXTcube machine to the MAINTAINERS file
2019-06-28 18:15 [Qemu-devel] [PATCH v2 0/4] m68k: Add basic support for the NeXTcube machine Thomas Huth
` (2 preceding siblings ...)
2019-06-28 18:15 ` [Qemu-devel] [PATCH v2 3/4] m68k: Add NeXTcube machine Thomas Huth
@ 2019-06-28 18:15 ` Thomas Huth
2019-06-29 12:27 ` Philippe Mathieu-Daudé
2019-06-29 14:40 ` [Qemu-devel] [PATCH v2 0/4] m68k: Add basic support for the NeXTcube machine Philippe Mathieu-Daudé
4 siblings, 1 reply; 17+ messages in thread
From: Thomas Huth @ 2019-06-28 18:15 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Philippe Mathieu-Daudé, Laurent Vivier
I don't have much clue about the NeXT hardware, but at least I know now
the source files a little bit, so I volunteer to pick up patches and send
PULL requests for them until someone else with more knowledge steps up
to do this job instead.
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index cad58b9487..6b4fa7221f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -900,6 +900,13 @@ F: hw/char/mcf_uart.c
F: hw/net/mcf_fec.c
F: include/hw/m68k/mcf*.h
+NeXTcube
+M: Thomas Huth <huth@tuxfamily.org>
+S: Odd Fixes
+F: hw/m68k/next-*.c
+F: hw/display/next-fb.c
+F: include/hw/m68k/next-cube.h
+
MicroBlaze Machines
-------------------
petalogix_s3adsp1800
--
2.21.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH v2 4/4] m68k: Add an entry for the NeXTcube machine to the MAINTAINERS file
2019-06-28 18:15 ` [Qemu-devel] [PATCH v2 4/4] m68k: Add an entry for the NeXTcube machine to the MAINTAINERS file Thomas Huth
@ 2019-06-29 12:27 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-06-29 12:27 UTC (permalink / raw)
To: Thomas Huth, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Laurent Vivier
On 6/28/19 8:15 PM, Thomas Huth wrote:
> I don't have much clue about the NeXT hardware, but at least I know now
> the source files a little bit, so I volunteer to pick up patches and send
> PULL requests for them until someone else with more knowledge steps up
> to do this job instead.
>
> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> MAINTAINERS | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index cad58b9487..6b4fa7221f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -900,6 +900,13 @@ F: hw/char/mcf_uart.c
> F: hw/net/mcf_fec.c
> F: include/hw/m68k/mcf*.h
>
> +NeXTcube
> +M: Thomas Huth <huth@tuxfamily.org>
> +S: Odd Fixes
> +F: hw/m68k/next-*.c
> +F: hw/display/next-fb.c
> +F: include/hw/m68k/next-cube.h
> +
> MicroBlaze Machines
> -------------------
> petalogix_s3adsp1800
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH v2 0/4] m68k: Add basic support for the NeXTcube machine
2019-06-28 18:15 [Qemu-devel] [PATCH v2 0/4] m68k: Add basic support for the NeXTcube machine Thomas Huth
` (3 preceding siblings ...)
2019-06-28 18:15 ` [Qemu-devel] [PATCH v2 4/4] m68k: Add an entry for the NeXTcube machine to the MAINTAINERS file Thomas Huth
@ 2019-06-29 14:40 ` Philippe Mathieu-Daudé
4 siblings, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-06-29 14:40 UTC (permalink / raw)
To: Thomas Huth, qemu-devel; +Cc: Peter Maydell, Laurent Vivier
On 6/28/19 8:15 PM, Thomas Huth wrote:
> Bryce apparently never got around to work on this again, so I'll have
> another try now ...
>
> During Google Summer of Code 2011, Bryce Lanham added the possibility to
> emulate the NeXTcube machine in QEMU, e.g. see this URL for some details:
>
> https://wiki.qemu.org/Google_Summer_of_Code_2011#NeXT_machines_system_emulation
I'm not sure you used the correct URL, the GSoC entry is not very
useful. I found this one more helpful (v1):
https://lists.gnu.org/archive/html/qemu-devel/2011-08/msg02158.html
> But since the machine requires a 68040 CPU and this was not included in
> upstream QEMU in 2011 yet, the patches have never been merged to upstream.
>
> Then, during the last years, Laurent completed the full 680x0 support in
> upstream QEMU, so we could finally merge the NeXTcube support, too.
>
> The QEMU interfaces changed a lot since 2011, so I had to modify the
> sources quite a bit, but with the attached patches, it is now possible
> to boot up to the firmware monitor again.
>
> Note that boot device emulation is either still missing (network and SCSI),
> so you can not boot any operating systems with this machine yet. I have
> the patches for these devices in my brach here:
>
> https://gitlab.com/huth/qemu/commits/next-cube
>
> ... but they are not quite working yet, so I'll submit them later once
> they have been fixed and the basic support patches of this series have
> been merged.
>
> v2:
> - Don't use memory_region_allocate_system_memory() for the framebuffer
> device anymore
> - Turn the keyboard device into a proper QOM device
> - Put the global variables in the third patch into the machine state
> structure
> - Got rid of the "//" C++ comments
^ permalink raw reply [flat|nested] 17+ messages in thread