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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c84ca21sm51404403f8f.63.2025.01.07.11.29.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 Jan 2025 11:29:28 -0800 (PST) Message-ID: <628776e4-bd9f-4823-a2c5-b8ddf79afc70@linaro.org> Date: Tue, 7 Jan 2025 20:29:27 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/3] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB To: Jamin Lin , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , Joel Stanley , Bin Meng , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:SD (Secure Card)" Cc: troy_lee@aspeedtech.com, yunlin.tang@aspeedtech.com References: <20241114094839.4128404-1-jamin_lin@aspeedtech.com> <20241114094839.4128404-4-jamin_lin@aspeedtech.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20241114094839.4128404-4-jamin_lin@aspeedtech.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 14/11/24 10:48, Jamin Lin wrote: > The Write Protect pin of SDHCI model is default active low to match the SDHCI > spec. So, write enable the bit 19 should be 1 and write protected the bit 19 > should be 0 at the Present State Register (0x24). > > According to the design of AST2600 EVB, the Write Protected pin is active > high by default. To support it, introduces a new "sdhci_wp_inverted" > property in ASPEED MACHINE State and set it true for AST2600 EVB > and set "wp_inverted" property true of sdhci-generic model. > > Signed-off-by: Jamin Lin > Reviewed-by: Andrew Jeffery > --- > hw/arm/aspeed.c | 7 +++++++ > include/hw/arm/aspeed.h | 1 + > 2 files changed, 8 insertions(+) Acked-by: Philippe Mathieu-Daudé