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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-474949e0a3csm44816625e9.0.2025.10.22.12.05.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Oct 2025 12:05:23 -0700 (PDT) Message-ID: <62d5c5d1-529e-4344-b8a7-f058d65ae8cf@linaro.org> Date: Wed, 22 Oct 2025 21:05:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] hw/ppc/e500: Check for compatible CPU type instead of aborting ungracefully Content-Language: en-US To: Thomas Huth , Bernhard Beschow , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, BALATON Zoltan References: <20251015111243.1585018-1-thuth@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20251015111243.1585018-1-thuth@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 15/10/25 13:12, Thomas Huth wrote: > From: Thomas Huth > > When using the ppce500 machine with an embedded CPU type that has > the right MMU model, but is not part of the e500 CPU family, QEMU > currently aborts ungracefully: > > $ ./qemu-system-ppc -machine ppce500 -cpu e200z5 -nographic > qemu-system-ppc: ../qemu/hw/core/gpio.c:108: qdev_get_gpio_in_named: > Assertion `n >= 0 && n < gpio_list->num_in' failed. > Aborted (core dumped) > > The ppce500 machine expects a CPU with certain GPIO interrupt pins, > so let's replace the coarse check for the MMU_BOOKE206 model with > a more precise check that only allows CPUs from the e500 family. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3162 > Signed-off-by: Thomas Huth > --- > v2: Drop the old check for the MMU_BOOKE206 model > > hw/ppc/e500.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Queued and merged, thanks!