[PATCH 0/4] hw/pci-host: Re-use generic pci_host_data_le_ops MemoryRegionOps

[PATCH 0/4] hw/pci-host: Re-use generic pci_host_data_le_ops MemoryRegionOps

[Philippe Mathieu-Daudé]

Add the 'config-reg-check-high-bit' property in order to re-use
the generic pci_host_data_le_ops MemoryRegionOps.

Philippe Mathieu-Daudé (4):
  hw/pci/pci_host: Add 'config-reg-check-high-bit' property
  hw/pci-host/astro: Re-use generic pci_host_data_le_ops MemoryRegionOps
  hw/pci-host/dino: Re-use generic pci_host_data_le_ops MemoryRegionOps
  hw/pci-host/sabre: Re-use generic pci_host_data_le_ops MemoryRegionOps

 include/hw/pci/pci_host.h |  1 +
 hw/pci-host/astro.c       | 35 ++++++++---------------------------
 hw/pci-host/dino.c        | 30 ++++++++----------------------
 hw/pci-host/sabre.c       | 34 +++-------------------------------
 hw/pci/pci_host.c         | 10 +++++++---
 hw/pci-host/trace-events  |  4 ----
 6 files changed, 27 insertions(+), 87 deletions(-)

-- 
2.51.0

[PATCH 1/4] hw/pci/pci_host: Add 'config-reg-check-high-bit' property

[Philippe Mathieu-Daudé]

In order to have more PCI host bridges to re-use the
generic pci_host_data_le_ops MemoryRegionOps, add the
'config-reg-check-high-bit' property (%true by default).

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/pci/pci_host.h |  1 +
 hw/pci/pci_host.c         | 10 +++++++---
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/include/hw/pci/pci_host.h b/include/hw/pci/pci_host.h
index 954dd446fa4..c04a567ec57 100644
--- a/include/hw/pci/pci_host.h
+++ b/include/hw/pci/pci_host.h
@@ -43,6 +43,7 @@ struct PCIHostState {
     MemoryRegion data_mem;
     MemoryRegion mmcfg;
     uint32_t config_reg;
+    bool config_reg_check_high_bit;
     bool mig_enabled;
     PCIBus *bus;
     bool bypass_iommu;
diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c
index b5c624e12e8..06003188e1d 100644
--- a/hw/pci/pci_host.c
+++ b/hw/pci/pci_host.c
@@ -184,8 +184,10 @@ static void pci_host_data_write(void *opaque, hwaddr addr,
 {
     PCIHostState *s = opaque;
 
-    if (s->config_reg & (1u << 31))
-        pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
+    if (s->config_reg_check_high_bit && !(s->config_reg & (1U << 31))) {
+        return;
+    }
+    pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
 }
 
 static uint64_t pci_host_data_read(void *opaque,
@@ -193,7 +195,7 @@ static uint64_t pci_host_data_read(void *opaque,
 {
     PCIHostState *s = opaque;
 
-    if (!(s->config_reg & (1U << 31))) {
+    if (s->config_reg_check_high_bit && !(s->config_reg & (1U << 31))) {
         return 0xffffffff;
     }
     return pci_data_read(s->bus, s->config_reg | (addr & 3), len);
@@ -237,6 +239,8 @@ const VMStateDescription vmstate_pcihost = {
 static const Property pci_host_properties_common[] = {
     DEFINE_PROP_BOOL("x-config-reg-migration-enabled", PCIHostState,
                      mig_enabled, true),
+    DEFINE_PROP_BOOL("config-reg-check-high-bit", PCIHostState,
+                     config_reg_check_high_bit, true),
     DEFINE_PROP_BOOL(PCI_HOST_BYPASS_IOMMU, PCIHostState, bypass_iommu, false),
 };
 
-- 
2.51.0

[PATCH 2/4] hw/pci-host/astro: Re-use generic pci_host_data_le_ops MemoryRegionOps

[Philippe Mathieu-Daudé]

Avoid duplicating code, clear the "config-reg-check-high-bit"
property in .instance_init() in order to re-use the generic
pci_host_data_le_ops MemoryRegionOps.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/pci-host/astro.c      | 35 ++++++++---------------------------
 hw/pci-host/trace-events |  2 --
 2 files changed, 8 insertions(+), 29 deletions(-)

diff --git a/hw/pci-host/astro.c b/hw/pci-host/astro.c
index 0bd66ab3de3..110070486d7 100644
--- a/hw/pci-host/astro.c
+++ b/hw/pci-host/astro.c
@@ -230,32 +230,6 @@ static const MemoryRegionOps elroy_chip_ops = {
 };
 
 
-/* Unlike pci_config_data_le_ops, no check of high bit set in config_reg.  */
-
-static uint64_t elroy_config_data_read(void *opaque, hwaddr addr, unsigned len)
-{
-    uint64_t val;
-
-    PCIHostState *s = opaque;
-    val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
-    trace_elroy_pci_config_data_read(s->config_reg | (addr & 3), len, val);
-    return val;
-}
-
-static void elroy_config_data_write(void *opaque, hwaddr addr,
-                                   uint64_t val, unsigned len)
-{
-    PCIHostState *s = opaque;
-    pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
-    trace_elroy_pci_config_data_write(s->config_reg | (addr & 3), len, val);
-}
-
-static const MemoryRegionOps elroy_config_data_ops = {
-    .read = elroy_config_data_read,
-    .write = elroy_config_data_write,
-    .endianness = DEVICE_LITTLE_ENDIAN,
-};
-
 static uint64_t elroy_config_addr_read(void *opaque, hwaddr addr, unsigned len)
 {
     ElroyState *s = opaque;
@@ -424,6 +398,12 @@ static void elroy_reset(DeviceState *dev)
     }
 }
 
+static void elroy_pcihost_instance_init(Object *obj)
+{
+    object_property_set_bool(obj, "config-reg-check-high-bit", false,
+                             &error_fatal);
+}
+
 static void elroy_pcihost_realize(DeviceState *dev, Error **errp)
 {
     ElroyState *s = ELROY_PCI_HOST_BRIDGE(dev);
@@ -440,7 +420,7 @@ static void elroy_pcihost_realize(DeviceState *dev, Error **errp)
                           &elroy_config_addr_ops, dev,
                           "pci-conf-idx", 8);
     memory_region_init_io(&phb->data_mem, obj,
-                          &elroy_config_data_ops, dev,
+                          &pci_host_data_le_ops, dev,
                           "pci-conf-data", 8);
     memory_region_add_subregion(&s->this_mem, 0x40,
                                 &phb->conf_mem);
@@ -497,6 +477,7 @@ static const TypeInfo elroy_pcihost_info = {
     .name          = TYPE_ELROY_PCI_HOST_BRIDGE,
     .parent        = TYPE_PCI_HOST_BRIDGE,
     .instance_size = sizeof(ElroyState),
+    .instance_init = elroy_pcihost_instance_init,
     .class_init    = elroy_pcihost_class_init,
 };
 
diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events
index a6fd88c2c46..792ab25729b 100644
--- a/hw/pci-host/trace-events
+++ b/hw/pci-host/trace-events
@@ -76,7 +76,5 @@ astro_chip_read(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %d
 astro_chip_write(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %d val 0x%"PRIx64
 elroy_read(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %d val 0x%"PRIx64
 elroy_write(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %d val 0x%"PRIx64
-elroy_pci_config_data_read(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %d val 0x%"PRIx64
-elroy_pci_config_data_write(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %d val 0x%"PRIx64
 iosapic_reg_write(uint64_t reg_select, int size, uint64_t val) "reg_select 0x%"PRIx64" size %d val 0x%"PRIx64
 iosapic_reg_read(uint64_t reg_select, int size, uint64_t val) "reg_select 0x%"PRIx64" size %d val 0x%"PRIx64
-- 
2.51.0

[PATCH 3/4] hw/pci-host/dino: Re-use generic pci_host_data_le_ops MemoryRegionOps

[Philippe Mathieu-Daudé]

Avoid duplicating code, clear the "config-reg-check-high-bit"
property in .instance_init() in order to re-use the generic
pci_host_data_le_ops MemoryRegionOps.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/pci-host/dino.c | 30 ++++++++----------------------
 1 file changed, 8 insertions(+), 22 deletions(-)

diff --git a/hw/pci-host/dino.c b/hw/pci-host/dino.c
index 924053499c1..e317167dbfa 100644
--- a/hw/pci-host/dino.c
+++ b/hw/pci-host/dino.c
@@ -302,27 +302,6 @@ static const VMStateDescription vmstate_dino = {
     }
 };
 
-/* Unlike pci_config_data_le_ops, no check of high bit set in config_reg.  */
-
-static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned len)
-{
-    PCIHostState *s = opaque;
-    return pci_data_read(s->bus, s->config_reg | (addr & 3), len);
-}
-
-static void dino_config_data_write(void *opaque, hwaddr addr,
-                                   uint64_t val, unsigned len)
-{
-    PCIHostState *s = opaque;
-    pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
-}
-
-static const MemoryRegionOps dino_config_data_ops = {
-    .read = dino_config_data_read,
-    .write = dino_config_data_write,
-    .endianness = DEVICE_LITTLE_ENDIAN,
-};
-
 static uint64_t dino_config_addr_read(void *opaque, hwaddr addr, unsigned len)
 {
     DinoState *s = opaque;
@@ -410,6 +389,12 @@ static void dino_pcihost_reset(DeviceState *dev)
     s->toc_addr = 0xFFFA0030; /* IO_COMMAND of CPU */
 }
 
+static void dino_pcihost_instance_init(Object *obj)
+{
+    object_property_set_bool(obj, "config-reg-check-high-bit", false,
+                             &error_fatal);
+}
+
 static void dino_pcihost_realize(DeviceState *dev, Error **errp)
 {
     DinoState *s = DINO_PCI_HOST_BRIDGE(dev);
@@ -424,7 +409,7 @@ static void dino_pcihost_realize(DeviceState *dev, Error **errp)
                           &dino_config_addr_ops, DEVICE(s),
                           "pci-conf-idx", 4);
     memory_region_init_io(&phb->data_mem, OBJECT(phb),
-                          &dino_config_data_ops, DEVICE(s),
+                          &pci_host_data_le_ops, DEVICE(s),
                           "pci-conf-data", 4);
     memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR,
                                 &phb->conf_mem);
@@ -505,6 +490,7 @@ static const TypeInfo dino_pcihost_info = {
     .name          = TYPE_DINO_PCI_HOST_BRIDGE,
     .parent        = TYPE_PCI_HOST_BRIDGE,
     .instance_size = sizeof(DinoState),
+    .instance_init = dino_pcihost_instance_init,
     .class_init    = dino_pcihost_class_init,
 };
 
-- 
2.51.0

[PATCH 4/4] hw/pci-host/sabre: Re-use generic pci_host_data_le_ops MemoryRegionOps

[Philippe Mathieu-Daudé]

Avoid duplicating code, re-use the generic generic
pci_host_data_le_ops MemoryRegionOps.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/pci-host/sabre.c      | 34 +++-------------------------------
 hw/pci-host/trace-events |  2 --
 2 files changed, 3 insertions(+), 33 deletions(-)

diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c
index f95e5db583a..cc7229025f6 100644
--- a/hw/pci-host/sabre.c
+++ b/hw/pci-host/sabre.c
@@ -246,28 +246,6 @@ static const MemoryRegionOps sabre_config_ops = {
     .endianness = DEVICE_BIG_ENDIAN,
 };
 
-static void sabre_pci_config_write(void *opaque, hwaddr addr,
-                                   uint64_t val, unsigned size)
-{
-    SabreState *s = opaque;
-    PCIHostState *phb = PCI_HOST_BRIDGE(s);
-
-    trace_sabre_pci_config_write(addr, val);
-    pci_data_write(phb->bus, addr, val, size);
-}
-
-static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr,
-                                      unsigned size)
-{
-    uint32_t ret;
-    SabreState *s = opaque;
-    PCIHostState *phb = PCI_HOST_BRIDGE(s);
-
-    ret = pci_data_read(phb->bus, addr, size);
-    trace_sabre_pci_config_read(addr, ret);
-    return ret;
-}
-
 /* The sabre host has an IRQ line for each IRQ line of each slot.  */
 static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num)
 {
@@ -361,12 +339,6 @@ static void sabre_reset(DeviceState *d)
     pci_bridge_update_mappings(PCI_BRIDGE(pci_dev));
 }
 
-static const MemoryRegionOps pci_config_ops = {
-    .read = sabre_pci_config_read,
-    .write = sabre_pci_config_write,
-    .endianness = DEVICE_LITTLE_ENDIAN,
-};
-
 static void sabre_realize(DeviceState *dev, Error **errp)
 {
     SabreState *s = SABRE(dev);
@@ -430,12 +402,12 @@ static void sabre_init(Object *obj)
 
     /* sabre_config */
     memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, s,
-                          "sabre-config", 0x10000);
+                          "pci-conf-idx", 0x10000);
     /* at region 0 */
     sysbus_init_mmio(sbd, &s->sabre_config);
 
-    memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s,
-                          "sabre-pci-config", 0x1000000);
+    memory_region_init_io(&s->pci_config, OBJECT(s), &pci_host_data_le_ops, s,
+                          "pci-data-idx", 0x1000000);
     /* at region 1 */
     sysbus_init_mmio(sbd, &s->pci_config);
 
diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events
index 792ab25729b..20c3cae47a2 100644
--- a/hw/pci-host/trace-events
+++ b/hw/pci-host/trace-events
@@ -35,8 +35,6 @@ sabre_set_request(int irq_num) "request irq %d"
 sabre_clear_request(int irq_num) "clear request irq %d"
 sabre_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64
 sabre_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64
-sabre_pci_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64
-sabre_pci_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64
 sabre_pci_set_irq(int irq_num, int level) "set irq_in %d level %d"
 sabre_pci_set_obio_irq(int irq_num, int level) "set irq %d level %d"
 
-- 
2.51.0

Re: [PATCH 3/4] hw/pci-host/dino: Re-use generic pci_host_data_le_ops MemoryRegionOps

[Philippe Mathieu-Daudé]

On 27/10/25 14:30, Philippe Mathieu-Daudé wrote:
> Avoid duplicating code, clear the "config-reg-check-high-bit"
> property in .instance_init() in order to re-use the generic
> pci_host_data_le_ops MemoryRegionOps.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/pci-host/dino.c | 30 ++++++++----------------------
>   1 file changed, 8 insertions(+), 22 deletions(-)
> 
> diff --git a/hw/pci-host/dino.c b/hw/pci-host/dino.c
> index 924053499c1..e317167dbfa 100644
> --- a/hw/pci-host/dino.c
> +++ b/hw/pci-host/dino.c
> @@ -302,27 +302,6 @@ static const VMStateDescription vmstate_dino = {
>       }
>   };
>   
> -/* Unlike pci_config_data_le_ops, no check of high bit set in config_reg.  */
> -
> -static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned len)
> -{
> -    PCIHostState *s = opaque;
> -    return pci_data_read(s->bus, s->config_reg | (addr & 3), len);
> -}
> -
> -static void dino_config_data_write(void *opaque, hwaddr addr,
> -                                   uint64_t val, unsigned len)
> -{
> -    PCIHostState *s = opaque;
> -    pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
> -}
> -
> -static const MemoryRegionOps dino_config_data_ops = {
> -    .read = dino_config_data_read,
> -    .write = dino_config_data_write,
> -    .endianness = DEVICE_LITTLE_ENDIAN,
> -};
> -
>   static uint64_t dino_config_addr_read(void *opaque, hwaddr addr, unsigned len)
>   {
>       DinoState *s = opaque;
> @@ -410,6 +389,12 @@ static void dino_pcihost_reset(DeviceState *dev)
>       s->toc_addr = 0xFFFA0030; /* IO_COMMAND of CPU */
>   }
>   
> +static void dino_pcihost_instance_init(Object *obj)
> +{
> +    object_property_set_bool(obj, "config-reg-check-high-bit", false,
> +                             &error_fatal);
> +}
> +
>   static void dino_pcihost_realize(DeviceState *dev, Error **errp)
>   {
>       DinoState *s = DINO_PCI_HOST_BRIDGE(dev);
> @@ -424,7 +409,7 @@ static void dino_pcihost_realize(DeviceState *dev, Error **errp)
>                             &dino_config_addr_ops, DEVICE(s),
>                             "pci-conf-idx", 4);
>       memory_region_init_io(&phb->data_mem, OBJECT(phb),
> -                          &dino_config_data_ops, DEVICE(s),
> +                          &pci_host_data_le_ops, DEVICE(s),

Pre-existing but better to pass the correct opaque type:

                              &pci_host_data_le_ops, phb,

>                             "pci-conf-data", 4);
>       memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR,
>                                   &phb->conf_mem);
> @@ -505,6 +490,7 @@ static const TypeInfo dino_pcihost_info = {
>       .name          = TYPE_DINO_PCI_HOST_BRIDGE,
>       .parent        = TYPE_PCI_HOST_BRIDGE,
>       .instance_size = sizeof(DinoState),
> +    .instance_init = dino_pcihost_instance_init,
>       .class_init    = dino_pcihost_class_init,
>   };
>