Re: [PATCH 34/38] target/hexagon: Add initial MMU model

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

On 12/3/25 22:15, Sid Manning wrote:
> 
> 
>> -----Original Message-----
>> From: Philippe Mathieu-Daudé <philmd@linaro.org>
>> Sent: Wednesday, March 12, 2025 2:20 PM
>> To: Brian Cain <brian.cain@oss.qualcomm.com>; qemu-devel@nongnu.org
>> Cc: richard.henderson@linaro.org; Matheus Bernardino (QUIC)
>> <quic_mathbern@quicinc.com>; ale@rev.ng; anjo@rev.ng; Marco Liebel
>> (QUIC) <quic_mliebel@quicinc.com>; ltaylorsimpson@gmail.com;
>> alex.bennee@linaro.org; Mark Burton (QUIC)
>> <quic_mburton@quicinc.com>; Sid Manning <sidneym@quicinc.com>; Brian
>> Cain <bcain@quicinc.com>; Michael Lambert <mlambert@quicinc.com>
>> Subject: Re: [PATCH 34/38] target/hexagon: Add initial MMU model
>>
>> WARNING: This email originated from outside of Qualcomm. Please be wary
>> of any links or attachments, and do not enable macros.
>>
>> On 1/3/25 06:26, Brian Cain wrote:
>>> From: Brian Cain <bcain@quicinc.com>
>>>
>>> Co-authored-by: Taylor Simpson <ltaylorsimpson@gmail.com>
>>> Co-authored-by: Michael Lambert <mlambert@quicinc.com>
>>> Co-authored-by: Sid Manning <sidneym@quicinc.com>
>>> Co-authored-by: Matheus Tavares Bernardino
>> <quic_mathbern@quicinc.com>
>>> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
>>> ---
>>>    target/hexagon/cpu-param.h |   4 +
>>>    target/hexagon/cpu.h       |  13 +
>>>    target/hexagon/hex_mmu.h   |  30 +++
>>>    target/hexagon/internal.h  |   3 +
>>>    target/hexagon/cpu.c       |  27 +-
>>>    target/hexagon/hex_mmu.c   | 528
>> +++++++++++++++++++++++++++++++++++++
>>>    target/hexagon/machine.c   |  30 +++
>>>    target/hexagon/translate.c |   2 +-
>>>    target/hexagon/meson.build |   3 +-
>>>    9 files changed, 637 insertions(+), 3 deletions(-)
>>>    create mode 100644 target/hexagon/hex_mmu.h
>>>    create mode 100644 target/hexagon/hex_mmu.c
>>
>>
>>> diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index
>>> 34c39cecd9..7ff678195d 100644
>>> --- a/target/hexagon/cpu.c
>>> +++ b/target/hexagon/cpu.c
>>> @@ -28,6 +28,7 @@
>>>    #include "exec/gdbstub.h"
>>>    #include "cpu_helper.h"
>>>    #include "max.h"
>>> +#include "hex_mmu.h"
>>>
>>>    #ifndef CONFIG_USER_ONLY
>>>    #include "sys_macros.h"
>>> @@ -283,6 +284,18 @@ static void
>> hexagon_restore_state_to_opc(CPUState *cs,
>>>        cpu_env(cs)->gpr[HEX_REG_PC] = data[0];
>>>    }
>>>
>>> +
>>> +#ifndef CONFIG_USER_ONLY
>>> +static void mmu_reset(CPUHexagonState *env) {
>>> +    CPUState *cs = env_cpu(env);
>>> +    if (cs->cpu_index == 0) {
>>
>> This doesn't scale to heterogeneous emulation.
> [Sid Manning]
> Heterogeneous emulation, you mean a version of QEMU with something like ARM and Hexagon configured to run concurrently?

Yes.

> I think we can substitute this with env->threadId, threadId is the same htid (hardware thread id)

That looks safer (and could be your CPUClass::get_arch_id implementation).