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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381c116abf3sm13362914f8f.101.2024.11.04.06.27.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 04 Nov 2024 06:27:26 -0800 (PST) Message-ID: <63c232c2-a325-48d6-8ed4-753a7c6e3b4e@redhat.com> Date: Mon, 4 Nov 2024 15:27:24 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC 18/21] arm/cpu: Introduce a customizable kvm host cpu model Content-Language: en-US To: =?UTF-8?Q?Daniel_P=2E_Berrang=C3=A9?= , Peter Maydell Cc: eric.auger.pro@gmail.com, cohuck@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, abologna@redhat.com, jdenemar@redhat.com, shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com References: <20241025101959.601048-1-eric.auger@redhat.com> <20241025101959.601048-19-eric.auger@redhat.com> From: Eric Auger In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.34, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Daniel, On 10/28/24 18:04, Daniel P. Berrangé wrote: > On Mon, Oct 28, 2024 at 04:48:18PM +0000, Peter Maydell wrote: >> On Mon, 28 Oct 2024 at 16:35, Daniel P. Berrangé wrote: >>> On Mon, Oct 28, 2024 at 04:16:31PM +0000, Peter Maydell wrote: >>>> On Fri, 25 Oct 2024 at 14:24, Daniel P. Berrangé wrote: >>>>> On Fri, Oct 25, 2024 at 03:18:25PM +0200, Eric Auger wrote: >>>>>> On 10/25/24 15:06, Daniel P. Berrangé wrote: >>>>>>> Also, is this naming convention really the same one that users >>>>>>> will see when they look at /proc/cpuinfo to view features ? It >>>>>> No it is not. I do agree that the custom cpu model is very low level. It >>>>>> is very well suited to test all series turning ID regs as writable but >>>>>> this would require an extra layer that adapts /proc/cpuinfo feature >>>>>> level to this regid/field abstraction. >>>>>> >>>>>> In /cpu/proc you will see somethink like: >>>>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp >>>>>> asimdhp cpuid asimdrdm lrcpc dcpop asimddp >>>>> Right, IMHO, this is the terminology that QEMU must use in user >>>>> facing APIs. >>>> /proc/cpuinfo's naming is rather weird for historical >>>> reasons (for instance there is only one FEAT_FP16 feature >>>> but cpuinfo lists "fphp" and "asimdhp" separately). >>> There's plenty of wierd history in x86 too. In this >>> case I might suggest just picking one of the two >>> common names, and ignoring the other. >>> >>> If we really wanted to, we could alias the 2nd name >>> to the first, but its likely not worth the bother. >> Or we could use the standard set of architectural >> feature names, and not have the problem at all, and not >> have to document what we mean by our nonstandard names. >> (cpuinfo names do actually mostly line up with the >> standard names, just not 100%. Similarly gcc/clang command >> line options are mostly the architectural feature name.) > Ah, right, yes. Sorry I mis-understood you originally to be suggesting > the same low level names as this patch. If my understanding is correct, Peter suggested to rely on the terminology used in https://developer.arm.com/documentation/109697/2024_09 the doc pointed to by Oliver. So I think the next step is to understand how those "high level" features do map onto low level ID register field values. I think a high level feature can map onto separate fields in separate ID regs. This may not be the most common case though. Thanks Eric > > With regards, > Daniel