Re: [PATCH] target/arm: Disable SVE extensions when SVE is disabled

[Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>]

W dniu 26.05.2024 o 22:45, Richard Henderson pisze:
> From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
> 
> Cc: qemu-stable@nongnu.org
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2304
> Reported-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

> ---
> 
> Marcin added the correct patch to the issue 3 weeks ago, so I'm giving
> him authorship here.  I only updated the comment a bit.

I am not fully sure is it everything needed to be honest.

Value 0x0000 in [3:0] means "The SVE instructions are implemented".

The way why it works is probably because QEMU keeps "there is no SVE" 
information separately and do not emulate them.

> Marcin, if you'd reply to this with your s-o-b, that would be helpful.

done


> r~
> 
> ---
>   target/arm/cpu64.c | 6 +++++-
>   1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index c15d086049..862d2b92fa 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -109,7 +109,11 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
>            * No explicit bits enabled, and no implicit bits from sve-max-vq.
>            */
>           if (!cpu_isar_feature(aa64_sve, cpu)) {
> -            /* SVE is disabled and so are all vector lengths.  Good. */
> +            /*
> +             * SVE is disabled and so are all vector lengths.  Good.
> +             * Disable all SVE extensions as well.
> +             */
> +            cpu->isar.id_aa64zfr0 = 0;
>               return;
>           }
>