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[83.11.37.15]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a62b5d80ff0sm220452466b.95.2024.05.26.14.06.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 26 May 2024 14:06:36 -0700 (PDT) Message-ID: <63ff94b6-98df-4e5e-9c53-7a03c7309cd3@linaro.org> Date: Sun, 26 May 2024 23:06:35 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/arm: Disable SVE extensions when SVE is disabled To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-stable@nongnu.org References: <20240526204551.553282-1-richard.henderson@linaro.org> From: Marcin Juszkiewicz Content-Language: pl-PL, en-GB, en-HK Organization: Linaro In-Reply-To: <20240526204551.553282-1-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=marcin.juszkiewicz@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org W dniu 26.05.2024 o 22:45, Richard Henderson pisze: > From: Marcin Juszkiewicz > > Cc: qemu-stable@nongnu.org > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2304 > Reported-by: Marcin Juszkiewicz > Signed-off-by: Richard Henderson Signed-off-by: Marcin Juszkiewicz > --- > > Marcin added the correct patch to the issue 3 weeks ago, so I'm giving > him authorship here. I only updated the comment a bit. I am not fully sure is it everything needed to be honest. Value 0x0000 in [3:0] means "The SVE instructions are implemented". The way why it works is probably because QEMU keeps "there is no SVE" information separately and do not emulate them. > Marcin, if you'd reply to this with your s-o-b, that would be helpful. done > r~ > > --- > target/arm/cpu64.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index c15d086049..862d2b92fa 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -109,7 +109,11 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) > * No explicit bits enabled, and no implicit bits from sve-max-vq. > */ > if (!cpu_isar_feature(aa64_sve, cpu)) { > - /* SVE is disabled and so are all vector lengths. Good. */ > + /* > + * SVE is disabled and so are all vector lengths. Good. > + * Disable all SVE extensions as well. > + */ > + cpu->isar.id_aa64zfr0 = 0; > return; > } >