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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7c573d89b9asm108637085a.99.2025.03.13.08.21.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 13 Mar 2025 08:21:38 -0700 (PDT) Message-ID: <64152d6c-4125-426e-9102-ec3e3afef1d4@redhat.com> Date: Thu, 13 Mar 2025 16:21:33 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v2 05/20] hw/arm/smmuv3-accel: Associate a pxb-pcie bus Content-Language: en-US To: Shameerali Kolothum Thodi , =?UTF-8?Q?Daniel_P=2E_Berrang=C3=A9?= Cc: "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "peter.maydell@linaro.org" , "jgg@nvidia.com" , "nicolinc@nvidia.com" , "ddutile@redhat.com" , "nathanc@nvidia.com" , "mochs@nvidia.com" , "smostafa@google.com" , Linuxarm , "Wangzhou (B)" , jiangkunkun , Jonathan Cameron , "zhangfei.gao@linaro.org" References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> <20250311141045.66620-6-shameerali.kolothum.thodi@huawei.com> <79bcc36c-1a12-4b18-a54c-afe734d6bef0@redhat.com> <9ffee8119fc441aeb760073c5f152fa4@huawei.com> <2f44b284cb854844889b9ee8b6239e0a@huawei.com> From: Eric Auger In-Reply-To: <2f44b284cb854844889b9ee8b6239e0a@huawei.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Shameer, On 3/12/25 6:28 PM, Shameerali Kolothum Thodi wrote: > >> -----Original Message----- >> From: Daniel P. Berrangé >> Sent: Wednesday, March 12, 2025 4:39 PM >> To: Shameerali Kolothum Thodi >> Cc: eric.auger@redhat.com; qemu-arm@nongnu.org; qemu- >> devel@nongnu.org; peter.maydell@linaro.org; jgg@nvidia.com; >> nicolinc@nvidia.com; ddutile@redhat.com; nathanc@nvidia.com; >> mochs@nvidia.com; smostafa@google.com; Linuxarm >> ; Wangzhou (B) ; >> jiangkunkun ; Jonathan Cameron >> ; zhangfei.gao@linaro.org >> Subject: Re: [RFC PATCH v2 05/20] hw/arm/smmuv3-accel: Associate a pxb- >> pcie bus >> >> On Wed, Mar 12, 2025 at 04:34:18PM +0000, Shameerali Kolothum Thodi >> wrote: >>> Hi Eric, >>> >>>> -----Original Message----- >>>> From: Eric Auger >>>> Sent: Wednesday, March 12, 2025 4:08 PM >>>> To: Shameerali Kolothum Thodi >>>> ; qemu-arm@nongnu.org; >>>> qemu-devel@nongnu.org >>>> Cc: peter.maydell@linaro.org; jgg@nvidia.com; nicolinc@nvidia.com; >>>> ddutile@redhat.com; berrange@redhat.com; nathanc@nvidia.com; >>>> mochs@nvidia.com; smostafa@google.com; Linuxarm >>>> ; Wangzhou (B) ; >>>> jiangkunkun ; Jonathan Cameron >>>> ; zhangfei.gao@linaro.org >>>> Subject: Re: [RFC PATCH v2 05/20] hw/arm/smmuv3-accel: Associate a >> pxb- >>>> pcie bus >>>> >>>> Hi Shameer, >>>> >>>> >>>> On 3/11/25 3:10 PM, Shameer Kolothum wrote: >>>>> User must associate a pxb-pcie root bus to smmuv3-accel >>>>> and that is set as the primary-bus for the smmu dev. >>>> why do we require a pxb-pcie root bus? why can't pci.0 root bus be used >>>> for simpler use cases (ie. I just want to passthough a NIC in >>>> accelerated mode). Or may pci.0 is also called a pax-pcie root bus? >>> The idea was since pcie.0 is the default RC with virt, leave that to cases >> where >>> we want to attach any emulated devices and use pxb-pcie based RCs for >> vfio-pci. >> >> The majority of management applications will never do anything other >> than a flat PCI(e) topology by default. Some might enable pxb-pcie as >> an optional but plenty won't ever support it. If you want to maximise >> the potential usefulness of the ssmmuv3-accel, and it is technically >> viable, it would be worth permitting choice of attachment to the root >> bus as an alteranative to the pxb. > Ok. I will look into this. Though I am not sure when we have smmuv3-accel > to pcie.0 we can still have additional smmuv3-accel with pxb-pcie or not. > It looks like pxb-pcie will be plugged into pcie.0. And if that is the case > IORT mappings will be difficult I guess. I need to double check. Indeed it makes things more difficult in terms of id mapping but I think it would bring some benefits to be able to plug the accel smmu on pci.0 too. some logic should be there already because you can bypass the SMMU on a given pxb while enabled on pci.0: see [PATCH v5 0/9] IOMMU: Add support for IOMMU Bypass Feature https://lore.kernel.org/all/1625748919-52456-1-git-send-email-wangxingang5@huawei.com/ Eric > > Thanks, > Shameer