From: Andrew Jeffery <andrew@codeconstruct.com.au>
To: "Jamin Lin" <jamin_lin@aspeedtech.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>, "Joel Stanley" <joel@jms.id.au>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: troy_lee@aspeedtech.com, yunlin.tang@aspeedtech.com
Subject: Re: [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions
Date: Thu, 30 Jan 2025 14:35:25 +1030 [thread overview]
Message-ID: <64382a15c40b33fcfeeecee5489e0a034313b7ec.camel@codeconstruct.com.au> (raw)
In-Reply-To: <20250121070424.2465942-12-jamin_lin@aspeedtech.com>
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> Added new definitions for AST2700_A1_SILICON_REV and
> AST2750_A1_SILICON_REV to
> identify the A1 silicon revisions.
>
> Update "aspeed_ast2700_scu_reset" to set the silicon_rev field in the
> SCU
> registers.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
> hw/misc/aspeed_scu.c | 3 +++
> include/hw/misc/aspeed_scu.h | 2 ++
> 2 files changed, 5 insertions(+)
>
> diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
> index bac1441b06..f049a9fd96 100644
> --- a/hw/misc/aspeed_scu.c
> +++ b/hw/misc/aspeed_scu.c
> @@ -559,6 +559,8 @@ static uint32_t aspeed_silicon_revs[] = {
> AST2700_A0_SILICON_REV,
> AST2720_A0_SILICON_REV,
> AST2750_A0_SILICON_REV,
> + AST2700_A1_SILICON_REV,
> + AST2750_A1_SILICON_REV,
> };
>
> bool is_supported_silicon_rev(uint32_t silicon_rev)
> @@ -938,6 +940,7 @@ static void aspeed_ast2700_scu_reset(DeviceState
> *dev)
> AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
>
> memcpy(s->regs, asc->resets, asc->nr_regs * 4);
> + s->regs[AST2700_SILICON_REV] = s->silicon_rev;
Has s->silicon_rev been set?
Should we now remove the AST2700_SILICON_REV entry from asc->resets?
This seems like a fix regardless. Perhaps separate it from the addition
of the new silicon IDs?
> }
>
> static void aspeed_2700_scu_class_init(ObjectClass *klass, void
> *data)
> diff --git a/include/hw/misc/aspeed_scu.h
> b/include/hw/misc/aspeed_scu.h
> index 356be95e45..684b48b722 100644
> --- a/include/hw/misc/aspeed_scu.h
> +++ b/include/hw/misc/aspeed_scu.h
> @@ -54,6 +54,8 @@ struct AspeedSCUState {
> #define AST2700_A0_SILICON_REV 0x06000103U
> #define AST2720_A0_SILICON_REV 0x06000203U
> #define AST2750_A0_SILICON_REV 0x06000003U
> +#define AST2700_A1_SILICON_REV 0x06010103U
> +#define AST2750_A1_SILICON_REV 0x06010003U
These look fine.
Andrew
>
> #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) ==
> 0x04)
>
next prev parent reply other threads:[~2025-01-30 4:06 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0 Jamin Lin via
2025-01-29 17:03 ` Cédric Le Goater
2025-01-30 3:22 ` Andrew Jeffery
2025-02-04 6:50 ` Jamin Lin
2025-02-04 7:34 ` Cédric Le Goater
2025-02-04 8:22 ` Jamin Lin
2025-02-04 10:26 ` Cédric Le Goater
2025-01-30 3:27 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 02/18] hw/intc/aspeed: Support different memory region ops Jamin Lin via
2025-01-30 3:32 ` Andrew Jeffery
2025-02-04 7:00 ` Jamin Lin
2025-01-21 7:04 ` [PATCH v1 03/18] hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0 Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 04/18] hw/intc/aspeed: Support setting different memory and register size Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 05/18] hw/intc/aspeed: Introduce helper functions for enable and status registers Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 06/18] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address Jamin Lin via
2025-01-30 3:55 ` Andrew Jeffery
2025-02-04 9:45 ` Jamin Lin
2025-01-21 7:04 ` [PATCH v1 07/18] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 08/18] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 09/18] hw/intc/aspeed: Add ID to trace events for better debugging Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 10/18] hw/intc/aspeed: Add Support for AST2700 INTC1 Controller Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions Jamin Lin via
2025-01-30 4:05 ` Andrew Jeffery [this message]
2025-02-04 7:23 ` Jamin Lin
2025-02-04 7:29 ` Cédric Le Goater
2025-01-21 7:04 ` [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 Jamin Lin via
2025-01-30 4:19 ` Andrew Jeffery
2025-02-04 9:43 ` Jamin Lin
2025-02-05 3:50 ` Andrew Jeffery
2025-02-05 7:12 ` Jamin Lin
2025-02-05 23:39 ` Andrew Jeffery
2025-02-06 4:55 ` Joel Stanley
2025-02-06 5:15 ` Jamin Lin
2025-02-06 7:17 ` Cédric Le Goater
2025-02-06 7:22 ` Jamin Lin
2025-02-06 7:22 ` Cédric Le Goater
2025-02-06 7:24 ` Jamin Lin
2025-01-21 7:04 ` [PATCH v1 13/18] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 14/18] hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1 Jamin Lin via
2025-01-30 4:22 ` Andrew Jeffery
2025-02-03 8:55 ` Jamin Lin
2025-01-21 7:04 ` [PATCH v1 15/18] hw/misc/aspeed_hace: Fix coding style Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 16/18] hw/misc/aspeed_hace: Add AST2700 support Jamin Lin via
2025-01-30 4:30 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 17/18] hw/arm/aspeed_ast27x0: Add HACE support for AST2700 Jamin Lin via
2025-01-30 4:32 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 18/18] hw/misc/aspeed_hace: (DROP) Fix boot issue in the Crypto Manager Self Test(WORKAROUND) Jamin Lin via
2025-01-31 7:34 ` [PATCH v1 00/18] Support AST2700 A1 Cédric Le Goater
2025-02-04 8:05 ` Jamin Lin
2025-06-30 20:28 ` Cédric Le Goater
2025-07-02 1:57 ` Jamin Lin
2025-07-02 6:43 ` Cédric Le Goater
2025-07-03 7:43 ` Jamin Lin
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