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([2804:7f0:bcc0:f7fc:9d46:b65e:128d:39a8]) by smtp.gmail.com with ESMTPSA id l12-20020a170903244c00b001c877f27d1fsm5473588pls.11.2023.11.14.03.20.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 14 Nov 2023 03:20:40 -0800 (PST) Message-ID: <6439d06c-7b9b-4fe7-83dd-a33be98ef98e@ventanamicro.com> Date: Tue, 14 Nov 2023 08:20:35 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/riscv: don't verify ISA compatibility for zicntr and zihpm To: =?UTF-8?Q?Cl=C3=A9ment_Chigot?= , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Alistair Francis , Palmer Dabbelt , Bin Meng References: <20231114094412.413408-1-chigot@adacore.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20231114094412.413408-1-chigot@adacore.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org (adding maintainers in the CC) On 11/14/23 06:44, Clément Chigot wrote: > The extensions zicntr and zihpm were officially added in the privilege > instruction set specification 1.12. However, QEMU has been implemented > them long before it and thus they are forced to be on during the cpu > initialization to ensure compatibility (see riscv_cpu_init). > riscv_cpu_disable_priv_spec_isa_exts was not updated when the above > behavior was introduced, resulting in these extensions to be disabled > after all. > Please add the following tags: Fixes: c004099330 ("target/riscv: add zicntr extension flag for TCG") Fixes: 0824121660 ("target/riscv: add zihpm extension flag for TCG") > Signed-off-by: Clément Chigot > --- Reviewed-by: Daniel Henrique Barboza > target/riscv/tcg/tcg-cpu.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 08adad304d..8a35683a34 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -250,6 +250,15 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) > for (edata = isa_edata_arr; edata && edata->name; edata++) { > if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && > (env->priv_ver < edata->min_version)) { > + /* > + * These two extensions are always enabled as they were supported > + * by QEMU before they were added as extensions in the ISA. > + */ > + if (!strcmp(edata->name, "zicntr") || > + !strcmp(edata->name, "zihpm")) { > + continue; > + } > + > isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); > #ifndef CONFIG_USER_ONLY > warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx