Re: [kvm-unit-tests PATCH v4 08/12] arm: pmu: Test SW_INCR event count

[Zenghui Yu via <qemu-devel@nongnu.org>]

Hi Eric,

On 2020/4/3 15:13, Eric Auger wrote:

> +static void test_sw_incr(void)
> +{
> +	uint32_t events[] = {SW_INCR, SW_INCR};
> +	int i;
> +
> +	if (!satisfy_prerequisites(events, ARRAY_SIZE(events)))
> +		return;
> +
> +	pmu_reset();
> +
> +	write_regn_el0(pmevtyper, 0, SW_INCR | PMEVTYPER_EXCLUDE_EL0);
> +	write_regn_el0(pmevtyper, 1, SW_INCR | PMEVTYPER_EXCLUDE_EL0);
> +	/* enable counters #0 and #1 */
> +	write_sysreg_s(0x3, PMCNTENSET_EL0);
> +
> +	write_regn_el0(pmevcntr, 0, PRE_OVERFLOW);
> +
> +	for (i = 0; i < 100; i++)
> +		write_sysreg(0x1, pmswinc_el0);
> +
> +	report_info("SW_INCR counter #0 has value %ld", read_regn_el0(pmevcntr, 0));
> +	report(read_regn_el0(pmevcntr, 0) == PRE_OVERFLOW,
> +		"PWSYNC does not increment if PMCR.E is unset");
> +
> +	pmu_reset();
> +
> +	write_regn_el0(pmevcntr, 0, PRE_OVERFLOW);
> +	write_sysreg_s(0x3, PMCNTENSET_EL0);
> +	set_pmcr(pmu.pmcr_ro | PMU_PMCR_E);
> +
> +	for (i = 0; i < 100; i++)
> +		write_sysreg(0x3, pmswinc_el0);
> +
> +	report(read_regn_el0(pmevcntr, 0)  == 84, "counter #1 after + 100 SW_INCR");

"counter #0 after + 100 SW_INCR"

> +	report(read_regn_el0(pmevcntr, 1)  == 100,
> +		"counter #0 after + 100 SW_INCR");

"counter #1 after + 100 SW_INCR"

> +	report_info("counter values after 100 SW_INCR #0=%ld #1=%ld",
> +		    read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1));
> +	report(read_sysreg(pmovsclr_el0) == 0x1,
> +		"overflow reg after 100 SW_INCR");
> +}
> +
>  #endif
>  
>  /*

Zenghui