* [PATCH 0/3] target/mips: Remove vendor specific CPU definitions
@ 2021-01-12 21:01 Philippe Mathieu-Daudé
2021-01-12 21:01 ` [PATCH 1/3] target/mips: Remove CPU_R5900 definition Philippe Mathieu-Daudé
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-12 21:01 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson,
Philippe Mathieu-Daudé, Aurelien Jarno
Trivial patches to sanitize MIPS CPU definitions.
Based-on: mips-next
Philippe Mathieu-Daudé (3):
target/mips: Remove CPU_R5900 definition
target/mips: Remove CPU_NANOMIPS32 definition
target/mips: Remove vendor specific CPU definitions
target/mips/mips-defs.h | 9 ---------
target/mips/cpu-defs.c.inc | 16 +++++++++-------
2 files changed, 9 insertions(+), 16 deletions(-)
--
2.26.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/3] target/mips: Remove CPU_R5900 definition
2021-01-12 21:01 [PATCH 0/3] target/mips: Remove vendor specific CPU definitions Philippe Mathieu-Daudé
@ 2021-01-12 21:01 ` Philippe Mathieu-Daudé
2021-01-12 21:01 ` [PATCH 2/3] target/mips: Remove CPU_NANOMIPS32 definition Philippe Mathieu-Daudé
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-12 21:01 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson,
Philippe Mathieu-Daudé, Aurelien Jarno
Commit 823f2897bdd ("target/mips: Disable R5900 support")
removed the single CPU using the CPU_R5900 definition.
As it is unused, remove it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/mips-defs.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 6b8e6800115..b7879be9e90 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -61,7 +61,6 @@
#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
-#define CPU_R5900 (CPU_MIPS3 | INSN_R5900)
#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
--
2.26.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/3] target/mips: Remove CPU_NANOMIPS32 definition
2021-01-12 21:01 [PATCH 0/3] target/mips: Remove vendor specific CPU definitions Philippe Mathieu-Daudé
2021-01-12 21:01 ` [PATCH 1/3] target/mips: Remove CPU_R5900 definition Philippe Mathieu-Daudé
@ 2021-01-12 21:01 ` Philippe Mathieu-Daudé
2021-01-12 21:01 ` [PATCH 3/3] target/mips: Remove vendor specific CPU definitions Philippe Mathieu-Daudé
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-12 21:01 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson,
Philippe Mathieu-Daudé, Aurelien Jarno
nanoMIPS not a CPU, but an ISA. The nanoMIPS ISA is already
defined as ISA_NANOMIPS32.
Remove this incorrect definition and update the single CPU
implementing it, the I7200.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/mips-defs.h | 3 ---
target/mips/cpu-defs.c.inc | 4 ++--
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index b7879be9e90..3704db85532 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -86,9 +86,6 @@
#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6)
#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6)
-/* Wave Computing: "nanoMIPS" */
-#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
-
#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT)
/*
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index ba22ff4bcd1..9f7bac87932 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -486,8 +486,8 @@ const mips_def_t mips_defs[] =
.CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 |
- ASE_MT,
+ .insn_flags = CPU_MIPS32R6 | ISA_NANOMIPS32 |
+ ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 | ASE_MT,
.mmu_type = MMU_TYPE_R4000,
},
#if defined(TARGET_MIPS64)
--
2.26.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/3] target/mips: Remove vendor specific CPU definitions
2021-01-12 21:01 [PATCH 0/3] target/mips: Remove vendor specific CPU definitions Philippe Mathieu-Daudé
2021-01-12 21:01 ` [PATCH 1/3] target/mips: Remove CPU_R5900 definition Philippe Mathieu-Daudé
2021-01-12 21:01 ` [PATCH 2/3] target/mips: Remove CPU_NANOMIPS32 definition Philippe Mathieu-Daudé
@ 2021-01-12 21:01 ` Philippe Mathieu-Daudé
2021-01-12 21:34 ` [PATCH 0/3] " Richard Henderson
2021-01-14 16:01 ` Philippe Mathieu-Daudé
4 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-12 21:01 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson,
Philippe Mathieu-Daudé, Aurelien Jarno
Vendor specific CPU definitions are not very useful. Use the
ISA definitions instead, which are more helpful when looking
at the various CPU definitions.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/mips-defs.h | 5 -----
target/mips/cpu-defs.c.inc | 12 +++++++-----
2 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 3704db85532..0a12d982a72 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -60,9 +60,6 @@
#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
-#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
-#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
-#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
#define CPU_MIPS64 (ISA_MIPS3)
@@ -86,8 +83,6 @@
#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6)
#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6)
-#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT)
-
/*
* Strictly follow the architecture standard:
* - Disallow "special" instruction handling for PMON/SPIM.
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index 9f7bac87932..e03b2a998cd 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -531,7 +531,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 40,
.PABITS = 32,
- .insn_flags = CPU_VR54XX,
+ .insn_flags = CPU_MIPS4 | INSN_VR54XX,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -781,7 +781,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 40,
.PABITS = 40,
- .insn_flags = CPU_LOONGSON2E,
+ .insn_flags = CPU_MIPS3 | INSN_LOONGSON2E,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -801,7 +801,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 40,
.PABITS = 40,
- .insn_flags = CPU_LOONGSON2F,
+ .insn_flags = CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -830,7 +830,8 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 42,
.PABITS = 48,
- .insn_flags = CPU_LOONGSON3A,
+ .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
+ ASE_LMMI | ASE_LEXT,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -887,7 +888,8 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 48,
.PABITS = 48,
- .insn_flags = CPU_LOONGSON3A,
+ .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
+ ASE_LMMI | ASE_LEXT,
.mmu_type = MMU_TYPE_R4000,
},
{
--
2.26.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 0/3] target/mips: Remove vendor specific CPU definitions
2021-01-12 21:01 [PATCH 0/3] target/mips: Remove vendor specific CPU definitions Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2021-01-12 21:01 ` [PATCH 3/3] target/mips: Remove vendor specific CPU definitions Philippe Mathieu-Daudé
@ 2021-01-12 21:34 ` Richard Henderson
2021-01-14 16:01 ` Philippe Mathieu-Daudé
4 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2021-01-12 21:34 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Aurelien Jarno
On 1/12/21 11:01 AM, Philippe Mathieu-Daudé wrote:
> Trivial patches to sanitize MIPS CPU definitions.
>
> Based-on: mips-next
>
> Philippe Mathieu-Daudé (3):
> target/mips: Remove CPU_R5900 definition
> target/mips: Remove CPU_NANOMIPS32 definition
> target/mips: Remove vendor specific CPU definitions
>
> target/mips/mips-defs.h | 9 ---------
> target/mips/cpu-defs.c.inc | 16 +++++++++-------
> 2 files changed, 9 insertions(+), 16 deletions(-)
>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/3] target/mips: Remove vendor specific CPU definitions
2021-01-12 21:01 [PATCH 0/3] target/mips: Remove vendor specific CPU definitions Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2021-01-12 21:34 ` [PATCH 0/3] " Richard Henderson
@ 2021-01-14 16:01 ` Philippe Mathieu-Daudé
4 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-14 16:01 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson, Aurelien Jarno
On 1/12/21 10:01 PM, Philippe Mathieu-Daudé wrote:
> Trivial patches to sanitize MIPS CPU definitions.
>
> Based-on: mips-next
>
> Philippe Mathieu-Daudé (3):
> target/mips: Remove CPU_R5900 definition
> target/mips: Remove CPU_NANOMIPS32 definition
> target/mips: Remove vendor specific CPU definitions
>
> target/mips/mips-defs.h | 9 ---------
> target/mips/cpu-defs.c.inc | 16 +++++++++-------
> 2 files changed, 9 insertions(+), 16 deletions(-)
Thanks, applied to mips-next.
^ permalink raw reply [flat|nested] 6+ messages in thread
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2021-01-12 21:01 ` [PATCH 2/3] target/mips: Remove CPU_NANOMIPS32 definition Philippe Mathieu-Daudé
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