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([2a10:d582:31e:0:2e31:bfde:d946:d752]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47a7d810c3esm40275215e9.13.2025.12.09.07.04.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Dec 2025 07:04:39 -0800 (PST) Message-ID: <64beb7f0-5406-433a-9cca-f94c5f4164ff@linaro.org> Date: Tue, 9 Dec 2025 15:04:39 +0000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] target/arm: Allow writes to FNG1, FNG0, A2 To: qemu-devel@nongnu.org References: <20251204180617.1190660-1-jim.macarthur@linaro.org> <20251204180617.1190660-3-jim.macarthur@linaro.org> <59cb24e2-699e-4511-84e5-ad5d3ee90b58@linaro.org> Content-Language: en-US Cc: richard.henderson@linaro.org From: Jim MacArthur In-Reply-To: <59cb24e2-699e-4511-84e5-ad5d3ee90b58@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=jim.macarthur@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/5/25 15:30, Richard Henderson wrote: > On 12/4/25 12:04, Jim MacArthur wrote: >> @@ -6121,8 +6131,16 @@ static void tcr2_el2_write(CPUARMState *env, >> const ARMCPRegInfo *ri, >>       if (cpu_isar_feature(aa64_mec, cpu)) { >>           valid_mask |= TCR2_AMEC0 | TCR2_AMEC1; >>       } >> +    if (cpu_isar_feature(aa64_asid2, cpu)) { >> +        valid_mask |= TCR2_FNG1 | TCR2_FNG0 | TCR2_A2; >> +        require_flush = true; >> +    } >>       value &= valid_mask; >>       raw_write(env, ri, value); >> + >> +    if (require_flush) { >> +        tlb_flush(CPU(cpu)); >> +    } > > Just because A2 is valid doesn't mean the A2 bit changed. > > Compare, for instance, vmsa_ttbr_write, where we notice if the ASID > has changed before performing the flush. > > Note as well that we don't need to flush all tlbs.  In tcr2_el1_write > we know that we are only affecting the EL1&0 regime (alle1_tlbmask).  > In tcr2_el2_write, we know that we are only affecting the EL2&0 regime > (see the E2H part of vae2_tlbmask). > > > r~ > Before I make a full patch series, can I check this looks correct? In tcr2_el1_write:     if (cpu_isar_feature(aa64_asid2, cpu)) {         uint64_t asid_nonglobal_flags = TCR2_FNG1 | TCR2_FNG0 | TCR2_A2;         valid_mask |= asid_nonglobal_flags;         require_flush = ((raw_read(env, ri) ^ value) & asid_nonglobal_flags) != 0;     }     value &= valid_mask;     raw_write(env, ri, value);     if (require_flush) {         tlb_flush_by_mmuidx(CPU(cpu), alle1_tlbmask(env));     } And then in tcr_el2_write, the same check but flushing by: ARMMMUIdxBit_E20_2 |ARMMMUIdxBit_E20_2_PAN | ARMMMUIdxBit_E20_2_GCS | ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_0_GCS, as used in vmsa_tcr_ttbr_el2_write. This could be factored out into a constant function like alle1_tlbmask. Jim