From: Andrew Jeffery <andrew@codeconstruct.com.au>
To: "Jamin Lin" <jamin_lin@aspeedtech.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>, "Joel Stanley" <joel@jms.id.au>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: Troy Lee <troy_lee@aspeedtech.com>,
Yunlin Tang <yunlin.tang@aspeedtech.com>
Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
Date: Thu, 06 Feb 2025 10:09:19 +1030 [thread overview]
Message-ID: <64d943d2e53c70ca55b33ec7a9b103368d72acc0.camel@codeconstruct.com.au> (raw)
In-Reply-To: <SI2PR06MB50410511510D84B854672E8CFCF72@SI2PR06MB5041.apcprd06.prod.outlook.com>
Hi Jamin,
> > >
> > > The design of the OR gates for GICINT 196 is as follows:
> >
> > 196? You discuss 192 below.
> >
> Sorry typo. I update my comments.
>
> The design of the OR gates for GICINT 196 is as follows:
> It has interrupt sources ranging from 0 to 31, with its output pin connected to
> INTC_IO "T0 GICINT_196".
> The output pin is then connected to INTC_CPU "GIC_192_201" at bit 4, and
> its bit 4 output should be connected to GIC 196.
> The design of INTC_CPU GIC_192_201 have 10 output pins, mapped as following:
> Bit 0 -> GIC 192
> Bit 1 -> GIC 193
> Bit 2 -> GIC 194
> Bit 3 -> GIC 195
> Bit 4 -> GIC 196
>
> Jamin
> |-------------------------------------------------------------------------------------------------------|
> | AST2700 A1 Design |
> | To GICINT196 |
> | |
> | ETH1 |-----------| |--------------------------| |--------------| |
> | -------->|0 | | INTC_IO | | orgates[0] | |
> | ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0 | |
> | -------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1 | |
> | ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2 | |
> | -------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3 OR[0:9] |-----| |
> | UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4 | | |
> | -------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5 | | |
> | UART1 | 22| orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6 | | |
> | -------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7 | | |
> | UART2 | 24| orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8 | | |
> | -------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9 | | |
> | UART3 | 26| |--------------------------| |--------------| | |
> | ---------|10 27| | |
> | UART5 | 28| | |
> | -------->|11 29| | |
> | UART6 | | | |
> | -------->|12 30| |-----------------------------------------------------------------------| |
> | UART7 | 31| | |
> | -------->|13 | | |
> | UART8 | OR[0:31] | | |------------------------------| |----------| |
> | -------->|14 | | | INTC | | GIC | |
> | UART9 | | | |inpin[0:0]--------->outpin[0] |---------->|192 | |
> | -------->|15 | | |inpin[0:1]--------->outpin[1] |---------->|193 | |
> | UART10 | | | |inpin[0:2]--------->outpin[2] |---------->|194 | |
> | -------->|16 | | |inpin[0:3]--------->outpin[3] |---------->|195 | |
> | UART11 | | |--------------> |inpin[0:4]--------->outpin[4] |---------->|196 | |
> | -------->|17 | |inpin[0:5]--------->outpin[5] |---------->|197 | |
> | UART12 | | |inpin[0:6]--------->outpin[6] |---------->|198 | |
> | -------->|18 | |inpin[0:7]--------->outpin[7] |---------->|199 | |
> | |-----------| |inpin[0:8]--------->outpin[8] |---------->|200 | |
> | |inpin[0:9]--------->outpin[9] |---------->|201 | |
> |-------------------------------------------------------------------------------------------------------|
> |-------------------------------------------------------------------------------------------------------|
> | ETH1 |-----------| orgates[1]------->|inpin[1]|---------->outpin[10]|---------->|128 | |
> | -------->|0 | orgates[2]------->|inpin[2]|---------->outpin[11]|---------->|129 | |
> | ETH2 | 4| orgates[3]------->|inpin[3]|---------->outpin[12]|---------->|130 | |
> | -------->|1 5| orgates[4]------->|inpin[4]|---------->outpin[13]|---------->|131 | |
> | ETH3 | 6|---->orgates[5]------->|inpin[5]|---------->outpin[14]|---------->|132 | |
> | -------->|2 19| orgates[6]------->|inpin[6]|---------->outpin[15]|---------->|133 | |
> | UART0 | 20| orgates[7]------->|inpin[7]|---------->outpin[16]|---------->|134 | |
> | -------->|7 21| orgates[8]------->|inpin[8]|---------->outpin[17]|---------->|135 | |
> | UART1 | 22| orgates[9]------->|inpin[9]|---------->outpin[18]|---------->|136 | |
> | -------->|8 23| |------------------------------| |----------| |
> | UART2 | 24| |
> | -------->|9 25| AST2700 A0 Design |
> | UART3 | 26| |
> | -------->|10 27| |
> | UART5 | 28| |
> | -------->|11 29| GICINT132 |
> | UART6 | | |
> | -------->|12 30| |
> | UART7 | 31| |
> | -------->|13 | |
> | UART8 | OR[0:31] | |
> | -------->|14 | |
> | UART9 | | |
> | -------->|15 | |
> | UART10 | | |
> | -------->|16 | |
> | UART11 | | |
> | -------->|17 | |
> | UART12 | | |
> | -------->|18 | |
> | |-----------| |
> | |
> |-------------------------------------------------------------------------------------------------------|
> >
Thanks, I'll consider this updated diagram as well while I put my own
together from the other pieces of info you've provided.
Andrew
next prev parent reply other threads:[~2025-02-05 23:41 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0 Jamin Lin via
2025-01-29 17:03 ` Cédric Le Goater
2025-01-30 3:22 ` Andrew Jeffery
2025-02-04 6:50 ` Jamin Lin
2025-02-04 7:34 ` Cédric Le Goater
2025-02-04 8:22 ` Jamin Lin
2025-02-04 10:26 ` Cédric Le Goater
2025-01-30 3:27 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 02/18] hw/intc/aspeed: Support different memory region ops Jamin Lin via
2025-01-30 3:32 ` Andrew Jeffery
2025-02-04 7:00 ` Jamin Lin
2025-01-21 7:04 ` [PATCH v1 03/18] hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0 Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 04/18] hw/intc/aspeed: Support setting different memory and register size Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 05/18] hw/intc/aspeed: Introduce helper functions for enable and status registers Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 06/18] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address Jamin Lin via
2025-01-30 3:55 ` Andrew Jeffery
2025-02-04 9:45 ` Jamin Lin
2025-01-21 7:04 ` [PATCH v1 07/18] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 08/18] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 09/18] hw/intc/aspeed: Add ID to trace events for better debugging Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 10/18] hw/intc/aspeed: Add Support for AST2700 INTC1 Controller Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions Jamin Lin via
2025-01-30 4:05 ` Andrew Jeffery
2025-02-04 7:23 ` Jamin Lin
2025-02-04 7:29 ` Cédric Le Goater
2025-01-21 7:04 ` [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 Jamin Lin via
2025-01-30 4:19 ` Andrew Jeffery
2025-02-04 9:43 ` Jamin Lin
2025-02-05 3:50 ` Andrew Jeffery
2025-02-05 7:12 ` Jamin Lin
2025-02-05 23:39 ` Andrew Jeffery [this message]
2025-02-06 4:55 ` Joel Stanley
2025-02-06 5:15 ` Jamin Lin
2025-02-06 7:17 ` Cédric Le Goater
2025-02-06 7:22 ` Jamin Lin
2025-02-06 7:22 ` Cédric Le Goater
2025-02-06 7:24 ` Jamin Lin
2025-01-21 7:04 ` [PATCH v1 13/18] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 14/18] hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1 Jamin Lin via
2025-01-30 4:22 ` Andrew Jeffery
2025-02-03 8:55 ` Jamin Lin
2025-01-21 7:04 ` [PATCH v1 15/18] hw/misc/aspeed_hace: Fix coding style Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 16/18] hw/misc/aspeed_hace: Add AST2700 support Jamin Lin via
2025-01-30 4:30 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 17/18] hw/arm/aspeed_ast27x0: Add HACE support for AST2700 Jamin Lin via
2025-01-30 4:32 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 18/18] hw/misc/aspeed_hace: (DROP) Fix boot issue in the Crypto Manager Self Test(WORKAROUND) Jamin Lin via
2025-01-31 7:34 ` [PATCH v1 00/18] Support AST2700 A1 Cédric Le Goater
2025-02-04 8:05 ` Jamin Lin
2025-06-30 20:28 ` Cédric Le Goater
2025-07-02 1:57 ` Jamin Lin
2025-07-02 6:43 ` Cédric Le Goater
2025-07-03 7:43 ` Jamin Lin
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