From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Brian Cain <brian.cain@oss.qualcomm.com>, qemu-devel@nongnu.org
Cc: ltaylorsimpson@gmail.com, matheus.bernardino@oss.qualcomm.com,
marco.liebel@oss.qualcomm.com, quic_mburton@quicinc.com,
sid.manning@oss.qualcomm.com, ale@rev.ng, anjo@rev.ng,
Brian Cain <bcain@quicinc.com>
Subject: Re: [PATCH v5 24/35] target/hexagon: Add sysemu TCG overrides
Date: Wed, 25 Mar 2026 20:24:32 +0100 [thread overview]
Message-ID: <65ebb608-fe2b-46ae-bf2f-a09b39f257e0@linaro.org> (raw)
In-Reply-To: <20260311034923.1044737-25-brian.cain@oss.qualcomm.com>
On 11/3/26 04:49, Brian Cain wrote:
> From: Brian Cain <bcain@quicinc.com>
>
> Define TCG overrides for setprio(), crswap(,sgp{0,1,1:0}).
>
> Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> ---
> target/hexagon/cpu_helper.h | 18 ++++++++++++++++
> target/hexagon/gen_tcg_sys.h | 40 ++++++++++++++++++++++++++++++++++++
> target/hexagon/helper.h | 1 +
> target/hexagon/genptr.c | 4 ++++
> target/hexagon/op_helper.c | 10 ++++++++-
> target/hexagon/hex_common.py | 2 ++
> target/hexagon/meson.build | 13 ++++++------
> 7 files changed, 81 insertions(+), 7 deletions(-)
> create mode 100644 target/hexagon/cpu_helper.h
> create mode 100644 target/hexagon/gen_tcg_sys.h
> diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
> index 327c233c01b..d9d84f05553 100644
> --- a/target/hexagon/op_helper.c
> +++ b/target/hexagon/op_helper.c
> @@ -19,9 +19,10 @@
> #include "qemu/log.h"
> #include "accel/tcg/cpu-ldst.h"
> #include "accel/tcg/probe.h"
> +#include "qemu/main-loop.h"
"qemu/main-loop.h" doesn't seem used in this patch.
> +#include "cpu.h"
> #include "exec/helper-proto.h"
> #include "fpu/softfloat.h"
> -#include "cpu.h"
> #include "internal.h"
> #include "macros.h"
> #include "sys_macros.h"
> @@ -31,6 +32,7 @@
> #include "mmvec/mmvec.h"
> #include "mmvec/macros.h"
> #include "op_helper.h"
> +#include "cpu_helper.h"
> #include "translate.h"
> #ifndef CONFIG_USER_ONLY
> #include "hexswi.h"
> @@ -1412,6 +1414,12 @@ uint64_t HELPER(greg_read_pair)(CPUHexagonState *env, uint32_t reg)
> {
> g_assert_not_reached();
> }
> +
> +void HELPER(setprio)(CPUHexagonState *env, uint32_t thread, uint32_t prio)
> +{
> + g_assert_not_reached();
> +}
> +
> #endif
next prev parent reply other threads:[~2026-03-25 19:24 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-11 3:48 [PATCH v5 00/35] Hexagon system emulation, Part 1/3 Brian Cain
2026-03-11 3:48 ` [PATCH v5 01/35] docs: Add hexagon sysemu docs Brian Cain
2026-03-11 3:48 ` [PATCH v5 02/35] docs/system: Add hexagon CPU emulation Brian Cain
2026-03-11 3:48 ` [PATCH v5 03/35] target/hexagon: Fix badva reference, delete CAUSE Brian Cain
2026-03-11 3:48 ` [PATCH v5 04/35] target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof Brian Cain
2026-03-11 3:48 ` [PATCH v5 05/35] target/hexagon: Handle system/guest registers in gen_analyze_funcs.py and hex_common.py Brian Cain
2026-03-11 3:48 ` [PATCH v5 06/35] target/hexagon: Suppress unused-variable warnings for sysemu source regs Brian Cain
2026-03-12 21:03 ` Taylor Simpson
2026-03-11 3:48 ` [PATCH v5 07/35] target/hexagon: Make gen_exception_end_tb non-static Brian Cain
2026-03-11 3:48 ` [PATCH v5 08/35] target/hexagon: Switch to tag_ignore(), generate via get_{user, sys}_tags() Brian Cain via qemu development
2026-03-11 3:48 ` [PATCH v5 09/35] target/hexagon: Add privilege check, use tag_ignore() Brian Cain
2026-03-11 3:48 ` [PATCH v5 10/35] target/hexagon: Add a placeholder fp exception Brian Cain
2026-03-11 3:48 ` [PATCH v5 11/35] target/hexagon: Add guest, system reg number defs Brian Cain
2026-03-11 3:49 ` [PATCH v5 12/35] target/hexagon: Add guest, system reg number state Brian Cain
2026-03-11 3:49 ` [PATCH v5 13/35] target/hexagon: Add TCG values for sreg, greg Brian Cain
2026-03-11 3:49 ` [PATCH v5 14/35] target/hexagon: Add guest/sys reg writes to DisasContext Brian Cain
2026-03-11 3:49 ` [PATCH v5 15/35] target/hexagon: Add imported macro, attr defs for sysemu Brian Cain
2026-03-11 3:49 ` [PATCH v5 16/35] target/hexagon: Add new macro definitions " Brian Cain
2026-03-11 3:49 ` [PATCH v5 17/35] target/hexagon: Add handlers for guest/sysreg r/w Brian Cain
2026-03-11 3:49 ` [PATCH v5 18/35] target/hexagon: Add placeholder greg/sreg r/w helpers Brian Cain
2026-03-11 3:49 ` [PATCH v5 19/35] target/hexagon: Add vmstate representation Brian Cain
2026-03-25 19:21 ` Philippe Mathieu-Daudé
2026-03-11 3:49 ` [PATCH v5 20/35] target/hexagon: Make A_PRIV, "J2_trap*" insts need_env() Brian Cain
2026-03-11 3:49 ` [PATCH v5 21/35] target/hexagon: Define register fields for system regs Brian Cain
2026-03-11 3:49 ` [PATCH v5 22/35] target/hexagon: Implement do_raise_exception() Brian Cain
2026-03-11 3:49 ` [PATCH v5 23/35] target/hexagon: Add system reg insns Brian Cain
2026-03-11 3:49 ` [PATCH v5 24/35] target/hexagon: Add sysemu TCG overrides Brian Cain
2026-03-25 19:24 ` Philippe Mathieu-Daudé [this message]
2026-03-11 3:49 ` [PATCH v5 25/35] target/hexagon: Add implicit attributes to sysemu macros Brian Cain
2026-03-11 3:49 ` [PATCH v5 26/35] target/hexagon: Add TCG overrides for int handler insts Brian Cain
2026-03-11 3:49 ` [PATCH v5 27/35] target/hexagon: Add TCG overrides for thread ctl Brian Cain
2026-03-11 3:49 ` [PATCH v5 28/35] target/hexagon: Add TCG overrides for rte, nmi Brian Cain
2026-03-11 3:49 ` [PATCH v5 29/35] target/hexagon: Add sreg_{read,write} helpers Brian Cain
2026-03-25 19:26 ` Philippe Mathieu-Daudé
2026-03-11 3:49 ` [PATCH v5 30/35] target/hexagon: Add cpu modes, mmu indices, next_PC to state Brian Cain
2026-03-11 3:49 ` [PATCH v5 31/35] hw/hexagon: Introduce hexagon TLB device Brian Cain
2026-03-25 19:38 ` Philippe Mathieu-Daudé
2026-03-11 3:49 ` [PATCH v5 32/35] target/hexagon: Add stubs for modify_ssr/get_exe_mode Brian Cain
2026-03-11 3:49 ` [PATCH v5 33/35] target/hexagon: Add clear_wait_mode() definition Brian Cain
2026-03-11 3:49 ` [PATCH v5 34/35] target/hexagon: Define f{S,G}ET_FIELD macros Brian Cain
2026-03-11 3:49 ` [PATCH v5 35/35] target/hexagon: Add hex_interrupts support Brian Cain
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=65ebb608-fe2b-46ae-bf2f-a09b39f257e0@linaro.org \
--to=philmd@linaro.org \
--cc=ale@rev.ng \
--cc=anjo@rev.ng \
--cc=bcain@quicinc.com \
--cc=brian.cain@oss.qualcomm.com \
--cc=ltaylorsimpson@gmail.com \
--cc=marco.liebel@oss.qualcomm.com \
--cc=matheus.bernardino@oss.qualcomm.com \
--cc=qemu-devel@nongnu.org \
--cc=quic_mburton@quicinc.com \
--cc=sid.manning@oss.qualcomm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox