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([2001:8004:2728:321b:5fc1:fe4b:9b89:f799]) by smtp.gmail.com with ESMTPSA id lp18-20020a056a003d5200b006db0f35296esm1924219pfb.148.2024.01.17.12.32.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Jan 2024 12:32:51 -0800 (PST) Message-ID: <65fea2a9-841f-43b1-a756-66efe5c9f263@linaro.org> Date: Thu, 18 Jan 2024 07:32:45 +1100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/i386: pcrel: store low bits of physical address in data[0] To: Paolo Bonzini , qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Mark Cave-Ayland References: <20240117155143.172890-1-pbonzini@redhat.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240117155143.172890-1-pbonzini@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c36; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/18/24 02:51, Paolo Bonzini wrote: > For PC-relative translation blocks, env->eip changes during the > execution of a translation block, Therefore, QEMU must be able to > recover an instruction's PC just from the TranslationBlock struct and > the instruction data with. Because a TB will not span two pages, QEMU > stores all the low bits of EIP in the instruction data and replaces them > in x86_restore_state_to_opc. Bits 12 and higher (which may vary between > executions of a PCREL TB, since these only use the physical address in > the hash key) are kept unmodified from env->eip. The assumption is that > these bits of EIP, unlike bits 0-11, will not change as the translation > block executes. > > Unfortunately, this is incorrect when the CS base is not aligned to a page. > Then the linear address of the instructions (i.e. the one with the > CS base addred) indeed will never span two pages, but bits 12+ of EIP added > can actually change. For example, if CS base is 0x80262200 and EIP = > 0x6FF4, the first instruction in the translation block will be at linear > address 0x802691F4. Even a very small TB will cross to EIP = 0x7xxx, > while the linear addresses will remain comfortably within a single page. > > The fix is simply to use the low bits of the linear address for data[0], > since those don't change. Then x86_restore_state_to_opc uses tb->cs_base > to compute a temporary linear address (referring to some unknown > instruction in the TB, but with the correct values of bits 12 and higher); > the low bits are replaced with data[0], and EIP is obtained by subtracting > again the CS base. > > Huge thanks to Mark Cave-Ayland for the image and initial debugging, > and to Gitlab user @kjliew for help with bisecting another occurrence > of (hopefully!) the same bug. > > It should be relatively easy to write a testcase that performs MMIO on > an EIP with different bits 12+ than the first instruction of the translation > block; any help is welcome. > > Fixes: e3a79e0e878 ("target/i386: Enable TARGET_TB_PCREL", 2022-10-11) > Cc: qemu-stable@nongnu.org > Cc: Mark Cave-Ayland > Cc: Richard Henderson > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1964 > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2012 > Signed-off-by: Paolo Bonzini > --- > target/i386/tcg/tcg-cpu.c | 20 ++++++++++++++++---- > target/i386/tcg/translate.c | 1 - > 2 files changed, 16 insertions(+), 5 deletions(-) Wow, that is subtle. Reviewed-by: Richard Henderson r~