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[95.125.227.10]) by smtp.gmail.com with ESMTPSA id o12sm3687610wrc.85.2021.11.11.03.50.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 Nov 2021 03:50:01 -0800 (PST) Subject: Re: [PATCH v3 20/20] target/riscv: Enable uxl field write To: LIU Zhiwei , qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> <20211111055800.42672-21-zhiwei_liu@c-sky.com> From: Richard Henderson Message-ID: <663dcab0-3370-7716-2abb-187893de6103@linaro.org> Date: Thu, 11 Nov 2021 12:49:58 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20211111055800.42672-21-zhiwei_liu@c-sky.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::431 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -52 X-Spam_score: -5.3 X-Spam_bar: ----- X-Spam_report: (-5.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-3.999, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/11/21 6:58 AM, LIU Zhiwei wrote: > Signed-off-by: LIU Zhiwei > --- > target/riscv/csr.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 8f8f170768..43eaa6c710 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -553,15 +553,14 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, > * RV32: MPV and GVA are not in mstatus. The current plan is to > * add them to mstatush. For now, we just don't support it. > */ > - mask |= MSTATUS_MPV | MSTATUS_GVA; > + mask |= MSTATUS_MPV | MSTATUS_GVA | MSTATUS64_UXL; > } > > mstatus = (mstatus & ~mask) | (val & mask); > > if (riscv_cpu_mxl(env) == MXL_RV64) { > - /* SXL and UXL fields are for now read only */ > + /* SXL fields are for now read only */ > mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64); > - mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64); > } > env->mstatus = mstatus; Still missing the update for write_sstatus, which I think is simply an update to sstatus_v1_10_mask. r~