* [RFC PATCH v2 01/78] include/qemu/compiler.h: replace QEMU_FALLTHROUGH with fallthrough
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-17 22:00 ` Eric Blake
2023-10-18 10:32 ` Alex Bennée
2023-10-13 7:56 ` [RFC PATCH v2 02/78] block: add fallthrough pseudo-keyword Emmanouil Pitsidianakis
` (77 subsequent siblings)
78 siblings, 2 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Gerd Hoffmann, Marc-André Lureau,
Eric Auger, Peter Maydell, Song Gao, Xiaojuan Yang,
Richard Henderson, open list:ARM SMMU
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
audio/pwaudio.c | 8 ++++----
hw/arm/smmuv3.c | 2 +-
include/qemu/compiler.h | 30 +++++++++++++++++++++++-------
include/qemu/osdep.h | 4 ++--
target/loongarch/cpu.c | 4 ++--
target/loongarch/translate.c | 2 +-
tcg/optimize.c | 8 ++++----
7 files changed, 37 insertions(+), 21 deletions(-)
diff --git a/audio/pwaudio.c b/audio/pwaudio.c
index 3ce5f6507b..bf26fadb06 100644
--- a/audio/pwaudio.c
+++ b/audio/pwaudio.c
@@ -1,29 +1,29 @@
/*
* QEMU PipeWire audio driver
*
* Copyright (c) 2023 Red Hat Inc.
*
* Author: Dorinda Bassey <dbassey@redhat.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
+#include <spa/param/audio/format-utils.h>
+#include <spa/utils/ringbuffer.h>
+#include <spa/utils/result.h>
+#include <spa/param/props.h>
#include "qemu/osdep.h"
#include "qemu/module.h"
#include "audio.h"
#include <errno.h>
#include "qemu/error-report.h"
#include "qapi/error.h"
-#include <spa/param/audio/format-utils.h>
-#include <spa/utils/ringbuffer.h>
-#include <spa/utils/result.h>
-#include <spa/param/props.h>
#include <pipewire/pipewire.h>
#include "trace.h"
#define AUDIO_CAP "pipewire"
#define RINGBUFFER_SIZE (1u << 22)
#define RINGBUFFER_MASK (RINGBUFFER_SIZE - 1)
#include "audio_int.h"
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 6f2b2bd45f..545d82ff04 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -1166,210 +1166,210 @@ smmuv3_invalidate_ste(gpointer key, gpointer value, gpointer user_data)
static int smmuv3_cmdq_consume(SMMUv3State *s)
{
SMMUState *bs = ARM_SMMU(s);
SMMUCmdError cmd_error = SMMU_CERROR_NONE;
SMMUQueue *q = &s->cmdq;
SMMUCommandType type = 0;
if (!smmuv3_cmdq_enabled(s)) {
return 0;
}
/*
* some commands depend on register values, typically CR0. In case those
* register values change while handling the command, spec says it
* is UNPREDICTABLE whether the command is interpreted under the new
* or old value.
*/
while (!smmuv3_q_empty(q)) {
uint32_t pending = s->gerror ^ s->gerrorn;
Cmd cmd;
trace_smmuv3_cmdq_consume(Q_PROD(q), Q_CONS(q),
Q_PROD_WRAP(q), Q_CONS_WRAP(q));
if (FIELD_EX32(pending, GERROR, CMDQ_ERR)) {
break;
}
if (queue_read(q, &cmd) != MEMTX_OK) {
cmd_error = SMMU_CERROR_ABT;
break;
}
type = CMD_TYPE(&cmd);
trace_smmuv3_cmdq_opcode(smmu_cmd_string(type));
qemu_mutex_lock(&s->mutex);
switch (type) {
case SMMU_CMD_SYNC:
if (CMD_SYNC_CS(&cmd) & CMD_SYNC_SIG_IRQ) {
smmuv3_trigger_irq(s, SMMU_IRQ_CMD_SYNC, 0);
}
break;
case SMMU_CMD_PREFETCH_CONFIG:
case SMMU_CMD_PREFETCH_ADDR:
break;
case SMMU_CMD_CFGI_STE:
{
uint32_t sid = CMD_SID(&cmd);
IOMMUMemoryRegion *mr = smmu_iommu_mr(bs, sid);
SMMUDevice *sdev;
if (CMD_SSEC(&cmd)) {
cmd_error = SMMU_CERROR_ILL;
break;
}
if (!mr) {
break;
}
trace_smmuv3_cmdq_cfgi_ste(sid);
sdev = container_of(mr, SMMUDevice, iommu);
smmuv3_flush_config(sdev);
break;
}
case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */
{
uint32_t sid = CMD_SID(&cmd), mask;
uint8_t range = CMD_STE_RANGE(&cmd);
SMMUSIDRange sid_range;
if (CMD_SSEC(&cmd)) {
cmd_error = SMMU_CERROR_ILL;
break;
}
mask = (1ULL << (range + 1)) - 1;
sid_range.start = sid & ~mask;
sid_range.end = sid_range.start + mask;
trace_smmuv3_cmdq_cfgi_ste_range(sid_range.start, sid_range.end);
g_hash_table_foreach_remove(bs->configs, smmuv3_invalidate_ste,
&sid_range);
break;
}
case SMMU_CMD_CFGI_CD:
case SMMU_CMD_CFGI_CD_ALL:
{
uint32_t sid = CMD_SID(&cmd);
IOMMUMemoryRegion *mr = smmu_iommu_mr(bs, sid);
SMMUDevice *sdev;
if (CMD_SSEC(&cmd)) {
cmd_error = SMMU_CERROR_ILL;
break;
}
if (!mr) {
break;
}
trace_smmuv3_cmdq_cfgi_cd(sid);
sdev = container_of(mr, SMMUDevice, iommu);
smmuv3_flush_config(sdev);
break;
}
case SMMU_CMD_TLBI_NH_ASID:
{
uint16_t asid = CMD_ASID(&cmd);
if (!STAGE1_SUPPORTED(s)) {
cmd_error = SMMU_CERROR_ILL;
break;
}
trace_smmuv3_cmdq_tlbi_nh_asid(asid);
smmu_inv_notifiers_all(&s->smmu_state);
smmu_iotlb_inv_asid(bs, asid);
break;
}
case SMMU_CMD_TLBI_NH_ALL:
if (!STAGE1_SUPPORTED(s)) {
cmd_error = SMMU_CERROR_ILL;
break;
}
- QEMU_FALLTHROUGH;
+ fallthrough;
case SMMU_CMD_TLBI_NSNH_ALL:
trace_smmuv3_cmdq_tlbi_nh();
smmu_inv_notifiers_all(&s->smmu_state);
smmu_iotlb_inv_all(bs);
break;
case SMMU_CMD_TLBI_NH_VAA:
case SMMU_CMD_TLBI_NH_VA:
if (!STAGE1_SUPPORTED(s)) {
cmd_error = SMMU_CERROR_ILL;
break;
}
smmuv3_range_inval(bs, &cmd);
break;
case SMMU_CMD_TLBI_S12_VMALL:
{
uint16_t vmid = CMD_VMID(&cmd);
if (!STAGE2_SUPPORTED(s)) {
cmd_error = SMMU_CERROR_ILL;
break;
}
trace_smmuv3_cmdq_tlbi_s12_vmid(vmid);
smmu_inv_notifiers_all(&s->smmu_state);
smmu_iotlb_inv_vmid(bs, vmid);
break;
}
case SMMU_CMD_TLBI_S2_IPA:
if (!STAGE2_SUPPORTED(s)) {
cmd_error = SMMU_CERROR_ILL;
break;
}
/*
* As currently only either s1 or s2 are supported
* we can reuse same function for s2.
*/
smmuv3_range_inval(bs, &cmd);
break;
case SMMU_CMD_TLBI_EL3_ALL:
case SMMU_CMD_TLBI_EL3_VA:
case SMMU_CMD_TLBI_EL2_ALL:
case SMMU_CMD_TLBI_EL2_ASID:
case SMMU_CMD_TLBI_EL2_VA:
case SMMU_CMD_TLBI_EL2_VAA:
case SMMU_CMD_ATC_INV:
case SMMU_CMD_PRI_RESP:
case SMMU_CMD_RESUME:
case SMMU_CMD_STALL_TERM:
trace_smmuv3_unhandled_cmd(type);
break;
default:
cmd_error = SMMU_CERROR_ILL;
break;
}
qemu_mutex_unlock(&s->mutex);
if (cmd_error) {
if (cmd_error == SMMU_CERROR_ILL) {
qemu_log_mask(LOG_GUEST_ERROR,
"Illegal command type: %d\n", CMD_TYPE(&cmd));
}
break;
}
/*
* We only increment the cons index after the completion of
* the command. We do that because the SYNC returns immediately
* and does not check the completion of previous commands
*/
queue_cons_incr(q);
}
if (cmd_error) {
trace_smmuv3_cmdq_consume_error(smmu_cmd_string(type), cmd_error);
smmu_write_cmdq_err(s, cmd_error);
smmuv3_trigger_irq(s, SMMU_IRQ_GERROR, R_GERROR_CMDQ_ERR_MASK);
}
trace_smmuv3_cmdq_consume_out(Q_PROD(q), Q_CONS(q),
Q_PROD_WRAP(q), Q_CONS_WRAP(q));
return 0;
}
diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h
index 1109482a00..959982805d 100644
--- a/include/qemu/compiler.h
+++ b/include/qemu/compiler.h
@@ -1,215 +1,231 @@
/* compiler.h: macros to abstract away compiler specifics
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef COMPILER_H
#define COMPILER_H
#define HOST_BIG_ENDIAN (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)
/* HOST_LONG_BITS is the size of a native pointer in bits. */
#define HOST_LONG_BITS (__SIZEOF_POINTER__ * 8)
#if defined __clang_analyzer__ || defined __COVERITY__
#define QEMU_STATIC_ANALYSIS 1
#endif
#ifdef __cplusplus
#define QEMU_EXTERN_C extern "C"
#else
#define QEMU_EXTERN_C extern
#endif
#if defined(_WIN32) && (defined(__x86_64__) || defined(__i386__))
# define QEMU_PACKED __attribute__((gcc_struct, packed))
#else
# define QEMU_PACKED __attribute__((packed))
#endif
#define QEMU_ALIGNED(X) __attribute__((aligned(X)))
#ifndef glue
#define xglue(x, y) x ## y
#define glue(x, y) xglue(x, y)
#define stringify(s) tostring(s)
#define tostring(s) #s
#endif
/* Expands into an identifier stemN, where N is another number each time */
#define MAKE_IDENTFIER(stem) glue(stem, __COUNTER__)
#ifndef likely
#define likely(x) __builtin_expect(!!(x), 1)
#define unlikely(x) __builtin_expect(!!(x), 0)
#endif
#ifndef container_of
#define container_of(ptr, type, member) ({ \
const typeof(((type *) 0)->member) *__mptr = (ptr); \
(type *) ((char *) __mptr - offsetof(type, member));})
#endif
#define sizeof_field(type, field) sizeof(((type *)0)->field)
/*
* Calculate the number of bytes up to and including the given 'field' of
* 'container'.
*/
#define endof(container, field) \
(offsetof(container, field) + sizeof_field(container, field))
/* Convert from a base type to a parent type, with compile time checking. */
#define DO_UPCAST(type, field, dev) ( __extension__ ( { \
char __attribute__((unused)) offset_must_be_zero[ \
-offsetof(type, field)]; \
container_of(dev, type, field);}))
#define typeof_field(type, field) typeof(((type *)0)->field)
#define type_check(t1,t2) ((t1*)0 - (t2*)0)
#define QEMU_BUILD_BUG_ON_STRUCT(x) \
struct { \
int:(x) ? -1 : 1; \
}
#define QEMU_BUILD_BUG_MSG(x, msg) _Static_assert(!(x), msg)
#define QEMU_BUILD_BUG_ON(x) QEMU_BUILD_BUG_MSG(x, "not expecting: " #x)
#define QEMU_BUILD_BUG_ON_ZERO(x) (sizeof(QEMU_BUILD_BUG_ON_STRUCT(x)) - \
sizeof(QEMU_BUILD_BUG_ON_STRUCT(x)))
#if !defined(__clang__) && defined(_WIN32)
/*
* Map __printf__ to __gnu_printf__ because we want standard format strings even
* when MinGW or GLib include files use __printf__.
*/
# define __printf__ __gnu_printf__
#endif
#ifndef __has_warning
#define __has_warning(x) 0 /* compatibility with non-clang compilers */
#endif
#ifndef __has_feature
#define __has_feature(x) 0 /* compatibility with non-clang compilers */
#endif
#ifndef __has_builtin
#define __has_builtin(x) 0 /* compatibility with non-clang compilers */
#endif
#if __has_builtin(__builtin_assume_aligned) || !defined(__clang__)
#define HAS_ASSUME_ALIGNED
#endif
#ifndef __has_attribute
#define __has_attribute(x) 0 /* compatibility with older GCC */
#endif
#if defined(__SANITIZE_ADDRESS__) || __has_feature(address_sanitizer)
# define QEMU_SANITIZE_ADDRESS 1
#endif
#if defined(__SANITIZE_THREAD__) || __has_feature(thread_sanitizer)
# define QEMU_SANITIZE_THREAD 1
#endif
/*
* GCC doesn't provide __has_attribute() until GCC 5, but we know all the GCC
* versions we support have the "flatten" attribute. Clang may not have the
* "flatten" attribute but always has __has_attribute() to check for it.
*/
#if __has_attribute(flatten) || !defined(__clang__)
# define QEMU_FLATTEN __attribute__((flatten))
#else
# define QEMU_FLATTEN
#endif
/*
* If __attribute__((error)) is present, use it to produce an error at
* compile time. Otherwise, one must wait for the linker to diagnose
* the missing symbol.
*/
#if __has_attribute(error)
# define QEMU_ERROR(X) __attribute__((error(X)))
#else
# define QEMU_ERROR(X)
#endif
/*
* The nonstring variable attribute specifies that an object or member
* declaration with type array of char or pointer to char is intended
* to store character arrays that do not necessarily contain a terminating
* NUL character. This is useful in detecting uses of such arrays or pointers
* with functions that expect NUL-terminated strings, and to avoid warnings
* when such an array or pointer is used as an argument to a bounded string
* manipulation function such as strncpy.
*/
#if __has_attribute(nonstring)
# define QEMU_NONSTRING __attribute__((nonstring))
#else
# define QEMU_NONSTRING
#endif
/*
* Forced inlining may be desired to encourage constant propagation
* of function parameters. However, it can also make debugging harder,
* so disable it for a non-optimizing build.
*/
#if defined(__OPTIMIZE__)
#define QEMU_ALWAYS_INLINE __attribute__((always_inline))
#else
#define QEMU_ALWAYS_INLINE
#endif
-/**
- * In most cases, normal "fallthrough" comments are good enough for
- * switch-case statements, but sometimes the compiler has problems
- * with those. In that case you can use QEMU_FALLTHROUGH instead.
+/*
+ * Add the pseudo keyword 'fallthrough' so case statement blocks
+ * must end with any of these keywords:
+ * break;
+ * fallthrough;
+ * continue;
+ * goto <label>;
+ * return [expression];
+ *
+ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Statement-Attributes.html#Statement-Attributes
*/
-#if __has_attribute(fallthrough)
-# define QEMU_FALLTHROUGH __attribute__((fallthrough))
+
+/*
+ * glib_macros.h contains its own definition of fallthrough, so if we define
+ * the pseudokeyword here it will expand when the glib header checks for the
+ * attribute. glib headers must be #included after this header.
+ */
+#ifdef fallthrough
+#undef fallthrough
+#endif
+
+#if __has_attribute(__fallthrough__)
+# define fallthrough __attribute__((__fallthrough__))
#else
-# define QEMU_FALLTHROUGH do {} while (0) /* fallthrough */
+# define fallthrough do {} while (0) /* fallthrough */
#endif
#ifdef CONFIG_CFI
/*
* If CFI is enabled, use an attribute to disable cfi-icall on the following
* function
*/
#define QEMU_DISABLE_CFI __attribute__((no_sanitize("cfi-icall")))
#else
/* If CFI is not enabled, use an empty define to not change the behavior */
#define QEMU_DISABLE_CFI
#endif
/*
* Apple clang version 14 has a bug in its __builtin_subcll(); define
* BUILTIN_SUBCLL_BROKEN for the offending versions so we can avoid it.
* When a version of Apple clang which has this bug fixed is released
* we can add an upper bound to this check.
* See https://gitlab.com/qemu-project/qemu/-/issues/1631
* and https://gitlab.com/qemu-project/qemu/-/issues/1659 for details.
* The bug never made it into any upstream LLVM releases, only Apple ones.
*/
#if defined(__apple_build_version__) && __clang_major__ >= 14
#define BUILTIN_SUBCLL_BROKEN
#endif
#if __has_attribute(annotate)
#define QEMU_ANNOTATE(x) __attribute__((annotate(x)))
#else
#define QEMU_ANNOTATE(x)
#endif
#if __has_attribute(used)
# define QEMU_USED __attribute__((used))
#else
# define QEMU_USED
#endif
#endif /* COMPILER_H */
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
index 475a1c62ff..8f790f0deb 100644
--- a/include/qemu/osdep.h
+++ b/include/qemu/osdep.h
@@ -1,171 +1,171 @@
/*
* OS includes and handling of OS dependencies
*
* This header exists to pull in some common system headers that
* most code in QEMU will want, and to fix up some possible issues with
* it (missing defines, Windows weirdness, and so on).
*
* To avoid getting into possible circular include dependencies, this
* file should not include any other QEMU headers, with the exceptions
* of config-host.h, config-target.h, qemu/compiler.h,
* sysemu/os-posix.h, sysemu/os-win32.h, glib-compat.h and
* qemu/typedefs.h, all of which are doing a similar job to this file
* and are under similar constraints.
*
* This header also contains prototypes for functions defined in
* os-*.c and util/oslib-*.c; those would probably be better split
* out into separate header files.
*
* In an ideal world this header would contain only:
* (1) things which everybody needs
* (2) things without which code would work on most platforms but
* fail to compile or misbehave on a minority of host OSes
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef QEMU_OSDEP_H
#define QEMU_OSDEP_H
#if !defined _FORTIFY_SOURCE && defined __OPTIMIZE__ && __OPTIMIZE__ && defined __linux__
# define _FORTIFY_SOURCE 2
#endif
#include "config-host.h"
#ifdef NEED_CPU_H
#include CONFIG_TARGET
#else
#include "exec/poison.h"
#endif
/*
* HOST_WORDS_BIGENDIAN was replaced with HOST_BIG_ENDIAN. Prevent it from
* creeping back in.
*/
#pragma GCC poison HOST_WORDS_BIGENDIAN
/*
* TARGET_WORDS_BIGENDIAN was replaced with TARGET_BIG_ENDIAN. Prevent it from
* creeping back in.
*/
#pragma GCC poison TARGET_WORDS_BIGENDIAN
-#include "qemu/compiler.h"
-
/* Older versions of C++ don't get definitions of various macros from
* stdlib.h unless we define these macros before first inclusion of
* that system header.
*/
#ifndef __STDC_CONSTANT_MACROS
#define __STDC_CONSTANT_MACROS
#endif
#ifndef __STDC_LIMIT_MACROS
#define __STDC_LIMIT_MACROS
#endif
#ifndef __STDC_FORMAT_MACROS
#define __STDC_FORMAT_MACROS
#endif
/* The following block of code temporarily renames the daemon() function so the
* compiler does not see the warning associated with it in stdlib.h on OSX
*/
#ifdef __APPLE__
#define daemon qemu_fake_daemon_function
#include <stdlib.h>
#undef daemon
QEMU_EXTERN_C int daemon(int, int);
#endif
#ifdef _WIN32
/* as defined in sdkddkver.h */
#ifndef _WIN32_WINNT
#define _WIN32_WINNT 0x0602 /* Windows 8 API (should be >= the one from glib) */
#endif
/* reduces the number of implicitly included headers */
#ifndef WIN32_LEAN_AND_MEAN
#define WIN32_LEAN_AND_MEAN
#endif
#endif
/* enable C99/POSIX format strings (needs mingw32-runtime 3.15 or later) */
#ifdef __MINGW32__
#define __USE_MINGW_ANSI_STDIO 1
#endif
/*
* We need the FreeBSD "legacy" definitions. Rust needs the FreeBSD 11 system
* calls since it doesn't use libc at all, so we have to emulate that despite
* FreeBSD 11 being EOL'd.
*/
#ifdef __FreeBSD__
#define _WANT_FREEBSD11_STAT
#define _WANT_FREEBSD11_STATFS
#define _WANT_FREEBSD11_DIRENT
#define _WANT_KERNEL_ERRNO
#define _WANT_SEMUN
#endif
#include <stdarg.h>
#include <stddef.h>
#include <stdbool.h>
#include <stdint.h>
#include <sys/types.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <strings.h>
#include <inttypes.h>
#include <limits.h>
/* Put unistd.h before time.h as that triggers localtime_r/gmtime_r
* function availability on recentish Mingw-w64 platforms. */
#include <unistd.h>
#include <time.h>
#include <ctype.h>
#include <errno.h>
#include <fcntl.h>
#include <getopt.h>
#include <sys/stat.h>
#include <sys/time.h>
#include <assert.h>
/* setjmp must be declared before sysemu/os-win32.h
* because it is redefined there. */
#include <setjmp.h>
#include <signal.h>
#ifdef CONFIG_IOVEC
#include <sys/uio.h>
#endif
#if defined(__linux__) && defined(__sparc__)
/* The SPARC definition of QEMU_VMALLOC_ALIGN needs SHMLBA */
#include <sys/shm.h>
#endif
#ifndef _WIN32
#include <sys/wait.h>
#else
#define WIFEXITED(x) 1
#define WEXITSTATUS(x) (x)
#endif
#ifdef __APPLE__
#include <AvailabilityMacros.h>
#endif
/*
* This is somewhat like a system header; it must be outside any extern "C"
* block because it includes system headers itself, including glib.h,
* which will not compile if inside an extern "C" block.
*/
#include "glib-compat.h"
+#include "qemu/compiler.h"
+
#ifdef _WIN32
#include "sysemu/os-win32.h"
#endif
#ifdef CONFIG_POSIX
#include "sysemu/os-posix.h"
#endif
#ifdef __cplusplus
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 2bea7ca5d5..e01d626b15 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -142,145 +142,145 @@ static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env)
static void loongarch_cpu_do_interrupt(CPUState *cs)
{
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
CPULoongArchState *env = &cpu->env;
bool update_badinstr = 1;
int cause = -1;
const char *name;
bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR);
uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS);
if (cs->exception_index != EXCCODE_INT) {
if (cs->exception_index < 0 ||
cs->exception_index >= ARRAY_SIZE(excp_names)) {
name = "unknown";
} else {
name = excp_names[cs->exception_index];
}
qemu_log_mask(CPU_LOG_INT,
"%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx
" TLBRERA " TARGET_FMT_lx " %s exception\n", __func__,
env->pc, env->CSR_ERA, env->CSR_TLBRERA, name);
}
switch (cs->exception_index) {
case EXCCODE_DBP:
env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1);
env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC);
goto set_DERA;
set_DERA:
env->CSR_DERA = env->pc;
env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1);
set_pc(env, env->CSR_EENTRY + 0x480);
break;
case EXCCODE_INT:
if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1);
goto set_DERA;
}
- QEMU_FALLTHROUGH;
+ fallthrough;
case EXCCODE_PIF:
case EXCCODE_ADEF:
cause = cs->exception_index;
update_badinstr = 0;
break;
case EXCCODE_SYS:
case EXCCODE_BRK:
case EXCCODE_INE:
case EXCCODE_IPE:
case EXCCODE_FPD:
case EXCCODE_FPE:
case EXCCODE_SXD:
case EXCCODE_ASXD:
env->CSR_BADV = env->pc;
- QEMU_FALLTHROUGH;
+ fallthrough;
case EXCCODE_BCE:
case EXCCODE_ADEM:
case EXCCODE_PIL:
case EXCCODE_PIS:
case EXCCODE_PME:
case EXCCODE_PNR:
case EXCCODE_PNX:
case EXCCODE_PPI:
cause = cs->exception_index;
break;
default:
qemu_log("Error: exception(%d) has not been supported\n",
cs->exception_index);
abort();
}
if (update_badinstr) {
env->CSR_BADI = cpu_ldl_code(env, env->pc);
}
/* Save PLV and IE */
if (tlbfill) {
env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV,
FIELD_EX64(env->CSR_CRMD,
CSR_CRMD, PLV));
env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE,
FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE));
/* set the DA mode */
env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1);
env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0);
env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA,
PC, (env->pc >> 2));
} else {
env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE,
EXCODE_MCODE(cause));
env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE,
EXCODE_SUBCODE(cause));
env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV,
FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE,
FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE));
env->CSR_ERA = env->pc;
}
env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
if (vec_size) {
vec_size = (1 << vec_size) * 4;
}
if (cs->exception_index == EXCCODE_INT) {
/* Interrupt */
uint32_t vector = 0;
uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS);
pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE);
/* Find the highest-priority interrupt. */
vector = 31 - clz32(pending);
set_pc(env, env->CSR_EENTRY + \
(EXCCODE_EXTERNAL_INT + vector) * vec_size);
qemu_log_mask(CPU_LOG_INT,
"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
" cause %d\n" " A " TARGET_FMT_lx " D "
TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS"
TARGET_FMT_lx "\n",
__func__, env->pc, env->CSR_ERA,
cause, env->CSR_BADV, env->CSR_DERA, vector,
env->CSR_ECFG, env->CSR_ESTAT);
} else {
if (tlbfill) {
set_pc(env, env->CSR_TLBRENTRY);
} else {
set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size);
}
qemu_log_mask(CPU_LOG_INT,
"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
" cause %d%s\n, ESTAT " TARGET_FMT_lx
" EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx
"BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu
" cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc,
tlbfill ? env->CSR_TLBRERA : env->CSR_ERA,
cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT,
env->CSR_ECFG,
tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV,
env->CSR_BADI, env->gpr[11], cs->cpu_index,
env->CSR_ASID);
}
cs->exception_index = -1;
}
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 21f4db6fbd..36fceb1beb 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -304,24 +304,24 @@ static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
static void loongarch_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
switch (ctx->base.is_jmp) {
case DISAS_STOP:
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
tcg_gen_lookup_and_goto_ptr();
break;
case DISAS_TOO_MANY:
gen_goto_tb(ctx, 0, ctx->base.pc_next);
break;
case DISAS_NORETURN:
break;
case DISAS_EXIT_UPDATE:
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
- QEMU_FALLTHROUGH;
+ fallthrough;
case DISAS_EXIT:
tcg_gen_exit_tb(NULL, 0);
break;
default:
g_assert_not_reached();
}
}
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 3013eb04e6..3da135a353 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1062,81 +1062,81 @@ static bool fold_brcond(OptContext *ctx, TCGOp *op)
static bool fold_brcond2(OptContext *ctx, TCGOp *op)
{
TCGCond cond = op->args[4];
TCGArg label = op->args[5];
int i, inv = 0;
if (swap_commutative2(&op->args[0], &op->args[2])) {
op->args[4] = cond = tcg_swap_cond(cond);
}
i = do_constant_folding_cond2(&op->args[0], &op->args[2], cond);
if (i >= 0) {
goto do_brcond_const;
}
switch (cond) {
case TCG_COND_LT:
case TCG_COND_GE:
/*
* Simplify LT/GE comparisons vs zero to a single compare
* vs the high word of the input.
*/
if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val == 0 &&
arg_is_const(op->args[3]) && arg_info(op->args[3])->val == 0) {
goto do_brcond_high;
}
break;
case TCG_COND_NE:
inv = 1;
- QEMU_FALLTHROUGH;
+ fallthrough;
case TCG_COND_EQ:
/*
* Simplify EQ/NE comparisons where one of the pairs
* can be simplified.
*/
i = do_constant_folding_cond(TCG_TYPE_I32, op->args[0],
op->args[2], cond);
switch (i ^ inv) {
case 0:
goto do_brcond_const;
case 1:
goto do_brcond_high;
}
i = do_constant_folding_cond(TCG_TYPE_I32, op->args[1],
op->args[3], cond);
switch (i ^ inv) {
case 0:
goto do_brcond_const;
case 1:
op->opc = INDEX_op_brcond_i32;
op->args[1] = op->args[2];
op->args[2] = cond;
op->args[3] = label;
break;
}
break;
default:
break;
do_brcond_high:
op->opc = INDEX_op_brcond_i32;
op->args[0] = op->args[1];
op->args[1] = op->args[3];
op->args[2] = cond;
op->args[3] = label;
break;
do_brcond_const:
if (i == 0) {
tcg_op_remove(ctx->tcg, op);
return true;
}
op->opc = INDEX_op_br;
op->args[0] = label;
break;
}
return false;
}
@@ -1424,46 +1424,46 @@ static bool fold_extract2(OptContext *ctx, TCGOp *op)
static bool fold_exts(OptContext *ctx, TCGOp *op)
{
uint64_t s_mask_old, s_mask, z_mask, sign;
bool type_change = false;
if (fold_const1(ctx, op)) {
return true;
}
z_mask = arg_info(op->args[1])->z_mask;
s_mask = arg_info(op->args[1])->s_mask;
s_mask_old = s_mask;
switch (op->opc) {
CASE_OP_32_64(ext8s):
sign = INT8_MIN;
z_mask = (uint8_t)z_mask;
break;
CASE_OP_32_64(ext16s):
sign = INT16_MIN;
z_mask = (uint16_t)z_mask;
break;
case INDEX_op_ext_i32_i64:
type_change = true;
- QEMU_FALLTHROUGH;
+ fallthrough;
case INDEX_op_ext32s_i64:
sign = INT32_MIN;
z_mask = (uint32_t)z_mask;
break;
default:
g_assert_not_reached();
}
if (z_mask & sign) {
z_mask |= sign;
}
s_mask |= sign << 1;
ctx->z_mask = z_mask;
ctx->s_mask = s_mask;
if (!type_change) {
ctx->a_mask = s_mask & ~s_mask_old;
}
return fold_masks(ctx, op);
}
@@ -1471,40 +1471,40 @@ static bool fold_exts(OptContext *ctx, TCGOp *op)
static bool fold_extu(OptContext *ctx, TCGOp *op)
{
uint64_t z_mask_old, z_mask;
bool type_change = false;
if (fold_const1(ctx, op)) {
return true;
}
z_mask_old = z_mask = arg_info(op->args[1])->z_mask;
switch (op->opc) {
CASE_OP_32_64(ext8u):
z_mask = (uint8_t)z_mask;
break;
CASE_OP_32_64(ext16u):
z_mask = (uint16_t)z_mask;
break;
case INDEX_op_extrl_i64_i32:
case INDEX_op_extu_i32_i64:
type_change = true;
- QEMU_FALLTHROUGH;
+ fallthrough;
case INDEX_op_ext32u_i64:
z_mask = (uint32_t)z_mask;
break;
case INDEX_op_extrh_i64_i32:
type_change = true;
z_mask >>= 32;
break;
default:
g_assert_not_reached();
}
ctx->z_mask = z_mask;
ctx->s_mask = smask_from_zmask(z_mask);
if (!type_change) {
ctx->a_mask = z_mask_old ^ z_mask;
}
return fold_masks(ctx, op);
}
@@ -1835,75 +1835,75 @@ static bool fold_negsetcond(OptContext *ctx, TCGOp *op)
static bool fold_setcond2(OptContext *ctx, TCGOp *op)
{
TCGCond cond = op->args[5];
int i, inv = 0;
if (swap_commutative2(&op->args[1], &op->args[3])) {
op->args[5] = cond = tcg_swap_cond(cond);
}
i = do_constant_folding_cond2(&op->args[1], &op->args[3], cond);
if (i >= 0) {
goto do_setcond_const;
}
switch (cond) {
case TCG_COND_LT:
case TCG_COND_GE:
/*
* Simplify LT/GE comparisons vs zero to a single compare
* vs the high word of the input.
*/
if (arg_is_const(op->args[3]) && arg_info(op->args[3])->val == 0 &&
arg_is_const(op->args[4]) && arg_info(op->args[4])->val == 0) {
goto do_setcond_high;
}
break;
case TCG_COND_NE:
inv = 1;
- QEMU_FALLTHROUGH;
+ fallthrough;
case TCG_COND_EQ:
/*
* Simplify EQ/NE comparisons where one of the pairs
* can be simplified.
*/
i = do_constant_folding_cond(TCG_TYPE_I32, op->args[1],
op->args[3], cond);
switch (i ^ inv) {
case 0:
goto do_setcond_const;
case 1:
goto do_setcond_high;
}
i = do_constant_folding_cond(TCG_TYPE_I32, op->args[2],
op->args[4], cond);
switch (i ^ inv) {
case 0:
goto do_setcond_const;
case 1:
op->args[2] = op->args[3];
op->args[3] = cond;
op->opc = INDEX_op_setcond_i32;
break;
}
break;
default:
break;
do_setcond_high:
op->args[1] = op->args[2];
op->args[2] = op->args[4];
op->args[3] = cond;
op->opc = INDEX_op_setcond_i32;
break;
}
ctx->z_mask = 1;
ctx->s_mask = smask_from_zmask(1);
return false;
do_setcond_const:
return tcg_opt_gen_movi(ctx, op, op->args[0], i);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* Re: [RFC PATCH v2 01/78] include/qemu/compiler.h: replace QEMU_FALLTHROUGH with fallthrough
2023-10-13 7:56 ` [RFC PATCH v2 01/78] include/qemu/compiler.h: replace QEMU_FALLTHROUGH with fallthrough Emmanouil Pitsidianakis
@ 2023-10-17 22:00 ` Eric Blake
2023-10-18 10:32 ` Alex Bennée
1 sibling, 0 replies; 91+ messages in thread
From: Eric Blake @ 2023-10-17 22:00 UTC (permalink / raw)
To: Emmanouil Pitsidianakis
Cc: qemu-devel, Gerd Hoffmann, Marc-André Lureau, Eric Auger,
Peter Maydell, Song Gao, Xiaojuan Yang, Richard Henderson,
open list:ARM SMMU
On Fri, Oct 13, 2023 at 10:56:28AM +0300, Emmanouil Pitsidianakis wrote:
> Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
The subject line gives the 'what', but the commit body is
conspicuously lacking on the 'why'.
> ---
> audio/pwaudio.c | 8 ++++----
> hw/arm/smmuv3.c | 2 +-
> include/qemu/compiler.h | 30 +++++++++++++++++++++++-------
> include/qemu/osdep.h | 4 ++--
> target/loongarch/cpu.c | 4 ++--
> target/loongarch/translate.c | 2 +-
> tcg/optimize.c | 8 ++++----
> 7 files changed, 37 insertions(+), 21 deletions(-)
>
> diff --git a/audio/pwaudio.c b/audio/pwaudio.c
> index 3ce5f6507b..bf26fadb06 100644
> --- a/audio/pwaudio.c
> +++ b/audio/pwaudio.c
> @@ -1,29 +1,29 @@
> /*
> * QEMU PipeWire audio driver
> *
> * Copyright (c) 2023 Red Hat Inc.
> *
> * Author: Dorinda Bassey <dbassey@redhat.com>
> *
> * SPDX-License-Identifier: GPL-2.0-or-later
> */
>
> +#include <spa/param/audio/format-utils.h>
> +#include <spa/utils/ringbuffer.h>
> +#include <spa/utils/result.h>
> +#include <spa/param/props.h>
> #include "qemu/osdep.h"
> #include "qemu/module.h"
> #include "audio.h"
> #include <errno.h>
> #include "qemu/error-report.h"
> #include "qapi/error.h"
> -#include <spa/param/audio/format-utils.h>
> -#include <spa/utils/ringbuffer.h>
> -#include <spa/utils/result.h>
> -#include <spa/param/props.h>
Rearranging #includes should be called out in the commit message, or
even better split into its own commit as it is distinct from renaming
the fallthrough macro.
>
> #include <pipewire/pipewire.h>
> #include "trace.h"
>
> #define AUDIO_CAP "pipewire"
> #define RINGBUFFER_SIZE (1u << 22)
> #define RINGBUFFER_MASK (RINGBUFFER_SIZE - 1)
>
> #include "audio_int.h"
> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
> index 6f2b2bd45f..545d82ff04 100644
> --- a/hw/arm/smmuv3.c
> +++ b/hw/arm/smmuv3.c
> @@ -1166,210 +1166,210 @@ smmuv3_invalidate_ste(gpointer key, gpointer value, gpointer user_data)
Wow, your git settings picked up a LOT of context - makes for a longer
email, but in this particular case, it IS nice to see the impact of
the fallthrough by seeing the full switch statment.
...
> qemu_mutex_lock(&s->mutex);
> switch (type) {
> case SMMU_CMD_SYNC:
...
> case SMMU_CMD_TLBI_NH_ALL:
> if (!STAGE1_SUPPORTED(s)) {
> cmd_error = SMMU_CERROR_ILL;
> break;
> }
> - QEMU_FALLTHROUGH;
> + fallthrough;
> case SMMU_CMD_TLBI_NSNH_ALL:
Yes, that still looks legible to me.
> +++ b/include/qemu/compiler.h
> @@ -1,215 +1,231 @@
...
> #if defined(__OPTIMIZE__)
> #define QEMU_ALWAYS_INLINE __attribute__((always_inline))
> #else
> #define QEMU_ALWAYS_INLINE
> #endif
>
> -/**
> - * In most cases, normal "fallthrough" comments are good enough for
> - * switch-case statements, but sometimes the compiler has problems
> - * with those. In that case you can use QEMU_FALLTHROUGH instead.
> +/*
> + * Add the pseudo keyword 'fallthrough' so case statement blocks
> + * must end with any of these keywords:
> + * break;
> + * fallthrough;
> + * continue;
> + * goto <label>;
> + * return [expression];
> + *
> + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Statement-Attributes.html#Statement-Attributes
> */
> -#if __has_attribute(fallthrough)
> -# define QEMU_FALLTHROUGH __attribute__((fallthrough))
> +
> +/*
> + * glib_macros.h contains its own definition of fallthrough, so if we define
> + * the pseudokeyword here it will expand when the glib header checks for the
> + * attribute. glib headers must be #included after this header.
> + */
> +#ifdef fallthrough
> +#undef fallthrough
> +#endif
> +
> +#if __has_attribute(__fallthrough__)
> +# define fallthrough __attribute__((__fallthrough__))
> #else
> -# define QEMU_FALLTHROUGH do {} while (0) /* fallthrough */
> +# define fallthrough do {} while (0) /* fallthrough */
> #endif
>
Looks okay.
> +++ b/include/qemu/osdep.h
> @@ -1,171 +1,171 @@
> /*
> * TARGET_WORDS_BIGENDIAN was replaced with TARGET_BIG_ENDIAN. Prevent it from
> * creeping back in.
> */
> #pragma GCC poison TARGET_WORDS_BIGENDIAN
>
> -#include "qemu/compiler.h"
> -
> /* Older versions of C++ don't get definitions of various macros from
> * stdlib.h unless we define these macros before first inclusion of
> * that system header.
> */
...
> /*
> * This is somewhat like a system header; it must be outside any extern "C"
> * block because it includes system headers itself, including glib.h,
> * which will not compile if inside an extern "C" block.
> */
> #include "glib-compat.h"
>
> +#include "qemu/compiler.h"
> +
The commit message should detail why we had to sink this include
later, and any audit you did to ensure that none of the intermediate
code is impacted by that change.
At this point, since the series is RFC, I'll leave merely:
Acked-by: Eric Blake <eblake@redhat.com>
but if others like the approach, I'll probably replace it with R-b in
the next version.
--
Eric Blake, Principal Software Engineer
Red Hat, Inc.
Virtualization: qemu.org | libguestfs.org
^ permalink raw reply [flat|nested] 91+ messages in thread* Re: [RFC PATCH v2 01/78] include/qemu/compiler.h: replace QEMU_FALLTHROUGH with fallthrough
2023-10-13 7:56 ` [RFC PATCH v2 01/78] include/qemu/compiler.h: replace QEMU_FALLTHROUGH with fallthrough Emmanouil Pitsidianakis
2023-10-17 22:00 ` Eric Blake
@ 2023-10-18 10:32 ` Alex Bennée
[not found] ` <2q0zq.6gn2tubfhjrk@linaro.org>
1 sibling, 1 reply; 91+ messages in thread
From: Alex Bennée @ 2023-10-18 10:32 UTC (permalink / raw)
To: Emmanouil Pitsidianakis
Cc: Gerd Hoffmann, Marc-André Lureau, Eric Auger, Peter Maydell,
Song Gao, Xiaojuan Yang, Richard Henderson, open list:ARM SMMU,
qemu-devel
Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org> writes:
> Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
> ---
> audio/pwaudio.c | 8 ++++----
> hw/arm/smmuv3.c | 2 +-
> include/qemu/compiler.h | 30 +++++++++++++++++++++++-------
> include/qemu/osdep.h | 4 ++--
> target/loongarch/cpu.c | 4 ++--
> target/loongarch/translate.c | 2 +-
> tcg/optimize.c | 8 ++++----
> 7 files changed, 37 insertions(+), 21 deletions(-)
>
> diff --git a/audio/pwaudio.c b/audio/pwaudio.c
> index 3ce5f6507b..bf26fadb06 100644
> --- a/audio/pwaudio.c
> +++ b/audio/pwaudio.c
> @@ -1,29 +1,29 @@
> /*
> * QEMU PipeWire audio driver
> *
> * Copyright (c) 2023 Red Hat Inc.
> *
> * Author: Dorinda Bassey <dbassey@redhat.com>
> *
> * SPDX-License-Identifier: GPL-2.0-or-later
> */
>
> +#include <spa/param/audio/format-utils.h>
> +#include <spa/utils/ringbuffer.h>
> +#include <spa/utils/result.h>
> +#include <spa/param/props.h>
> #include "qemu/osdep.h"
> #include "qemu/module.h"
> #include "audio.h"
> #include <errno.h>
> #include "qemu/error-report.h"
> #include "qapi/error.h"
> -#include <spa/param/audio/format-utils.h>
> -#include <spa/utils/ringbuffer.h>
> -#include <spa/utils/result.h>
> -#include <spa/param/props.h>
Was this an autofmt change sneaking in? osdep.h should always be first
per style.rst.
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 91+ messages in thread
* [RFC PATCH v2 02/78] block: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 01/78] include/qemu/compiler.h: replace QEMU_FALLTHROUGH with fallthrough Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-17 22:11 ` Eric Blake
2023-10-13 7:56 ` [RFC PATCH v2 03/78] fpu/softfloat: " Emmanouil Pitsidianakis
` (76 subsequent siblings)
78 siblings, 1 reply; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, John Snow, Vladimir Sementsov-Ogievskiy,
Kevin Wolf, Hanna Reitz, Stefan Hajnoczi, Fam Zheng,
Ronnie Sahlberg, Paolo Bonzini, Peter Lieven, Jeff Cody,
open list:Block Jobs
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
block/block-copy.c | 1 +
block/file-posix.c | 1 +
block/io.c | 1 +
block/iscsi.c | 1 +
block/qcow2-cluster.c | 5 ++++-
block/vhdx.c | 17 +++++++++++++----
6 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/block/block-copy.c b/block/block-copy.c
index 1c60368d72..b4ceb6a079 100644
--- a/block/block-copy.c
+++ b/block/block-copy.c
@@ -473,78 +473,79 @@ static int coroutine_fn GRAPH_RDLOCK
block_copy_do_copy(BlockCopyState *s, int64_t offset, int64_t bytes,
BlockCopyMethod *method, bool *error_is_read)
{
int ret;
int64_t nbytes = MIN(offset + bytes, s->len) - offset;
void *bounce_buffer = NULL;
assert(offset >= 0 && bytes > 0 && INT64_MAX - offset >= bytes);
assert(QEMU_IS_ALIGNED(offset, s->cluster_size));
assert(QEMU_IS_ALIGNED(bytes, s->cluster_size));
assert(offset < s->len);
assert(offset + bytes <= s->len ||
offset + bytes == QEMU_ALIGN_UP(s->len, s->cluster_size));
assert(nbytes < INT_MAX);
switch (*method) {
case COPY_WRITE_ZEROES:
ret = bdrv_co_pwrite_zeroes(s->target, offset, nbytes, s->write_flags &
~BDRV_REQ_WRITE_COMPRESSED);
if (ret < 0) {
trace_block_copy_write_zeroes_fail(s, offset, ret);
*error_is_read = false;
}
return ret;
case COPY_RANGE_SMALL:
case COPY_RANGE_FULL:
ret = bdrv_co_copy_range(s->source, offset, s->target, offset, nbytes,
0, s->write_flags);
if (ret >= 0) {
/* Successful copy-range, increase chunk size. */
*method = COPY_RANGE_FULL;
return 0;
}
trace_block_copy_copy_range_fail(s, offset, ret);
*method = COPY_READ_WRITE;
/* Fall through to read+write with allocated buffer */
+ fallthrough;
case COPY_READ_WRITE_CLUSTER:
case COPY_READ_WRITE:
/*
* In case of failed copy_range request above, we may proceed with
* buffered request larger than BLOCK_COPY_MAX_BUFFER.
* Still, further requests will be properly limited, so don't care too
* much. Moreover the most likely case (copy_range is unsupported for
* the configuration, so the very first copy_range request fails)
* is handled by setting large copy_size only after first successful
* copy_range.
*/
bounce_buffer = qemu_blockalign(s->source->bs, nbytes);
ret = bdrv_co_pread(s->source, offset, nbytes, bounce_buffer, 0);
if (ret < 0) {
trace_block_copy_read_fail(s, offset, ret);
*error_is_read = true;
goto out;
}
ret = bdrv_co_pwrite(s->target, offset, nbytes, bounce_buffer,
s->write_flags);
if (ret < 0) {
trace_block_copy_write_fail(s, offset, ret);
*error_is_read = false;
goto out;
}
out:
qemu_vfree(bounce_buffer);
break;
default:
abort();
}
return ret;
}
diff --git a/block/file-posix.c b/block/file-posix.c
index 50e2b20d5c..31c7719da5 100644
--- a/block/file-posix.c
+++ b/block/file-posix.c
@@ -972,69 +972,70 @@ static int raw_check_lock_bytes(int fd, uint64_t perm, uint64_t shared_perm,
static int raw_handle_perm_lock(BlockDriverState *bs,
RawPermLockOp op,
uint64_t new_perm, uint64_t new_shared,
Error **errp)
{
BDRVRawState *s = bs->opaque;
int ret = 0;
Error *local_err = NULL;
if (!s->use_lock) {
return 0;
}
if (bdrv_get_flags(bs) & BDRV_O_INACTIVE) {
return 0;
}
switch (op) {
case RAW_PL_PREPARE:
if ((s->perm | new_perm) == s->perm &&
(s->shared_perm & new_shared) == s->shared_perm)
{
/*
* We are going to unlock bytes, it should not fail. If it fail due
* to some fs-dependent permission-unrelated reasons (which occurs
* sometimes on NFS and leads to abort in bdrv_replace_child) we
* can't prevent such errors by any check here. And we ignore them
* anyway in ABORT and COMMIT.
*/
return 0;
}
ret = raw_apply_lock_bytes(s, s->fd, s->perm | new_perm,
~s->shared_perm | ~new_shared,
false, errp);
if (!ret) {
ret = raw_check_lock_bytes(s->fd, new_perm, new_shared, errp);
if (!ret) {
return 0;
}
error_append_hint(errp,
"Is another process using the image [%s]?\n",
bs->filename);
}
/* fall through to unlock bytes. */
+ fallthrough;
case RAW_PL_ABORT:
raw_apply_lock_bytes(s, s->fd, s->perm, ~s->shared_perm,
true, &local_err);
if (local_err) {
/* Theoretically the above call only unlocks bytes and it cannot
* fail. Something weird happened, report it.
*/
warn_report_err(local_err);
}
break;
case RAW_PL_COMMIT:
raw_apply_lock_bytes(s, s->fd, new_perm, ~new_shared,
true, &local_err);
if (local_err) {
/* Theoretically the above call only unlocks bytes and it cannot
* fail. Something weird happened, report it.
*/
warn_report_err(local_err);
}
break;
}
return ret;
}
/* Sets a specific flag */
diff --git a/block/io.c b/block/io.c
index e7f9448d5a..cc05457d02 100644
--- a/block/io.c
+++ b/block/io.c
@@ -2007,43 +2007,44 @@ static inline void coroutine_fn
bdrv_co_write_req_finish(BdrvChild *child, int64_t offset, int64_t bytes,
BdrvTrackedRequest *req, int ret)
{
int64_t end_sector = DIV_ROUND_UP(offset + bytes, BDRV_SECTOR_SIZE);
BlockDriverState *bs = child->bs;
bdrv_check_request(offset, bytes, &error_abort);
qatomic_inc(&bs->write_gen);
/*
* Discard cannot extend the image, but in error handling cases, such as
* when reverting a qcow2 cluster allocation, the discarded range can pass
* the end of image file, so we cannot assert about BDRV_TRACKED_DISCARD
* here. Instead, just skip it, since semantically a discard request
* beyond EOF cannot expand the image anyway.
*/
if (ret == 0 &&
(req->type == BDRV_TRACKED_TRUNCATE ||
end_sector > bs->total_sectors) &&
req->type != BDRV_TRACKED_DISCARD) {
bs->total_sectors = end_sector;
bdrv_parent_cb_resize(bs);
bdrv_dirty_bitmap_truncate(bs, end_sector << BDRV_SECTOR_BITS);
}
if (req->bytes) {
switch (req->type) {
case BDRV_TRACKED_WRITE:
stat64_max(&bs->wr_highest_offset, offset + bytes);
/* fall through, to set dirty bits */
+ fallthrough;
case BDRV_TRACKED_DISCARD:
bdrv_set_dirty(bs, offset, bytes);
break;
default:
break;
}
}
}
/*
* Forwards an already correctly aligned write request to the BlockDriver,
* after possibly fragmenting it.
*/
diff --git a/block/iscsi.c b/block/iscsi.c
index 5640c8b565..2fb7037748 100644
--- a/block/iscsi.c
+++ b/block/iscsi.c
@@ -1430,69 +1430,70 @@ static void iscsi_nop_timed_event(void *opaque)
static void iscsi_readcapacity_sync(IscsiLun *iscsilun, Error **errp)
{
struct scsi_task *task = NULL;
struct scsi_readcapacity10 *rc10 = NULL;
struct scsi_readcapacity16 *rc16 = NULL;
int retries = ISCSI_CMD_RETRIES;
do {
if (task != NULL) {
scsi_free_scsi_task(task);
task = NULL;
}
switch (iscsilun->type) {
case TYPE_DISK:
task = iscsi_readcapacity16_sync(iscsilun->iscsi, iscsilun->lun);
if (task != NULL && task->status == SCSI_STATUS_GOOD) {
rc16 = scsi_datain_unmarshall(task);
if (rc16 == NULL) {
error_setg(errp, "iSCSI: Failed to unmarshall readcapacity16 data.");
} else {
iscsilun->block_size = rc16->block_length;
iscsilun->num_blocks = rc16->returned_lba + 1;
iscsilun->lbpme = !!rc16->lbpme;
iscsilun->lbprz = !!rc16->lbprz;
iscsilun->use_16_for_rw = (rc16->returned_lba > 0xffffffff);
}
break;
}
if (task != NULL && task->status == SCSI_STATUS_CHECK_CONDITION
&& task->sense.key == SCSI_SENSE_UNIT_ATTENTION) {
break;
}
/* Fall through and try READ CAPACITY(10) instead. */
+ fallthrough;
case TYPE_ROM:
task = iscsi_readcapacity10_sync(iscsilun->iscsi, iscsilun->lun, 0, 0);
if (task != NULL && task->status == SCSI_STATUS_GOOD) {
rc10 = scsi_datain_unmarshall(task);
if (rc10 == NULL) {
error_setg(errp, "iSCSI: Failed to unmarshall readcapacity10 data.");
} else {
iscsilun->block_size = rc10->block_size;
if (rc10->lba == 0) {
/* blank disk loaded */
iscsilun->num_blocks = 0;
} else {
iscsilun->num_blocks = rc10->lba + 1;
}
}
}
break;
default:
return;
}
} while (task != NULL && task->status == SCSI_STATUS_CHECK_CONDITION
&& task->sense.key == SCSI_SENSE_UNIT_ATTENTION
&& retries-- > 0);
if (task == NULL || task->status != SCSI_STATUS_GOOD) {
error_setg(errp, "iSCSI: failed to send readcapacity10/16 command");
} else if (!iscsilun->block_size ||
iscsilun->block_size % BDRV_SECTOR_SIZE) {
error_setg(errp, "iSCSI: the target returned an invalid "
"block size of %d.", iscsilun->block_size);
}
if (task) {
scsi_free_scsi_task(task);
}
}
diff --git a/block/qcow2-cluster.c b/block/qcow2-cluster.c
index f4f6cd6ad0..c50143d493 100644
--- a/block/qcow2-cluster.c
+++ b/block/qcow2-cluster.c
@@ -1327,36 +1327,39 @@ static int coroutine_fn calculate_l2_meta(BlockDriverState *bs,
/*
* Returns true if writing to the cluster pointed to by @l2_entry
* requires a new allocation (that is, if the cluster is unallocated
* or has refcount > 1 and therefore cannot be written in-place).
*/
static bool cluster_needs_new_alloc(BlockDriverState *bs, uint64_t l2_entry)
{
switch (qcow2_get_cluster_type(bs, l2_entry)) {
case QCOW2_CLUSTER_NORMAL:
+ fallthrough;
case QCOW2_CLUSTER_ZERO_ALLOC:
if (l2_entry & QCOW_OFLAG_COPIED) {
return false;
}
- /* fallthrough */
+ fallthrough;
case QCOW2_CLUSTER_UNALLOCATED:
+ fallthrough;
case QCOW2_CLUSTER_COMPRESSED:
+ fallthrough;
case QCOW2_CLUSTER_ZERO_PLAIN:
return true;
default:
abort();
}
}
/*
* Returns the number of contiguous clusters that can be written to
* using one single write request, starting from @l2_index.
* At most @nb_clusters are checked.
*
* If @new_alloc is true this counts clusters that are either
* unallocated, or allocated but with refcount > 1 (so they need to be
* newly allocated and COWed).
*
* If @new_alloc is false this counts clusters that are already
* allocated and can be overwritten in-place (this includes clusters
* of type QCOW2_CLUSTER_ZERO_ALLOC).
*/
diff --git a/block/vhdx.c b/block/vhdx.c
index a67edcc03e..9000b3fcea 100644
--- a/block/vhdx.c
+++ b/block/vhdx.c
@@ -1176,60 +1176,65 @@ static int coroutine_fn GRAPH_RDLOCK
vhdx_co_readv(BlockDriverState *bs, int64_t sector_num, int nb_sectors,
QEMUIOVector *qiov)
{
BDRVVHDXState *s = bs->opaque;
int ret = 0;
VHDXSectorInfo sinfo;
uint64_t bytes_done = 0;
QEMUIOVector hd_qiov;
qemu_iovec_init(&hd_qiov, qiov->niov);
qemu_co_mutex_lock(&s->lock);
while (nb_sectors > 0) {
/* We are a differencing file, so we need to inspect the sector bitmap
* to see if we have the data or not */
if (s->params.data_bits & VHDX_PARAMS_HAS_PARENT) {
/* not supported yet */
ret = -ENOTSUP;
goto exit;
} else {
vhdx_block_translate(s, sector_num, nb_sectors, &sinfo);
qemu_iovec_reset(&hd_qiov);
qemu_iovec_concat(&hd_qiov, qiov, bytes_done, sinfo.bytes_avail);
/* check the payload block state */
switch (s->bat[sinfo.bat_idx] & VHDX_BAT_STATE_BIT_MASK) {
- case PAYLOAD_BLOCK_NOT_PRESENT: /* fall through */
+ case PAYLOAD_BLOCK_NOT_PRESENT:
+ fallthrough;
case PAYLOAD_BLOCK_UNDEFINED:
+ fallthrough;
case PAYLOAD_BLOCK_UNMAPPED:
+ fallthrough;
case PAYLOAD_BLOCK_UNMAPPED_v095:
+ fallthrough;
case PAYLOAD_BLOCK_ZERO:
/* return zero */
qemu_iovec_memset(&hd_qiov, 0, 0, sinfo.bytes_avail);
break;
case PAYLOAD_BLOCK_FULLY_PRESENT:
qemu_co_mutex_unlock(&s->lock);
ret = bdrv_co_preadv(bs->file, sinfo.file_offset,
sinfo.sectors_avail * BDRV_SECTOR_SIZE,
&hd_qiov, 0);
qemu_co_mutex_lock(&s->lock);
if (ret < 0) {
goto exit;
}
break;
case PAYLOAD_BLOCK_PARTIALLY_PRESENT:
/* we don't yet support difference files, fall through
* to error */
+ fallthrough;
default:
ret = -EIO;
goto exit;
break;
}
nb_sectors -= sinfo.sectors_avail;
sector_num += sinfo.sectors_avail;
bytes_done += sinfo.bytes_avail;
}
}
ret = 0;
@@ -1330,155 +1335,159 @@ static int coroutine_fn GRAPH_RDLOCK
vhdx_co_writev(BlockDriverState *bs, int64_t sector_num, int nb_sectors,
QEMUIOVector *qiov, int flags)
{
int ret = -ENOTSUP;
BDRVVHDXState *s = bs->opaque;
VHDXSectorInfo sinfo;
uint64_t bytes_done = 0;
uint64_t bat_entry = 0;
uint64_t bat_entry_offset = 0;
QEMUIOVector hd_qiov;
struct iovec iov1 = { 0 };
struct iovec iov2 = { 0 };
int sectors_to_write;
int bat_state;
uint64_t bat_prior_offset = 0;
bool bat_update = false;
qemu_iovec_init(&hd_qiov, qiov->niov);
qemu_co_mutex_lock(&s->lock);
ret = vhdx_user_visible_write(bs, s);
if (ret < 0) {
goto exit;
}
while (nb_sectors > 0) {
bool use_zero_buffers = false;
bat_update = false;
if (s->params.data_bits & VHDX_PARAMS_HAS_PARENT) {
/* not supported yet */
ret = -ENOTSUP;
goto exit;
} else {
vhdx_block_translate(s, sector_num, nb_sectors, &sinfo);
sectors_to_write = sinfo.sectors_avail;
qemu_iovec_reset(&hd_qiov);
/* check the payload block state */
bat_state = s->bat[sinfo.bat_idx] & VHDX_BAT_STATE_BIT_MASK;
switch (bat_state) {
case PAYLOAD_BLOCK_ZERO:
/* in this case, we need to preserve zero writes for
* data that is not part of this write, so we must pad
* the rest of the buffer to zeroes */
use_zero_buffers = true;
- /* fall through */
- case PAYLOAD_BLOCK_NOT_PRESENT: /* fall through */
+ fallthrough;
+ case PAYLOAD_BLOCK_NOT_PRESENT:
+ fallthrough;
case PAYLOAD_BLOCK_UNMAPPED:
+ fallthrough;
case PAYLOAD_BLOCK_UNMAPPED_v095:
+ fallthrough;
case PAYLOAD_BLOCK_UNDEFINED:
bat_prior_offset = sinfo.file_offset;
ret = vhdx_allocate_block(bs, s, &sinfo.file_offset,
&use_zero_buffers);
if (ret < 0) {
goto exit;
}
/*
* once we support differencing files, this may also be
* partially present
*/
/* update block state to the newly specified state */
vhdx_update_bat_table_entry(bs, s, &sinfo, &bat_entry,
&bat_entry_offset,
PAYLOAD_BLOCK_FULLY_PRESENT);
bat_update = true;
/*
* Since we just allocated a block, file_offset is the
* beginning of the payload block. It needs to be the
* write address, which includes the offset into the
* block, unless the entire block needs to read as
* zeroes but truncation was not able to provide them,
* in which case we need to fill in the rest.
*/
if (!use_zero_buffers) {
sinfo.file_offset += sinfo.block_offset;
} else {
/* zero fill the front, if any */
if (sinfo.block_offset) {
iov1.iov_len = sinfo.block_offset;
iov1.iov_base = qemu_blockalign(bs, iov1.iov_len);
memset(iov1.iov_base, 0, iov1.iov_len);
qemu_iovec_concat_iov(&hd_qiov, &iov1, 1, 0,
iov1.iov_len);
sectors_to_write += iov1.iov_len >> BDRV_SECTOR_BITS;
}
/* our actual data */
qemu_iovec_concat(&hd_qiov, qiov, bytes_done,
sinfo.bytes_avail);
/* zero fill the back, if any */
if ((sinfo.bytes_avail - sinfo.block_offset) <
s->block_size) {
iov2.iov_len = s->block_size -
(sinfo.bytes_avail + sinfo.block_offset);
iov2.iov_base = qemu_blockalign(bs, iov2.iov_len);
memset(iov2.iov_base, 0, iov2.iov_len);
qemu_iovec_concat_iov(&hd_qiov, &iov2, 1, 0,
iov2.iov_len);
sectors_to_write += iov2.iov_len >> BDRV_SECTOR_BITS;
}
}
- /* fall through */
+ fallthrough;
case PAYLOAD_BLOCK_FULLY_PRESENT:
/* if the file offset address is in the header zone,
* there is a problem */
if (sinfo.file_offset < (1 * MiB)) {
ret = -EFAULT;
goto error_bat_restore;
}
if (!use_zero_buffers) {
qemu_iovec_concat(&hd_qiov, qiov, bytes_done,
sinfo.bytes_avail);
}
/* block exists, so we can just overwrite it */
qemu_co_mutex_unlock(&s->lock);
ret = bdrv_co_pwritev(bs->file, sinfo.file_offset,
sectors_to_write * BDRV_SECTOR_SIZE,
&hd_qiov, 0);
qemu_co_mutex_lock(&s->lock);
if (ret < 0) {
goto error_bat_restore;
}
break;
case PAYLOAD_BLOCK_PARTIALLY_PRESENT:
/* we don't yet support difference files, fall through
* to error */
+ fallthrough;
default:
ret = -EIO;
goto exit;
break;
}
if (bat_update) {
/* this will update the BAT entry into the log journal, and
* then flush the log journal out to disk */
ret = vhdx_log_write_and_flush(bs, s, &bat_entry,
sizeof(VHDXBatEntry),
bat_entry_offset);
if (ret < 0) {
goto exit;
}
}
nb_sectors -= sinfo.sectors_avail;
sector_num += sinfo.sectors_avail;
bytes_done += sinfo.bytes_avail;
}
}
goto exit;
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* Re: [RFC PATCH v2 02/78] block: add fallthrough pseudo-keyword
2023-10-13 7:56 ` [RFC PATCH v2 02/78] block: add fallthrough pseudo-keyword Emmanouil Pitsidianakis
@ 2023-10-17 22:11 ` Eric Blake
2023-10-18 5:50 ` Manos Pitsidianakis
0 siblings, 1 reply; 91+ messages in thread
From: Eric Blake @ 2023-10-17 22:11 UTC (permalink / raw)
To: Emmanouil Pitsidianakis
Cc: qemu-devel, John Snow, Vladimir Sementsov-Ogievskiy, Kevin Wolf,
Hanna Reitz, Stefan Hajnoczi, Fam Zheng, Ronnie Sahlberg,
Paolo Bonzini, Peter Lieven, Jeff Cody, open list:Block Jobs
On Fri, Oct 13, 2023 at 10:56:29AM +0300, Emmanouil Pitsidianakis wrote:
> In preparation of raising -Wimplicit-fallthrough to 5, replace all
> fall-through comments with the fallthrough attribute pseudo-keyword.
>
> Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
> ---
> block/block-copy.c | 1 +
> block/file-posix.c | 1 +
> block/io.c | 1 +
> block/iscsi.c | 1 +
> block/qcow2-cluster.c | 5 ++++-
> block/vhdx.c | 17 +++++++++++++----
> 6 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/block/block-copy.c b/block/block-copy.c
> index 1c60368d72..b4ceb6a079 100644
> --- a/block/block-copy.c
> +++ b/block/block-copy.c
...
> case COPY_RANGE_FULL:
> ret = bdrv_co_copy_range(s->source, offset, s->target, offset, nbytes,
> 0, s->write_flags);
> if (ret >= 0) {
> /* Successful copy-range, increase chunk size. */
> *method = COPY_RANGE_FULL;
> return 0;
> }
>
> trace_block_copy_copy_range_fail(s, offset, ret);
> *method = COPY_READ_WRITE;
> /* Fall through to read+write with allocated buffer */
> + fallthrough;
>
> case COPY_READ_WRITE_CLUSTER:
> case COPY_READ_WRITE:
I like how you kept the comments.
> +++ b/block/qcow2-cluster.c
> @@ -1327,36 +1327,39 @@ static int coroutine_fn calculate_l2_meta(BlockDriverState *bs,
> /*
> * Returns true if writing to the cluster pointed to by @l2_entry
> * requires a new allocation (that is, if the cluster is unallocated
> * or has refcount > 1 and therefore cannot be written in-place).
> */
> static bool cluster_needs_new_alloc(BlockDriverState *bs, uint64_t l2_entry)
> {
> switch (qcow2_get_cluster_type(bs, l2_entry)) {
> case QCOW2_CLUSTER_NORMAL:
> + fallthrough;
> case QCOW2_CLUSTER_ZERO_ALLOC:
Why is this one needed? It looks two case labels for the same code is
okay; the fallthrough attribute is only needed once a case label is no
lonter empty.
> if (l2_entry & QCOW_OFLAG_COPIED) {
> return false;
> }
> - /* fallthrough */
> + fallthrough;
This one makes sense.
> case QCOW2_CLUSTER_UNALLOCATED:
> + fallthrough;
> case QCOW2_CLUSTER_COMPRESSED:
> + fallthrough;
These two also look spurious.
> case QCOW2_CLUSTER_ZERO_PLAIN:
> return true;
> default:
> abort();
> }
> }
...
> +++ b/block/vhdx.c
> @@ -1176,60 +1176,65 @@ static int coroutine_fn GRAPH_RDLOCK
> vhdx_co_readv(BlockDriverState *bs, int64_t sector_num, int nb_sectors,
> QEMUIOVector *qiov)
...
> /* check the payload block state */
> switch (s->bat[sinfo.bat_idx] & VHDX_BAT_STATE_BIT_MASK) {
> - case PAYLOAD_BLOCK_NOT_PRESENT: /* fall through */
> + case PAYLOAD_BLOCK_NOT_PRESENT:
> + fallthrough;
> case PAYLOAD_BLOCK_UNDEFINED:
> + fallthrough;
> case PAYLOAD_BLOCK_UNMAPPED:
> + fallthrough;
> case PAYLOAD_BLOCK_UNMAPPED_v095:
> + fallthrough;
All four of these look spurious; although the old comment is also
spurious, so I'd be happy with deleting it without replacement.
> case PAYLOAD_BLOCK_ZERO:
> /* return zero */
> qemu_iovec_memset(&hd_qiov, 0, 0, sinfo.bytes_avail);
> break;
> case PAYLOAD_BLOCK_FULLY_PRESENT:
> qemu_co_mutex_unlock(&s->lock);
> ret = bdrv_co_preadv(bs->file, sinfo.file_offset,
> sinfo.sectors_avail * BDRV_SECTOR_SIZE,
> &hd_qiov, 0);
> qemu_co_mutex_lock(&s->lock);
> if (ret < 0) {
> goto exit;
> }
> break;
> case PAYLOAD_BLOCK_PARTIALLY_PRESENT:
> /* we don't yet support difference files, fall through
> * to error */
> + fallthrough;
> default:
But keeping this one because of the comment is reasonable.
...
> switch (bat_state) {
> case PAYLOAD_BLOCK_ZERO:
> /* in this case, we need to preserve zero writes for
> * data that is not part of this write, so we must pad
> * the rest of the buffer to zeroes */
> use_zero_buffers = true;
> - /* fall through */
> - case PAYLOAD_BLOCK_NOT_PRESENT: /* fall through */
> + fallthrough;
> + case PAYLOAD_BLOCK_NOT_PRESENT:
This one is necessary;
> + fallthrough;
> case PAYLOAD_BLOCK_UNMAPPED:
> + fallthrough;
> case PAYLOAD_BLOCK_UNMAPPED_v095:
> + fallthrough;
> case PAYLOAD_BLOCK_UNDEFINED:
but these three seem spurious.
I like the direction this is headed in, but there's enough I pointed
out that I'll withhold R-b on this version.
--
Eric Blake, Principal Software Engineer
Red Hat, Inc.
Virtualization: qemu.org | libguestfs.org
^ permalink raw reply [flat|nested] 91+ messages in thread* Re: [RFC PATCH v2 02/78] block: add fallthrough pseudo-keyword
2023-10-17 22:11 ` Eric Blake
@ 2023-10-18 5:50 ` Manos Pitsidianakis
0 siblings, 0 replies; 91+ messages in thread
From: Manos Pitsidianakis @ 2023-10-18 5:50 UTC (permalink / raw)
To: Eric Blake
Cc: qemu-devel, John Snow, Vladimir Sementsov-Ogievskiy, Kevin Wolf,
Hanna Reitz, Stefan Hajnoczi, Fam Zheng, Ronnie Sahlberg,
Paolo Bonzini, Peter Lieven, Jeff Cody, Block Jobs
On Wed, 18 Oct 2023 01:11, Eric Blake <eblake@redhat.com> wrote:
>> static bool cluster_needs_new_alloc(BlockDriverState *bs, uint64_t
>> l2_entry)
>> {
>> switch (qcow2_get_cluster_type(bs, l2_entry)) {
>> case QCOW2_CLUSTER_NORMAL:
>> + fallthrough;
>> case QCOW2_CLUSTER_ZERO_ALLOC:
>
>Why is this one needed? It looks two case labels for the same code is
>okay; the fallthrough attribute is only needed once a case label is no
>lonter empty.
> ...
>These two also look spurious.
>
> ...
>but these three seem spurious.
Thanks for pointing it out, Eric. Indeed these are mistakes.
By the way, there's a newer version posted [0] because as you noticed I
accidentally left --function-context on git-format-patch and didn't
notice that some of them blew up in size.
Also, the consensus in v1 was to reject this patch series in general
[1].
[0]: <cover.1697186560.git.manos.pitsidianakis@linaro.org>
https://lore.kernel.org/qemu-devel/cover.1697186560.git.manos.pitsidianakis@linaro.org/
[1]:
<CAFEAcA_fLBe9CuWFYpeuejj8dcerhFtPNX+iVaVFvH4SXx1oAg@mail.gmail.com>
https://lore.kernel.org/qemu-devel/CAFEAcA_fLBe9CuWFYpeuejj8dcerhFtPNX+iVaVFvH4SXx1oAg@mail.gmail.com/
--
Manos
^ permalink raw reply [flat|nested] 91+ messages in thread
* [RFC PATCH v2 03/78] fpu/softfloat: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 01/78] include/qemu/compiler.h: replace QEMU_FALLTHROUGH with fallthrough Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 02/78] block: add fallthrough pseudo-keyword Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 04/78] qapi/opts-visitor: " Emmanouil Pitsidianakis
` (75 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Aurelien Jarno, Peter Maydell,
Alex Bennée
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
fpu/softfloat-parts.c.inc | 8 ++++----
fpu/softfloat.c | 7 ++++---
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
index a44649f4f4..df64cc7a29 100644
--- a/fpu/softfloat-parts.c.inc
+++ b/fpu/softfloat-parts.c.inc
@@ -138,166 +138,166 @@ static void partsN(canonicalize)(FloatPartsN *p, float_status *status,
/*
* Round and uncanonicalize a floating-point number by parts. There
* are FRAC_SHIFT bits that may require rounding at the bottom of the
* fraction; these bits will be removed. The exponent will be biased
* by EXP_BIAS and must be bounded by [EXP_MAX-1, 0].
*/
static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s,
const FloatFmt *fmt)
{
const int exp_max = fmt->exp_max;
const int frac_shift = fmt->frac_shift;
const uint64_t round_mask = fmt->round_mask;
const uint64_t frac_lsb = round_mask + 1;
const uint64_t frac_lsbm1 = round_mask ^ (round_mask >> 1);
const uint64_t roundeven_mask = round_mask | frac_lsb;
uint64_t inc;
bool overflow_norm = false;
int exp, flags = 0;
switch (s->float_rounding_mode) {
case float_round_nearest_even:
if (N > 64 && frac_lsb == 0) {
inc = ((p->frac_hi & 1) || (p->frac_lo & round_mask) != frac_lsbm1
? frac_lsbm1 : 0);
} else {
inc = ((p->frac_lo & roundeven_mask) != frac_lsbm1
? frac_lsbm1 : 0);
}
break;
case float_round_ties_away:
inc = frac_lsbm1;
break;
case float_round_to_zero:
overflow_norm = true;
inc = 0;
break;
case float_round_up:
inc = p->sign ? 0 : round_mask;
overflow_norm = p->sign;
break;
case float_round_down:
inc = p->sign ? round_mask : 0;
overflow_norm = !p->sign;
break;
case float_round_to_odd:
overflow_norm = true;
- /* fall through */
+ fallthrough;
case float_round_to_odd_inf:
if (N > 64 && frac_lsb == 0) {
inc = p->frac_hi & 1 ? 0 : round_mask;
} else {
inc = p->frac_lo & frac_lsb ? 0 : round_mask;
}
break;
default:
g_assert_not_reached();
}
exp = p->exp + fmt->exp_bias;
if (likely(exp > 0)) {
if (p->frac_lo & round_mask) {
flags |= float_flag_inexact;
if (frac_addi(p, p, inc)) {
frac_shr(p, 1);
p->frac_hi |= DECOMPOSED_IMPLICIT_BIT;
exp++;
}
p->frac_lo &= ~round_mask;
}
if (fmt->arm_althp) {
/* ARM Alt HP eschews Inf and NaN for a wider exponent. */
if (unlikely(exp > exp_max)) {
/* Overflow. Return the maximum normal. */
flags = float_flag_invalid;
exp = exp_max;
frac_allones(p);
p->frac_lo &= ~round_mask;
}
} else if (unlikely(exp >= exp_max)) {
flags |= float_flag_overflow;
if (s->rebias_overflow) {
exp -= fmt->exp_re_bias;
} else if (overflow_norm) {
flags |= float_flag_inexact;
exp = exp_max - 1;
frac_allones(p);
p->frac_lo &= ~round_mask;
} else {
flags |= float_flag_inexact;
p->cls = float_class_inf;
exp = exp_max;
frac_clear(p);
}
}
frac_shr(p, frac_shift);
} else if (unlikely(s->rebias_underflow)) {
flags |= float_flag_underflow;
exp += fmt->exp_re_bias;
if (p->frac_lo & round_mask) {
flags |= float_flag_inexact;
if (frac_addi(p, p, inc)) {
frac_shr(p, 1);
p->frac_hi |= DECOMPOSED_IMPLICIT_BIT;
exp++;
}
p->frac_lo &= ~round_mask;
}
frac_shr(p, frac_shift);
} else if (s->flush_to_zero) {
flags |= float_flag_output_denormal;
p->cls = float_class_zero;
exp = 0;
frac_clear(p);
} else {
bool is_tiny = s->tininess_before_rounding || exp < 0;
if (!is_tiny) {
FloatPartsN discard;
is_tiny = !frac_addi(&discard, p, inc);
}
frac_shrjam(p, !fmt->m68k_denormal - exp);
if (p->frac_lo & round_mask) {
/* Need to recompute round-to-even/round-to-odd. */
switch (s->float_rounding_mode) {
case float_round_nearest_even:
if (N > 64 && frac_lsb == 0) {
inc = ((p->frac_hi & 1) ||
(p->frac_lo & round_mask) != frac_lsbm1
? frac_lsbm1 : 0);
} else {
inc = ((p->frac_lo & roundeven_mask) != frac_lsbm1
? frac_lsbm1 : 0);
}
break;
case float_round_to_odd:
case float_round_to_odd_inf:
if (N > 64 && frac_lsb == 0) {
inc = p->frac_hi & 1 ? 0 : round_mask;
} else {
inc = p->frac_lo & frac_lsb ? 0 : round_mask;
}
break;
default:
break;
}
flags |= float_flag_inexact;
frac_addi(p, p, inc);
p->frac_lo &= ~round_mask;
}
exp = (p->frac_hi & DECOMPOSED_IMPLICIT_BIT) && !fmt->m68k_denormal;
frac_shr(p, frac_shift);
if (is_tiny && (flags & float_flag_inexact)) {
flags |= float_flag_underflow;
}
if (exp == 0 && frac_eqz(p)) {
p->cls = float_class_zero;
}
}
p->exp = exp;
float_raise(flags, s);
}
@@ -1051,219 +1051,219 @@ static void partsN(round_to_int)(FloatPartsN *a, FloatRoundMode rmode,
/*
* Returns the result of converting the floating-point value `a' to
* the two's complement integer format. The conversion is performed
* according to the IEC/IEEE Standard for Binary Floating-Point
* Arithmetic---which means in particular that the conversion is
* rounded according to the current rounding mode. If `a' is a NaN,
* the largest positive integer is returned. Otherwise, if the
* conversion overflows, the largest integer with the same sign as `a'
* is returned.
*/
static int64_t partsN(float_to_sint)(FloatPartsN *p, FloatRoundMode rmode,
int scale, int64_t min, int64_t max,
float_status *s)
{
int flags = 0;
uint64_t r;
switch (p->cls) {
case float_class_snan:
flags |= float_flag_invalid_snan;
- /* fall through */
+ fallthrough;
case float_class_qnan:
flags |= float_flag_invalid;
r = max;
break;
case float_class_inf:
flags = float_flag_invalid | float_flag_invalid_cvti;
r = p->sign ? min : max;
break;
case float_class_zero:
return 0;
case float_class_normal:
/* TODO: N - 2 is frac_size for rounding; could use input fmt. */
if (parts_round_to_int_normal(p, rmode, scale, N - 2)) {
flags = float_flag_inexact;
}
if (p->exp <= DECOMPOSED_BINARY_POINT) {
r = p->frac_hi >> (DECOMPOSED_BINARY_POINT - p->exp);
} else {
r = UINT64_MAX;
}
if (p->sign) {
if (r <= -(uint64_t)min) {
r = -r;
} else {
flags = float_flag_invalid | float_flag_invalid_cvti;
r = min;
}
} else if (r > max) {
flags = float_flag_invalid | float_flag_invalid_cvti;
r = max;
}
break;
default:
g_assert_not_reached();
}
float_raise(flags, s);
return r;
}
/*
* Returns the result of converting the floating-point value `a' to
* the unsigned integer format. The conversion is performed according
* to the IEC/IEEE Standard for Binary Floating-Point
* Arithmetic---which means in particular that the conversion is
* rounded according to the current rounding mode. If `a' is a NaN,
* the largest unsigned integer is returned. Otherwise, if the
* conversion overflows, the largest unsigned integer is returned. If
* the 'a' is negative, the result is rounded and zero is returned;
* values that do not round to zero will raise the inexact exception
* flag.
*/
static uint64_t partsN(float_to_uint)(FloatPartsN *p, FloatRoundMode rmode,
int scale, uint64_t max, float_status *s)
{
int flags = 0;
uint64_t r;
switch (p->cls) {
case float_class_snan:
flags |= float_flag_invalid_snan;
- /* fall through */
+ fallthrough;
case float_class_qnan:
flags |= float_flag_invalid;
r = max;
break;
case float_class_inf:
flags = float_flag_invalid | float_flag_invalid_cvti;
r = p->sign ? 0 : max;
break;
case float_class_zero:
return 0;
case float_class_normal:
/* TODO: N - 2 is frac_size for rounding; could use input fmt. */
if (parts_round_to_int_normal(p, rmode, scale, N - 2)) {
flags = float_flag_inexact;
if (p->cls == float_class_zero) {
r = 0;
break;
}
}
if (p->sign) {
flags = float_flag_invalid | float_flag_invalid_cvti;
r = 0;
} else if (p->exp > DECOMPOSED_BINARY_POINT) {
flags = float_flag_invalid | float_flag_invalid_cvti;
r = max;
} else {
r = p->frac_hi >> (DECOMPOSED_BINARY_POINT - p->exp);
if (r > max) {
flags = float_flag_invalid | float_flag_invalid_cvti;
r = max;
}
}
break;
default:
g_assert_not_reached();
}
float_raise(flags, s);
return r;
}
/*
* Like partsN(float_to_sint), except do not saturate the result.
* Instead, return the rounded unbounded precision two's compliment result,
* modulo 2**(bitsm1 + 1).
*/
static int64_t partsN(float_to_sint_modulo)(FloatPartsN *p,
FloatRoundMode rmode,
int bitsm1, float_status *s)
{
int flags = 0;
uint64_t r;
bool overflow = false;
switch (p->cls) {
case float_class_snan:
flags |= float_flag_invalid_snan;
- /* fall through */
+ fallthrough;
case float_class_qnan:
flags |= float_flag_invalid;
r = 0;
break;
case float_class_inf:
overflow = true;
r = 0;
break;
case float_class_zero:
return 0;
case float_class_normal:
/* TODO: N - 2 is frac_size for rounding; could use input fmt. */
if (parts_round_to_int_normal(p, rmode, 0, N - 2)) {
flags = float_flag_inexact;
}
if (p->exp <= DECOMPOSED_BINARY_POINT) {
/*
* Because we rounded to integral, and exp < 64,
* we know frac_low is zero.
*/
r = p->frac_hi >> (DECOMPOSED_BINARY_POINT - p->exp);
if (p->exp < bitsm1) {
/* Result in range. */
} else if (p->exp == bitsm1) {
/* The only in-range value is INT_MIN. */
overflow = !p->sign || p->frac_hi != DECOMPOSED_IMPLICIT_BIT;
} else {
overflow = true;
}
} else {
/* Overflow, but there might still be bits to return. */
int shl = p->exp - DECOMPOSED_BINARY_POINT;
if (shl < N) {
frac_shl(p, shl);
r = p->frac_hi;
} else {
r = 0;
}
overflow = true;
}
if (p->sign) {
r = -r;
}
break;
default:
g_assert_not_reached();
}
if (overflow) {
flags = float_flag_invalid | float_flag_invalid_cvti;
}
float_raise(flags, s);
return r;
}
/*
* Integer to float conversions
*
* Returns the result of converting the two's complement integer `a'
* to the floating-point format. The conversion is performed according
* to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
*/
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 027a8e576d..e16e1896ee 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -1811,56 +1811,57 @@ static bool floatx80_unpack_canonical(FloatParts128 *p, floatx80 f,
static floatx80 floatx80_round_pack_canonical(FloatParts128 *p,
float_status *s)
{
const FloatFmt *fmt = &floatx80_params[s->floatx80_rounding_precision];
uint64_t frac;
int exp;
switch (p->cls) {
case float_class_normal:
if (s->floatx80_rounding_precision == floatx80_precision_x) {
parts_uncanon_normal(p, s, fmt);
frac = p->frac_hi;
exp = p->exp;
} else {
FloatParts64 p64;
p64.sign = p->sign;
p64.exp = p->exp;
frac_truncjam(&p64, p);
parts_uncanon_normal(&p64, s, fmt);
frac = p64.frac;
exp = p64.exp;
}
if (exp != fmt->exp_max) {
break;
}
/* rounded to inf -- fall through to set frac correctly */
+ fallthrough;
case float_class_inf:
/* x86 and m68k differ in the setting of the integer bit. */
frac = floatx80_infinity_low;
exp = fmt->exp_max;
break;
case float_class_zero:
frac = 0;
exp = 0;
break;
case float_class_snan:
case float_class_qnan:
/* NaNs have the integer bit set. */
frac = p->frac_hi | (1ull << 63);
exp = fmt->exp_max;
break;
default:
g_assert_not_reached();
}
return packFloatx80(p->sign, exp, frac);
}
/*
* Addition and subtraction
*/
@@ -2668,35 +2669,35 @@ floatx80 floatx80_mod(floatx80 a, floatx80 b, float_status *status)
static void parts_float_to_ahp(FloatParts64 *a, float_status *s)
{
switch (a->cls) {
case float_class_snan:
float_raise(float_flag_invalid_snan, s);
- /* fall through */
+ fallthrough;
case float_class_qnan:
/*
* There is no NaN in the destination format. Raise Invalid
* and return a zero with the sign of the input NaN.
*/
float_raise(float_flag_invalid, s);
a->cls = float_class_zero;
break;
case float_class_inf:
/*
* There is no Inf in the destination format. Raise Invalid
* and return the maximum normal with the correct sign.
*/
float_raise(float_flag_invalid, s);
a->cls = float_class_normal;
a->exp = float16_params_ahp.exp_max;
a->frac = MAKE_64BIT_MASK(float16_params_ahp.frac_shift,
float16_params_ahp.frac_size + 1);
break;
case float_class_normal:
case float_class_zero:
break;
default:
g_assert_not_reached();
}
}
@@ -3190,53 +3191,53 @@ static int64_t float128_to_int64_scalbn(float128 a, FloatRoundMode rmode,
static Int128 float128_to_int128_scalbn(float128 a, FloatRoundMode rmode,
int scale, float_status *s)
{
int flags = 0;
Int128 r;
FloatParts128 p;
float128_unpack_canonical(&p, a, s);
switch (p.cls) {
case float_class_snan:
flags |= float_flag_invalid_snan;
- /* fall through */
+ fallthrough;
case float_class_qnan:
flags |= float_flag_invalid;
r = UINT128_MAX;
break;
case float_class_inf:
flags = float_flag_invalid | float_flag_invalid_cvti;
r = p.sign ? INT128_MIN : INT128_MAX;
break;
case float_class_zero:
return int128_zero();
case float_class_normal:
if (parts_round_to_int_normal(&p, rmode, scale, 128 - 2)) {
flags = float_flag_inexact;
}
if (p.exp < 127) {
int shift = 127 - p.exp;
r = int128_urshift(int128_make128(p.frac_lo, p.frac_hi), shift);
if (p.sign) {
r = int128_neg(r);
}
} else if (p.exp == 127 && p.sign && p.frac_lo == 0 &&
p.frac_hi == DECOMPOSED_IMPLICIT_BIT) {
r = INT128_MIN;
} else {
flags = float_flag_invalid | float_flag_invalid_cvti;
r = p.sign ? INT128_MIN : INT128_MAX;
}
break;
default:
g_assert_not_reached();
}
float_raise(flags, s);
return r;
}
@@ -3617,54 +3618,54 @@ static uint64_t float128_to_uint64_scalbn(float128 a, FloatRoundMode rmode,
static Int128 float128_to_uint128_scalbn(float128 a, FloatRoundMode rmode,
int scale, float_status *s)
{
int flags = 0;
Int128 r;
FloatParts128 p;
float128_unpack_canonical(&p, a, s);
switch (p.cls) {
case float_class_snan:
flags |= float_flag_invalid_snan;
- /* fall through */
+ fallthrough;
case float_class_qnan:
flags |= float_flag_invalid;
r = UINT128_MAX;
break;
case float_class_inf:
flags = float_flag_invalid | float_flag_invalid_cvti;
r = p.sign ? int128_zero() : UINT128_MAX;
break;
case float_class_zero:
return int128_zero();
case float_class_normal:
if (parts_round_to_int_normal(&p, rmode, scale, 128 - 2)) {
flags = float_flag_inexact;
if (p.cls == float_class_zero) {
r = int128_zero();
break;
}
}
if (p.sign) {
flags = float_flag_invalid | float_flag_invalid_cvti;
r = int128_zero();
} else if (p.exp <= 127) {
int shift = 127 - p.exp;
r = int128_urshift(int128_make128(p.frac_lo, p.frac_hi), shift);
} else {
flags = float_flag_invalid | float_flag_invalid_cvti;
r = UINT128_MAX;
}
break;
default:
g_assert_not_reached();
}
float_raise(flags, s);
return r;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 04/78] qapi/opts-visitor: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (2 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 03/78] fpu/softfloat: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-17 22:11 ` Eric Blake
2023-10-13 7:56 ` [RFC PATCH v2 05/78] qobject/json: " Emmanouil Pitsidianakis
` (74 subsequent siblings)
78 siblings, 1 reply; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Markus Armbruster, Michael Roth
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
qapi/opts-visitor.c | 1 +
qapi/string-input-visitor.c | 4 ++--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/qapi/opts-visitor.c b/qapi/opts-visitor.c
index 8f1efab8b9..d7376bf239 100644
--- a/qapi/opts-visitor.c
+++ b/qapi/opts-visitor.c
@@ -249,41 +249,42 @@ static GenericList *
opts_next_list(Visitor *v, GenericList *tail, size_t size)
{
OptsVisitor *ov = to_ov(v);
switch (ov->list_mode) {
case LM_TRAVERSED:
return NULL;
case LM_SIGNED_INTERVAL:
case LM_UNSIGNED_INTERVAL:
if (ov->list_mode == LM_SIGNED_INTERVAL) {
if (ov->range_next.s < ov->range_limit.s) {
++ov->range_next.s;
break;
}
} else if (ov->range_next.u < ov->range_limit.u) {
++ov->range_next.u;
break;
}
ov->list_mode = LM_IN_PROGRESS;
/* range has been completed, fall through in order to pop option */
+ fallthrough;
case LM_IN_PROGRESS: {
const QemuOpt *opt;
opt = g_queue_pop_head(ov->repeated_opts);
if (g_queue_is_empty(ov->repeated_opts)) {
g_hash_table_remove(ov->unprocessed_opts, opt->name);
ov->repeated_opts = NULL;
ov->list_mode = LM_TRAVERSED;
return NULL;
}
break;
}
default:
abort();
}
tail->next = g_malloc0(size);
return tail->next;
}
diff --git a/qapi/string-input-visitor.c b/qapi/string-input-visitor.c
index 197139c1c0..1ce43da20b 100644
--- a/qapi/string-input-visitor.c
+++ b/qapi/string-input-visitor.c
@@ -182,41 +182,41 @@ static int try_parse_int64_list_entry(StringInputVisitor *siv, int64_t *obj)
static bool parse_type_int64(Visitor *v, const char *name, int64_t *obj,
Error **errp)
{
StringInputVisitor *siv = to_siv(v);
int64_t val;
switch (siv->lm) {
case LM_NONE:
/* just parse a simple int64, bail out if not completely consumed */
if (qemu_strtoi64(siv->string, NULL, 0, &val)) {
error_setg(errp, QERR_INVALID_PARAMETER_VALUE,
name ? name : "null", "int64");
return false;
}
*obj = val;
return true;
case LM_UNPARSED:
if (try_parse_int64_list_entry(siv, obj)) {
error_setg(errp, QERR_INVALID_PARAMETER_VALUE, name ? name : "null",
"list of int64 values or ranges");
return false;
}
assert(siv->lm == LM_INT64_RANGE);
- /* fall through */
+ fallthrough;
case LM_INT64_RANGE:
/* return the next element in the range */
assert(siv->rangeNext.i64 <= siv->rangeEnd.i64);
*obj = siv->rangeNext.i64++;
if (siv->rangeNext.i64 > siv->rangeEnd.i64 || *obj == INT64_MAX) {
/* end of range, check if there is more to parse */
siv->lm = siv->unparsed_string[0] ? LM_UNPARSED : LM_END;
}
return true;
case LM_END:
error_setg(errp, "Fewer list elements expected");
return false;
default:
abort();
}
}
@@ -272,41 +272,41 @@ static int try_parse_uint64_list_entry(StringInputVisitor *siv, uint64_t *obj)
static bool parse_type_uint64(Visitor *v, const char *name, uint64_t *obj,
Error **errp)
{
StringInputVisitor *siv = to_siv(v);
uint64_t val;
switch (siv->lm) {
case LM_NONE:
/* just parse a simple uint64, bail out if not completely consumed */
if (qemu_strtou64(siv->string, NULL, 0, &val)) {
error_setg(errp, QERR_INVALID_PARAMETER_VALUE, name ? name : "null",
"uint64");
return false;
}
*obj = val;
return true;
case LM_UNPARSED:
if (try_parse_uint64_list_entry(siv, obj)) {
error_setg(errp, QERR_INVALID_PARAMETER_VALUE, name ? name : "null",
"list of uint64 values or ranges");
return false;
}
assert(siv->lm == LM_UINT64_RANGE);
- /* fall through */
+ fallthrough;
case LM_UINT64_RANGE:
/* return the next element in the range */
assert(siv->rangeNext.u64 <= siv->rangeEnd.u64);
*obj = siv->rangeNext.u64++;
if (siv->rangeNext.u64 > siv->rangeEnd.u64 || *obj == UINT64_MAX) {
/* end of range, check if there is more to parse */
siv->lm = siv->unparsed_string[0] ? LM_UNPARSED : LM_END;
}
return true;
case LM_END:
error_setg(errp, "Fewer list elements expected");
return false;
default:
abort();
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* Re: [RFC PATCH v2 04/78] qapi/opts-visitor: add fallthrough pseudo-keyword
2023-10-13 7:56 ` [RFC PATCH v2 04/78] qapi/opts-visitor: " Emmanouil Pitsidianakis
@ 2023-10-17 22:11 ` Eric Blake
0 siblings, 0 replies; 91+ messages in thread
From: Eric Blake @ 2023-10-17 22:11 UTC (permalink / raw)
To: Emmanouil Pitsidianakis; +Cc: qemu-devel, Markus Armbruster, Michael Roth
On Fri, Oct 13, 2023 at 10:56:31AM +0300, Emmanouil Pitsidianakis wrote:
> In preparation of raising -Wimplicit-fallthrough to 5, replace all
> fall-through comments with the fallthrough attribute pseudo-keyword.
>
> Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
> ---
> qapi/opts-visitor.c | 1 +
> qapi/string-input-visitor.c | 4 ++--
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
Reviewed-by: Eric Blake <eblake@redhat.com>
--
Eric Blake, Principal Software Engineer
Red Hat, Inc.
Virtualization: qemu.org | libguestfs.org
^ permalink raw reply [flat|nested] 91+ messages in thread
* [RFC PATCH v2 05/78] qobject/json: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (3 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 04/78] qapi/opts-visitor: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 06/78] tcg: " Emmanouil Pitsidianakis
` (73 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Markus Armbruster
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
qobject/json-lexer.c | 4 ++--
qobject/json-parser.c | 5 +++--
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/qobject/json-lexer.c b/qobject/json-lexer.c
index 51341d96e4..ab74470ac6 100644
--- a/qobject/json-lexer.c
+++ b/qobject/json-lexer.c
@@ -283,61 +283,61 @@ void json_lexer_init(JSONLexer *lexer, bool enable_interpolation)
static void json_lexer_feed_char(JSONLexer *lexer, char ch, bool flush)
{
int new_state;
bool char_consumed = false;
lexer->x++;
if (ch == '\n') {
lexer->x = 0;
lexer->y++;
}
while (flush ? lexer->state != lexer->start_state : !char_consumed) {
new_state = next_state(lexer, ch, flush, &char_consumed);
if (char_consumed) {
assert(!flush);
g_string_append_c(lexer->token, ch);
}
switch (new_state) {
case JSON_LCURLY:
case JSON_RCURLY:
case JSON_LSQUARE:
case JSON_RSQUARE:
case JSON_COLON:
case JSON_COMMA:
case JSON_INTERP:
case JSON_INTEGER:
case JSON_FLOAT:
case JSON_KEYWORD:
case JSON_STRING:
json_message_process_token(lexer, lexer->token, new_state,
lexer->x, lexer->y);
- /* fall through */
+ fallthrough;
case IN_START:
g_string_truncate(lexer->token, 0);
new_state = lexer->start_state;
break;
case JSON_ERROR:
json_message_process_token(lexer, lexer->token, JSON_ERROR,
lexer->x, lexer->y);
new_state = IN_RECOVERY;
- /* fall through */
+ fallthrough;
case IN_RECOVERY:
g_string_truncate(lexer->token, 0);
break;
default:
break;
}
lexer->state = new_state;
}
/* Do not let a single token grow to an arbitrarily large size,
* this is a security consideration.
*/
if (lexer->token->len > MAX_TOKEN_SIZE) {
json_message_process_token(lexer, lexer->token, lexer->state,
lexer->x, lexer->y);
g_string_truncate(lexer->token, 0);
lexer->state = lexer->start_state;
}
}
diff --git a/qobject/json-parser.c b/qobject/json-parser.c
index d498db6e70..4dc622dcc9 100644
--- a/qobject/json-parser.c
+++ b/qobject/json-parser.c
@@ -95,137 +95,137 @@ static int cvt4hex(const char *s)
/**
* parse_string(): Parse a JSON string
*
* From RFC 8259 "The JavaScript Object Notation (JSON) Data
* Interchange Format":
*
* char = unescaped /
* escape (
* %x22 / ; " quotation mark U+0022
* %x5C / ; \ reverse solidus U+005C
* %x2F / ; / solidus U+002F
* %x62 / ; b backspace U+0008
* %x66 / ; f form feed U+000C
* %x6E / ; n line feed U+000A
* %x72 / ; r carriage return U+000D
* %x74 / ; t tab U+0009
* %x75 4HEXDIG ) ; uXXXX U+XXXX
* escape = %x5C ; \
* quotation-mark = %x22 ; "
* unescaped = %x20-21 / %x23-5B / %x5D-10FFFF
*
* Extensions over RFC 8259:
* - Extra escape sequence in strings:
* 0x27 (apostrophe) is recognized after escape, too
* - Single-quoted strings:
* Like double-quoted strings, except they're delimited by %x27
* (apostrophe) instead of %x22 (quotation mark), and can't contain
* unescaped apostrophe, but can contain unescaped quotation mark.
*
* Note:
* - Encoding is modified UTF-8.
* - Invalid Unicode characters are rejected.
* - Control characters \x00..\x1F are rejected by the lexer.
*/
static QString *parse_string(JSONParserContext *ctxt, JSONToken *token)
{
const char *ptr = token->str;
GString *str;
char quote;
const char *beg;
int cp, trailing;
char *end;
ssize_t len;
char utf8_buf[5];
assert(*ptr == '"' || *ptr == '\'');
quote = *ptr++;
str = g_string_new(NULL);
while (*ptr != quote) {
assert(*ptr);
switch (*ptr) {
case '\\':
beg = ptr++;
switch (*ptr++) {
case '"':
g_string_append_c(str, '"');
break;
case '\'':
g_string_append_c(str, '\'');
break;
case '\\':
g_string_append_c(str, '\\');
break;
case '/':
g_string_append_c(str, '/');
break;
case 'b':
g_string_append_c(str, '\b');
break;
case 'f':
g_string_append_c(str, '\f');
break;
case 'n':
g_string_append_c(str, '\n');
break;
case 'r':
g_string_append_c(str, '\r');
break;
case 't':
g_string_append_c(str, '\t');
break;
case 'u':
cp = cvt4hex(ptr);
ptr += 4;
/* handle surrogate pairs */
if (cp >= 0xD800 && cp <= 0xDBFF
&& ptr[0] == '\\' && ptr[1] == 'u') {
/* leading surrogate followed by \u */
cp = 0x10000 + ((cp & 0x3FF) << 10);
trailing = cvt4hex(ptr + 2);
if (trailing >= 0xDC00 && trailing <= 0xDFFF) {
/* followed by trailing surrogate */
cp |= trailing & 0x3FF;
ptr += 6;
} else {
cp = -1; /* invalid */
}
}
if (mod_utf8_encode(utf8_buf, sizeof(utf8_buf), cp) < 0) {
parse_error(ctxt, token,
"%.*s is not a valid Unicode character",
(int)(ptr - beg), beg);
goto out;
}
g_string_append(str, utf8_buf);
break;
default:
parse_error(ctxt, token, "invalid escape sequence in string");
goto out;
}
break;
case '%':
if (ctxt->ap) {
if (ptr[1] != '%') {
parse_error(ctxt, token, "can't interpolate into string");
goto out;
}
ptr++;
}
- /* fall through */
+ fallthrough;
default:
cp = mod_utf8_codepoint(ptr, 6, &end);
if (cp < 0) {
parse_error(ctxt, token, "invalid UTF-8 sequence in string");
goto out;
}
ptr = end;
len = mod_utf8_encode(utf8_buf, sizeof(utf8_buf), cp);
assert(len >= 0);
g_string_append(str, utf8_buf);
}
}
return qstring_from_gstring(str);
@@ -481,51 +481,52 @@ static QObject *parse_interpolation(JSONParserContext *ctxt)
static QObject *parse_literal(JSONParserContext *ctxt)
{
JSONToken *token;
token = parser_context_pop_token(ctxt);
assert(token);
switch (token->type) {
case JSON_STRING:
return QOBJECT(parse_string(ctxt, token));
case JSON_INTEGER: {
/*
* Represent JSON_INTEGER as QNUM_I64 if possible, else as
* QNUM_U64, else as QNUM_DOUBLE. Note that qemu_strtoi64()
* and qemu_strtou64() fail with ERANGE when it's not
* possible.
*
* qnum_get_int() will then work for any signed 64-bit
* JSON_INTEGER, qnum_get_uint() for any unsigned 64-bit
* integer, and qnum_get_double() both for any JSON_INTEGER
* and any JSON_FLOAT (with precision loss for integers beyond
* 53 bits)
*/
int ret;
int64_t value;
uint64_t uvalue;
ret = qemu_strtoi64(token->str, NULL, 10, &value);
if (!ret) {
return QOBJECT(qnum_from_int(value));
}
assert(ret == -ERANGE);
if (token->str[0] != '-') {
ret = qemu_strtou64(token->str, NULL, 10, &uvalue);
if (!ret) {
return QOBJECT(qnum_from_uint(uvalue));
}
assert(ret == -ERANGE);
}
+ /* fall through to JSON_FLOAT */
+ fallthrough;
}
- /* fall through to JSON_FLOAT */
case JSON_FLOAT:
/* FIXME dependent on locale; a pervasive issue in QEMU */
/* FIXME our lexer matches RFC 8259 in forbidding Inf or NaN,
* but those might be useful extensions beyond JSON */
return QOBJECT(qnum_from_double(strtod(token->str, NULL)));
default:
abort();
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 06/78] tcg: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (4 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 05/78] qobject/json: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 07/78] hw/virtio/virtio-balloon.c: " Emmanouil Pitsidianakis
` (72 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Paolo Bonzini, Richard Henderson,
Eduardo Habkost, WANG Xuerui, Philippe Mathieu-Daudé,
Aurelien Jarno, Huacai Chen, Jiaxun Yang, Aleksandar Rikalo,
Palmer Dabbelt, Alistair Francis, Stefan Weil,
open list:AArch64 TCG target, open list:RISC-V TCG target
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
target/i386/tcg/translate.c | 3 +++
tcg/aarch64/tcg-target.c.inc | 15 ++++++++++++++-
tcg/arm/tcg-target.c.inc | 5 +++--
tcg/i386/tcg-target.c.inc | 20 ++++++++++++++------
tcg/loongarch64/tcg-target.c.inc | 4 ++--
tcg/mips/tcg-target.c.inc | 8 ++++++--
tcg/ppc/tcg-target.c.inc | 19 ++++++++++++++-----
tcg/riscv/tcg-target.c.inc | 5 +++--
tcg/s390x/tcg-target.c.inc | 8 ++++++--
tcg/tcg-op-gvec.c | 24 ++++++++++++------------
tcg/tcg-op-ldst.c | 2 +-
tcg/tcg.c | 24 +++++++++++++-----------
tcg/tci.c | 2 +-
tcg/tci/tcg-target.c.inc | 2 +-
14 files changed, 93 insertions(+), 48 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index d2061ec44a..e42e3dd653 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -1966,83 +1966,84 @@ static void gen_rotc_rm_T1(DisasContext *s, MemOp ot, int op1,
/* XXX: add faster immediate case */
static void gen_shiftd_rm_T1(DisasContext *s, MemOp ot, int op1,
bool is_right, TCGv count_in)
{
target_ulong mask = (ot == MO_64 ? 63 : 31);
TCGv count;
/* load */
if (op1 == OR_TMP0) {
gen_op_ld_v(s, ot, s->T0, s->A0);
} else {
gen_op_mov_v_reg(s, ot, s->T0, op1);
}
count = tcg_temp_new();
tcg_gen_andi_tl(count, count_in, mask);
switch (ot) {
case MO_16:
/* Note: we implement the Intel behaviour for shift count > 16.
This means "shrdw C, B, A" shifts A:B:A >> C. Build the B:A
portion by constructing it as a 32-bit value. */
if (is_right) {
tcg_gen_deposit_tl(s->tmp0, s->T0, s->T1, 16, 16);
tcg_gen_mov_tl(s->T1, s->T0);
tcg_gen_mov_tl(s->T0, s->tmp0);
} else {
tcg_gen_deposit_tl(s->T1, s->T0, s->T1, 16, 16);
}
/*
* If TARGET_X86_64 defined then fall through into MO_32 case,
* otherwise fall through default case.
*/
+ fallthrough;
case MO_32:
#ifdef TARGET_X86_64
/* Concatenate the two 32-bit values and use a 64-bit shift. */
tcg_gen_subi_tl(s->tmp0, count, 1);
if (is_right) {
tcg_gen_concat_tl_i64(s->T0, s->T0, s->T1);
tcg_gen_shr_i64(s->tmp0, s->T0, s->tmp0);
tcg_gen_shr_i64(s->T0, s->T0, count);
} else {
tcg_gen_concat_tl_i64(s->T0, s->T1, s->T0);
tcg_gen_shl_i64(s->tmp0, s->T0, s->tmp0);
tcg_gen_shl_i64(s->T0, s->T0, count);
tcg_gen_shri_i64(s->tmp0, s->tmp0, 32);
tcg_gen_shri_i64(s->T0, s->T0, 32);
}
break;
#endif
default:
tcg_gen_subi_tl(s->tmp0, count, 1);
if (is_right) {
tcg_gen_shr_tl(s->tmp0, s->T0, s->tmp0);
tcg_gen_subfi_tl(s->tmp4, mask + 1, count);
tcg_gen_shr_tl(s->T0, s->T0, count);
tcg_gen_shl_tl(s->T1, s->T1, s->tmp4);
} else {
tcg_gen_shl_tl(s->tmp0, s->T0, s->tmp0);
if (ot == MO_16) {
/* Only needed if count > 16, for Intel behaviour. */
tcg_gen_subfi_tl(s->tmp4, 33, count);
tcg_gen_shr_tl(s->tmp4, s->T1, s->tmp4);
tcg_gen_or_tl(s->tmp0, s->tmp0, s->tmp4);
}
tcg_gen_subfi_tl(s->tmp4, mask + 1, count);
tcg_gen_shl_tl(s->T0, s->T0, count);
tcg_gen_shr_tl(s->T1, s->T1, s->tmp4);
}
tcg_gen_movi_tl(s->tmp4, 0);
tcg_gen_movcond_tl(TCG_COND_EQ, s->T1, count, s->tmp4,
s->tmp4, s->T1);
tcg_gen_or_tl(s->T0, s->T0, s->T1);
break;
}
/* store */
gen_op_st_rm_T0_A0(s, ot, op1);
gen_shift_flags(s, ot, s->T0, s->tmp0, count, is_right);
}
@@ -3078,3750 +3079,3751 @@ static void gen_cmpxchg16b(DisasContext *s, CPUX86State *env, int modrm)
/* convert one instruction. s->base.is_jmp is set if the translation must
be stopped. Return the next pc value */
static bool disas_insn(DisasContext *s, CPUState *cpu)
{
CPUX86State *env = cpu_env(cpu);
int b, prefixes;
int shift;
MemOp ot, aflag, dflag;
int modrm, reg, rm, mod, op, opreg, val;
bool orig_cc_op_dirty = s->cc_op_dirty;
CCOp orig_cc_op = s->cc_op;
target_ulong orig_pc_save = s->pc_save;
s->pc = s->base.pc_next;
s->override = -1;
#ifdef TARGET_X86_64
s->rex_r = 0;
s->rex_x = 0;
s->rex_b = 0;
#endif
s->rip_offset = 0; /* for relative ip address */
s->vex_l = 0;
s->vex_v = 0;
s->vex_w = false;
switch (sigsetjmp(s->jmpbuf, 0)) {
case 0:
break;
case 1:
gen_exception_gpf(s);
return true;
case 2:
/* Restore state that may affect the next instruction. */
s->pc = s->base.pc_next;
/*
* TODO: These save/restore can be removed after the table-based
* decoder is complete; we will be decoding the insn completely
* before any code generation that might affect these variables.
*/
s->cc_op_dirty = orig_cc_op_dirty;
s->cc_op = orig_cc_op;
s->pc_save = orig_pc_save;
/* END TODO */
s->base.num_insns--;
tcg_remove_ops_after(s->prev_insn_end);
s->base.is_jmp = DISAS_TOO_MANY;
return false;
default:
g_assert_not_reached();
}
prefixes = 0;
next_byte:
s->prefix = prefixes;
b = x86_ldub_code(env, s);
/* Collect prefixes. */
switch (b) {
default:
break;
case 0x0f:
b = x86_ldub_code(env, s) + 0x100;
break;
case 0xf3:
prefixes |= PREFIX_REPZ;
prefixes &= ~PREFIX_REPNZ;
goto next_byte;
case 0xf2:
prefixes |= PREFIX_REPNZ;
prefixes &= ~PREFIX_REPZ;
goto next_byte;
case 0xf0:
prefixes |= PREFIX_LOCK;
goto next_byte;
case 0x2e:
s->override = R_CS;
goto next_byte;
case 0x36:
s->override = R_SS;
goto next_byte;
case 0x3e:
s->override = R_DS;
goto next_byte;
case 0x26:
s->override = R_ES;
goto next_byte;
case 0x64:
s->override = R_FS;
goto next_byte;
case 0x65:
s->override = R_GS;
goto next_byte;
case 0x66:
prefixes |= PREFIX_DATA;
goto next_byte;
case 0x67:
prefixes |= PREFIX_ADR;
goto next_byte;
#ifdef TARGET_X86_64
case 0x40 ... 0x4f:
if (CODE64(s)) {
/* REX prefix */
prefixes |= PREFIX_REX;
s->vex_w = (b >> 3) & 1;
s->rex_r = (b & 0x4) << 1;
s->rex_x = (b & 0x2) << 2;
s->rex_b = (b & 0x1) << 3;
goto next_byte;
}
break;
#endif
case 0xc5: /* 2-byte VEX */
case 0xc4: /* 3-byte VEX */
if (CODE32(s) && !VM86(s)) {
int vex2 = x86_ldub_code(env, s);
s->pc--; /* rewind the advance_pc() x86_ldub_code() did */
if (!CODE64(s) && (vex2 & 0xc0) != 0xc0) {
/* 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b,
otherwise the instruction is LES or LDS. */
break;
}
disas_insn_new(s, cpu, b);
return s->pc;
}
break;
}
/* Post-process prefixes. */
if (CODE64(s)) {
/* In 64-bit mode, the default data size is 32-bit. Select 64-bit
data with rex_w, and 16-bit data with 0x66; rex_w takes precedence
over 0x66 if both are present. */
dflag = (REX_W(s) ? MO_64 : prefixes & PREFIX_DATA ? MO_16 : MO_32);
/* In 64-bit mode, 0x67 selects 32-bit addressing. */
aflag = (prefixes & PREFIX_ADR ? MO_32 : MO_64);
} else {
/* In 16/32-bit mode, 0x66 selects the opposite data size. */
if (CODE32(s) ^ ((prefixes & PREFIX_DATA) != 0)) {
dflag = MO_32;
} else {
dflag = MO_16;
}
/* In 16/32-bit mode, 0x67 selects the opposite addressing. */
if (CODE32(s) ^ ((prefixes & PREFIX_ADR) != 0)) {
aflag = MO_32;
} else {
aflag = MO_16;
}
}
s->prefix = prefixes;
s->aflag = aflag;
s->dflag = dflag;
/* now check op code */
switch (b) {
/**************************/
/* arith & logic */
case 0x00 ... 0x05:
case 0x08 ... 0x0d:
case 0x10 ... 0x15:
case 0x18 ... 0x1d:
case 0x20 ... 0x25:
case 0x28 ... 0x2d:
case 0x30 ... 0x35:
case 0x38 ... 0x3d:
{
int f;
op = (b >> 3) & 7;
f = (b >> 1) & 3;
ot = mo_b_d(b, dflag);
switch(f) {
case 0: /* OP Ev, Gv */
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
opreg = OR_TMP0;
} else if (op == OP_XORL && rm == reg) {
xor_zero:
/* xor reg, reg optimisation */
set_cc_op(s, CC_OP_CLR);
tcg_gen_movi_tl(s->T0, 0);
gen_op_mov_reg_v(s, ot, reg, s->T0);
break;
} else {
opreg = rm;
}
gen_op_mov_v_reg(s, ot, s->T1, reg);
gen_op(s, op, ot, opreg);
break;
case 1: /* OP Gv, Ev */
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
reg = ((modrm >> 3) & 7) | REX_R(s);
rm = (modrm & 7) | REX_B(s);
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, s->T1, s->A0);
} else if (op == OP_XORL && rm == reg) {
goto xor_zero;
} else {
gen_op_mov_v_reg(s, ot, s->T1, rm);
}
gen_op(s, op, ot, reg);
break;
case 2: /* OP A, Iv */
val = insn_get(env, s, ot);
tcg_gen_movi_tl(s->T1, val);
gen_op(s, op, ot, OR_EAX);
break;
}
}
break;
case 0x82:
if (CODE64(s))
goto illegal_op;
/* fall through */
+ fallthrough;
case 0x80: /* GRP1 */
case 0x81:
case 0x83:
{
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
op = (modrm >> 3) & 7;
if (mod != 3) {
if (b == 0x83)
s->rip_offset = 1;
else
s->rip_offset = insn_const_size(ot);
gen_lea_modrm(env, s, modrm);
opreg = OR_TMP0;
} else {
opreg = rm;
}
switch(b) {
default:
case 0x80:
case 0x81:
case 0x82:
val = insn_get(env, s, ot);
break;
case 0x83:
val = (int8_t)insn_get(env, s, MO_8);
break;
}
tcg_gen_movi_tl(s->T1, val);
gen_op(s, op, ot, opreg);
}
break;
/**************************/
/* inc, dec, and other misc arith */
case 0x40 ... 0x47: /* inc Gv */
ot = dflag;
gen_inc(s, ot, OR_EAX + (b & 7), 1);
break;
case 0x48 ... 0x4f: /* dec Gv */
ot = dflag;
gen_inc(s, ot, OR_EAX + (b & 7), -1);
break;
case 0xf6: /* GRP3 */
case 0xf7:
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
op = (modrm >> 3) & 7;
if (mod != 3) {
if (op == 0) {
s->rip_offset = insn_const_size(ot);
}
gen_lea_modrm(env, s, modrm);
/* For those below that handle locked memory, don't load here. */
if (!(s->prefix & PREFIX_LOCK)
|| op != 2) {
gen_op_ld_v(s, ot, s->T0, s->A0);
}
} else {
gen_op_mov_v_reg(s, ot, s->T0, rm);
}
switch(op) {
case 0: /* test */
val = insn_get(env, s, ot);
tcg_gen_movi_tl(s->T1, val);
gen_op_testl_T0_T1_cc(s);
set_cc_op(s, CC_OP_LOGICB + ot);
break;
case 2: /* not */
if (s->prefix & PREFIX_LOCK) {
if (mod == 3) {
goto illegal_op;
}
tcg_gen_movi_tl(s->T0, ~0);
tcg_gen_atomic_xor_fetch_tl(s->T0, s->A0, s->T0,
s->mem_index, ot | MO_LE);
} else {
tcg_gen_not_tl(s->T0, s->T0);
if (mod != 3) {
gen_op_st_v(s, ot, s->T0, s->A0);
} else {
gen_op_mov_reg_v(s, ot, rm, s->T0);
}
}
break;
case 3: /* neg */
if (s->prefix & PREFIX_LOCK) {
TCGLabel *label1;
TCGv a0, t0, t1, t2;
if (mod == 3) {
goto illegal_op;
}
a0 = s->A0;
t0 = s->T0;
label1 = gen_new_label();
gen_set_label(label1);
t1 = tcg_temp_new();
t2 = tcg_temp_new();
tcg_gen_mov_tl(t2, t0);
tcg_gen_neg_tl(t1, t0);
tcg_gen_atomic_cmpxchg_tl(t0, a0, t0, t1,
s->mem_index, ot | MO_LE);
tcg_gen_brcond_tl(TCG_COND_NE, t0, t2, label1);
tcg_gen_neg_tl(s->T0, t0);
} else {
tcg_gen_neg_tl(s->T0, s->T0);
if (mod != 3) {
gen_op_st_v(s, ot, s->T0, s->A0);
} else {
gen_op_mov_reg_v(s, ot, rm, s->T0);
}
}
gen_op_update_neg_cc(s);
set_cc_op(s, CC_OP_SUBB + ot);
break;
case 4: /* mul */
switch(ot) {
case MO_8:
gen_op_mov_v_reg(s, MO_8, s->T1, R_EAX);
tcg_gen_ext8u_tl(s->T0, s->T0);
tcg_gen_ext8u_tl(s->T1, s->T1);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(s->T0, s->T0, s->T1);
gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);
tcg_gen_mov_tl(cpu_cc_dst, s->T0);
tcg_gen_andi_tl(cpu_cc_src, s->T0, 0xff00);
set_cc_op(s, CC_OP_MULB);
break;
case MO_16:
gen_op_mov_v_reg(s, MO_16, s->T1, R_EAX);
tcg_gen_ext16u_tl(s->T0, s->T0);
tcg_gen_ext16u_tl(s->T1, s->T1);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(s->T0, s->T0, s->T1);
gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);
tcg_gen_mov_tl(cpu_cc_dst, s->T0);
tcg_gen_shri_tl(s->T0, s->T0, 16);
gen_op_mov_reg_v(s, MO_16, R_EDX, s->T0);
tcg_gen_mov_tl(cpu_cc_src, s->T0);
set_cc_op(s, CC_OP_MULW);
break;
default:
case MO_32:
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
tcg_gen_trunc_tl_i32(s->tmp3_i32, cpu_regs[R_EAX]);
tcg_gen_mulu2_i32(s->tmp2_i32, s->tmp3_i32,
s->tmp2_i32, s->tmp3_i32);
tcg_gen_extu_i32_tl(cpu_regs[R_EAX], s->tmp2_i32);
tcg_gen_extu_i32_tl(cpu_regs[R_EDX], s->tmp3_i32);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
tcg_gen_mov_tl(cpu_cc_src, cpu_regs[R_EDX]);
set_cc_op(s, CC_OP_MULL);
break;
#ifdef TARGET_X86_64
case MO_64:
tcg_gen_mulu2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX],
s->T0, cpu_regs[R_EAX]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
tcg_gen_mov_tl(cpu_cc_src, cpu_regs[R_EDX]);
set_cc_op(s, CC_OP_MULQ);
break;
#endif
}
break;
case 5: /* imul */
switch(ot) {
case MO_8:
gen_op_mov_v_reg(s, MO_8, s->T1, R_EAX);
tcg_gen_ext8s_tl(s->T0, s->T0);
tcg_gen_ext8s_tl(s->T1, s->T1);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(s->T0, s->T0, s->T1);
gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);
tcg_gen_mov_tl(cpu_cc_dst, s->T0);
tcg_gen_ext8s_tl(s->tmp0, s->T0);
tcg_gen_sub_tl(cpu_cc_src, s->T0, s->tmp0);
set_cc_op(s, CC_OP_MULB);
break;
case MO_16:
gen_op_mov_v_reg(s, MO_16, s->T1, R_EAX);
tcg_gen_ext16s_tl(s->T0, s->T0);
tcg_gen_ext16s_tl(s->T1, s->T1);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(s->T0, s->T0, s->T1);
gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);
tcg_gen_mov_tl(cpu_cc_dst, s->T0);
tcg_gen_ext16s_tl(s->tmp0, s->T0);
tcg_gen_sub_tl(cpu_cc_src, s->T0, s->tmp0);
tcg_gen_shri_tl(s->T0, s->T0, 16);
gen_op_mov_reg_v(s, MO_16, R_EDX, s->T0);
set_cc_op(s, CC_OP_MULW);
break;
default:
case MO_32:
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
tcg_gen_trunc_tl_i32(s->tmp3_i32, cpu_regs[R_EAX]);
tcg_gen_muls2_i32(s->tmp2_i32, s->tmp3_i32,
s->tmp2_i32, s->tmp3_i32);
tcg_gen_extu_i32_tl(cpu_regs[R_EAX], s->tmp2_i32);
tcg_gen_extu_i32_tl(cpu_regs[R_EDX], s->tmp3_i32);
tcg_gen_sari_i32(s->tmp2_i32, s->tmp2_i32, 31);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
tcg_gen_sub_i32(s->tmp2_i32, s->tmp2_i32, s->tmp3_i32);
tcg_gen_extu_i32_tl(cpu_cc_src, s->tmp2_i32);
set_cc_op(s, CC_OP_MULL);
break;
#ifdef TARGET_X86_64
case MO_64:
tcg_gen_muls2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX],
s->T0, cpu_regs[R_EAX]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
tcg_gen_sari_tl(cpu_cc_src, cpu_regs[R_EAX], 63);
tcg_gen_sub_tl(cpu_cc_src, cpu_cc_src, cpu_regs[R_EDX]);
set_cc_op(s, CC_OP_MULQ);
break;
#endif
}
break;
case 6: /* div */
switch(ot) {
case MO_8:
gen_helper_divb_AL(tcg_env, s->T0);
break;
case MO_16:
gen_helper_divw_AX(tcg_env, s->T0);
break;
default:
case MO_32:
gen_helper_divl_EAX(tcg_env, s->T0);
break;
#ifdef TARGET_X86_64
case MO_64:
gen_helper_divq_EAX(tcg_env, s->T0);
break;
#endif
}
break;
case 7: /* idiv */
switch(ot) {
case MO_8:
gen_helper_idivb_AL(tcg_env, s->T0);
break;
case MO_16:
gen_helper_idivw_AX(tcg_env, s->T0);
break;
default:
case MO_32:
gen_helper_idivl_EAX(tcg_env, s->T0);
break;
#ifdef TARGET_X86_64
case MO_64:
gen_helper_idivq_EAX(tcg_env, s->T0);
break;
#endif
}
break;
default:
goto unknown_op;
}
break;
case 0xfe: /* GRP4 */
case 0xff: /* GRP5 */
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
op = (modrm >> 3) & 7;
if (op >= 2 && b == 0xfe) {
goto unknown_op;
}
if (CODE64(s)) {
if (op == 2 || op == 4) {
/* operand size for jumps is 64 bit */
ot = MO_64;
} else if (op == 3 || op == 5) {
ot = dflag != MO_16 ? MO_32 + REX_W(s) : MO_16;
} else if (op == 6) {
/* default push size is 64 bit */
ot = mo_pushpop(s, dflag);
}
}
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
if (op >= 2 && op != 3 && op != 5)
gen_op_ld_v(s, ot, s->T0, s->A0);
} else {
gen_op_mov_v_reg(s, ot, s->T0, rm);
}
switch(op) {
case 0: /* inc Ev */
if (mod != 3)
opreg = OR_TMP0;
else
opreg = rm;
gen_inc(s, ot, opreg, 1);
break;
case 1: /* dec Ev */
if (mod != 3)
opreg = OR_TMP0;
else
opreg = rm;
gen_inc(s, ot, opreg, -1);
break;
case 2: /* call Ev */
/* XXX: optimize if memory (no 'and' is necessary) */
if (dflag == MO_16) {
tcg_gen_ext16u_tl(s->T0, s->T0);
}
gen_push_v(s, eip_next_tl(s));
gen_op_jmp_v(s, s->T0);
gen_bnd_jmp(s);
s->base.is_jmp = DISAS_JUMP;
break;
case 3: /* lcall Ev */
if (mod == 3) {
goto illegal_op;
}
gen_op_ld_v(s, ot, s->T1, s->A0);
gen_add_A0_im(s, 1 << ot);
gen_op_ld_v(s, MO_16, s->T0, s->A0);
do_lcall:
if (PE(s) && !VM86(s)) {
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
gen_helper_lcall_protected(tcg_env, s->tmp2_i32, s->T1,
tcg_constant_i32(dflag - 1),
eip_next_tl(s));
} else {
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);
gen_helper_lcall_real(tcg_env, s->tmp2_i32, s->tmp3_i32,
tcg_constant_i32(dflag - 1),
eip_next_i32(s));
}
s->base.is_jmp = DISAS_JUMP;
break;
case 4: /* jmp Ev */
if (dflag == MO_16) {
tcg_gen_ext16u_tl(s->T0, s->T0);
}
gen_op_jmp_v(s, s->T0);
gen_bnd_jmp(s);
s->base.is_jmp = DISAS_JUMP;
break;
case 5: /* ljmp Ev */
if (mod == 3) {
goto illegal_op;
}
gen_op_ld_v(s, ot, s->T1, s->A0);
gen_add_A0_im(s, 1 << ot);
gen_op_ld_v(s, MO_16, s->T0, s->A0);
do_ljmp:
if (PE(s) && !VM86(s)) {
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
gen_helper_ljmp_protected(tcg_env, s->tmp2_i32, s->T1,
eip_next_tl(s));
} else {
gen_op_movl_seg_T0_vm(s, R_CS);
gen_op_jmp_v(s, s->T1);
}
s->base.is_jmp = DISAS_JUMP;
break;
case 6: /* push Ev */
gen_push_v(s, s->T0);
break;
default:
goto unknown_op;
}
break;
case 0x84: /* test Ev, Gv */
case 0x85:
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_op_mov_v_reg(s, ot, s->T1, reg);
gen_op_testl_T0_T1_cc(s);
set_cc_op(s, CC_OP_LOGICB + ot);
break;
case 0xa8: /* test eAX, Iv */
case 0xa9:
ot = mo_b_d(b, dflag);
val = insn_get(env, s, ot);
gen_op_mov_v_reg(s, ot, s->T0, OR_EAX);
tcg_gen_movi_tl(s->T1, val);
gen_op_testl_T0_T1_cc(s);
set_cc_op(s, CC_OP_LOGICB + ot);
break;
case 0x98: /* CWDE/CBW */
switch (dflag) {
#ifdef TARGET_X86_64
case MO_64:
gen_op_mov_v_reg(s, MO_32, s->T0, R_EAX);
tcg_gen_ext32s_tl(s->T0, s->T0);
gen_op_mov_reg_v(s, MO_64, R_EAX, s->T0);
break;
#endif
case MO_32:
gen_op_mov_v_reg(s, MO_16, s->T0, R_EAX);
tcg_gen_ext16s_tl(s->T0, s->T0);
gen_op_mov_reg_v(s, MO_32, R_EAX, s->T0);
break;
case MO_16:
gen_op_mov_v_reg(s, MO_8, s->T0, R_EAX);
tcg_gen_ext8s_tl(s->T0, s->T0);
gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);
break;
default:
g_assert_not_reached();
}
break;
case 0x99: /* CDQ/CWD */
switch (dflag) {
#ifdef TARGET_X86_64
case MO_64:
gen_op_mov_v_reg(s, MO_64, s->T0, R_EAX);
tcg_gen_sari_tl(s->T0, s->T0, 63);
gen_op_mov_reg_v(s, MO_64, R_EDX, s->T0);
break;
#endif
case MO_32:
gen_op_mov_v_reg(s, MO_32, s->T0, R_EAX);
tcg_gen_ext32s_tl(s->T0, s->T0);
tcg_gen_sari_tl(s->T0, s->T0, 31);
gen_op_mov_reg_v(s, MO_32, R_EDX, s->T0);
break;
case MO_16:
gen_op_mov_v_reg(s, MO_16, s->T0, R_EAX);
tcg_gen_ext16s_tl(s->T0, s->T0);
tcg_gen_sari_tl(s->T0, s->T0, 15);
gen_op_mov_reg_v(s, MO_16, R_EDX, s->T0);
break;
default:
g_assert_not_reached();
}
break;
case 0x1af: /* imul Gv, Ev */
case 0x69: /* imul Gv, Ev, I */
case 0x6b:
ot = dflag;
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
if (b == 0x69)
s->rip_offset = insn_const_size(ot);
else if (b == 0x6b)
s->rip_offset = 1;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
if (b == 0x69) {
val = insn_get(env, s, ot);
tcg_gen_movi_tl(s->T1, val);
} else if (b == 0x6b) {
val = (int8_t)insn_get(env, s, MO_8);
tcg_gen_movi_tl(s->T1, val);
} else {
gen_op_mov_v_reg(s, ot, s->T1, reg);
}
switch (ot) {
#ifdef TARGET_X86_64
case MO_64:
tcg_gen_muls2_i64(cpu_regs[reg], s->T1, s->T0, s->T1);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[reg]);
tcg_gen_sari_tl(cpu_cc_src, cpu_cc_dst, 63);
tcg_gen_sub_tl(cpu_cc_src, cpu_cc_src, s->T1);
break;
#endif
case MO_32:
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);
tcg_gen_muls2_i32(s->tmp2_i32, s->tmp3_i32,
s->tmp2_i32, s->tmp3_i32);
tcg_gen_extu_i32_tl(cpu_regs[reg], s->tmp2_i32);
tcg_gen_sari_i32(s->tmp2_i32, s->tmp2_i32, 31);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[reg]);
tcg_gen_sub_i32(s->tmp2_i32, s->tmp2_i32, s->tmp3_i32);
tcg_gen_extu_i32_tl(cpu_cc_src, s->tmp2_i32);
break;
default:
tcg_gen_ext16s_tl(s->T0, s->T0);
tcg_gen_ext16s_tl(s->T1, s->T1);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(s->T0, s->T0, s->T1);
tcg_gen_mov_tl(cpu_cc_dst, s->T0);
tcg_gen_ext16s_tl(s->tmp0, s->T0);
tcg_gen_sub_tl(cpu_cc_src, s->T0, s->tmp0);
gen_op_mov_reg_v(s, ot, reg, s->T0);
break;
}
set_cc_op(s, CC_OP_MULB + ot);
break;
case 0x1c0:
case 0x1c1: /* xadd Ev, Gv */
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
mod = (modrm >> 6) & 3;
gen_op_mov_v_reg(s, ot, s->T0, reg);
if (mod == 3) {
rm = (modrm & 7) | REX_B(s);
gen_op_mov_v_reg(s, ot, s->T1, rm);
tcg_gen_add_tl(s->T0, s->T0, s->T1);
gen_op_mov_reg_v(s, ot, reg, s->T1);
gen_op_mov_reg_v(s, ot, rm, s->T0);
} else {
gen_lea_modrm(env, s, modrm);
if (s->prefix & PREFIX_LOCK) {
tcg_gen_atomic_fetch_add_tl(s->T1, s->A0, s->T0,
s->mem_index, ot | MO_LE);
tcg_gen_add_tl(s->T0, s->T0, s->T1);
} else {
gen_op_ld_v(s, ot, s->T1, s->A0);
tcg_gen_add_tl(s->T0, s->T0, s->T1);
gen_op_st_v(s, ot, s->T0, s->A0);
}
gen_op_mov_reg_v(s, ot, reg, s->T1);
}
gen_op_update2_cc(s);
set_cc_op(s, CC_OP_ADDB + ot);
break;
case 0x1b0:
case 0x1b1: /* cmpxchg Ev, Gv */
{
TCGv oldv, newv, cmpv, dest;
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
mod = (modrm >> 6) & 3;
oldv = tcg_temp_new();
newv = tcg_temp_new();
cmpv = tcg_temp_new();
gen_op_mov_v_reg(s, ot, newv, reg);
tcg_gen_mov_tl(cmpv, cpu_regs[R_EAX]);
gen_extu(ot, cmpv);
if (s->prefix & PREFIX_LOCK) {
if (mod == 3) {
goto illegal_op;
}
gen_lea_modrm(env, s, modrm);
tcg_gen_atomic_cmpxchg_tl(oldv, s->A0, cmpv, newv,
s->mem_index, ot | MO_LE);
} else {
if (mod == 3) {
rm = (modrm & 7) | REX_B(s);
gen_op_mov_v_reg(s, ot, oldv, rm);
gen_extu(ot, oldv);
/*
* Unlike the memory case, where "the destination operand receives
* a write cycle without regard to the result of the comparison",
* rm must not be touched altogether if the write fails, including
* not zero-extending it on 64-bit processors. So, precompute
* the result of a successful writeback and perform the movcond
* directly on cpu_regs. Also need to write accumulator first, in
* case rm is part of RAX too.
*/
dest = gen_op_deposit_reg_v(s, ot, rm, newv, newv);
tcg_gen_movcond_tl(TCG_COND_EQ, dest, oldv, cmpv, newv, dest);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, oldv, s->A0);
/*
* Perform an unconditional store cycle like physical cpu;
* must be before changing accumulator to ensure
* idempotency if the store faults and the instruction
* is restarted
*/
tcg_gen_movcond_tl(TCG_COND_EQ, newv, oldv, cmpv, newv, oldv);
gen_op_st_v(s, ot, newv, s->A0);
}
}
/*
* Write EAX only if the cmpxchg fails; reuse newv as the destination,
* since it's dead here.
*/
dest = gen_op_deposit_reg_v(s, ot, R_EAX, newv, oldv);
tcg_gen_movcond_tl(TCG_COND_EQ, dest, oldv, cmpv, dest, newv);
tcg_gen_mov_tl(cpu_cc_src, oldv);
tcg_gen_mov_tl(s->cc_srcT, cmpv);
tcg_gen_sub_tl(cpu_cc_dst, cmpv, oldv);
set_cc_op(s, CC_OP_SUBB + ot);
}
break;
case 0x1c7: /* cmpxchg8b */
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
switch ((modrm >> 3) & 7) {
case 1: /* CMPXCHG8, CMPXCHG16 */
if (mod == 3) {
goto illegal_op;
}
#ifdef TARGET_X86_64
if (dflag == MO_64) {
if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) {
goto illegal_op;
}
gen_cmpxchg16b(s, env, modrm);
break;
}
#endif
if (!(s->cpuid_features & CPUID_CX8)) {
goto illegal_op;
}
gen_cmpxchg8b(s, env, modrm);
break;
case 7: /* RDSEED, RDPID with f3 prefix */
if (mod != 3 ||
(s->prefix & (PREFIX_LOCK | PREFIX_REPNZ))) {
goto illegal_op;
}
if (s->prefix & PREFIX_REPZ) {
if (!(s->cpuid_ext_features & CPUID_7_0_ECX_RDPID)) {
goto illegal_op;
}
gen_helper_rdpid(s->T0, tcg_env);
rm = (modrm & 7) | REX_B(s);
gen_op_mov_reg_v(s, dflag, rm, s->T0);
break;
} else {
if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_RDSEED)) {
goto illegal_op;
}
goto do_rdrand;
}
case 6: /* RDRAND */
if (mod != 3 ||
(s->prefix & (PREFIX_LOCK | PREFIX_REPZ | PREFIX_REPNZ)) ||
!(s->cpuid_ext_features & CPUID_EXT_RDRAND)) {
goto illegal_op;
}
do_rdrand:
translator_io_start(&s->base);
gen_helper_rdrand(s->T0, tcg_env);
rm = (modrm & 7) | REX_B(s);
gen_op_mov_reg_v(s, dflag, rm, s->T0);
set_cc_op(s, CC_OP_EFLAGS);
break;
default:
goto illegal_op;
}
break;
/**************************/
/* push/pop */
case 0x50 ... 0x57: /* push */
gen_op_mov_v_reg(s, MO_32, s->T0, (b & 7) | REX_B(s));
gen_push_v(s, s->T0);
break;
case 0x58 ... 0x5f: /* pop */
ot = gen_pop_T0(s);
/* NOTE: order is important for pop %sp */
gen_pop_update(s, ot);
gen_op_mov_reg_v(s, ot, (b & 7) | REX_B(s), s->T0);
break;
case 0x60: /* pusha */
if (CODE64(s))
goto illegal_op;
gen_pusha(s);
break;
case 0x61: /* popa */
if (CODE64(s))
goto illegal_op;
gen_popa(s);
break;
case 0x68: /* push Iv */
case 0x6a:
ot = mo_pushpop(s, dflag);
if (b == 0x68)
val = insn_get(env, s, ot);
else
val = (int8_t)insn_get(env, s, MO_8);
tcg_gen_movi_tl(s->T0, val);
gen_push_v(s, s->T0);
break;
case 0x8f: /* pop Ev */
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
ot = gen_pop_T0(s);
if (mod == 3) {
/* NOTE: order is important for pop %sp */
gen_pop_update(s, ot);
rm = (modrm & 7) | REX_B(s);
gen_op_mov_reg_v(s, ot, rm, s->T0);
} else {
/* NOTE: order is important too for MMU exceptions */
s->popl_esp_hack = 1 << ot;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
s->popl_esp_hack = 0;
gen_pop_update(s, ot);
}
break;
case 0xc8: /* enter */
{
int level;
val = x86_lduw_code(env, s);
level = x86_ldub_code(env, s);
gen_enter(s, val, level);
}
break;
case 0xc9: /* leave */
gen_leave(s);
break;
case 0x06: /* push es */
case 0x0e: /* push cs */
case 0x16: /* push ss */
case 0x1e: /* push ds */
if (CODE64(s))
goto illegal_op;
gen_op_movl_T0_seg(s, b >> 3);
gen_push_v(s, s->T0);
break;
case 0x1a0: /* push fs */
case 0x1a8: /* push gs */
gen_op_movl_T0_seg(s, (b >> 3) & 7);
gen_push_v(s, s->T0);
break;
case 0x07: /* pop es */
case 0x17: /* pop ss */
case 0x1f: /* pop ds */
if (CODE64(s))
goto illegal_op;
reg = b >> 3;
ot = gen_pop_T0(s);
gen_movl_seg_T0(s, reg);
gen_pop_update(s, ot);
break;
case 0x1a1: /* pop fs */
case 0x1a9: /* pop gs */
ot = gen_pop_T0(s);
gen_movl_seg_T0(s, (b >> 3) & 7);
gen_pop_update(s, ot);
break;
/**************************/
/* mov */
case 0x88:
case 0x89: /* mov Gv, Ev */
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
/* generate a generic store */
gen_ldst_modrm(env, s, modrm, ot, reg, 1);
break;
case 0xc6:
case 0xc7: /* mov Ev, Iv */
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
if (mod != 3) {
s->rip_offset = insn_const_size(ot);
gen_lea_modrm(env, s, modrm);
}
val = insn_get(env, s, ot);
tcg_gen_movi_tl(s->T0, val);
if (mod != 3) {
gen_op_st_v(s, ot, s->T0, s->A0);
} else {
gen_op_mov_reg_v(s, ot, (modrm & 7) | REX_B(s), s->T0);
}
break;
case 0x8a:
case 0x8b: /* mov Ev, Gv */
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_op_mov_reg_v(s, ot, reg, s->T0);
break;
case 0x8e: /* mov seg, Gv */
modrm = x86_ldub_code(env, s);
reg = (modrm >> 3) & 7;
if (reg >= 6 || reg == R_CS)
goto illegal_op;
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
gen_movl_seg_T0(s, reg);
break;
case 0x8c: /* mov Gv, seg */
modrm = x86_ldub_code(env, s);
reg = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
if (reg >= 6)
goto illegal_op;
gen_op_movl_T0_seg(s, reg);
ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
case 0x1b6: /* movzbS Gv, Eb */
case 0x1b7: /* movzwS Gv, Eb */
case 0x1be: /* movsbS Gv, Eb */
case 0x1bf: /* movswS Gv, Eb */
{
MemOp d_ot;
MemOp s_ot;
/* d_ot is the size of destination */
d_ot = dflag;
/* ot is the size of source */
ot = (b & 1) + MO_8;
/* s_ot is the sign+size of source */
s_ot = b & 8 ? MO_SIGN | ot : ot;
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
if (mod == 3) {
if (s_ot == MO_SB && byte_reg_is_xH(s, rm)) {
tcg_gen_sextract_tl(s->T0, cpu_regs[rm - 4], 8, 8);
} else {
gen_op_mov_v_reg(s, ot, s->T0, rm);
switch (s_ot) {
case MO_UB:
tcg_gen_ext8u_tl(s->T0, s->T0);
break;
case MO_SB:
tcg_gen_ext8s_tl(s->T0, s->T0);
break;
case MO_UW:
tcg_gen_ext16u_tl(s->T0, s->T0);
break;
default:
case MO_SW:
tcg_gen_ext16s_tl(s->T0, s->T0);
break;
}
}
gen_op_mov_reg_v(s, d_ot, reg, s->T0);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, s_ot, s->T0, s->A0);
gen_op_mov_reg_v(s, d_ot, reg, s->T0);
}
}
break;
case 0x8d: /* lea */
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
if (mod == 3)
goto illegal_op;
reg = ((modrm >> 3) & 7) | REX_R(s);
{
AddressParts a = gen_lea_modrm_0(env, s, modrm);
TCGv ea = gen_lea_modrm_1(s, a, false);
gen_lea_v_seg(s, s->aflag, ea, -1, -1);
gen_op_mov_reg_v(s, dflag, reg, s->A0);
}
break;
case 0xa0: /* mov EAX, Ov */
case 0xa1:
case 0xa2: /* mov Ov, EAX */
case 0xa3:
{
target_ulong offset_addr;
ot = mo_b_d(b, dflag);
offset_addr = insn_get_addr(env, s, s->aflag);
tcg_gen_movi_tl(s->A0, offset_addr);
gen_add_A0_ds_seg(s);
if ((b & 2) == 0) {
gen_op_ld_v(s, ot, s->T0, s->A0);
gen_op_mov_reg_v(s, ot, R_EAX, s->T0);
} else {
gen_op_mov_v_reg(s, ot, s->T0, R_EAX);
gen_op_st_v(s, ot, s->T0, s->A0);
}
}
break;
case 0xd7: /* xlat */
tcg_gen_mov_tl(s->A0, cpu_regs[R_EBX]);
tcg_gen_ext8u_tl(s->T0, cpu_regs[R_EAX]);
tcg_gen_add_tl(s->A0, s->A0, s->T0);
gen_extu(s->aflag, s->A0);
gen_add_A0_ds_seg(s);
gen_op_ld_v(s, MO_8, s->T0, s->A0);
gen_op_mov_reg_v(s, MO_8, R_EAX, s->T0);
break;
case 0xb0 ... 0xb7: /* mov R, Ib */
val = insn_get(env, s, MO_8);
tcg_gen_movi_tl(s->T0, val);
gen_op_mov_reg_v(s, MO_8, (b & 7) | REX_B(s), s->T0);
break;
case 0xb8 ... 0xbf: /* mov R, Iv */
#ifdef TARGET_X86_64
if (dflag == MO_64) {
uint64_t tmp;
/* 64 bit case */
tmp = x86_ldq_code(env, s);
reg = (b & 7) | REX_B(s);
tcg_gen_movi_tl(s->T0, tmp);
gen_op_mov_reg_v(s, MO_64, reg, s->T0);
} else
#endif
{
ot = dflag;
val = insn_get(env, s, ot);
reg = (b & 7) | REX_B(s);
tcg_gen_movi_tl(s->T0, val);
gen_op_mov_reg_v(s, ot, reg, s->T0);
}
break;
case 0x91 ... 0x97: /* xchg R, EAX */
do_xchg_reg_eax:
ot = dflag;
reg = (b & 7) | REX_B(s);
rm = R_EAX;
goto do_xchg_reg;
case 0x86:
case 0x87: /* xchg Ev, Gv */
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
mod = (modrm >> 6) & 3;
if (mod == 3) {
rm = (modrm & 7) | REX_B(s);
do_xchg_reg:
gen_op_mov_v_reg(s, ot, s->T0, reg);
gen_op_mov_v_reg(s, ot, s->T1, rm);
gen_op_mov_reg_v(s, ot, rm, s->T0);
gen_op_mov_reg_v(s, ot, reg, s->T1);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_mov_v_reg(s, ot, s->T0, reg);
/* for xchg, lock is implicit */
tcg_gen_atomic_xchg_tl(s->T1, s->A0, s->T0,
s->mem_index, ot | MO_LE);
gen_op_mov_reg_v(s, ot, reg, s->T1);
}
break;
case 0xc4: /* les Gv */
/* In CODE64 this is VEX3; see above. */
op = R_ES;
goto do_lxx;
case 0xc5: /* lds Gv */
/* In CODE64 this is VEX2; see above. */
op = R_DS;
goto do_lxx;
case 0x1b2: /* lss Gv */
op = R_SS;
goto do_lxx;
case 0x1b4: /* lfs Gv */
op = R_FS;
goto do_lxx;
case 0x1b5: /* lgs Gv */
op = R_GS;
do_lxx:
ot = dflag != MO_16 ? MO_32 : MO_16;
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
mod = (modrm >> 6) & 3;
if (mod == 3)
goto illegal_op;
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, s->T1, s->A0);
gen_add_A0_im(s, 1 << ot);
/* load the segment first to handle exceptions properly */
gen_op_ld_v(s, MO_16, s->T0, s->A0);
gen_movl_seg_T0(s, op);
/* then put the data */
gen_op_mov_reg_v(s, ot, reg, s->T1);
break;
/************************/
/* shifts */
case 0xc0:
case 0xc1:
/* shift Ev,Ib */
shift = 2;
grp2:
{
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
op = (modrm >> 3) & 7;
if (mod != 3) {
if (shift == 2) {
s->rip_offset = 1;
}
gen_lea_modrm(env, s, modrm);
opreg = OR_TMP0;
} else {
opreg = (modrm & 7) | REX_B(s);
}
/* simpler op */
if (shift == 0) {
gen_shift(s, op, ot, opreg, OR_ECX);
} else {
if (shift == 2) {
shift = x86_ldub_code(env, s);
}
gen_shifti(s, op, ot, opreg, shift);
}
}
break;
case 0xd0:
case 0xd1:
/* shift Ev,1 */
shift = 1;
goto grp2;
case 0xd2:
case 0xd3:
/* shift Ev,cl */
shift = 0;
goto grp2;
case 0x1a4: /* shld imm */
op = 0;
shift = 1;
goto do_shiftd;
case 0x1a5: /* shld cl */
op = 0;
shift = 0;
goto do_shiftd;
case 0x1ac: /* shrd imm */
op = 1;
shift = 1;
goto do_shiftd;
case 0x1ad: /* shrd cl */
op = 1;
shift = 0;
do_shiftd:
ot = dflag;
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
reg = ((modrm >> 3) & 7) | REX_R(s);
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
opreg = OR_TMP0;
} else {
opreg = rm;
}
gen_op_mov_v_reg(s, ot, s->T1, reg);
if (shift) {
TCGv imm = tcg_constant_tl(x86_ldub_code(env, s));
gen_shiftd_rm_T1(s, ot, opreg, op, imm);
} else {
gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]);
}
break;
/************************/
/* floats */
case 0xd8 ... 0xdf:
{
bool update_fip = true;
if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
/* if CR0.EM or CR0.TS are set, generate an FPU exception */
/* XXX: what to do if illegal op ? */
gen_exception(s, EXCP07_PREX);
break;
}
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
rm = modrm & 7;
op = ((b & 7) << 3) | ((modrm >> 3) & 7);
if (mod != 3) {
/* memory op */
AddressParts a = gen_lea_modrm_0(env, s, modrm);
TCGv ea = gen_lea_modrm_1(s, a, false);
TCGv last_addr = tcg_temp_new();
bool update_fdp = true;
tcg_gen_mov_tl(last_addr, ea);
gen_lea_v_seg(s, s->aflag, ea, a.def_seg, s->override);
switch (op) {
case 0x00 ... 0x07: /* fxxxs */
case 0x10 ... 0x17: /* fixxxl */
case 0x20 ... 0x27: /* fxxxl */
case 0x30 ... 0x37: /* fixxx */
{
int op1;
op1 = op & 7;
switch (op >> 4) {
case 0:
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
gen_helper_flds_FT0(tcg_env, s->tmp2_i32);
break;
case 1:
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
gen_helper_fildl_FT0(tcg_env, s->tmp2_i32);
break;
case 2:
tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0,
s->mem_index, MO_LEUQ);
gen_helper_fldl_FT0(tcg_env, s->tmp1_i64);
break;
case 3:
default:
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LESW);
gen_helper_fildl_FT0(tcg_env, s->tmp2_i32);
break;
}
gen_helper_fp_arith_ST0_FT0(op1);
if (op1 == 3) {
/* fcomp needs pop */
gen_helper_fpop(tcg_env);
}
}
break;
case 0x08: /* flds */
case 0x0a: /* fsts */
case 0x0b: /* fstps */
case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
switch (op & 7) {
case 0:
switch (op >> 4) {
case 0:
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
gen_helper_flds_ST0(tcg_env, s->tmp2_i32);
break;
case 1:
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
gen_helper_fildl_ST0(tcg_env, s->tmp2_i32);
break;
case 2:
tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0,
s->mem_index, MO_LEUQ);
gen_helper_fldl_ST0(tcg_env, s->tmp1_i64);
break;
case 3:
default:
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LESW);
gen_helper_fildl_ST0(tcg_env, s->tmp2_i32);
break;
}
break;
case 1:
/* XXX: the corresponding CPUID bit must be tested ! */
switch (op >> 4) {
case 1:
gen_helper_fisttl_ST0(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
break;
case 2:
gen_helper_fisttll_ST0(s->tmp1_i64, tcg_env);
tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0,
s->mem_index, MO_LEUQ);
break;
case 3:
default:
gen_helper_fistt_ST0(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUW);
break;
}
gen_helper_fpop(tcg_env);
break;
default:
switch (op >> 4) {
case 0:
gen_helper_fsts_ST0(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
break;
case 1:
gen_helper_fistl_ST0(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
break;
case 2:
gen_helper_fstl_ST0(s->tmp1_i64, tcg_env);
tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0,
s->mem_index, MO_LEUQ);
break;
case 3:
default:
gen_helper_fist_ST0(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUW);
break;
}
if ((op & 7) == 3) {
gen_helper_fpop(tcg_env);
}
break;
}
break;
case 0x0c: /* fldenv mem */
gen_helper_fldenv(tcg_env, s->A0,
tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x0d: /* fldcw mem */
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUW);
gen_helper_fldcw(tcg_env, s->tmp2_i32);
update_fip = update_fdp = false;
break;
case 0x0e: /* fnstenv mem */
gen_helper_fstenv(tcg_env, s->A0,
tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x0f: /* fnstcw mem */
gen_helper_fnstcw(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUW);
update_fip = update_fdp = false;
break;
case 0x1d: /* fldt mem */
gen_helper_fldt_ST0(tcg_env, s->A0);
break;
case 0x1f: /* fstpt mem */
gen_helper_fstt_ST0(tcg_env, s->A0);
gen_helper_fpop(tcg_env);
break;
case 0x2c: /* frstor mem */
gen_helper_frstor(tcg_env, s->A0,
tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x2e: /* fnsave mem */
gen_helper_fsave(tcg_env, s->A0,
tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x2f: /* fnstsw mem */
gen_helper_fnstsw(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUW);
update_fip = update_fdp = false;
break;
case 0x3c: /* fbld */
gen_helper_fbld_ST0(tcg_env, s->A0);
break;
case 0x3e: /* fbstp */
gen_helper_fbst_ST0(tcg_env, s->A0);
gen_helper_fpop(tcg_env);
break;
case 0x3d: /* fildll */
tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0,
s->mem_index, MO_LEUQ);
gen_helper_fildll_ST0(tcg_env, s->tmp1_i64);
break;
case 0x3f: /* fistpll */
gen_helper_fistll_ST0(s->tmp1_i64, tcg_env);
tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0,
s->mem_index, MO_LEUQ);
gen_helper_fpop(tcg_env);
break;
default:
goto unknown_op;
}
if (update_fdp) {
int last_seg = s->override >= 0 ? s->override : a.def_seg;
tcg_gen_ld_i32(s->tmp2_i32, tcg_env,
offsetof(CPUX86State,
segs[last_seg].selector));
tcg_gen_st16_i32(s->tmp2_i32, tcg_env,
offsetof(CPUX86State, fpds));
tcg_gen_st_tl(last_addr, tcg_env,
offsetof(CPUX86State, fpdp));
}
} else {
/* register float ops */
opreg = rm;
switch (op) {
case 0x08: /* fld sti */
gen_helper_fpush(tcg_env);
gen_helper_fmov_ST0_STN(tcg_env,
tcg_constant_i32((opreg + 1) & 7));
break;
case 0x09: /* fxchg sti */
case 0x29: /* fxchg4 sti, undocumented op */
case 0x39: /* fxchg7 sti, undocumented op */
gen_helper_fxchg_ST0_STN(tcg_env, tcg_constant_i32(opreg));
break;
case 0x0a: /* grp d9/2 */
switch (rm) {
case 0: /* fnop */
/*
* check exceptions (FreeBSD FPU probe)
* needs to be treated as I/O because of ferr_irq
*/
translator_io_start(&s->base);
gen_helper_fwait(tcg_env);
update_fip = false;
break;
default:
goto unknown_op;
}
break;
case 0x0c: /* grp d9/4 */
switch (rm) {
case 0: /* fchs */
gen_helper_fchs_ST0(tcg_env);
break;
case 1: /* fabs */
gen_helper_fabs_ST0(tcg_env);
break;
case 4: /* ftst */
gen_helper_fldz_FT0(tcg_env);
gen_helper_fcom_ST0_FT0(tcg_env);
break;
case 5: /* fxam */
gen_helper_fxam_ST0(tcg_env);
break;
default:
goto unknown_op;
}
break;
case 0x0d: /* grp d9/5 */
{
switch (rm) {
case 0:
gen_helper_fpush(tcg_env);
gen_helper_fld1_ST0(tcg_env);
break;
case 1:
gen_helper_fpush(tcg_env);
gen_helper_fldl2t_ST0(tcg_env);
break;
case 2:
gen_helper_fpush(tcg_env);
gen_helper_fldl2e_ST0(tcg_env);
break;
case 3:
gen_helper_fpush(tcg_env);
gen_helper_fldpi_ST0(tcg_env);
break;
case 4:
gen_helper_fpush(tcg_env);
gen_helper_fldlg2_ST0(tcg_env);
break;
case 5:
gen_helper_fpush(tcg_env);
gen_helper_fldln2_ST0(tcg_env);
break;
case 6:
gen_helper_fpush(tcg_env);
gen_helper_fldz_ST0(tcg_env);
break;
default:
goto unknown_op;
}
}
break;
case 0x0e: /* grp d9/6 */
switch (rm) {
case 0: /* f2xm1 */
gen_helper_f2xm1(tcg_env);
break;
case 1: /* fyl2x */
gen_helper_fyl2x(tcg_env);
break;
case 2: /* fptan */
gen_helper_fptan(tcg_env);
break;
case 3: /* fpatan */
gen_helper_fpatan(tcg_env);
break;
case 4: /* fxtract */
gen_helper_fxtract(tcg_env);
break;
case 5: /* fprem1 */
gen_helper_fprem1(tcg_env);
break;
case 6: /* fdecstp */
gen_helper_fdecstp(tcg_env);
break;
default:
case 7: /* fincstp */
gen_helper_fincstp(tcg_env);
break;
}
break;
case 0x0f: /* grp d9/7 */
switch (rm) {
case 0: /* fprem */
gen_helper_fprem(tcg_env);
break;
case 1: /* fyl2xp1 */
gen_helper_fyl2xp1(tcg_env);
break;
case 2: /* fsqrt */
gen_helper_fsqrt(tcg_env);
break;
case 3: /* fsincos */
gen_helper_fsincos(tcg_env);
break;
case 5: /* fscale */
gen_helper_fscale(tcg_env);
break;
case 4: /* frndint */
gen_helper_frndint(tcg_env);
break;
case 6: /* fsin */
gen_helper_fsin(tcg_env);
break;
default:
case 7: /* fcos */
gen_helper_fcos(tcg_env);
break;
}
break;
case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
{
int op1;
op1 = op & 7;
if (op >= 0x20) {
gen_helper_fp_arith_STN_ST0(op1, opreg);
if (op >= 0x30) {
gen_helper_fpop(tcg_env);
}
} else {
gen_helper_fmov_FT0_STN(tcg_env,
tcg_constant_i32(opreg));
gen_helper_fp_arith_ST0_FT0(op1);
}
}
break;
case 0x02: /* fcom */
case 0x22: /* fcom2, undocumented op */
gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
gen_helper_fcom_ST0_FT0(tcg_env);
break;
case 0x03: /* fcomp */
case 0x23: /* fcomp3, undocumented op */
case 0x32: /* fcomp5, undocumented op */
gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
gen_helper_fcom_ST0_FT0(tcg_env);
gen_helper_fpop(tcg_env);
break;
case 0x15: /* da/5 */
switch (rm) {
case 1: /* fucompp */
gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(1));
gen_helper_fucom_ST0_FT0(tcg_env);
gen_helper_fpop(tcg_env);
gen_helper_fpop(tcg_env);
break;
default:
goto unknown_op;
}
break;
case 0x1c:
switch (rm) {
case 0: /* feni (287 only, just do nop here) */
break;
case 1: /* fdisi (287 only, just do nop here) */
break;
case 2: /* fclex */
gen_helper_fclex(tcg_env);
update_fip = false;
break;
case 3: /* fninit */
gen_helper_fninit(tcg_env);
update_fip = false;
break;
case 4: /* fsetpm (287 only, just do nop here) */
break;
default:
goto unknown_op;
}
break;
case 0x1d: /* fucomi */
if (!(s->cpuid_features & CPUID_CMOV)) {
goto illegal_op;
}
gen_update_cc_op(s);
gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
gen_helper_fucomi_ST0_FT0(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x1e: /* fcomi */
if (!(s->cpuid_features & CPUID_CMOV)) {
goto illegal_op;
}
gen_update_cc_op(s);
gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
gen_helper_fcomi_ST0_FT0(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x28: /* ffree sti */
gen_helper_ffree_STN(tcg_env, tcg_constant_i32(opreg));
break;
case 0x2a: /* fst sti */
gen_helper_fmov_STN_ST0(tcg_env, tcg_constant_i32(opreg));
break;
case 0x2b: /* fstp sti */
case 0x0b: /* fstp1 sti, undocumented op */
case 0x3a: /* fstp8 sti, undocumented op */
case 0x3b: /* fstp9 sti, undocumented op */
gen_helper_fmov_STN_ST0(tcg_env, tcg_constant_i32(opreg));
gen_helper_fpop(tcg_env);
break;
case 0x2c: /* fucom st(i) */
gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
gen_helper_fucom_ST0_FT0(tcg_env);
break;
case 0x2d: /* fucomp st(i) */
gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
gen_helper_fucom_ST0_FT0(tcg_env);
gen_helper_fpop(tcg_env);
break;
case 0x33: /* de/3 */
switch (rm) {
case 1: /* fcompp */
gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(1));
gen_helper_fcom_ST0_FT0(tcg_env);
gen_helper_fpop(tcg_env);
gen_helper_fpop(tcg_env);
break;
default:
goto unknown_op;
}
break;
case 0x38: /* ffreep sti, undocumented op */
gen_helper_ffree_STN(tcg_env, tcg_constant_i32(opreg));
gen_helper_fpop(tcg_env);
break;
case 0x3c: /* df/4 */
switch (rm) {
case 0:
gen_helper_fnstsw(s->tmp2_i32, tcg_env);
tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32);
gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);
break;
default:
goto unknown_op;
}
break;
case 0x3d: /* fucomip */
if (!(s->cpuid_features & CPUID_CMOV)) {
goto illegal_op;
}
gen_update_cc_op(s);
gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
gen_helper_fucomi_ST0_FT0(tcg_env);
gen_helper_fpop(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x3e: /* fcomip */
if (!(s->cpuid_features & CPUID_CMOV)) {
goto illegal_op;
}
gen_update_cc_op(s);
gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
gen_helper_fcomi_ST0_FT0(tcg_env);
gen_helper_fpop(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x10 ... 0x13: /* fcmovxx */
case 0x18 ... 0x1b:
{
int op1;
TCGLabel *l1;
static const uint8_t fcmov_cc[8] = {
(JCC_B << 1),
(JCC_Z << 1),
(JCC_BE << 1),
(JCC_P << 1),
};
if (!(s->cpuid_features & CPUID_CMOV)) {
goto illegal_op;
}
op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
l1 = gen_new_label();
gen_jcc1_noeob(s, op1, l1);
gen_helper_fmov_ST0_STN(tcg_env,
tcg_constant_i32(opreg));
gen_set_label(l1);
}
break;
default:
goto unknown_op;
}
}
if (update_fip) {
tcg_gen_ld_i32(s->tmp2_i32, tcg_env,
offsetof(CPUX86State, segs[R_CS].selector));
tcg_gen_st16_i32(s->tmp2_i32, tcg_env,
offsetof(CPUX86State, fpcs));
tcg_gen_st_tl(eip_cur_tl(s),
tcg_env, offsetof(CPUX86State, fpip));
}
}
break;
/************************/
/* string ops */
case 0xa4: /* movsS */
case 0xa5:
ot = mo_b_d(b, dflag);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_movs(s, ot);
} else {
gen_movs(s, ot);
}
break;
case 0xaa: /* stosS */
case 0xab:
ot = mo_b_d(b, dflag);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_stos(s, ot);
} else {
gen_stos(s, ot);
}
break;
case 0xac: /* lodsS */
case 0xad:
ot = mo_b_d(b, dflag);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_lods(s, ot);
} else {
gen_lods(s, ot);
}
break;
case 0xae: /* scasS */
case 0xaf:
ot = mo_b_d(b, dflag);
if (prefixes & PREFIX_REPNZ) {
gen_repz_scas(s, ot, 1);
} else if (prefixes & PREFIX_REPZ) {
gen_repz_scas(s, ot, 0);
} else {
gen_scas(s, ot);
}
break;
case 0xa6: /* cmpsS */
case 0xa7:
ot = mo_b_d(b, dflag);
if (prefixes & PREFIX_REPNZ) {
gen_repz_cmps(s, ot, 1);
} else if (prefixes & PREFIX_REPZ) {
gen_repz_cmps(s, ot, 0);
} else {
gen_cmps(s, ot);
}
break;
case 0x6c: /* insS */
case 0x6d:
ot = mo_b_d32(b, dflag);
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_EDX]);
tcg_gen_ext16u_i32(s->tmp2_i32, s->tmp2_i32);
if (!gen_check_io(s, ot, s->tmp2_i32,
SVM_IOIO_TYPE_MASK | SVM_IOIO_STR_MASK)) {
break;
}
translator_io_start(&s->base);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_ins(s, ot);
} else {
gen_ins(s, ot);
}
break;
case 0x6e: /* outsS */
case 0x6f:
ot = mo_b_d32(b, dflag);
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_EDX]);
tcg_gen_ext16u_i32(s->tmp2_i32, s->tmp2_i32);
if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_STR_MASK)) {
break;
}
translator_io_start(&s->base);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_outs(s, ot);
} else {
gen_outs(s, ot);
}
break;
/************************/
/* port I/O */
case 0xe4:
case 0xe5:
ot = mo_b_d32(b, dflag);
val = x86_ldub_code(env, s);
tcg_gen_movi_i32(s->tmp2_i32, val);
if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_TYPE_MASK)) {
break;
}
translator_io_start(&s->base);
gen_helper_in_func(ot, s->T1, s->tmp2_i32);
gen_op_mov_reg_v(s, ot, R_EAX, s->T1);
gen_bpt_io(s, s->tmp2_i32, ot);
break;
case 0xe6:
case 0xe7:
ot = mo_b_d32(b, dflag);
val = x86_ldub_code(env, s);
tcg_gen_movi_i32(s->tmp2_i32, val);
if (!gen_check_io(s, ot, s->tmp2_i32, 0)) {
break;
}
translator_io_start(&s->base);
gen_op_mov_v_reg(s, ot, s->T1, R_EAX);
tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);
gen_helper_out_func(ot, s->tmp2_i32, s->tmp3_i32);
gen_bpt_io(s, s->tmp2_i32, ot);
break;
case 0xec:
case 0xed:
ot = mo_b_d32(b, dflag);
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_EDX]);
tcg_gen_ext16u_i32(s->tmp2_i32, s->tmp2_i32);
if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_TYPE_MASK)) {
break;
}
translator_io_start(&s->base);
gen_helper_in_func(ot, s->T1, s->tmp2_i32);
gen_op_mov_reg_v(s, ot, R_EAX, s->T1);
gen_bpt_io(s, s->tmp2_i32, ot);
break;
case 0xee:
case 0xef:
ot = mo_b_d32(b, dflag);
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_EDX]);
tcg_gen_ext16u_i32(s->tmp2_i32, s->tmp2_i32);
if (!gen_check_io(s, ot, s->tmp2_i32, 0)) {
break;
}
translator_io_start(&s->base);
gen_op_mov_v_reg(s, ot, s->T1, R_EAX);
tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);
gen_helper_out_func(ot, s->tmp2_i32, s->tmp3_i32);
gen_bpt_io(s, s->tmp2_i32, ot);
break;
/************************/
/* control */
case 0xc2: /* ret im */
val = x86_ldsw_code(env, s);
ot = gen_pop_T0(s);
gen_stack_update(s, val + (1 << ot));
/* Note that gen_pop_T0 uses a zero-extending load. */
gen_op_jmp_v(s, s->T0);
gen_bnd_jmp(s);
s->base.is_jmp = DISAS_JUMP;
break;
case 0xc3: /* ret */
ot = gen_pop_T0(s);
gen_pop_update(s, ot);
/* Note that gen_pop_T0 uses a zero-extending load. */
gen_op_jmp_v(s, s->T0);
gen_bnd_jmp(s);
s->base.is_jmp = DISAS_JUMP;
break;
case 0xca: /* lret im */
val = x86_ldsw_code(env, s);
do_lret:
if (PE(s) && !VM86(s)) {
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_lret_protected(tcg_env, tcg_constant_i32(dflag - 1),
tcg_constant_i32(val));
} else {
gen_stack_A0(s);
/* pop offset */
gen_op_ld_v(s, dflag, s->T0, s->A0);
/* NOTE: keeping EIP updated is not a problem in case of
exception */
gen_op_jmp_v(s, s->T0);
/* pop selector */
gen_add_A0_im(s, 1 << dflag);
gen_op_ld_v(s, dflag, s->T0, s->A0);
gen_op_movl_seg_T0_vm(s, R_CS);
/* add stack offset */
gen_stack_update(s, val + (2 << dflag));
}
s->base.is_jmp = DISAS_EOB_ONLY;
break;
case 0xcb: /* lret */
val = 0;
goto do_lret;
case 0xcf: /* iret */
gen_svm_check_intercept(s, SVM_EXIT_IRET);
if (!PE(s) || VM86(s)) {
/* real mode or vm86 mode */
if (!check_vm86_iopl(s)) {
break;
}
gen_helper_iret_real(tcg_env, tcg_constant_i32(dflag - 1));
} else {
gen_helper_iret_protected(tcg_env, tcg_constant_i32(dflag - 1),
eip_next_i32(s));
}
set_cc_op(s, CC_OP_EFLAGS);
s->base.is_jmp = DISAS_EOB_ONLY;
break;
case 0xe8: /* call im */
{
int diff = (dflag != MO_16
? (int32_t)insn_get(env, s, MO_32)
: (int16_t)insn_get(env, s, MO_16));
gen_push_v(s, eip_next_tl(s));
gen_bnd_jmp(s);
gen_jmp_rel(s, dflag, diff, 0);
}
break;
case 0x9a: /* lcall im */
{
unsigned int selector, offset;
if (CODE64(s))
goto illegal_op;
ot = dflag;
offset = insn_get(env, s, ot);
selector = insn_get(env, s, MO_16);
tcg_gen_movi_tl(s->T0, selector);
tcg_gen_movi_tl(s->T1, offset);
}
goto do_lcall;
case 0xe9: /* jmp im */
{
int diff = (dflag != MO_16
? (int32_t)insn_get(env, s, MO_32)
: (int16_t)insn_get(env, s, MO_16));
gen_bnd_jmp(s);
gen_jmp_rel(s, dflag, diff, 0);
}
break;
case 0xea: /* ljmp im */
{
unsigned int selector, offset;
if (CODE64(s))
goto illegal_op;
ot = dflag;
offset = insn_get(env, s, ot);
selector = insn_get(env, s, MO_16);
tcg_gen_movi_tl(s->T0, selector);
tcg_gen_movi_tl(s->T1, offset);
}
goto do_ljmp;
case 0xeb: /* jmp Jb */
{
int diff = (int8_t)insn_get(env, s, MO_8);
gen_jmp_rel(s, dflag, diff, 0);
}
break;
case 0x70 ... 0x7f: /* jcc Jb */
{
int diff = (int8_t)insn_get(env, s, MO_8);
gen_bnd_jmp(s);
gen_jcc(s, b, diff);
}
break;
case 0x180 ... 0x18f: /* jcc Jv */
{
int diff = (dflag != MO_16
? (int32_t)insn_get(env, s, MO_32)
: (int16_t)insn_get(env, s, MO_16));
gen_bnd_jmp(s);
gen_jcc(s, b, diff);
}
break;
case 0x190 ... 0x19f: /* setcc Gv */
modrm = x86_ldub_code(env, s);
gen_setcc1(s, b, s->T0);
gen_ldst_modrm(env, s, modrm, MO_8, OR_TMP0, 1);
break;
case 0x140 ... 0x14f: /* cmov Gv, Ev */
if (!(s->cpuid_features & CPUID_CMOV)) {
goto illegal_op;
}
ot = dflag;
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
gen_cmovcc1(env, s, ot, b, modrm, reg);
break;
/************************/
/* flags */
case 0x9c: /* pushf */
gen_svm_check_intercept(s, SVM_EXIT_PUSHF);
if (check_vm86_iopl(s)) {
gen_update_cc_op(s);
gen_helper_read_eflags(s->T0, tcg_env);
gen_push_v(s, s->T0);
}
break;
case 0x9d: /* popf */
gen_svm_check_intercept(s, SVM_EXIT_POPF);
if (check_vm86_iopl(s)) {
int mask = TF_MASK | AC_MASK | ID_MASK | NT_MASK;
if (CPL(s) == 0) {
mask |= IF_MASK | IOPL_MASK;
} else if (CPL(s) <= IOPL(s)) {
mask |= IF_MASK;
}
if (dflag == MO_16) {
mask &= 0xffff;
}
ot = gen_pop_T0(s);
gen_helper_write_eflags(tcg_env, s->T0, tcg_constant_i32(mask));
gen_pop_update(s, ot);
set_cc_op(s, CC_OP_EFLAGS);
/* abort translation because TF/AC flag may change */
s->base.is_jmp = DISAS_EOB_NEXT;
}
break;
case 0x9e: /* sahf */
if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
goto illegal_op;
tcg_gen_shri_tl(s->T0, cpu_regs[R_EAX], 8);
gen_compute_eflags(s);
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
tcg_gen_andi_tl(s->T0, s->T0, CC_S | CC_Z | CC_A | CC_P | CC_C);
tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, s->T0);
break;
case 0x9f: /* lahf */
if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
goto illegal_op;
gen_compute_eflags(s);
/* Note: gen_compute_eflags() only gives the condition codes */
tcg_gen_ori_tl(s->T0, cpu_cc_src, 0x02);
tcg_gen_deposit_tl(cpu_regs[R_EAX], cpu_regs[R_EAX], s->T0, 8, 8);
break;
case 0xf5: /* cmc */
gen_compute_eflags(s);
tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);
break;
case 0xf8: /* clc */
gen_compute_eflags(s);
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C);
break;
case 0xf9: /* stc */
gen_compute_eflags(s);
tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C);
break;
case 0xfc: /* cld */
tcg_gen_movi_i32(s->tmp2_i32, 1);
tcg_gen_st_i32(s->tmp2_i32, tcg_env, offsetof(CPUX86State, df));
break;
case 0xfd: /* std */
tcg_gen_movi_i32(s->tmp2_i32, -1);
tcg_gen_st_i32(s->tmp2_i32, tcg_env, offsetof(CPUX86State, df));
break;
/************************/
/* bit operations */
case 0x1ba: /* bt/bts/btr/btc Gv, im */
ot = dflag;
modrm = x86_ldub_code(env, s);
op = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
if (mod != 3) {
s->rip_offset = 1;
gen_lea_modrm(env, s, modrm);
if (!(s->prefix & PREFIX_LOCK)) {
gen_op_ld_v(s, ot, s->T0, s->A0);
}
} else {
gen_op_mov_v_reg(s, ot, s->T0, rm);
}
/* load shift */
val = x86_ldub_code(env, s);
tcg_gen_movi_tl(s->T1, val);
if (op < 4)
goto unknown_op;
op -= 4;
goto bt_op;
case 0x1a3: /* bt Gv, Ev */
op = 0;
goto do_btx;
case 0x1ab: /* bts */
op = 1;
goto do_btx;
case 0x1b3: /* btr */
op = 2;
goto do_btx;
case 0x1bb: /* btc */
op = 3;
do_btx:
ot = dflag;
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
gen_op_mov_v_reg(s, MO_32, s->T1, reg);
if (mod != 3) {
AddressParts a = gen_lea_modrm_0(env, s, modrm);
/* specific case: we need to add a displacement */
gen_exts(ot, s->T1);
tcg_gen_sari_tl(s->tmp0, s->T1, 3 + ot);
tcg_gen_shli_tl(s->tmp0, s->tmp0, ot);
tcg_gen_add_tl(s->A0, gen_lea_modrm_1(s, a, false), s->tmp0);
gen_lea_v_seg(s, s->aflag, s->A0, a.def_seg, s->override);
if (!(s->prefix & PREFIX_LOCK)) {
gen_op_ld_v(s, ot, s->T0, s->A0);
}
} else {
gen_op_mov_v_reg(s, ot, s->T0, rm);
}
bt_op:
tcg_gen_andi_tl(s->T1, s->T1, (1 << (3 + ot)) - 1);
tcg_gen_movi_tl(s->tmp0, 1);
tcg_gen_shl_tl(s->tmp0, s->tmp0, s->T1);
if (s->prefix & PREFIX_LOCK) {
switch (op) {
case 0: /* bt */
/* Needs no atomic ops; we suppressed the normal
memory load for LOCK above so do it now. */
gen_op_ld_v(s, ot, s->T0, s->A0);
break;
case 1: /* bts */
tcg_gen_atomic_fetch_or_tl(s->T0, s->A0, s->tmp0,
s->mem_index, ot | MO_LE);
break;
case 2: /* btr */
tcg_gen_not_tl(s->tmp0, s->tmp0);
tcg_gen_atomic_fetch_and_tl(s->T0, s->A0, s->tmp0,
s->mem_index, ot | MO_LE);
break;
default:
case 3: /* btc */
tcg_gen_atomic_fetch_xor_tl(s->T0, s->A0, s->tmp0,
s->mem_index, ot | MO_LE);
break;
}
tcg_gen_shr_tl(s->tmp4, s->T0, s->T1);
} else {
tcg_gen_shr_tl(s->tmp4, s->T0, s->T1);
switch (op) {
case 0: /* bt */
/* Data already loaded; nothing to do. */
break;
case 1: /* bts */
tcg_gen_or_tl(s->T0, s->T0, s->tmp0);
break;
case 2: /* btr */
tcg_gen_andc_tl(s->T0, s->T0, s->tmp0);
break;
default:
case 3: /* btc */
tcg_gen_xor_tl(s->T0, s->T0, s->tmp0);
break;
}
if (op != 0) {
if (mod != 3) {
gen_op_st_v(s, ot, s->T0, s->A0);
} else {
gen_op_mov_reg_v(s, ot, rm, s->T0);
}
}
}
/* Delay all CC updates until after the store above. Note that
C is the result of the test, Z is unchanged, and the others
are all undefined. */
switch (s->cc_op) {
case CC_OP_MULB ... CC_OP_MULQ:
case CC_OP_ADDB ... CC_OP_ADDQ:
case CC_OP_ADCB ... CC_OP_ADCQ:
case CC_OP_SUBB ... CC_OP_SUBQ:
case CC_OP_SBBB ... CC_OP_SBBQ:
case CC_OP_LOGICB ... CC_OP_LOGICQ:
case CC_OP_INCB ... CC_OP_INCQ:
case CC_OP_DECB ... CC_OP_DECQ:
case CC_OP_SHLB ... CC_OP_SHLQ:
case CC_OP_SARB ... CC_OP_SARQ:
case CC_OP_BMILGB ... CC_OP_BMILGQ:
/* Z was going to be computed from the non-zero status of CC_DST.
We can get that same Z value (and the new C value) by leaving
CC_DST alone, setting CC_SRC, and using a CC_OP_SAR of the
same width. */
tcg_gen_mov_tl(cpu_cc_src, s->tmp4);
set_cc_op(s, ((s->cc_op - CC_OP_MULB) & 3) + CC_OP_SARB);
break;
default:
/* Otherwise, generate EFLAGS and replace the C bit. */
gen_compute_eflags(s);
tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, s->tmp4,
ctz32(CC_C), 1);
break;
}
break;
case 0x1bc: /* bsf / tzcnt */
case 0x1bd: /* bsr / lzcnt */
ot = dflag;
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_extu(ot, s->T0);
/* Note that lzcnt and tzcnt are in different extensions. */
if ((prefixes & PREFIX_REPZ)
&& (b & 1
? s->cpuid_ext3_features & CPUID_EXT3_ABM
: s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1)) {
int size = 8 << ot;
/* For lzcnt/tzcnt, C bit is defined related to the input. */
tcg_gen_mov_tl(cpu_cc_src, s->T0);
if (b & 1) {
/* For lzcnt, reduce the target_ulong result by the
number of zeros that we expect to find at the top. */
tcg_gen_clzi_tl(s->T0, s->T0, TARGET_LONG_BITS);
tcg_gen_subi_tl(s->T0, s->T0, TARGET_LONG_BITS - size);
} else {
/* For tzcnt, a zero input must return the operand size. */
tcg_gen_ctzi_tl(s->T0, s->T0, size);
}
/* For lzcnt/tzcnt, Z bit is defined related to the result. */
gen_op_update1_cc(s);
set_cc_op(s, CC_OP_BMILGB + ot);
} else {
/* For bsr/bsf, only the Z bit is defined and it is related
to the input and not the result. */
tcg_gen_mov_tl(cpu_cc_dst, s->T0);
set_cc_op(s, CC_OP_LOGICB + ot);
/* ??? The manual says that the output is undefined when the
input is zero, but real hardware leaves it unchanged, and
real programs appear to depend on that. Accomplish this
by passing the output as the value to return upon zero. */
if (b & 1) {
/* For bsr, return the bit index of the first 1 bit,
not the count of leading zeros. */
tcg_gen_xori_tl(s->T1, cpu_regs[reg], TARGET_LONG_BITS - 1);
tcg_gen_clz_tl(s->T0, s->T0, s->T1);
tcg_gen_xori_tl(s->T0, s->T0, TARGET_LONG_BITS - 1);
} else {
tcg_gen_ctz_tl(s->T0, s->T0, cpu_regs[reg]);
}
}
gen_op_mov_reg_v(s, ot, reg, s->T0);
break;
/************************/
/* bcd */
case 0x27: /* daa */
if (CODE64(s))
goto illegal_op;
gen_update_cc_op(s);
gen_helper_daa(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x2f: /* das */
if (CODE64(s))
goto illegal_op;
gen_update_cc_op(s);
gen_helper_das(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x37: /* aaa */
if (CODE64(s))
goto illegal_op;
gen_update_cc_op(s);
gen_helper_aaa(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x3f: /* aas */
if (CODE64(s))
goto illegal_op;
gen_update_cc_op(s);
gen_helper_aas(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0xd4: /* aam */
if (CODE64(s))
goto illegal_op;
val = x86_ldub_code(env, s);
if (val == 0) {
gen_exception(s, EXCP00_DIVZ);
} else {
gen_helper_aam(tcg_env, tcg_constant_i32(val));
set_cc_op(s, CC_OP_LOGICB);
}
break;
case 0xd5: /* aad */
if (CODE64(s))
goto illegal_op;
val = x86_ldub_code(env, s);
gen_helper_aad(tcg_env, tcg_constant_i32(val));
set_cc_op(s, CC_OP_LOGICB);
break;
/************************/
/* misc */
case 0x90: /* nop */
/* XXX: correct lock test for all insn */
if (prefixes & PREFIX_LOCK) {
goto illegal_op;
}
/* If REX_B is set, then this is xchg eax, r8d, not a nop. */
if (REX_B(s)) {
goto do_xchg_reg_eax;
}
if (prefixes & PREFIX_REPZ) {
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_pause(tcg_env, cur_insn_len_i32(s));
s->base.is_jmp = DISAS_NORETURN;
}
break;
case 0x9b: /* fwait */
if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
(HF_MP_MASK | HF_TS_MASK)) {
gen_exception(s, EXCP07_PREX);
} else {
/* needs to be treated as I/O because of ferr_irq */
translator_io_start(&s->base);
gen_helper_fwait(tcg_env);
}
break;
case 0xcc: /* int3 */
gen_interrupt(s, EXCP03_INT3);
break;
case 0xcd: /* int N */
val = x86_ldub_code(env, s);
if (check_vm86_iopl(s)) {
gen_interrupt(s, val);
}
break;
case 0xce: /* into */
if (CODE64(s))
goto illegal_op;
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_into(tcg_env, cur_insn_len_i32(s));
break;
#ifdef WANT_ICEBP
case 0xf1: /* icebp (undocumented, exits to external debugger) */
gen_svm_check_intercept(s, SVM_EXIT_ICEBP);
gen_debug(s);
break;
#endif
case 0xfa: /* cli */
if (check_iopl(s)) {
gen_reset_eflags(s, IF_MASK);
}
break;
case 0xfb: /* sti */
if (check_iopl(s)) {
gen_set_eflags(s, IF_MASK);
/* interruptions are enabled only the first insn after sti */
gen_update_eip_next(s);
gen_eob_inhibit_irq(s, true);
}
break;
case 0x62: /* bound */
if (CODE64(s))
goto illegal_op;
ot = dflag;
modrm = x86_ldub_code(env, s);
reg = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
if (mod == 3)
goto illegal_op;
gen_op_mov_v_reg(s, ot, s->T0, reg);
gen_lea_modrm(env, s, modrm);
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
if (ot == MO_16) {
gen_helper_boundw(tcg_env, s->A0, s->tmp2_i32);
} else {
gen_helper_boundl(tcg_env, s->A0, s->tmp2_i32);
}
break;
case 0x1c8 ... 0x1cf: /* bswap reg */
reg = (b & 7) | REX_B(s);
#ifdef TARGET_X86_64
if (dflag == MO_64) {
tcg_gen_bswap64_i64(cpu_regs[reg], cpu_regs[reg]);
break;
}
#endif
tcg_gen_bswap32_tl(cpu_regs[reg], cpu_regs[reg], TCG_BSWAP_OZ);
break;
case 0xd6: /* salc */
if (CODE64(s))
goto illegal_op;
gen_compute_eflags_c(s, s->T0);
tcg_gen_neg_tl(s->T0, s->T0);
gen_op_mov_reg_v(s, MO_8, R_EAX, s->T0);
break;
case 0xe0: /* loopnz */
case 0xe1: /* loopz */
case 0xe2: /* loop */
case 0xe3: /* jecxz */
{
TCGLabel *l1, *l2;
int diff = (int8_t)insn_get(env, s, MO_8);
l1 = gen_new_label();
l2 = gen_new_label();
gen_update_cc_op(s);
b &= 3;
switch(b) {
case 0: /* loopnz */
case 1: /* loopz */
gen_op_add_reg_im(s, s->aflag, R_ECX, -1);
gen_op_jz_ecx(s, l2);
gen_jcc1(s, (JCC_Z << 1) | (b ^ 1), l1);
break;
case 2: /* loop */
gen_op_add_reg_im(s, s->aflag, R_ECX, -1);
gen_op_jnz_ecx(s, l1);
break;
default:
case 3: /* jcxz */
gen_op_jz_ecx(s, l1);
break;
}
gen_set_label(l2);
gen_jmp_rel_csize(s, 0, 1);
gen_set_label(l1);
gen_jmp_rel(s, dflag, diff, 0);
}
break;
case 0x130: /* wrmsr */
case 0x132: /* rdmsr */
if (check_cpl0(s)) {
gen_update_cc_op(s);
gen_update_eip_cur(s);
if (b & 2) {
gen_helper_rdmsr(tcg_env);
} else {
gen_helper_wrmsr(tcg_env);
s->base.is_jmp = DISAS_EOB_NEXT;
}
}
break;
case 0x131: /* rdtsc */
gen_update_cc_op(s);
gen_update_eip_cur(s);
translator_io_start(&s->base);
gen_helper_rdtsc(tcg_env);
break;
case 0x133: /* rdpmc */
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_rdpmc(tcg_env);
s->base.is_jmp = DISAS_NORETURN;
break;
case 0x134: /* sysenter */
/* For AMD SYSENTER is not valid in long mode */
if (LMA(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) {
goto illegal_op;
}
if (!PE(s)) {
gen_exception_gpf(s);
} else {
gen_helper_sysenter(tcg_env);
s->base.is_jmp = DISAS_EOB_ONLY;
}
break;
case 0x135: /* sysexit */
/* For AMD SYSEXIT is not valid in long mode */
if (LMA(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) {
goto illegal_op;
}
if (!PE(s) || CPL(s) != 0) {
gen_exception_gpf(s);
} else {
gen_helper_sysexit(tcg_env, tcg_constant_i32(dflag - 1));
s->base.is_jmp = DISAS_EOB_ONLY;
}
break;
case 0x105: /* syscall */
/* For Intel SYSCALL is only valid in long mode */
if (!LMA(s) && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1) {
goto illegal_op;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_syscall(tcg_env, cur_insn_len_i32(s));
/* TF handling for the syscall insn is different. The TF bit is checked
after the syscall insn completes. This allows #DB to not be
generated after one has entered CPL0 if TF is set in FMASK. */
gen_eob_worker(s, false, true);
break;
case 0x107: /* sysret */
/* For Intel SYSRET is only valid in long mode */
if (!LMA(s) && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1) {
goto illegal_op;
}
if (!PE(s) || CPL(s) != 0) {
gen_exception_gpf(s);
} else {
gen_helper_sysret(tcg_env, tcg_constant_i32(dflag - 1));
/* condition codes are modified only in long mode */
if (LMA(s)) {
set_cc_op(s, CC_OP_EFLAGS);
}
/* TF handling for the sysret insn is different. The TF bit is
checked after the sysret insn completes. This allows #DB to be
generated "as if" the syscall insn in userspace has just
completed. */
gen_eob_worker(s, false, true);
}
break;
case 0x1a2: /* cpuid */
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_cpuid(tcg_env);
break;
case 0xf4: /* hlt */
if (check_cpl0(s)) {
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_hlt(tcg_env, cur_insn_len_i32(s));
s->base.is_jmp = DISAS_NORETURN;
}
break;
case 0x100:
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
op = (modrm >> 3) & 7;
switch(op) {
case 0: /* sldt */
if (!PE(s) || VM86(s))
goto illegal_op;
if (s->flags & HF_UMIP_MASK && !check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_LDTR_READ);
tcg_gen_ld32u_tl(s->T0, tcg_env,
offsetof(CPUX86State, ldt.selector));
ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
case 2: /* lldt */
if (!PE(s) || VM86(s))
goto illegal_op;
if (check_cpl0(s)) {
gen_svm_check_intercept(s, SVM_EXIT_LDTR_WRITE);
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
gen_helper_lldt(tcg_env, s->tmp2_i32);
}
break;
case 1: /* str */
if (!PE(s) || VM86(s))
goto illegal_op;
if (s->flags & HF_UMIP_MASK && !check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_TR_READ);
tcg_gen_ld32u_tl(s->T0, tcg_env,
offsetof(CPUX86State, tr.selector));
ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
case 3: /* ltr */
if (!PE(s) || VM86(s))
goto illegal_op;
if (check_cpl0(s)) {
gen_svm_check_intercept(s, SVM_EXIT_TR_WRITE);
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
gen_helper_ltr(tcg_env, s->tmp2_i32);
}
break;
case 4: /* verr */
case 5: /* verw */
if (!PE(s) || VM86(s))
goto illegal_op;
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
gen_update_cc_op(s);
if (op == 4) {
gen_helper_verr(tcg_env, s->T0);
} else {
gen_helper_verw(tcg_env, s->T0);
}
set_cc_op(s, CC_OP_EFLAGS);
break;
default:
goto unknown_op;
}
break;
case 0x101:
modrm = x86_ldub_code(env, s);
switch (modrm) {
CASE_MODRM_MEM_OP(0): /* sgdt */
if (s->flags & HF_UMIP_MASK && !check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_GDTR_READ);
gen_lea_modrm(env, s, modrm);
tcg_gen_ld32u_tl(s->T0,
tcg_env, offsetof(CPUX86State, gdt.limit));
gen_op_st_v(s, MO_16, s->T0, s->A0);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(s->T0, tcg_env, offsetof(CPUX86State, gdt.base));
if (dflag == MO_16) {
tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);
}
gen_op_st_v(s, CODE64(s) + MO_32, s->T0, s->A0);
break;
case 0xc8: /* monitor */
if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || CPL(s) != 0) {
goto illegal_op;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
tcg_gen_mov_tl(s->A0, cpu_regs[R_EAX]);
gen_extu(s->aflag, s->A0);
gen_add_A0_ds_seg(s);
gen_helper_monitor(tcg_env, s->A0);
break;
case 0xc9: /* mwait */
if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || CPL(s) != 0) {
goto illegal_op;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_mwait(tcg_env, cur_insn_len_i32(s));
s->base.is_jmp = DISAS_NORETURN;
break;
case 0xca: /* clac */
if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP)
|| CPL(s) != 0) {
goto illegal_op;
}
gen_reset_eflags(s, AC_MASK);
s->base.is_jmp = DISAS_EOB_NEXT;
break;
case 0xcb: /* stac */
if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP)
|| CPL(s) != 0) {
goto illegal_op;
}
gen_set_eflags(s, AC_MASK);
s->base.is_jmp = DISAS_EOB_NEXT;
break;
CASE_MODRM_MEM_OP(1): /* sidt */
if (s->flags & HF_UMIP_MASK && !check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_IDTR_READ);
gen_lea_modrm(env, s, modrm);
tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, idt.limit));
gen_op_st_v(s, MO_16, s->T0, s->A0);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(s->T0, tcg_env, offsetof(CPUX86State, idt.base));
if (dflag == MO_16) {
tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);
}
gen_op_st_v(s, CODE64(s) + MO_32, s->T0, s->A0);
break;
case 0xd0: /* xgetbv */
if ((s->cpuid_ext_features & CPUID_EXT_XSAVE) == 0
|| (s->prefix & (PREFIX_LOCK | PREFIX_DATA
| PREFIX_REPZ | PREFIX_REPNZ))) {
goto illegal_op;
}
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]);
gen_helper_xgetbv(s->tmp1_i64, tcg_env, s->tmp2_i32);
tcg_gen_extr_i64_tl(cpu_regs[R_EAX], cpu_regs[R_EDX], s->tmp1_i64);
break;
case 0xd1: /* xsetbv */
if ((s->cpuid_ext_features & CPUID_EXT_XSAVE) == 0
|| (s->prefix & (PREFIX_LOCK | PREFIX_DATA
| PREFIX_REPZ | PREFIX_REPNZ))) {
goto illegal_op;
}
if (!check_cpl0(s)) {
break;
}
tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX],
cpu_regs[R_EDX]);
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]);
gen_helper_xsetbv(tcg_env, s->tmp2_i32, s->tmp1_i64);
/* End TB because translation flags may change. */
s->base.is_jmp = DISAS_EOB_NEXT;
break;
case 0xd8: /* VMRUN */
if (!SVME(s) || !PE(s)) {
goto illegal_op;
}
if (!check_cpl0(s)) {
break;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_vmrun(tcg_env, tcg_constant_i32(s->aflag - 1),
cur_insn_len_i32(s));
tcg_gen_exit_tb(NULL, 0);
s->base.is_jmp = DISAS_NORETURN;
break;
case 0xd9: /* VMMCALL */
if (!SVME(s)) {
goto illegal_op;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_vmmcall(tcg_env);
break;
case 0xda: /* VMLOAD */
if (!SVME(s) || !PE(s)) {
goto illegal_op;
}
if (!check_cpl0(s)) {
break;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_vmload(tcg_env, tcg_constant_i32(s->aflag - 1));
break;
case 0xdb: /* VMSAVE */
if (!SVME(s) || !PE(s)) {
goto illegal_op;
}
if (!check_cpl0(s)) {
break;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_vmsave(tcg_env, tcg_constant_i32(s->aflag - 1));
break;
case 0xdc: /* STGI */
if ((!SVME(s) && !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT))
|| !PE(s)) {
goto illegal_op;
}
if (!check_cpl0(s)) {
break;
}
gen_update_cc_op(s);
gen_helper_stgi(tcg_env);
s->base.is_jmp = DISAS_EOB_NEXT;
break;
case 0xdd: /* CLGI */
if (!SVME(s) || !PE(s)) {
goto illegal_op;
}
if (!check_cpl0(s)) {
break;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_clgi(tcg_env);
break;
case 0xde: /* SKINIT */
if ((!SVME(s) && !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT))
|| !PE(s)) {
goto illegal_op;
}
gen_svm_check_intercept(s, SVM_EXIT_SKINIT);
/* If not intercepted, not implemented -- raise #UD. */
goto illegal_op;
case 0xdf: /* INVLPGA */
if (!SVME(s) || !PE(s)) {
goto illegal_op;
}
if (!check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_INVLPGA);
if (s->aflag == MO_64) {
tcg_gen_mov_tl(s->A0, cpu_regs[R_EAX]);
} else {
tcg_gen_ext32u_tl(s->A0, cpu_regs[R_EAX]);
}
gen_helper_flush_page(tcg_env, s->A0);
s->base.is_jmp = DISAS_EOB_NEXT;
break;
CASE_MODRM_MEM_OP(2): /* lgdt */
if (!check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_GDTR_WRITE);
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, MO_16, s->T1, s->A0);
gen_add_A0_im(s, 2);
gen_op_ld_v(s, CODE64(s) + MO_32, s->T0, s->A0);
if (dflag == MO_16) {
tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);
}
tcg_gen_st_tl(s->T0, tcg_env, offsetof(CPUX86State, gdt.base));
tcg_gen_st32_tl(s->T1, tcg_env, offsetof(CPUX86State, gdt.limit));
break;
CASE_MODRM_MEM_OP(3): /* lidt */
if (!check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_IDTR_WRITE);
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, MO_16, s->T1, s->A0);
gen_add_A0_im(s, 2);
gen_op_ld_v(s, CODE64(s) + MO_32, s->T0, s->A0);
if (dflag == MO_16) {
tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);
}
tcg_gen_st_tl(s->T0, tcg_env, offsetof(CPUX86State, idt.base));
tcg_gen_st32_tl(s->T1, tcg_env, offsetof(CPUX86State, idt.limit));
break;
CASE_MODRM_OP(4): /* smsw */
if (s->flags & HF_UMIP_MASK && !check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_READ_CR0);
tcg_gen_ld_tl(s->T0, tcg_env, offsetof(CPUX86State, cr[0]));
/*
* In 32-bit mode, the higher 16 bits of the destination
* register are undefined. In practice CR0[31:0] is stored
* just like in 64-bit mode.
*/
mod = (modrm >> 6) & 3;
ot = (mod != 3 ? MO_16 : s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
case 0xee: /* rdpkru */
if (prefixes & PREFIX_LOCK) {
goto illegal_op;
}
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]);
gen_helper_rdpkru(s->tmp1_i64, tcg_env, s->tmp2_i32);
tcg_gen_extr_i64_tl(cpu_regs[R_EAX], cpu_regs[R_EDX], s->tmp1_i64);
break;
case 0xef: /* wrpkru */
if (prefixes & PREFIX_LOCK) {
goto illegal_op;
}
tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX],
cpu_regs[R_EDX]);
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]);
gen_helper_wrpkru(tcg_env, s->tmp2_i32, s->tmp1_i64);
break;
CASE_MODRM_OP(6): /* lmsw */
if (!check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0);
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
/*
* Only the 4 lower bits of CR0 are modified.
* PE cannot be set to zero if already set to one.
*/
tcg_gen_ld_tl(s->T1, tcg_env, offsetof(CPUX86State, cr[0]));
tcg_gen_andi_tl(s->T0, s->T0, 0xf);
tcg_gen_andi_tl(s->T1, s->T1, ~0xe);
tcg_gen_or_tl(s->T0, s->T0, s->T1);
gen_helper_write_crN(tcg_env, tcg_constant_i32(0), s->T0);
s->base.is_jmp = DISAS_EOB_NEXT;
break;
CASE_MODRM_MEM_OP(7): /* invlpg */
if (!check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_INVLPG);
gen_lea_modrm(env, s, modrm);
gen_helper_flush_page(tcg_env, s->A0);
s->base.is_jmp = DISAS_EOB_NEXT;
break;
case 0xf8: /* swapgs */
#ifdef TARGET_X86_64
if (CODE64(s)) {
if (check_cpl0(s)) {
tcg_gen_mov_tl(s->T0, cpu_seg_base[R_GS]);
tcg_gen_ld_tl(cpu_seg_base[R_GS], tcg_env,
offsetof(CPUX86State, kernelgsbase));
tcg_gen_st_tl(s->T0, tcg_env,
offsetof(CPUX86State, kernelgsbase));
}
break;
}
#endif
goto illegal_op;
case 0xf9: /* rdtscp */
if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP)) {
goto illegal_op;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
translator_io_start(&s->base);
gen_helper_rdtsc(tcg_env);
gen_helper_rdpid(s->T0, tcg_env);
gen_op_mov_reg_v(s, dflag, R_ECX, s->T0);
break;
default:
goto unknown_op;
}
break;
case 0x108: /* invd */
case 0x109: /* wbinvd; wbnoinvd with REPZ prefix */
if (check_cpl0(s)) {
gen_svm_check_intercept(s, (b & 1) ? SVM_EXIT_WBINVD : SVM_EXIT_INVD);
/* nothing to do */
}
break;
case 0x63: /* arpl or movslS (x86_64) */
#ifdef TARGET_X86_64
if (CODE64(s)) {
int d_ot;
/* d_ot is the size of destination */
d_ot = dflag;
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
if (mod == 3) {
gen_op_mov_v_reg(s, MO_32, s->T0, rm);
/* sign extend */
if (d_ot == MO_64) {
tcg_gen_ext32s_tl(s->T0, s->T0);
}
gen_op_mov_reg_v(s, d_ot, reg, s->T0);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, MO_32 | MO_SIGN, s->T0, s->A0);
gen_op_mov_reg_v(s, d_ot, reg, s->T0);
}
} else
#endif
{
TCGLabel *label1;
TCGv t0, t1, t2;
if (!PE(s) || VM86(s))
goto illegal_op;
t0 = tcg_temp_new();
t1 = tcg_temp_new();
t2 = tcg_temp_new();
ot = MO_16;
modrm = x86_ldub_code(env, s);
reg = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
rm = modrm & 7;
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, t0, s->A0);
} else {
gen_op_mov_v_reg(s, ot, t0, rm);
}
gen_op_mov_v_reg(s, ot, t1, reg);
tcg_gen_andi_tl(s->tmp0, t0, 3);
tcg_gen_andi_tl(t1, t1, 3);
tcg_gen_movi_tl(t2, 0);
label1 = gen_new_label();
tcg_gen_brcond_tl(TCG_COND_GE, s->tmp0, t1, label1);
tcg_gen_andi_tl(t0, t0, ~3);
tcg_gen_or_tl(t0, t0, t1);
tcg_gen_movi_tl(t2, CC_Z);
gen_set_label(label1);
if (mod != 3) {
gen_op_st_v(s, ot, t0, s->A0);
} else {
gen_op_mov_reg_v(s, ot, rm, t0);
}
gen_compute_eflags(s);
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2);
}
break;
case 0x102: /* lar */
case 0x103: /* lsl */
{
TCGLabel *label1;
TCGv t0;
if (!PE(s) || VM86(s))
goto illegal_op;
ot = dflag != MO_16 ? MO_32 : MO_16;
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
t0 = tcg_temp_new();
gen_update_cc_op(s);
if (b == 0x102) {
gen_helper_lar(t0, tcg_env, s->T0);
} else {
gen_helper_lsl(t0, tcg_env, s->T0);
}
tcg_gen_andi_tl(s->tmp0, cpu_cc_src, CC_Z);
label1 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, s->tmp0, 0, label1);
gen_op_mov_reg_v(s, ot, reg, t0);
gen_set_label(label1);
set_cc_op(s, CC_OP_EFLAGS);
}
break;
case 0x118:
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
op = (modrm >> 3) & 7;
switch(op) {
case 0: /* prefetchnta */
case 1: /* prefetchnt0 */
case 2: /* prefetchnt0 */
case 3: /* prefetchnt0 */
if (mod == 3)
goto illegal_op;
gen_nop_modrm(env, s, modrm);
/* nothing more to do */
break;
default: /* nop (multi byte) */
gen_nop_modrm(env, s, modrm);
break;
}
break;
case 0x11a:
modrm = x86_ldub_code(env, s);
if (s->flags & HF_MPX_EN_MASK) {
mod = (modrm >> 6) & 3;
reg = ((modrm >> 3) & 7) | REX_R(s);
if (prefixes & PREFIX_REPZ) {
/* bndcl */
if (reg >= 4
|| (prefixes & PREFIX_LOCK)
|| s->aflag == MO_16) {
goto illegal_op;
}
gen_bndck(env, s, modrm, TCG_COND_LTU, cpu_bndl[reg]);
} else if (prefixes & PREFIX_REPNZ) {
/* bndcu */
if (reg >= 4
|| (prefixes & PREFIX_LOCK)
|| s->aflag == MO_16) {
goto illegal_op;
}
TCGv_i64 notu = tcg_temp_new_i64();
tcg_gen_not_i64(notu, cpu_bndu[reg]);
gen_bndck(env, s, modrm, TCG_COND_GTU, notu);
} else if (prefixes & PREFIX_DATA) {
/* bndmov -- from reg/mem */
if (reg >= 4 || s->aflag == MO_16) {
goto illegal_op;
}
if (mod == 3) {
int reg2 = (modrm & 7) | REX_B(s);
if (reg2 >= 4 || (prefixes & PREFIX_LOCK)) {
goto illegal_op;
}
if (s->flags & HF_MPX_IU_MASK) {
tcg_gen_mov_i64(cpu_bndl[reg], cpu_bndl[reg2]);
tcg_gen_mov_i64(cpu_bndu[reg], cpu_bndu[reg2]);
}
} else {
gen_lea_modrm(env, s, modrm);
if (CODE64(s)) {
tcg_gen_qemu_ld_i64(cpu_bndl[reg], s->A0,
s->mem_index, MO_LEUQ);
tcg_gen_addi_tl(s->A0, s->A0, 8);
tcg_gen_qemu_ld_i64(cpu_bndu[reg], s->A0,
s->mem_index, MO_LEUQ);
} else {
tcg_gen_qemu_ld_i64(cpu_bndl[reg], s->A0,
s->mem_index, MO_LEUL);
tcg_gen_addi_tl(s->A0, s->A0, 4);
tcg_gen_qemu_ld_i64(cpu_bndu[reg], s->A0,
s->mem_index, MO_LEUL);
}
/* bnd registers are now in-use */
gen_set_hflag(s, HF_MPX_IU_MASK);
}
} else if (mod != 3) {
/* bndldx */
AddressParts a = gen_lea_modrm_0(env, s, modrm);
if (reg >= 4
|| (prefixes & PREFIX_LOCK)
|| s->aflag == MO_16
|| a.base < -1) {
goto illegal_op;
}
if (a.base >= 0) {
tcg_gen_addi_tl(s->A0, cpu_regs[a.base], a.disp);
} else {
tcg_gen_movi_tl(s->A0, 0);
}
gen_lea_v_seg(s, s->aflag, s->A0, a.def_seg, s->override);
if (a.index >= 0) {
tcg_gen_mov_tl(s->T0, cpu_regs[a.index]);
} else {
tcg_gen_movi_tl(s->T0, 0);
}
if (CODE64(s)) {
gen_helper_bndldx64(cpu_bndl[reg], tcg_env, s->A0, s->T0);
tcg_gen_ld_i64(cpu_bndu[reg], tcg_env,
offsetof(CPUX86State, mmx_t0.MMX_Q(0)));
} else {
gen_helper_bndldx32(cpu_bndu[reg], tcg_env, s->A0, s->T0);
tcg_gen_ext32u_i64(cpu_bndl[reg], cpu_bndu[reg]);
tcg_gen_shri_i64(cpu_bndu[reg], cpu_bndu[reg], 32);
}
gen_set_hflag(s, HF_MPX_IU_MASK);
}
}
gen_nop_modrm(env, s, modrm);
break;
case 0x11b:
modrm = x86_ldub_code(env, s);
if (s->flags & HF_MPX_EN_MASK) {
mod = (modrm >> 6) & 3;
reg = ((modrm >> 3) & 7) | REX_R(s);
if (mod != 3 && (prefixes & PREFIX_REPZ)) {
/* bndmk */
if (reg >= 4
|| (prefixes & PREFIX_LOCK)
|| s->aflag == MO_16) {
goto illegal_op;
}
AddressParts a = gen_lea_modrm_0(env, s, modrm);
if (a.base >= 0) {
tcg_gen_extu_tl_i64(cpu_bndl[reg], cpu_regs[a.base]);
if (!CODE64(s)) {
tcg_gen_ext32u_i64(cpu_bndl[reg], cpu_bndl[reg]);
}
} else if (a.base == -1) {
/* no base register has lower bound of 0 */
tcg_gen_movi_i64(cpu_bndl[reg], 0);
} else {
/* rip-relative generates #ud */
goto illegal_op;
}
tcg_gen_not_tl(s->A0, gen_lea_modrm_1(s, a, false));
if (!CODE64(s)) {
tcg_gen_ext32u_tl(s->A0, s->A0);
}
tcg_gen_extu_tl_i64(cpu_bndu[reg], s->A0);
/* bnd registers are now in-use */
gen_set_hflag(s, HF_MPX_IU_MASK);
break;
} else if (prefixes & PREFIX_REPNZ) {
/* bndcn */
if (reg >= 4
|| (prefixes & PREFIX_LOCK)
|| s->aflag == MO_16) {
goto illegal_op;
}
gen_bndck(env, s, modrm, TCG_COND_GTU, cpu_bndu[reg]);
} else if (prefixes & PREFIX_DATA) {
/* bndmov -- to reg/mem */
if (reg >= 4 || s->aflag == MO_16) {
goto illegal_op;
}
if (mod == 3) {
int reg2 = (modrm & 7) | REX_B(s);
if (reg2 >= 4 || (prefixes & PREFIX_LOCK)) {
goto illegal_op;
}
if (s->flags & HF_MPX_IU_MASK) {
tcg_gen_mov_i64(cpu_bndl[reg2], cpu_bndl[reg]);
tcg_gen_mov_i64(cpu_bndu[reg2], cpu_bndu[reg]);
}
} else {
gen_lea_modrm(env, s, modrm);
if (CODE64(s)) {
tcg_gen_qemu_st_i64(cpu_bndl[reg], s->A0,
s->mem_index, MO_LEUQ);
tcg_gen_addi_tl(s->A0, s->A0, 8);
tcg_gen_qemu_st_i64(cpu_bndu[reg], s->A0,
s->mem_index, MO_LEUQ);
} else {
tcg_gen_qemu_st_i64(cpu_bndl[reg], s->A0,
s->mem_index, MO_LEUL);
tcg_gen_addi_tl(s->A0, s->A0, 4);
tcg_gen_qemu_st_i64(cpu_bndu[reg], s->A0,
s->mem_index, MO_LEUL);
}
}
} else if (mod != 3) {
/* bndstx */
AddressParts a = gen_lea_modrm_0(env, s, modrm);
if (reg >= 4
|| (prefixes & PREFIX_LOCK)
|| s->aflag == MO_16
|| a.base < -1) {
goto illegal_op;
}
if (a.base >= 0) {
tcg_gen_addi_tl(s->A0, cpu_regs[a.base], a.disp);
} else {
tcg_gen_movi_tl(s->A0, 0);
}
gen_lea_v_seg(s, s->aflag, s->A0, a.def_seg, s->override);
if (a.index >= 0) {
tcg_gen_mov_tl(s->T0, cpu_regs[a.index]);
} else {
tcg_gen_movi_tl(s->T0, 0);
}
if (CODE64(s)) {
gen_helper_bndstx64(tcg_env, s->A0, s->T0,
cpu_bndl[reg], cpu_bndu[reg]);
} else {
gen_helper_bndstx32(tcg_env, s->A0, s->T0,
cpu_bndl[reg], cpu_bndu[reg]);
}
}
}
gen_nop_modrm(env, s, modrm);
break;
case 0x119: case 0x11c ... 0x11f: /* nop (multi byte) */
modrm = x86_ldub_code(env, s);
gen_nop_modrm(env, s, modrm);
break;
case 0x120: /* mov reg, crN */
case 0x122: /* mov crN, reg */
if (!check_cpl0(s)) {
break;
}
modrm = x86_ldub_code(env, s);
/*
* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
* AMD documentation (24594.pdf) and testing of Intel 386 and 486
* processors all show that the mod bits are assumed to be 1's,
* regardless of actual values.
*/
rm = (modrm & 7) | REX_B(s);
reg = ((modrm >> 3) & 7) | REX_R(s);
switch (reg) {
case 0:
if ((prefixes & PREFIX_LOCK) &&
(s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) {
reg = 8;
}
break;
case 2:
case 3:
case 4:
case 8:
break;
default:
goto unknown_op;
}
ot = (CODE64(s) ? MO_64 : MO_32);
translator_io_start(&s->base);
if (b & 2) {
gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0 + reg);
gen_op_mov_v_reg(s, ot, s->T0, rm);
gen_helper_write_crN(tcg_env, tcg_constant_i32(reg), s->T0);
s->base.is_jmp = DISAS_EOB_NEXT;
} else {
gen_svm_check_intercept(s, SVM_EXIT_READ_CR0 + reg);
gen_helper_read_crN(s->T0, tcg_env, tcg_constant_i32(reg));
gen_op_mov_reg_v(s, ot, rm, s->T0);
}
break;
case 0x121: /* mov reg, drN */
case 0x123: /* mov drN, reg */
if (check_cpl0(s)) {
modrm = x86_ldub_code(env, s);
/* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
* AMD documentation (24594.pdf) and testing of
* intel 386 and 486 processors all show that the mod bits
* are assumed to be 1's, regardless of actual values.
*/
rm = (modrm & 7) | REX_B(s);
reg = ((modrm >> 3) & 7) | REX_R(s);
if (CODE64(s))
ot = MO_64;
else
ot = MO_32;
if (reg >= 8) {
goto illegal_op;
}
if (b & 2) {
gen_svm_check_intercept(s, SVM_EXIT_WRITE_DR0 + reg);
gen_op_mov_v_reg(s, ot, s->T0, rm);
tcg_gen_movi_i32(s->tmp2_i32, reg);
gen_helper_set_dr(tcg_env, s->tmp2_i32, s->T0);
s->base.is_jmp = DISAS_EOB_NEXT;
} else {
gen_svm_check_intercept(s, SVM_EXIT_READ_DR0 + reg);
tcg_gen_movi_i32(s->tmp2_i32, reg);
gen_helper_get_dr(s->T0, tcg_env, s->tmp2_i32);
gen_op_mov_reg_v(s, ot, rm, s->T0);
}
}
break;
case 0x106: /* clts */
if (check_cpl0(s)) {
gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0);
gen_helper_clts(tcg_env);
/* abort block because static cpu state changed */
s->base.is_jmp = DISAS_EOB_NEXT;
}
break;
/* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
case 0x1c3: /* MOVNTI reg, mem */
if (!(s->cpuid_features & CPUID_SSE2))
goto illegal_op;
ot = mo_64_32(dflag);
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
if (mod == 3)
goto illegal_op;
reg = ((modrm >> 3) & 7) | REX_R(s);
/* generate a generic store */
gen_ldst_modrm(env, s, modrm, ot, reg, 1);
break;
case 0x1ae:
modrm = x86_ldub_code(env, s);
switch (modrm) {
CASE_MODRM_MEM_OP(0): /* fxsave */
if (!(s->cpuid_features & CPUID_FXSR)
|| (prefixes & PREFIX_LOCK)) {
goto illegal_op;
}
if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
gen_exception(s, EXCP07_PREX);
break;
}
gen_lea_modrm(env, s, modrm);
gen_helper_fxsave(tcg_env, s->A0);
break;
CASE_MODRM_MEM_OP(1): /* fxrstor */
if (!(s->cpuid_features & CPUID_FXSR)
|| (prefixes & PREFIX_LOCK)) {
goto illegal_op;
}
if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
gen_exception(s, EXCP07_PREX);
break;
}
gen_lea_modrm(env, s, modrm);
gen_helper_fxrstor(tcg_env, s->A0);
break;
CASE_MODRM_MEM_OP(2): /* ldmxcsr */
if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK)) {
goto illegal_op;
}
if (s->flags & HF_TS_MASK) {
gen_exception(s, EXCP07_PREX);
break;
}
gen_lea_modrm(env, s, modrm);
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL);
gen_helper_ldmxcsr(tcg_env, s->tmp2_i32);
break;
CASE_MODRM_MEM_OP(3): /* stmxcsr */
if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK)) {
goto illegal_op;
}
if (s->flags & HF_TS_MASK) {
gen_exception(s, EXCP07_PREX);
break;
}
gen_helper_update_mxcsr(tcg_env);
gen_lea_modrm(env, s, modrm);
tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, mxcsr));
gen_op_st_v(s, MO_32, s->T0, s->A0);
break;
CASE_MODRM_MEM_OP(4): /* xsave */
if ((s->cpuid_ext_features & CPUID_EXT_XSAVE) == 0
|| (prefixes & (PREFIX_LOCK | PREFIX_DATA
| PREFIX_REPZ | PREFIX_REPNZ))) {
goto illegal_op;
}
gen_lea_modrm(env, s, modrm);
tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX],
cpu_regs[R_EDX]);
gen_helper_xsave(tcg_env, s->A0, s->tmp1_i64);
break;
CASE_MODRM_MEM_OP(5): /* xrstor */
if ((s->cpuid_ext_features & CPUID_EXT_XSAVE) == 0
|| (prefixes & (PREFIX_LOCK | PREFIX_DATA
| PREFIX_REPZ | PREFIX_REPNZ))) {
goto illegal_op;
}
gen_lea_modrm(env, s, modrm);
tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX],
cpu_regs[R_EDX]);
gen_helper_xrstor(tcg_env, s->A0, s->tmp1_i64);
/* XRSTOR is how MPX is enabled, which changes how
we translate. Thus we need to end the TB. */
s->base.is_jmp = DISAS_EOB_NEXT;
break;
CASE_MODRM_MEM_OP(6): /* xsaveopt / clwb */
if (prefixes & PREFIX_LOCK) {
goto illegal_op;
}
if (prefixes & PREFIX_DATA) {
/* clwb */
if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_CLWB)) {
goto illegal_op;
}
gen_nop_modrm(env, s, modrm);
} else {
/* xsaveopt */
if ((s->cpuid_ext_features & CPUID_EXT_XSAVE) == 0
|| (s->cpuid_xsave_features & CPUID_XSAVE_XSAVEOPT) == 0
|| (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))) {
goto illegal_op;
}
gen_lea_modrm(env, s, modrm);
tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX],
cpu_regs[R_EDX]);
gen_helper_xsaveopt(tcg_env, s->A0, s->tmp1_i64);
}
break;
CASE_MODRM_MEM_OP(7): /* clflush / clflushopt */
if (prefixes & PREFIX_LOCK) {
goto illegal_op;
}
if (prefixes & PREFIX_DATA) {
/* clflushopt */
if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_CLFLUSHOPT)) {
goto illegal_op;
}
} else {
/* clflush */
if ((s->prefix & (PREFIX_REPZ | PREFIX_REPNZ))
|| !(s->cpuid_features & CPUID_CLFLUSH)) {
goto illegal_op;
}
}
gen_nop_modrm(env, s, modrm);
break;
case 0xc0 ... 0xc7: /* rdfsbase (f3 0f ae /0) */
case 0xc8 ... 0xcf: /* rdgsbase (f3 0f ae /1) */
case 0xd0 ... 0xd7: /* wrfsbase (f3 0f ae /2) */
case 0xd8 ... 0xdf: /* wrgsbase (f3 0f ae /3) */
if (CODE64(s)
&& (prefixes & PREFIX_REPZ)
&& !(prefixes & PREFIX_LOCK)
&& (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_FSGSBASE)) {
TCGv base, treg, src, dst;
/* Preserve hflags bits by testing CR4 at runtime. */
tcg_gen_movi_i32(s->tmp2_i32, CR4_FSGSBASE_MASK);
gen_helper_cr4_testbit(tcg_env, s->tmp2_i32);
base = cpu_seg_base[modrm & 8 ? R_GS : R_FS];
treg = cpu_regs[(modrm & 7) | REX_B(s)];
if (modrm & 0x10) {
/* wr*base */
dst = base, src = treg;
} else {
/* rd*base */
dst = treg, src = base;
}
if (s->dflag == MO_32) {
tcg_gen_ext32u_tl(dst, src);
} else {
tcg_gen_mov_tl(dst, src);
}
break;
}
goto unknown_op;
case 0xf8: /* sfence / pcommit */
if (prefixes & PREFIX_DATA) {
/* pcommit */
if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_PCOMMIT)
|| (prefixes & PREFIX_LOCK)) {
goto illegal_op;
}
break;
}
/* fallthru */
case 0xf9 ... 0xff: /* sfence */
if (!(s->cpuid_features & CPUID_SSE)
|| (prefixes & PREFIX_LOCK)) {
goto illegal_op;
}
tcg_gen_mb(TCG_MO_ST_ST | TCG_BAR_SC);
break;
case 0xe8 ... 0xef: /* lfence */
if (!(s->cpuid_features & CPUID_SSE)
|| (prefixes & PREFIX_LOCK)) {
goto illegal_op;
}
tcg_gen_mb(TCG_MO_LD_LD | TCG_BAR_SC);
break;
case 0xf0 ... 0xf7: /* mfence */
if (!(s->cpuid_features & CPUID_SSE2)
|| (prefixes & PREFIX_LOCK)) {
goto illegal_op;
}
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
break;
default:
goto unknown_op;
}
break;
case 0x10d: /* 3DNow! prefetch(w) */
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
if (mod == 3)
goto illegal_op;
gen_nop_modrm(env, s, modrm);
break;
case 0x1aa: /* rsm */
gen_svm_check_intercept(s, SVM_EXIT_RSM);
if (!(s->flags & HF_SMM_MASK))
goto illegal_op;
#ifdef CONFIG_USER_ONLY
/* we should not be in SMM mode */
g_assert_not_reached();
#else
gen_update_cc_op(s);
gen_update_eip_next(s);
gen_helper_rsm(tcg_env);
#endif /* CONFIG_USER_ONLY */
s->base.is_jmp = DISAS_EOB_ONLY;
break;
case 0x1b8: /* SSE4.2 popcnt */
if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) !=
PREFIX_REPZ)
goto illegal_op;
if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT))
goto illegal_op;
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
if (s->prefix & PREFIX_DATA) {
ot = MO_16;
} else {
ot = mo_64_32(dflag);
}
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_extu(ot, s->T0);
tcg_gen_mov_tl(cpu_cc_src, s->T0);
tcg_gen_ctpop_tl(s->T0, s->T0);
gen_op_mov_reg_v(s, ot, reg, s->T0);
set_cc_op(s, CC_OP_POPCNT);
break;
case 0x10e ... 0x117:
case 0x128 ... 0x12f:
case 0x138 ... 0x13a:
case 0x150 ... 0x179:
case 0x17c ... 0x17f:
case 0x1c2:
case 0x1c4 ... 0x1c6:
case 0x1d0 ... 0x1fe:
disas_insn_new(s, cpu, b);
break;
default:
goto unknown_op;
}
return true;
illegal_op:
gen_illegal_opcode(s);
return true;
unknown_op:
gen_unknown_opcode(env, s);
return true;
}
@@ -7034,30 +7036,31 @@ static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
static void i386_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
switch (dc->base.is_jmp) {
case DISAS_NORETURN:
break;
case DISAS_TOO_MANY:
gen_update_cc_op(dc);
gen_jmp_rel_csize(dc, 0, 0);
break;
case DISAS_EOB_NEXT:
gen_update_cc_op(dc);
gen_update_eip_cur(dc);
/* fall through */
+ fallthrough;
case DISAS_EOB_ONLY:
gen_eob(dc);
break;
case DISAS_EOB_INHIBIT_IRQ:
gen_update_cc_op(dc);
gen_update_eip_cur(dc);
gen_eob_inhibit_irq(dc, true);
break;
case DISAS_JUMP:
gen_jr(dc);
break;
default:
g_assert_not_reached();
}
}
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 3afb896a3a..1af7640aab 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -275,40 +275,40 @@ static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8)
static bool tcg_target_const_match(int64_t val, TCGType type, int ct, int vece)
{
if (ct & TCG_CT_CONST) {
return 1;
}
if (type == TCG_TYPE_I32) {
val = (int32_t)val;
}
if ((ct & TCG_CT_CONST_AIMM) && (is_aimm(val) || is_aimm(-val))) {
return 1;
}
if ((ct & TCG_CT_CONST_LIMM) && is_limm(val)) {
return 1;
}
if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
return 1;
}
if ((ct & TCG_CT_CONST_MONE) && val == -1) {
return 1;
}
switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) {
case 0:
break;
case TCG_CT_CONST_ANDI:
val = ~val;
- /* fallthru */
+ fallthrough;
case TCG_CT_CONST_ORRI:
if (val == deposit64(val, 32, 32, val)) {
int cmode, imm8;
return is_shimm1632(val, &cmode, &imm8);
}
break;
default:
/* Both bits should not be set for the same insn. */
g_assert_not_reached();
}
return 0;
}
@@ -1174,34 +1174,35 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd,
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
if (ret == arg) {
return true;
}
switch (type) {
case TCG_TYPE_I32:
case TCG_TYPE_I64:
if (ret < 32 && arg < 32) {
tcg_out_movr(s, type, ret, arg);
break;
} else if (ret < 32) {
tcg_out_insn(s, 3605, UMOV, type, ret, arg, 0, 0);
break;
} else if (arg < 32) {
tcg_out_insn(s, 3605, INS, 0, ret, arg, 4 << type, 0);
break;
}
/* FALLTHRU */
+ fallthrough;
case TCG_TYPE_V64:
tcg_debug_assert(ret >= 32 && arg >= 32);
tcg_out_insn(s, 3616, ORR, 0, 0, ret, arg, arg);
break;
case TCG_TYPE_V128:
tcg_debug_assert(ret >= 32 && arg >= 32);
tcg_out_insn(s, 3616, ORR, 1, 0, ret, arg, arg);
break;
default:
g_assert_not_reached();
}
return true;
}
@@ -2016,406 +2017,418 @@ void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
/* 99% of the time, we can signal the use of extension registers
by looking to see if the opcode handles 64-bit data. */
TCGType ext = (tcg_op_defs[opc].flags & TCG_OPF_64BIT) != 0;
/* Hoist the loads of the most common arguments. */
TCGArg a0 = args[0];
TCGArg a1 = args[1];
TCGArg a2 = args[2];
int c2 = const_args[2];
/* Some operands are defined with "rZ" constraint, a register or
the zero register. These need not actually test args[I] == 0. */
#define REG0(I) (const_args[I] ? TCG_REG_XZR : (TCGReg)args[I])
switch (opc) {
case INDEX_op_goto_ptr:
tcg_out_insn(s, 3207, BR, a0);
break;
case INDEX_op_br:
tcg_out_goto_label(s, arg_label(a0));
break;
case INDEX_op_ld8u_i32:
case INDEX_op_ld8u_i64:
tcg_out_ldst(s, I3312_LDRB, a0, a1, a2, 0);
break;
case INDEX_op_ld8s_i32:
tcg_out_ldst(s, I3312_LDRSBW, a0, a1, a2, 0);
break;
case INDEX_op_ld8s_i64:
tcg_out_ldst(s, I3312_LDRSBX, a0, a1, a2, 0);
break;
case INDEX_op_ld16u_i32:
case INDEX_op_ld16u_i64:
tcg_out_ldst(s, I3312_LDRH, a0, a1, a2, 1);
break;
case INDEX_op_ld16s_i32:
tcg_out_ldst(s, I3312_LDRSHW, a0, a1, a2, 1);
break;
case INDEX_op_ld16s_i64:
tcg_out_ldst(s, I3312_LDRSHX, a0, a1, a2, 1);
break;
case INDEX_op_ld_i32:
case INDEX_op_ld32u_i64:
tcg_out_ldst(s, I3312_LDRW, a0, a1, a2, 2);
break;
case INDEX_op_ld32s_i64:
tcg_out_ldst(s, I3312_LDRSWX, a0, a1, a2, 2);
break;
case INDEX_op_ld_i64:
tcg_out_ldst(s, I3312_LDRX, a0, a1, a2, 3);
break;
case INDEX_op_st8_i32:
case INDEX_op_st8_i64:
tcg_out_ldst(s, I3312_STRB, REG0(0), a1, a2, 0);
break;
case INDEX_op_st16_i32:
case INDEX_op_st16_i64:
tcg_out_ldst(s, I3312_STRH, REG0(0), a1, a2, 1);
break;
case INDEX_op_st_i32:
case INDEX_op_st32_i64:
tcg_out_ldst(s, I3312_STRW, REG0(0), a1, a2, 2);
break;
case INDEX_op_st_i64:
tcg_out_ldst(s, I3312_STRX, REG0(0), a1, a2, 3);
break;
case INDEX_op_add_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
+ fallthrough;
case INDEX_op_add_i64:
if (c2) {
tcg_out_addsubi(s, ext, a0, a1, a2);
} else {
tcg_out_insn(s, 3502, ADD, ext, a0, a1, a2);
}
break;
case INDEX_op_sub_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
+ fallthrough;
case INDEX_op_sub_i64:
if (c2) {
tcg_out_addsubi(s, ext, a0, a1, -a2);
} else {
tcg_out_insn(s, 3502, SUB, ext, a0, a1, a2);
}
break;
case INDEX_op_neg_i64:
case INDEX_op_neg_i32:
tcg_out_insn(s, 3502, SUB, ext, a0, TCG_REG_XZR, a1);
break;
case INDEX_op_and_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
+ fallthrough;
case INDEX_op_and_i64:
if (c2) {
tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, a2);
} else {
tcg_out_insn(s, 3510, AND, ext, a0, a1, a2);
}
break;
case INDEX_op_andc_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
+ fallthrough;
case INDEX_op_andc_i64:
if (c2) {
tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, ~a2);
} else {
tcg_out_insn(s, 3510, BIC, ext, a0, a1, a2);
}
break;
case INDEX_op_or_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
+ fallthrough;
case INDEX_op_or_i64:
if (c2) {
tcg_out_logicali(s, I3404_ORRI, ext, a0, a1, a2);
} else {
tcg_out_insn(s, 3510, ORR, ext, a0, a1, a2);
}
break;
case INDEX_op_orc_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
+ fallthrough;
case INDEX_op_orc_i64:
if (c2) {
tcg_out_logicali(s, I3404_ORRI, ext, a0, a1, ~a2);
} else {
tcg_out_insn(s, 3510, ORN, ext, a0, a1, a2);
}
break;
case INDEX_op_xor_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
+ fallthrough;
case INDEX_op_xor_i64:
if (c2) {
tcg_out_logicali(s, I3404_EORI, ext, a0, a1, a2);
} else {
tcg_out_insn(s, 3510, EOR, ext, a0, a1, a2);
}
break;
case INDEX_op_eqv_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
+ fallthrough;
case INDEX_op_eqv_i64:
if (c2) {
tcg_out_logicali(s, I3404_EORI, ext, a0, a1, ~a2);
} else {
tcg_out_insn(s, 3510, EON, ext, a0, a1, a2);
}
break;
case INDEX_op_not_i64:
case INDEX_op_not_i32:
tcg_out_insn(s, 3510, ORN, ext, a0, TCG_REG_XZR, a1);
break;
case INDEX_op_mul_i64:
case INDEX_op_mul_i32:
tcg_out_insn(s, 3509, MADD, ext, a0, a1, a2, TCG_REG_XZR);
break;
case INDEX_op_div_i64:
case INDEX_op_div_i32:
tcg_out_insn(s, 3508, SDIV, ext, a0, a1, a2);
break;
case INDEX_op_divu_i64:
case INDEX_op_divu_i32:
tcg_out_insn(s, 3508, UDIV, ext, a0, a1, a2);
break;
case INDEX_op_rem_i64:
case INDEX_op_rem_i32:
tcg_out_insn(s, 3508, SDIV, ext, TCG_REG_TMP0, a1, a2);
tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP0, a2, a1);
break;
case INDEX_op_remu_i64:
case INDEX_op_remu_i32:
tcg_out_insn(s, 3508, UDIV, ext, TCG_REG_TMP0, a1, a2);
tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP0, a2, a1);
break;
case INDEX_op_shl_i64:
case INDEX_op_shl_i32:
if (c2) {
tcg_out_shl(s, ext, a0, a1, a2);
} else {
tcg_out_insn(s, 3508, LSLV, ext, a0, a1, a2);
}
break;
case INDEX_op_shr_i64:
case INDEX_op_shr_i32:
if (c2) {
tcg_out_shr(s, ext, a0, a1, a2);
} else {
tcg_out_insn(s, 3508, LSRV, ext, a0, a1, a2);
}
break;
case INDEX_op_sar_i64:
case INDEX_op_sar_i32:
if (c2) {
tcg_out_sar(s, ext, a0, a1, a2);
} else {
tcg_out_insn(s, 3508, ASRV, ext, a0, a1, a2);
}
break;
case INDEX_op_rotr_i64:
case INDEX_op_rotr_i32:
if (c2) {
tcg_out_rotr(s, ext, a0, a1, a2);
} else {
tcg_out_insn(s, 3508, RORV, ext, a0, a1, a2);
}
break;
case INDEX_op_rotl_i64:
case INDEX_op_rotl_i32:
if (c2) {
tcg_out_rotl(s, ext, a0, a1, a2);
} else {
tcg_out_insn(s, 3502, SUB, 0, TCG_REG_TMP0, TCG_REG_XZR, a2);
tcg_out_insn(s, 3508, RORV, ext, a0, a1, TCG_REG_TMP0);
}
break;
case INDEX_op_clz_i64:
case INDEX_op_clz_i32:
tcg_out_cltz(s, ext, a0, a1, a2, c2, false);
break;
case INDEX_op_ctz_i64:
case INDEX_op_ctz_i32:
tcg_out_cltz(s, ext, a0, a1, a2, c2, true);
break;
case INDEX_op_brcond_i32:
a1 = (int32_t)a1;
/* FALLTHRU */
+ fallthrough;
case INDEX_op_brcond_i64:
tcg_out_brcond(s, ext, a2, a0, a1, const_args[1], arg_label(args[3]));
break;
case INDEX_op_setcond_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
+ fallthrough;
case INDEX_op_setcond_i64:
tcg_out_cmp(s, ext, a1, a2, c2);
/* Use CSET alias of CSINC Wd, WZR, WZR, invert(cond). */
tcg_out_insn(s, 3506, CSINC, TCG_TYPE_I32, a0, TCG_REG_XZR,
TCG_REG_XZR, tcg_invert_cond(args[3]));
break;
case INDEX_op_negsetcond_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
+ fallthrough;
case INDEX_op_negsetcond_i64:
tcg_out_cmp(s, ext, a1, a2, c2);
/* Use CSETM alias of CSINV Wd, WZR, WZR, invert(cond). */
tcg_out_insn(s, 3506, CSINV, ext, a0, TCG_REG_XZR,
TCG_REG_XZR, tcg_invert_cond(args[3]));
break;
case INDEX_op_movcond_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
+ fallthrough;
case INDEX_op_movcond_i64:
tcg_out_cmp(s, ext, a1, a2, c2);
tcg_out_insn(s, 3506, CSEL, ext, a0, REG0(3), REG0(4), args[5]);
break;
case INDEX_op_qemu_ld_a32_i32:
case INDEX_op_qemu_ld_a64_i32:
case INDEX_op_qemu_ld_a32_i64:
case INDEX_op_qemu_ld_a64_i64:
tcg_out_qemu_ld(s, a0, a1, a2, ext);
break;
case INDEX_op_qemu_st_a32_i32:
case INDEX_op_qemu_st_a64_i32:
case INDEX_op_qemu_st_a32_i64:
case INDEX_op_qemu_st_a64_i64:
tcg_out_qemu_st(s, REG0(0), a1, a2, ext);
break;
case INDEX_op_qemu_ld_a32_i128:
case INDEX_op_qemu_ld_a64_i128:
tcg_out_qemu_ldst_i128(s, a0, a1, a2, args[3], true);
break;
case INDEX_op_qemu_st_a32_i128:
case INDEX_op_qemu_st_a64_i128:
tcg_out_qemu_ldst_i128(s, REG0(0), REG0(1), a2, args[3], false);
break;
case INDEX_op_bswap64_i64:
tcg_out_rev(s, TCG_TYPE_I64, MO_64, a0, a1);
break;
case INDEX_op_bswap32_i64:
tcg_out_rev(s, TCG_TYPE_I32, MO_32, a0, a1);
if (a2 & TCG_BSWAP_OS) {
tcg_out_ext32s(s, a0, a0);
}
break;
case INDEX_op_bswap32_i32:
tcg_out_rev(s, TCG_TYPE_I32, MO_32, a0, a1);
break;
case INDEX_op_bswap16_i64:
case INDEX_op_bswap16_i32:
tcg_out_rev(s, TCG_TYPE_I32, MO_16, a0, a1);
if (a2 & TCG_BSWAP_OS) {
/* Output must be sign-extended. */
tcg_out_ext16s(s, ext, a0, a0);
} else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
/* Output must be zero-extended, but input isn't. */
tcg_out_ext16u(s, a0, a0);
}
break;
case INDEX_op_deposit_i64:
case INDEX_op_deposit_i32:
tcg_out_dep(s, ext, a0, REG0(2), args[3], args[4]);
break;
case INDEX_op_extract_i64:
case INDEX_op_extract_i32:
tcg_out_ubfm(s, ext, a0, a1, a2, a2 + args[3] - 1);
break;
case INDEX_op_sextract_i64:
case INDEX_op_sextract_i32:
tcg_out_sbfm(s, ext, a0, a1, a2, a2 + args[3] - 1);
break;
case INDEX_op_extract2_i64:
case INDEX_op_extract2_i32:
tcg_out_extr(s, ext, a0, REG0(2), REG0(1), args[3]);
break;
case INDEX_op_add2_i32:
tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3),
(int32_t)args[4], args[5], const_args[4],
const_args[5], false);
break;
case INDEX_op_add2_i64:
tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, REG0(2), REG0(3), args[4],
args[5], const_args[4], const_args[5], false);
break;
case INDEX_op_sub2_i32:
tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3),
(int32_t)args[4], args[5], const_args[4],
const_args[5], true);
break;
case INDEX_op_sub2_i64:
tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, REG0(2), REG0(3), args[4],
args[5], const_args[4], const_args[5], true);
break;
case INDEX_op_muluh_i64:
tcg_out_insn(s, 3508, UMULH, TCG_TYPE_I64, a0, a1, a2);
break;
case INDEX_op_mulsh_i64:
tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2);
break;
case INDEX_op_mb:
tcg_out_mb(s, a0);
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */
case INDEX_op_ext8s_i64:
case INDEX_op_ext8u_i32:
case INDEX_op_ext8u_i64:
case INDEX_op_ext16s_i64:
case INDEX_op_ext16s_i32:
case INDEX_op_ext16u_i64:
case INDEX_op_ext16u_i32:
case INDEX_op_ext32s_i64:
case INDEX_op_ext32u_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
case INDEX_op_extrl_i64_i32:
default:
g_assert_not_reached();
}
#undef REG0
}
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 0d9c2d157b..ceb747183d 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -504,41 +504,42 @@ static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8)
/* Test if a constant matches the constraint.
* TODO: define constraints for:
*
* ldr/str offset: between -0xfff and 0xfff
* ldrh/strh offset: between -0xff and 0xff
* mov operand2: values represented with x << (2 * y), x < 0x100
* add, sub, eor...: ditto
*/
static bool tcg_target_const_match(int64_t val, TCGType type, int ct, int vece)
{
if (ct & TCG_CT_CONST) {
return 1;
} else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) {
return 1;
} else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) {
return 1;
} else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) {
return 1;
} else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
return 1;
}
switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) {
case 0:
break;
case TCG_CT_CONST_ANDI:
val = ~val;
/* fallthru */
+ fallthrough;
case TCG_CT_CONST_ORRI:
if (val == deposit64(val, 32, 32, val)) {
int cmode, imm8;
return is_shimm1632(val, &cmode, &imm8);
}
break;
default:
/* Both bits should not be set for the same insn. */
g_assert_not_reached();
}
return 0;
}
@@ -2578,190 +2579,190 @@ static const ARMInsn vec_cmp0_insn[16] = {
static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
unsigned vecl, unsigned vece,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
TCGType type = vecl + TCG_TYPE_V64;
unsigned q = vecl;
TCGArg a0, a1, a2, a3;
int cmode, imm8;
a0 = args[0];
a1 = args[1];
a2 = args[2];
switch (opc) {
case INDEX_op_ld_vec:
tcg_out_ld(s, type, a0, a1, a2);
return;
case INDEX_op_st_vec:
tcg_out_st(s, type, a0, a1, a2);
return;
case INDEX_op_dupm_vec:
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
return;
case INDEX_op_dup2_vec:
tcg_out_dup2_vec(s, a0, a1, a2);
return;
case INDEX_op_abs_vec:
tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1);
return;
case INDEX_op_neg_vec:
tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1);
return;
case INDEX_op_not_vec:
tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1);
return;
case INDEX_op_add_vec:
tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2);
return;
case INDEX_op_mul_vec:
tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2);
return;
case INDEX_op_smax_vec:
tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2);
return;
case INDEX_op_smin_vec:
tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2);
return;
case INDEX_op_sub_vec:
tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
return;
case INDEX_op_ssadd_vec:
tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2);
return;
case INDEX_op_sssub_vec:
tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2);
return;
case INDEX_op_umax_vec:
tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2);
return;
case INDEX_op_umin_vec:
tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2);
return;
case INDEX_op_usadd_vec:
tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2);
return;
case INDEX_op_ussub_vec:
tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2);
return;
case INDEX_op_xor_vec:
tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
return;
case INDEX_op_arm_sshl_vec:
/*
* Note that Vm is the data and Vn is the shift count,
* therefore the arguments appear reversed.
*/
tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1);
return;
case INDEX_op_arm_ushl_vec:
/* See above. */
tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1);
return;
case INDEX_op_shli_vec:
tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece));
return;
case INDEX_op_shri_vec:
tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2);
return;
case INDEX_op_sari_vec:
tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2);
return;
case INDEX_op_arm_sli_vec:
tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece));
return;
case INDEX_op_andc_vec:
if (!const_args[2]) {
tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2);
return;
}
a2 = ~a2;
- /* fall through */
+ fallthrough;
case INDEX_op_and_vec:
if (const_args[2]) {
is_shimm1632(~a2, &cmode, &imm8);
if (a0 == a1) {
tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */
return;
}
tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */
a2 = a0;
}
tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2);
return;
case INDEX_op_orc_vec:
if (!const_args[2]) {
tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2);
return;
}
a2 = ~a2;
- /* fall through */
+ fallthrough;
case INDEX_op_or_vec:
if (const_args[2]) {
is_shimm1632(a2, &cmode, &imm8);
if (a0 == a1) {
tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */
return;
}
tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */
a2 = a0;
}
tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2);
return;
case INDEX_op_cmp_vec:
{
TCGCond cond = args[3];
if (cond == TCG_COND_NE) {
if (const_args[2]) {
tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1);
} else {
tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2);
tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0);
}
} else {
ARMInsn insn;
if (const_args[2]) {
insn = vec_cmp0_insn[cond];
if (insn) {
tcg_out_vreg2(s, insn, q, vece, a0, a1);
return;
}
tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0);
a2 = TCG_VEC_TMP;
}
insn = vec_cmp_insn[cond];
if (insn == 0) {
TCGArg t;
t = a1, a1 = a2, a2 = t;
cond = tcg_swap_cond(cond);
insn = vec_cmp_insn[cond];
tcg_debug_assert(insn != 0);
}
tcg_out_vreg3(s, insn, q, vece, a0, a1, a2);
}
}
return;
case INDEX_op_bitsel_vec:
a3 = args[3];
if (a0 == a3) {
tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1);
} else if (a0 == a2) {
tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1);
} else {
tcg_out_mov(s, type, a0, a1);
tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3);
}
return;
case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
default:
g_assert_not_reached();
}
}
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 788d608150..8f0764156e 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -173,28 +173,29 @@ static const tcg_insn_unit *tb_ret_addr;
static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
intptr_t value, intptr_t addend)
{
value += addend;
switch(type) {
case R_386_PC32:
value -= (uintptr_t)tcg_splitwx_to_rx(code_ptr);
if (value != (int32_t)value) {
return false;
}
/* FALLTHRU */
+ fallthrough;
case R_386_32:
tcg_patch32(code_ptr, value);
break;
case R_386_PC8:
value -= (uintptr_t)tcg_splitwx_to_rx(code_ptr);
if (value != (int8_t)value) {
return false;
}
tcg_patch8(code_ptr, value);
break;
default:
g_assert_not_reached();
}
return true;
}
/* test if a constant matches the constraint */
@@ -837,45 +838,46 @@ static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src)
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
int rexw = 0;
if (arg == ret) {
return true;
}
switch (type) {
case TCG_TYPE_I64:
rexw = P_REXW;
/* fallthru */
+ fallthrough;
case TCG_TYPE_I32:
if (ret < 16) {
if (arg < 16) {
tcg_out_modrm(s, OPC_MOVL_GvEv + rexw, ret, arg);
} else {
tcg_out_vex_modrm(s, OPC_MOVD_EyVy + rexw, arg, 0, ret);
}
} else {
if (arg < 16) {
tcg_out_vex_modrm(s, OPC_MOVD_VyEy + rexw, ret, 0, arg);
} else {
tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg);
}
}
break;
case TCG_TYPE_V64:
tcg_debug_assert(ret >= 16 && arg >= 16);
tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg);
break;
case TCG_TYPE_V128:
tcg_debug_assert(ret >= 16 && arg >= 16);
tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx, ret, 0, arg);
break;
case TCG_TYPE_V256:
tcg_debug_assert(ret >= 16 && arg >= 16);
tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx | P_VEXL, ret, 0, arg);
break;
default:
g_assert_not_reached();
}
return true;
}
@@ -888,31 +890,33 @@ static const int avx2_dup_insn[4] = {
static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
TCGReg r, TCGReg a)
{
if (have_avx2) {
int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0);
tcg_out_vex_modrm(s, avx2_dup_insn[vece] + vex_l, r, 0, a);
} else {
switch (vece) {
case MO_8:
/* ??? With zero in a register, use PSHUFB. */
tcg_out_vex_modrm(s, OPC_PUNPCKLBW, r, a, a);
a = r;
/* FALLTHRU */
+ fallthrough;
case MO_16:
tcg_out_vex_modrm(s, OPC_PUNPCKLWD, r, a, a);
a = r;
/* FALLTHRU */
+ fallthrough;
case MO_32:
tcg_out_vex_modrm(s, OPC_PSHUFD, r, 0, a);
/* imm8 operand: all output lanes selected from input lane 0. */
tcg_out8(s, 0);
break;
case MO_64:
tcg_out_vex_modrm(s, OPC_PUNPCKLQDQ, r, a, a);
break;
default:
g_assert_not_reached();
}
}
return true;
}
@@ -1112,44 +1116,45 @@ static inline void tcg_out_pop(TCGContext *s, int reg)
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
TCGReg arg1, intptr_t arg2)
{
switch (type) {
case TCG_TYPE_I32:
if (ret < 16) {
tcg_out_modrm_offset(s, OPC_MOVL_GvEv, ret, arg1, arg2);
} else {
tcg_out_vex_modrm_offset(s, OPC_MOVD_VyEy, ret, 0, arg1, arg2);
}
break;
case TCG_TYPE_I64:
if (ret < 16) {
tcg_out_modrm_offset(s, OPC_MOVL_GvEv | P_REXW, ret, arg1, arg2);
break;
}
/* FALLTHRU */
+ fallthrough;
case TCG_TYPE_V64:
/* There is no instruction that can validate 8-byte alignment. */
tcg_debug_assert(ret >= 16);
tcg_out_vex_modrm_offset(s, OPC_MOVQ_VqWq, ret, 0, arg1, arg2);
break;
case TCG_TYPE_V128:
/*
* The gvec infrastructure is asserts that v128 vector loads
* and stores use a 16-byte aligned offset. Validate that the
* final pointer is aligned by using an insn that will SIGSEGV.
*/
tcg_debug_assert(ret >= 16);
tcg_out_vex_modrm_offset(s, OPC_MOVDQA_VxWx, ret, 0, arg1, arg2);
break;
case TCG_TYPE_V256:
/*
* The gvec infrastructure only requires 16-byte alignment,
* so here we must use an unaligned load.
*/
tcg_debug_assert(ret >= 16);
tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx | P_VEXL,
ret, 0, arg1, arg2);
break;
default:
g_assert_not_reached();
}
}
@@ -1157,51 +1162,52 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
TCGReg arg1, intptr_t arg2)
{
switch (type) {
case TCG_TYPE_I32:
if (arg < 16) {
tcg_out_modrm_offset(s, OPC_MOVL_EvGv, arg, arg1, arg2);
} else {
tcg_out_vex_modrm_offset(s, OPC_MOVD_EyVy, arg, 0, arg1, arg2);
}
break;
case TCG_TYPE_I64:
if (arg < 16) {
tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_REXW, arg, arg1, arg2);
break;
}
/* FALLTHRU */
+ fallthrough;
case TCG_TYPE_V64:
/* There is no instruction that can validate 8-byte alignment. */
tcg_debug_assert(arg >= 16);
tcg_out_vex_modrm_offset(s, OPC_MOVQ_WqVq, arg, 0, arg1, arg2);
break;
case TCG_TYPE_V128:
/*
* The gvec infrastructure is asserts that v128 vector loads
* and stores use a 16-byte aligned offset. Validate that the
* final pointer is aligned by using an insn that will SIGSEGV.
*
* This specific instance is also used by TCG_CALL_RET_BY_VEC,
* for _WIN64, which must have SSE2 but may not have AVX.
*/
tcg_debug_assert(arg >= 16);
if (have_avx1) {
tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg2);
} else {
tcg_out_modrm_offset(s, OPC_MOVDQA_WxVx, arg, arg1, arg2);
}
break;
case TCG_TYPE_V256:
/*
* The gvec infrastructure only requires 16-byte alignment,
* so here we must use an unaligned store.
*/
tcg_debug_assert(arg >= 16);
tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx | P_VEXL,
arg, 0, arg1, arg2);
break;
default:
g_assert_not_reached();
}
}
@@ -1530,101 +1536,101 @@ static void tcg_out_brcond2(TCGContext *s, const TCGArg *args,
static void tcg_out_setcond(TCGContext *s, int rexw, TCGCond cond,
TCGArg dest, TCGArg arg1, TCGArg arg2,
int const_arg2, bool neg)
{
bool inv = false;
bool cleared;
switch (cond) {
case TCG_COND_NE:
inv = true;
- /* fall through */
+ fallthrough;
case TCG_COND_EQ:
/* If arg2 is 0, convert to LTU/GEU vs 1. */
if (const_arg2 && arg2 == 0) {
arg2 = 1;
goto do_ltu;
}
break;
case TCG_COND_LEU:
inv = true;
- /* fall through */
+ fallthrough;
case TCG_COND_GTU:
/* If arg2 is a register, swap for LTU/GEU. */
if (!const_arg2) {
TCGReg t = arg1;
arg1 = arg2;
arg2 = t;
goto do_ltu;
}
break;
case TCG_COND_GEU:
inv = true;
- /* fall through */
+ fallthrough;
case TCG_COND_LTU:
do_ltu:
/*
* Relying on the carry bit, use SBB to produce -1 if LTU, 0 if GEU.
* We can then use NEG or INC to produce the desired result.
* This is always smaller than the SETCC expansion.
*/
tcg_out_cmp(s, arg1, arg2, const_arg2, rexw);
/* X - X - C = -C = (C ? -1 : 0) */
tgen_arithr(s, ARITH_SBB + (neg ? rexw : 0), dest, dest);
if (inv && neg) {
/* ~(C ? -1 : 0) = (C ? 0 : -1) */
tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, dest);
} else if (inv) {
/* (C ? -1 : 0) + 1 = (C ? 0 : 1) */
tgen_arithi(s, ARITH_ADD, dest, 1, 0);
} else if (!neg) {
/* -(C ? -1 : 0) = (C ? 1 : 0) */
tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_NEG, dest);
}
return;
case TCG_COND_GE:
inv = true;
- /* fall through */
+ fallthrough;
case TCG_COND_LT:
/* If arg2 is 0, extract the sign bit. */
if (const_arg2 && arg2 == 0) {
tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, dest, arg1);
if (inv) {
tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, dest);
}
tcg_out_shifti(s, (neg ? SHIFT_SAR : SHIFT_SHR) + rexw,
dest, rexw ? 63 : 31);
return;
}
break;
default:
break;
}
/*
* If dest does not overlap the inputs, clearing it first is preferred.
* The XOR breaks any false dependency for the low-byte write to dest,
* and is also one byte smaller than MOVZBL.
*/
cleared = false;
if (dest != arg1 && (const_arg2 || dest != arg2)) {
tgen_arithr(s, ARITH_XOR, dest, dest);
cleared = true;
}
tcg_out_cmp(s, arg1, arg2, const_arg2, rexw);
tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest);
if (!cleared) {
tcg_out_ext8u(s, dest, dest);
}
if (neg) {
tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NEG, dest);
}
}
#if TCG_TARGET_REG_BITS == 32
@@ -2435,473 +2441,475 @@ void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
TCGArg a0, a1, a2;
int c, const_a2, vexop, rexw = 0;
#if TCG_TARGET_REG_BITS == 64
# define OP_32_64(x) \
case glue(glue(INDEX_op_, x), _i64): \
rexw = P_REXW; /* FALLTHRU */ \
+ fallthrough; \
case glue(glue(INDEX_op_, x), _i32)
#else
# define OP_32_64(x) \
case glue(glue(INDEX_op_, x), _i32)
#endif
/* Hoist the loads of the most common arguments. */
a0 = args[0];
a1 = args[1];
a2 = args[2];
const_a2 = const_args[2];
switch (opc) {
case INDEX_op_goto_ptr:
/* jmp to the given host address (could be epilogue) */
tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, a0);
break;
case INDEX_op_br:
tcg_out_jxx(s, JCC_JMP, arg_label(a0), 0);
break;
OP_32_64(ld8u):
/* Note that we can ignore REXW for the zero-extend to 64-bit. */
tcg_out_modrm_offset(s, OPC_MOVZBL, a0, a1, a2);
break;
OP_32_64(ld8s):
tcg_out_modrm_offset(s, OPC_MOVSBL + rexw, a0, a1, a2);
break;
OP_32_64(ld16u):
/* Note that we can ignore REXW for the zero-extend to 64-bit. */
tcg_out_modrm_offset(s, OPC_MOVZWL, a0, a1, a2);
break;
OP_32_64(ld16s):
tcg_out_modrm_offset(s, OPC_MOVSWL + rexw, a0, a1, a2);
break;
#if TCG_TARGET_REG_BITS == 64
case INDEX_op_ld32u_i64:
#endif
case INDEX_op_ld_i32:
tcg_out_ld(s, TCG_TYPE_I32, a0, a1, a2);
break;
OP_32_64(st8):
if (const_args[0]) {
tcg_out_modrm_offset(s, OPC_MOVB_EvIz, 0, a1, a2);
tcg_out8(s, a0);
} else {
tcg_out_modrm_offset(s, OPC_MOVB_EvGv | P_REXB_R, a0, a1, a2);
}
break;
OP_32_64(st16):
if (const_args[0]) {
tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_DATA16, 0, a1, a2);
tcg_out16(s, a0);
} else {
tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_DATA16, a0, a1, a2);
}
break;
#if TCG_TARGET_REG_BITS == 64
case INDEX_op_st32_i64:
#endif
case INDEX_op_st_i32:
if (const_args[0]) {
tcg_out_modrm_offset(s, OPC_MOVL_EvIz, 0, a1, a2);
tcg_out32(s, a0);
} else {
tcg_out_st(s, TCG_TYPE_I32, a0, a1, a2);
}
break;
OP_32_64(add):
/* For 3-operand addition, use LEA. */
if (a0 != a1) {
TCGArg c3 = 0;
if (const_a2) {
c3 = a2, a2 = -1;
} else if (a0 == a2) {
/* Watch out for dest = src + dest, since we've removed
the matching constraint on the add. */
tgen_arithr(s, ARITH_ADD + rexw, a0, a1);
break;
}
tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a2, 0, c3);
break;
}
c = ARITH_ADD;
goto gen_arith;
OP_32_64(sub):
c = ARITH_SUB;
goto gen_arith;
OP_32_64(and):
c = ARITH_AND;
goto gen_arith;
OP_32_64(or):
c = ARITH_OR;
goto gen_arith;
OP_32_64(xor):
c = ARITH_XOR;
goto gen_arith;
gen_arith:
if (const_a2) {
tgen_arithi(s, c + rexw, a0, a2, 0);
} else {
tgen_arithr(s, c + rexw, a0, a2);
}
break;
OP_32_64(andc):
if (const_a2) {
tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1);
tgen_arithi(s, ARITH_AND + rexw, a0, ~a2, 0);
} else {
tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1);
}
break;
OP_32_64(mul):
if (const_a2) {
int32_t val;
val = a2;
if (val == (int8_t)val) {
tcg_out_modrm(s, OPC_IMUL_GvEvIb + rexw, a0, a0);
tcg_out8(s, val);
} else {
tcg_out_modrm(s, OPC_IMUL_GvEvIz + rexw, a0, a0);
tcg_out32(s, val);
}
} else {
tcg_out_modrm(s, OPC_IMUL_GvEv + rexw, a0, a2);
}
break;
OP_32_64(div2):
tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IDIV, args[4]);
break;
OP_32_64(divu2):
tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_DIV, args[4]);
break;
OP_32_64(shl):
/* For small constant 3-operand shift, use LEA. */
if (const_a2 && a0 != a1 && (a2 - 1) < 3) {
if (a2 - 1 == 0) {
/* shl $1,a1,a0 -> lea (a1,a1),a0 */
tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a1, 0, 0);
} else {
/* shl $n,a1,a0 -> lea 0(,a1,n),a0 */
tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, -1, a1, a2, 0);
}
break;
}
c = SHIFT_SHL;
vexop = OPC_SHLX;
goto gen_shift_maybe_vex;
OP_32_64(shr):
c = SHIFT_SHR;
vexop = OPC_SHRX;
goto gen_shift_maybe_vex;
OP_32_64(sar):
c = SHIFT_SAR;
vexop = OPC_SARX;
goto gen_shift_maybe_vex;
OP_32_64(rotl):
c = SHIFT_ROL;
goto gen_shift;
OP_32_64(rotr):
c = SHIFT_ROR;
goto gen_shift;
gen_shift_maybe_vex:
if (have_bmi2) {
if (!const_a2) {
tcg_out_vex_modrm(s, vexop + rexw, a0, a2, a1);
break;
}
tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1);
}
/* FALLTHRU */
gen_shift:
if (const_a2) {
tcg_out_shifti(s, c + rexw, a0, a2);
} else {
tcg_out_modrm(s, OPC_SHIFT_cl + rexw, c, a0);
}
break;
OP_32_64(ctz):
tcg_out_ctz(s, rexw, args[0], args[1], args[2], const_args[2]);
break;
OP_32_64(clz):
tcg_out_clz(s, rexw, args[0], args[1], args[2], const_args[2]);
break;
OP_32_64(ctpop):
tcg_out_modrm(s, OPC_POPCNT + rexw, a0, a1);
break;
OP_32_64(brcond):
tcg_out_brcond(s, rexw, a2, a0, a1, const_args[1],
arg_label(args[3]), 0);
break;
OP_32_64(setcond):
tcg_out_setcond(s, rexw, args[3], a0, a1, a2, const_a2, false);
break;
OP_32_64(negsetcond):
tcg_out_setcond(s, rexw, args[3], a0, a1, a2, const_a2, true);
break;
OP_32_64(movcond):
tcg_out_movcond(s, rexw, args[5], a0, a1, a2, const_a2, args[3]);
break;
OP_32_64(bswap16):
if (a2 & TCG_BSWAP_OS) {
/* Output must be sign-extended. */
if (rexw) {
tcg_out_bswap64(s, a0);
tcg_out_shifti(s, SHIFT_SAR + rexw, a0, 48);
} else {
tcg_out_bswap32(s, a0);
tcg_out_shifti(s, SHIFT_SAR, a0, 16);
}
} else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
/* Output must be zero-extended, but input isn't. */
tcg_out_bswap32(s, a0);
tcg_out_shifti(s, SHIFT_SHR, a0, 16);
} else {
tcg_out_rolw_8(s, a0);
}
break;
OP_32_64(bswap32):
tcg_out_bswap32(s, a0);
if (rexw && (a2 & TCG_BSWAP_OS)) {
tcg_out_ext32s(s, a0, a0);
}
break;
OP_32_64(neg):
tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NEG, a0);
break;
OP_32_64(not):
tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, a0);
break;
case INDEX_op_qemu_ld_a64_i32:
if (TCG_TARGET_REG_BITS == 32) {
tcg_out_qemu_ld(s, a0, -1, a1, a2, args[3], TCG_TYPE_I32);
break;
}
- /* fall through */
+ fallthrough;
case INDEX_op_qemu_ld_a32_i32:
tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I32);
break;
case INDEX_op_qemu_ld_a32_i64:
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I64);
} else {
tcg_out_qemu_ld(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64);
}
break;
case INDEX_op_qemu_ld_a64_i64:
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I64);
} else {
tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
}
break;
case INDEX_op_qemu_ld_a32_i128:
case INDEX_op_qemu_ld_a64_i128:
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
tcg_out_qemu_ld(s, a0, a1, a2, -1, args[3], TCG_TYPE_I128);
break;
case INDEX_op_qemu_st_a64_i32:
case INDEX_op_qemu_st8_a64_i32:
if (TCG_TARGET_REG_BITS == 32) {
tcg_out_qemu_st(s, a0, -1, a1, a2, args[3], TCG_TYPE_I32);
break;
}
- /* fall through */
+ fallthrough;
case INDEX_op_qemu_st_a32_i32:
case INDEX_op_qemu_st8_a32_i32:
tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I32);
break;
case INDEX_op_qemu_st_a32_i64:
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I64);
} else {
tcg_out_qemu_st(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64);
}
break;
case INDEX_op_qemu_st_a64_i64:
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I64);
} else {
tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
}
break;
case INDEX_op_qemu_st_a32_i128:
case INDEX_op_qemu_st_a64_i128:
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
tcg_out_qemu_st(s, a0, a1, a2, -1, args[3], TCG_TYPE_I128);
break;
OP_32_64(mulu2):
tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_MUL, args[3]);
break;
OP_32_64(muls2):
tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IMUL, args[3]);
break;
OP_32_64(add2):
if (const_args[4]) {
tgen_arithi(s, ARITH_ADD + rexw, a0, args[4], 1);
} else {
tgen_arithr(s, ARITH_ADD + rexw, a0, args[4]);
}
if (const_args[5]) {
tgen_arithi(s, ARITH_ADC + rexw, a1, args[5], 1);
} else {
tgen_arithr(s, ARITH_ADC + rexw, a1, args[5]);
}
break;
OP_32_64(sub2):
if (const_args[4]) {
tgen_arithi(s, ARITH_SUB + rexw, a0, args[4], 1);
} else {
tgen_arithr(s, ARITH_SUB + rexw, a0, args[4]);
}
if (const_args[5]) {
tgen_arithi(s, ARITH_SBB + rexw, a1, args[5], 1);
} else {
tgen_arithr(s, ARITH_SBB + rexw, a1, args[5]);
}
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_brcond2_i32:
tcg_out_brcond2(s, args, const_args, 0);
break;
case INDEX_op_setcond2_i32:
tcg_out_setcond2(s, args, const_args);
break;
#else /* TCG_TARGET_REG_BITS == 64 */
case INDEX_op_ld32s_i64:
tcg_out_modrm_offset(s, OPC_MOVSLQ, a0, a1, a2);
break;
case INDEX_op_ld_i64:
tcg_out_ld(s, TCG_TYPE_I64, a0, a1, a2);
break;
case INDEX_op_st_i64:
if (const_args[0]) {
tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_REXW, 0, a1, a2);
tcg_out32(s, a0);
} else {
tcg_out_st(s, TCG_TYPE_I64, a0, a1, a2);
}
break;
case INDEX_op_bswap64_i64:
tcg_out_bswap64(s, a0);
break;
case INDEX_op_extrh_i64_i32:
tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32);
break;
#endif
OP_32_64(deposit):
if (args[3] == 0 && args[4] == 8) {
/* load bits 0..7 */
if (const_a2) {
tcg_out_opc(s, OPC_MOVB_Ib | P_REXB_RM | LOWREGMASK(a0),
0, a0, 0);
tcg_out8(s, a2);
} else {
tcg_out_modrm(s, OPC_MOVB_EvGv | P_REXB_R | P_REXB_RM, a2, a0);
}
} else if (TCG_TARGET_REG_BITS == 32 && args[3] == 8 && args[4] == 8) {
/* load bits 8..15 */
if (const_a2) {
tcg_out8(s, OPC_MOVB_Ib + a0 + 4);
tcg_out8(s, a2);
} else {
tcg_out_modrm(s, OPC_MOVB_EvGv, a2, a0 + 4);
}
} else if (args[3] == 0 && args[4] == 16) {
/* load bits 0..15 */
if (const_a2) {
tcg_out_opc(s, OPC_MOVL_Iv | P_DATA16 | LOWREGMASK(a0),
0, a0, 0);
tcg_out16(s, a2);
} else {
tcg_out_modrm(s, OPC_MOVL_EvGv | P_DATA16, a2, a0);
}
} else {
g_assert_not_reached();
}
break;
case INDEX_op_extract_i64:
if (a2 + args[3] == 32) {
/* This is a 32-bit zero-extending right shift. */
tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
tcg_out_shifti(s, SHIFT_SHR, a0, a2);
break;
}
/* FALLTHRU */
+ fallthrough;
case INDEX_op_extract_i32:
/* On the off-chance that we can use the high-byte registers.
Otherwise we emit the same ext16 + shift pattern that we
would have gotten from the normal tcg-op.c expansion. */
tcg_debug_assert(a2 == 8 && args[3] == 8);
if (a1 < 4 && a0 < 8) {
tcg_out_modrm(s, OPC_MOVZBL, a0, a1 + 4);
} else {
tcg_out_ext16u(s, a0, a1);
tcg_out_shifti(s, SHIFT_SHR, a0, 8);
}
break;
case INDEX_op_sextract_i32:
/* We don't implement sextract_i64, as we cannot sign-extend to
64-bits without using the REX prefix that explicitly excludes
access to the high-byte registers. */
tcg_debug_assert(a2 == 8 && args[3] == 8);
if (a1 < 4 && a0 < 8) {
tcg_out_modrm(s, OPC_MOVSBL, a0, a1 + 4);
} else {
tcg_out_ext16s(s, TCG_TYPE_I32, a0, a1);
tcg_out_shifti(s, SHIFT_SAR, a0, 8);
}
break;
OP_32_64(extract2):
/* Note that SHRD outputs to the r/m operand. */
tcg_out_modrm(s, OPC_SHRD_Ib + rexw, a2, a0);
tcg_out8(s, args[3]);
break;
case INDEX_op_mb:
tcg_out_mb(s, a0);
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */
case INDEX_op_ext8s_i64:
case INDEX_op_ext8u_i32:
case INDEX_op_ext8u_i64:
case INDEX_op_ext16s_i32:
case INDEX_op_ext16s_i64:
case INDEX_op_ext16u_i32:
case INDEX_op_ext16u_i64:
case INDEX_op_ext32s_i64:
case INDEX_op_ext32u_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
case INDEX_op_extrl_i64_i32:
default:
g_assert_not_reached();
}
#undef OP_32_64
}
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 801302d85d..728384ce51 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -992,35 +992,35 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
static void tcg_out_qemu_ld_indexed(TCGContext *s, MemOp opc, TCGType type,
TCGReg rd, HostAddress h)
{
/* Byte swapping is left to middle-end expansion. */
tcg_debug_assert((opc & MO_BSWAP) == 0);
switch (opc & MO_SSIZE) {
case MO_UB:
tcg_out_opc_ldx_bu(s, rd, h.base, h.index);
break;
case MO_SB:
tcg_out_opc_ldx_b(s, rd, h.base, h.index);
break;
case MO_UW:
tcg_out_opc_ldx_hu(s, rd, h.base, h.index);
break;
case MO_SW:
tcg_out_opc_ldx_h(s, rd, h.base, h.index);
break;
case MO_UL:
if (type == TCG_TYPE_I64) {
tcg_out_opc_ldx_wu(s, rd, h.base, h.index);
break;
}
- /* fallthrough */
+ fallthrough;
case MO_SL:
tcg_out_opc_ldx_w(s, rd, h.base, h.index);
break;
case MO_UQ:
tcg_out_opc_ldx_d(s, rd, h.base, h.index);
break;
default:
g_assert_not_reached();
}
}
@@ -1183,409 +1183,409 @@ void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
TCGArg a0 = args[0];
TCGArg a1 = args[1];
TCGArg a2 = args[2];
TCGArg a3 = args[3];
int c2 = const_args[2];
switch (opc) {
case INDEX_op_mb:
tcg_out_mb(s, a0);
break;
case INDEX_op_goto_ptr:
tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0);
break;
case INDEX_op_br:
tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SD10K16, arg_label(a0),
0);
tcg_out_opc_b(s, 0);
break;
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
break;
case INDEX_op_extrh_i64_i32:
tcg_out_opc_srai_d(s, a0, a1, 32);
break;
case INDEX_op_not_i32:
case INDEX_op_not_i64:
tcg_out_opc_nor(s, a0, a1, TCG_REG_ZERO);
break;
case INDEX_op_nor_i32:
case INDEX_op_nor_i64:
if (c2) {
tcg_out_opc_ori(s, a0, a1, a2);
tcg_out_opc_nor(s, a0, a0, TCG_REG_ZERO);
} else {
tcg_out_opc_nor(s, a0, a1, a2);
}
break;
case INDEX_op_andc_i32:
case INDEX_op_andc_i64:
if (c2) {
/* guaranteed to fit due to constraint */
tcg_out_opc_andi(s, a0, a1, ~a2);
} else {
tcg_out_opc_andn(s, a0, a1, a2);
}
break;
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
if (c2) {
/* guaranteed to fit due to constraint */
tcg_out_opc_ori(s, a0, a1, ~a2);
} else {
tcg_out_opc_orn(s, a0, a1, a2);
}
break;
case INDEX_op_and_i32:
case INDEX_op_and_i64:
if (c2) {
tcg_out_opc_andi(s, a0, a1, a2);
} else {
tcg_out_opc_and(s, a0, a1, a2);
}
break;
case INDEX_op_or_i32:
case INDEX_op_or_i64:
if (c2) {
tcg_out_opc_ori(s, a0, a1, a2);
} else {
tcg_out_opc_or(s, a0, a1, a2);
}
break;
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
if (c2) {
tcg_out_opc_xori(s, a0, a1, a2);
} else {
tcg_out_opc_xor(s, a0, a1, a2);
}
break;
case INDEX_op_extract_i32:
tcg_out_opc_bstrpick_w(s, a0, a1, a2, a2 + args[3] - 1);
break;
case INDEX_op_extract_i64:
tcg_out_opc_bstrpick_d(s, a0, a1, a2, a2 + args[3] - 1);
break;
case INDEX_op_deposit_i32:
tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1);
break;
case INDEX_op_deposit_i64:
tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1);
break;
case INDEX_op_bswap16_i32:
case INDEX_op_bswap16_i64:
tcg_out_opc_revb_2h(s, a0, a1);
if (a2 & TCG_BSWAP_OS) {
tcg_out_ext16s(s, TCG_TYPE_REG, a0, a0);
} else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
tcg_out_ext16u(s, a0, a0);
}
break;
case INDEX_op_bswap32_i32:
/* All 32-bit values are computed sign-extended in the register. */
a2 = TCG_BSWAP_OS;
- /* fallthrough */
+ fallthrough;
case INDEX_op_bswap32_i64:
tcg_out_opc_revb_2w(s, a0, a1);
if (a2 & TCG_BSWAP_OS) {
tcg_out_ext32s(s, a0, a0);
} else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
tcg_out_ext32u(s, a0, a0);
}
break;
case INDEX_op_bswap64_i64:
tcg_out_opc_revb_d(s, a0, a1);
break;
case INDEX_op_clz_i32:
tcg_out_clzctz(s, OPC_CLZ_W, a0, a1, a2, c2, true);
break;
case INDEX_op_clz_i64:
tcg_out_clzctz(s, OPC_CLZ_D, a0, a1, a2, c2, false);
break;
case INDEX_op_ctz_i32:
tcg_out_clzctz(s, OPC_CTZ_W, a0, a1, a2, c2, true);
break;
case INDEX_op_ctz_i64:
tcg_out_clzctz(s, OPC_CTZ_D, a0, a1, a2, c2, false);
break;
case INDEX_op_shl_i32:
if (c2) {
tcg_out_opc_slli_w(s, a0, a1, a2 & 0x1f);
} else {
tcg_out_opc_sll_w(s, a0, a1, a2);
}
break;
case INDEX_op_shl_i64:
if (c2) {
tcg_out_opc_slli_d(s, a0, a1, a2 & 0x3f);
} else {
tcg_out_opc_sll_d(s, a0, a1, a2);
}
break;
case INDEX_op_shr_i32:
if (c2) {
tcg_out_opc_srli_w(s, a0, a1, a2 & 0x1f);
} else {
tcg_out_opc_srl_w(s, a0, a1, a2);
}
break;
case INDEX_op_shr_i64:
if (c2) {
tcg_out_opc_srli_d(s, a0, a1, a2 & 0x3f);
} else {
tcg_out_opc_srl_d(s, a0, a1, a2);
}
break;
case INDEX_op_sar_i32:
if (c2) {
tcg_out_opc_srai_w(s, a0, a1, a2 & 0x1f);
} else {
tcg_out_opc_sra_w(s, a0, a1, a2);
}
break;
case INDEX_op_sar_i64:
if (c2) {
tcg_out_opc_srai_d(s, a0, a1, a2 & 0x3f);
} else {
tcg_out_opc_sra_d(s, a0, a1, a2);
}
break;
case INDEX_op_rotl_i32:
/* transform into equivalent rotr/rotri */
if (c2) {
tcg_out_opc_rotri_w(s, a0, a1, (32 - a2) & 0x1f);
} else {
tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2);
tcg_out_opc_rotr_w(s, a0, a1, TCG_REG_TMP0);
}
break;
case INDEX_op_rotl_i64:
/* transform into equivalent rotr/rotri */
if (c2) {
tcg_out_opc_rotri_d(s, a0, a1, (64 - a2) & 0x3f);
} else {
tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2);
tcg_out_opc_rotr_d(s, a0, a1, TCG_REG_TMP0);
}
break;
case INDEX_op_rotr_i32:
if (c2) {
tcg_out_opc_rotri_w(s, a0, a1, a2 & 0x1f);
} else {
tcg_out_opc_rotr_w(s, a0, a1, a2);
}
break;
case INDEX_op_rotr_i64:
if (c2) {
tcg_out_opc_rotri_d(s, a0, a1, a2 & 0x3f);
} else {
tcg_out_opc_rotr_d(s, a0, a1, a2);
}
break;
case INDEX_op_add_i32:
if (c2) {
tcg_out_addi(s, TCG_TYPE_I32, a0, a1, a2);
} else {
tcg_out_opc_add_w(s, a0, a1, a2);
}
break;
case INDEX_op_add_i64:
if (c2) {
tcg_out_addi(s, TCG_TYPE_I64, a0, a1, a2);
} else {
tcg_out_opc_add_d(s, a0, a1, a2);
}
break;
case INDEX_op_sub_i32:
if (c2) {
tcg_out_addi(s, TCG_TYPE_I32, a0, a1, -a2);
} else {
tcg_out_opc_sub_w(s, a0, a1, a2);
}
break;
case INDEX_op_sub_i64:
if (c2) {
tcg_out_addi(s, TCG_TYPE_I64, a0, a1, -a2);
} else {
tcg_out_opc_sub_d(s, a0, a1, a2);
}
break;
case INDEX_op_mul_i32:
tcg_out_opc_mul_w(s, a0, a1, a2);
break;
case INDEX_op_mul_i64:
tcg_out_opc_mul_d(s, a0, a1, a2);
break;
case INDEX_op_mulsh_i32:
tcg_out_opc_mulh_w(s, a0, a1, a2);
break;
case INDEX_op_mulsh_i64:
tcg_out_opc_mulh_d(s, a0, a1, a2);
break;
case INDEX_op_muluh_i32:
tcg_out_opc_mulh_wu(s, a0, a1, a2);
break;
case INDEX_op_muluh_i64:
tcg_out_opc_mulh_du(s, a0, a1, a2);
break;
case INDEX_op_div_i32:
tcg_out_opc_div_w(s, a0, a1, a2);
break;
case INDEX_op_div_i64:
tcg_out_opc_div_d(s, a0, a1, a2);
break;
case INDEX_op_divu_i32:
tcg_out_opc_div_wu(s, a0, a1, a2);
break;
case INDEX_op_divu_i64:
tcg_out_opc_div_du(s, a0, a1, a2);
break;
case INDEX_op_rem_i32:
tcg_out_opc_mod_w(s, a0, a1, a2);
break;
case INDEX_op_rem_i64:
tcg_out_opc_mod_d(s, a0, a1, a2);
break;
case INDEX_op_remu_i32:
tcg_out_opc_mod_wu(s, a0, a1, a2);
break;
case INDEX_op_remu_i64:
tcg_out_opc_mod_du(s, a0, a1, a2);
break;
case INDEX_op_setcond_i32:
case INDEX_op_setcond_i64:
tcg_out_setcond(s, args[3], a0, a1, a2, c2);
break;
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
tcg_out_movcond(s, args[5], a0, a1, a2, c2, args[3], args[4]);
break;
case INDEX_op_ld8s_i32:
case INDEX_op_ld8s_i64:
tcg_out_ldst(s, OPC_LD_B, a0, a1, a2);
break;
case INDEX_op_ld8u_i32:
case INDEX_op_ld8u_i64:
tcg_out_ldst(s, OPC_LD_BU, a0, a1, a2);
break;
case INDEX_op_ld16s_i32:
case INDEX_op_ld16s_i64:
tcg_out_ldst(s, OPC_LD_H, a0, a1, a2);
break;
case INDEX_op_ld16u_i32:
case INDEX_op_ld16u_i64:
tcg_out_ldst(s, OPC_LD_HU, a0, a1, a2);
break;
case INDEX_op_ld_i32:
case INDEX_op_ld32s_i64:
tcg_out_ldst(s, OPC_LD_W, a0, a1, a2);
break;
case INDEX_op_ld32u_i64:
tcg_out_ldst(s, OPC_LD_WU, a0, a1, a2);
break;
case INDEX_op_ld_i64:
tcg_out_ldst(s, OPC_LD_D, a0, a1, a2);
break;
case INDEX_op_st8_i32:
case INDEX_op_st8_i64:
tcg_out_ldst(s, OPC_ST_B, a0, a1, a2);
break;
case INDEX_op_st16_i32:
case INDEX_op_st16_i64:
tcg_out_ldst(s, OPC_ST_H, a0, a1, a2);
break;
case INDEX_op_st_i32:
case INDEX_op_st32_i64:
tcg_out_ldst(s, OPC_ST_W, a0, a1, a2);
break;
case INDEX_op_st_i64:
tcg_out_ldst(s, OPC_ST_D, a0, a1, a2);
break;
case INDEX_op_qemu_ld_a32_i32:
case INDEX_op_qemu_ld_a64_i32:
tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
break;
case INDEX_op_qemu_ld_a32_i64:
case INDEX_op_qemu_ld_a64_i64:
tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64);
break;
case INDEX_op_qemu_ld_a32_i128:
case INDEX_op_qemu_ld_a64_i128:
tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, true);
break;
case INDEX_op_qemu_st_a32_i32:
case INDEX_op_qemu_st_a64_i32:
tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32);
break;
case INDEX_op_qemu_st_a32_i64:
case INDEX_op_qemu_st_a64_i64:
tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64);
break;
case INDEX_op_qemu_st_a32_i128:
case INDEX_op_qemu_st_a64_i128:
tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, false);
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */
case INDEX_op_ext8s_i64:
case INDEX_op_ext8u_i32:
case INDEX_op_ext8u_i64:
case INDEX_op_ext16s_i32:
case INDEX_op_ext16s_i64:
case INDEX_op_ext16u_i32:
case INDEX_op_ext16u_i64:
case INDEX_op_ext32s_i64:
case INDEX_op_ext32u_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
case INDEX_op_extrl_i64_i32:
default:
g_assert_not_reached();
}
}
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index e2892edc6a..0effa5320a 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -891,51 +891,52 @@ static const uint8_t mips_cmp_map[16] = {
static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
TCGReg arg1, TCGReg arg2)
{
MIPSInsn s_opc = OPC_SLTU;
int cmp_map;
switch (cond) {
case TCG_COND_EQ:
if (arg2 != 0) {
tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
arg1 = ret;
}
tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1);
break;
case TCG_COND_NE:
if (arg2 != 0) {
tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
arg1 = ret;
}
tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1);
break;
case TCG_COND_LT:
case TCG_COND_GE:
case TCG_COND_LE:
case TCG_COND_GT:
s_opc = OPC_SLT;
/* FALLTHRU */
+ fallthrough;
case TCG_COND_LTU:
case TCG_COND_GEU:
case TCG_COND_LEU:
case TCG_COND_GTU:
cmp_map = mips_cmp_map[cond];
if (cmp_map & MIPS_CMP_SWAP) {
TCGReg t = arg1;
arg1 = arg2;
arg2 = t;
}
tcg_out_opc_reg(s, s_opc, ret, arg1, arg2);
if (cmp_map & MIPS_CMP_INV) {
tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
}
break;
default:
g_assert_not_reached();
break;
}
}
@@ -943,60 +944,61 @@ static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
TCGReg arg2, TCGLabel *l)
{
static const MIPSInsn b_zero[16] = {
[TCG_COND_LT] = OPC_BLTZ,
[TCG_COND_GT] = OPC_BGTZ,
[TCG_COND_LE] = OPC_BLEZ,
[TCG_COND_GE] = OPC_BGEZ,
};
MIPSInsn s_opc = OPC_SLTU;
MIPSInsn b_opc;
int cmp_map;
switch (cond) {
case TCG_COND_EQ:
b_opc = OPC_BEQ;
break;
case TCG_COND_NE:
b_opc = OPC_BNE;
break;
case TCG_COND_LT:
case TCG_COND_GT:
case TCG_COND_LE:
case TCG_COND_GE:
if (arg2 == 0) {
b_opc = b_zero[cond];
arg2 = arg1;
arg1 = 0;
break;
}
s_opc = OPC_SLT;
/* FALLTHRU */
+ fallthrough;
case TCG_COND_LTU:
case TCG_COND_GTU:
case TCG_COND_LEU:
case TCG_COND_GEU:
cmp_map = mips_cmp_map[cond];
if (cmp_map & MIPS_CMP_SWAP) {
TCGReg t = arg1;
arg1 = arg2;
arg2 = t;
}
tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2);
b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE);
arg1 = TCG_TMP0;
arg2 = TCG_REG_ZERO;
break;
default:
g_assert_not_reached();
break;
}
tcg_out_opc_br(s, b_opc, arg1, arg2);
tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0);
tcg_out_nop(s);
}
@@ -1096,54 +1098,55 @@ static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2)
{
bool eqz = false;
/* If one of the values is zero, put it last to match SEL*Z instructions */
if (use_mips32r6_instructions && v1 == 0) {
v1 = v2;
v2 = 0;
cond = tcg_invert_cond(cond);
}
switch (cond) {
case TCG_COND_EQ:
eqz = true;
/* FALLTHRU */
+ fallthrough;
case TCG_COND_NE:
if (c2 != 0) {
tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2);
c1 = TCG_TMP0;
}
break;
default:
/* Minimize code size by preferring a compare not requiring INV. */
if (mips_cmp_map[cond] & MIPS_CMP_INV) {
cond = tcg_invert_cond(cond);
eqz = true;
}
tcg_out_setcond(s, cond, TCG_TMP0, c1, c2);
c1 = TCG_TMP0;
break;
}
if (use_mips32r6_instructions) {
MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ;
MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ;
if (v2 != 0) {
tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1);
}
tcg_out_opc_reg(s, m_opc_t, ret, v1, c1);
if (v2 != 0) {
tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1);
}
} else {
MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN;
tcg_out_opc_reg(s, m_opc, ret, v1, c1);
/* This should be guaranteed via constraints */
tcg_debug_assert(v2 == ret);
}
}
@@ -1411,41 +1414,42 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
TCGReg base, MemOp opc, TCGType type)
{
switch (opc & MO_SSIZE) {
case MO_UB:
tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
break;
case MO_SB:
tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
break;
case MO_UW:
tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
break;
case MO_SW:
tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
break;
case MO_UL:
if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) {
tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
break;
}
/* FALLTHRU */
+ fallthrough;
case MO_SL:
tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
break;
case MO_UQ:
/* Prefer to load from offset 0 first, but allow for overlap. */
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
} else if (HOST_BIG_ENDIAN ? hi != base : lo == base) {
tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
} else {
tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
}
break;
default:
g_assert_not_reached();
}
}
@@ -1729,466 +1733,466 @@ void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
MIPSInsn i1, i2;
TCGArg a0, a1, a2;
int c2;
/*
* Note that many operands use the constraint set "rZ".
* We make use of the fact that 0 is the ZERO register,
* and hence such cases need not check for const_args.
*/
a0 = args[0];
a1 = args[1];
a2 = args[2];
c2 = const_args[2];
switch (opc) {
case INDEX_op_goto_ptr:
/* jmp to the given host address (could be epilogue) */
tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0);
} else {
tcg_out_nop(s);
}
break;
case INDEX_op_br:
tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO,
arg_label(a0));
break;
case INDEX_op_ld8u_i32:
case INDEX_op_ld8u_i64:
i1 = OPC_LBU;
goto do_ldst;
case INDEX_op_ld8s_i32:
case INDEX_op_ld8s_i64:
i1 = OPC_LB;
goto do_ldst;
case INDEX_op_ld16u_i32:
case INDEX_op_ld16u_i64:
i1 = OPC_LHU;
goto do_ldst;
case INDEX_op_ld16s_i32:
case INDEX_op_ld16s_i64:
i1 = OPC_LH;
goto do_ldst;
case INDEX_op_ld_i32:
case INDEX_op_ld32s_i64:
i1 = OPC_LW;
goto do_ldst;
case INDEX_op_ld32u_i64:
i1 = OPC_LWU;
goto do_ldst;
case INDEX_op_ld_i64:
i1 = OPC_LD;
goto do_ldst;
case INDEX_op_st8_i32:
case INDEX_op_st8_i64:
i1 = OPC_SB;
goto do_ldst;
case INDEX_op_st16_i32:
case INDEX_op_st16_i64:
i1 = OPC_SH;
goto do_ldst;
case INDEX_op_st_i32:
case INDEX_op_st32_i64:
i1 = OPC_SW;
goto do_ldst;
case INDEX_op_st_i64:
i1 = OPC_SD;
do_ldst:
tcg_out_ldst(s, i1, a0, a1, a2);
break;
case INDEX_op_add_i32:
i1 = OPC_ADDU, i2 = OPC_ADDIU;
goto do_binary;
case INDEX_op_add_i64:
i1 = OPC_DADDU, i2 = OPC_DADDIU;
goto do_binary;
case INDEX_op_or_i32:
case INDEX_op_or_i64:
i1 = OPC_OR, i2 = OPC_ORI;
goto do_binary;
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
i1 = OPC_XOR, i2 = OPC_XORI;
do_binary:
if (c2) {
tcg_out_opc_imm(s, i2, a0, a1, a2);
break;
}
do_binaryv:
tcg_out_opc_reg(s, i1, a0, a1, a2);
break;
case INDEX_op_sub_i32:
i1 = OPC_SUBU, i2 = OPC_ADDIU;
goto do_subtract;
case INDEX_op_sub_i64:
i1 = OPC_DSUBU, i2 = OPC_DADDIU;
do_subtract:
if (c2) {
tcg_out_opc_imm(s, i2, a0, a1, -a2);
break;
}
goto do_binaryv;
case INDEX_op_and_i32:
if (c2 && a2 != (uint16_t)a2) {
int msb = ctz32(~a2) - 1;
tcg_debug_assert(use_mips32r2_instructions);
tcg_debug_assert(is_p2m1(a2));
tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
break;
}
i1 = OPC_AND, i2 = OPC_ANDI;
goto do_binary;
case INDEX_op_and_i64:
if (c2 && a2 != (uint16_t)a2) {
int msb = ctz64(~a2) - 1;
tcg_debug_assert(use_mips32r2_instructions);
tcg_debug_assert(is_p2m1(a2));
tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0);
break;
}
i1 = OPC_AND, i2 = OPC_ANDI;
goto do_binary;
case INDEX_op_nor_i32:
case INDEX_op_nor_i64:
i1 = OPC_NOR;
goto do_binaryv;
case INDEX_op_mul_i32:
if (use_mips32_instructions) {
tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
break;
}
i1 = OPC_MULT, i2 = OPC_MFLO;
goto do_hilo1;
case INDEX_op_mulsh_i32:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2);
break;
}
i1 = OPC_MULT, i2 = OPC_MFHI;
goto do_hilo1;
case INDEX_op_muluh_i32:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2);
break;
}
i1 = OPC_MULTU, i2 = OPC_MFHI;
goto do_hilo1;
case INDEX_op_div_i32:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2);
break;
}
i1 = OPC_DIV, i2 = OPC_MFLO;
goto do_hilo1;
case INDEX_op_divu_i32:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2);
break;
}
i1 = OPC_DIVU, i2 = OPC_MFLO;
goto do_hilo1;
case INDEX_op_rem_i32:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2);
break;
}
i1 = OPC_DIV, i2 = OPC_MFHI;
goto do_hilo1;
case INDEX_op_remu_i32:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2);
break;
}
i1 = OPC_DIVU, i2 = OPC_MFHI;
goto do_hilo1;
case INDEX_op_mul_i64:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2);
break;
}
i1 = OPC_DMULT, i2 = OPC_MFLO;
goto do_hilo1;
case INDEX_op_mulsh_i64:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2);
break;
}
i1 = OPC_DMULT, i2 = OPC_MFHI;
goto do_hilo1;
case INDEX_op_muluh_i64:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2);
break;
}
i1 = OPC_DMULTU, i2 = OPC_MFHI;
goto do_hilo1;
case INDEX_op_div_i64:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2);
break;
}
i1 = OPC_DDIV, i2 = OPC_MFLO;
goto do_hilo1;
case INDEX_op_divu_i64:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2);
break;
}
i1 = OPC_DDIVU, i2 = OPC_MFLO;
goto do_hilo1;
case INDEX_op_rem_i64:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2);
break;
}
i1 = OPC_DDIV, i2 = OPC_MFHI;
goto do_hilo1;
case INDEX_op_remu_i64:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2);
break;
}
i1 = OPC_DDIVU, i2 = OPC_MFHI;
do_hilo1:
tcg_out_opc_reg(s, i1, 0, a1, a2);
tcg_out_opc_reg(s, i2, a0, 0, 0);
break;
case INDEX_op_muls2_i32:
i1 = OPC_MULT;
goto do_hilo2;
case INDEX_op_mulu2_i32:
i1 = OPC_MULTU;
goto do_hilo2;
case INDEX_op_muls2_i64:
i1 = OPC_DMULT;
goto do_hilo2;
case INDEX_op_mulu2_i64:
i1 = OPC_DMULTU;
do_hilo2:
tcg_out_opc_reg(s, i1, 0, a2, args[3]);
tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0);
tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0);
break;
case INDEX_op_not_i32:
case INDEX_op_not_i64:
i1 = OPC_NOR;
goto do_unary;
do_unary:
tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
break;
case INDEX_op_bswap16_i32:
case INDEX_op_bswap16_i64:
tcg_out_bswap16(s, a0, a1, a2);
break;
case INDEX_op_bswap32_i32:
tcg_out_bswap32(s, a0, a1, 0);
break;
case INDEX_op_bswap32_i64:
tcg_out_bswap32(s, a0, a1, a2);
break;
case INDEX_op_bswap64_i64:
tcg_out_bswap64(s, a0, a1);
break;
case INDEX_op_extrh_i64_i32:
tcg_out_dsra(s, a0, a1, 32);
break;
case INDEX_op_sar_i32:
i1 = OPC_SRAV, i2 = OPC_SRA;
goto do_shift;
case INDEX_op_shl_i32:
i1 = OPC_SLLV, i2 = OPC_SLL;
goto do_shift;
case INDEX_op_shr_i32:
i1 = OPC_SRLV, i2 = OPC_SRL;
goto do_shift;
case INDEX_op_rotr_i32:
i1 = OPC_ROTRV, i2 = OPC_ROTR;
do_shift:
if (c2) {
tcg_out_opc_sa(s, i2, a0, a1, a2);
break;
}
do_shiftv:
tcg_out_opc_reg(s, i1, a0, a2, a1);
break;
case INDEX_op_rotl_i32:
if (c2) {
tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2);
} else {
tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2);
tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1);
}
break;
case INDEX_op_sar_i64:
if (c2) {
tcg_out_dsra(s, a0, a1, a2);
break;
}
i1 = OPC_DSRAV;
goto do_shiftv;
case INDEX_op_shl_i64:
if (c2) {
tcg_out_dsll(s, a0, a1, a2);
break;
}
i1 = OPC_DSLLV;
goto do_shiftv;
case INDEX_op_shr_i64:
if (c2) {
tcg_out_dsrl(s, a0, a1, a2);
break;
}
i1 = OPC_DSRLV;
goto do_shiftv;
case INDEX_op_rotr_i64:
if (c2) {
tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2);
break;
}
i1 = OPC_DROTRV;
goto do_shiftv;
case INDEX_op_rotl_i64:
if (c2) {
tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2);
} else {
tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2);
tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1);
}
break;
case INDEX_op_clz_i32:
tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2);
break;
case INDEX_op_clz_i64:
tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2);
break;
case INDEX_op_deposit_i32:
tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
break;
case INDEX_op_deposit_i64:
tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
args[3] + args[4] - 1, args[3]);
break;
case INDEX_op_extract_i32:
tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
break;
case INDEX_op_extract_i64:
tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1,
args[3] - 1, a2);
break;
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
break;
case INDEX_op_brcond2_i32:
tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
break;
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]);
break;
case INDEX_op_setcond_i32:
case INDEX_op_setcond_i64:
tcg_out_setcond(s, args[3], a0, a1, a2);
break;
case INDEX_op_setcond2_i32:
tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
break;
case INDEX_op_qemu_ld_a64_i32:
if (TCG_TARGET_REG_BITS == 32) {
tcg_out_qemu_ld(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32);
break;
}
- /* fall through */
+ fallthrough;
case INDEX_op_qemu_ld_a32_i32:
tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
break;
case INDEX_op_qemu_ld_a32_i64:
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
} else {
tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
}
break;
case INDEX_op_qemu_ld_a64_i64:
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
} else {
tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
}
break;
case INDEX_op_qemu_st_a64_i32:
if (TCG_TARGET_REG_BITS == 32) {
tcg_out_qemu_st(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32);
break;
}
- /* fall through */
+ fallthrough;
case INDEX_op_qemu_st_a32_i32:
tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
break;
case INDEX_op_qemu_st_a32_i64:
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
} else {
tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
}
break;
case INDEX_op_qemu_st_a64_i64:
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
} else {
tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
}
break;
case INDEX_op_add2_i32:
tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
const_args[4], const_args[5], false);
break;
case INDEX_op_sub2_i32:
tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
const_args[4], const_args[5], true);
break;
case INDEX_op_mb:
tcg_out_mb(s, a0);
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */
case INDEX_op_ext8s_i64:
case INDEX_op_ext8u_i32:
case INDEX_op_ext8u_i64:
case INDEX_op_ext16s_i32:
case INDEX_op_ext16s_i64:
case INDEX_op_ext32s_i64:
case INDEX_op_ext32u_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
case INDEX_op_extrl_i64_i32:
default:
g_assert_not_reached();
}
}
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 5c873b2161..a438a02045 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -718,43 +718,45 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
if (ret == arg) {
return true;
}
switch (type) {
case TCG_TYPE_I64:
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
/* fallthru */
+ fallthrough;
case TCG_TYPE_I32:
if (ret < TCG_REG_V0) {
if (arg < TCG_REG_V0) {
tcg_out32(s, OR | SAB(arg, ret, arg));
break;
} else if (have_isa_2_07) {
tcg_out32(s, (type == TCG_TYPE_I32 ? MFVSRWZ : MFVSRD)
| VRT(arg) | RA(ret));
break;
} else {
/* Altivec does not support vector->integer moves. */
return false;
}
} else if (arg < TCG_REG_V0) {
if (have_isa_2_07) {
tcg_out32(s, (type == TCG_TYPE_I32 ? MTVSRWZ : MTVSRD)
| VRT(ret) | RA(arg));
break;
} else {
/* Altivec does not support integer->vector moves. */
return false;
}
}
/* fallthru */
+ fallthrough;
case TCG_TYPE_V64:
case TCG_TYPE_V128:
tcg_debug_assert(ret >= TCG_REG_V0 && arg >= TCG_REG_V0);
tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg));
break;
default:
g_assert_not_reached();
}
return true;
}
@@ -1292,64 +1294,66 @@ static void tcg_out_b(TCGContext *s, int mask, const tcg_insn_unit *target)
static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
TCGReg base, tcg_target_long offset)
{
tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
bool is_int_store = false;
TCGReg rs = TCG_REG_TMP1;
switch (opi) {
case LD: case LWA:
align = 3;
/* FALLTHRU */
+ fallthrough;
default:
if (rt > TCG_REG_R0 && rt < TCG_REG_V0) {
rs = rt;
break;
}
break;
case LXSD:
case STXSD:
align = 3;
break;
case LXV:
case STXV:
align = 15;
break;
case STD:
align = 3;
/* FALLTHRU */
+ fallthrough;
case STB: case STH: case STW:
is_int_store = true;
break;
}
/* For unaligned, or very large offsets, use the indexed form. */
if (offset & align || offset != (int32_t)offset || opi == 0) {
if (rs == base) {
rs = TCG_REG_R0;
}
tcg_debug_assert(!is_int_store || rs != rt);
tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
tcg_out32(s, opx | TAB(rt & 31, base, rs));
return;
}
l0 = (int16_t)offset;
offset = (offset - l0) >> 16;
l1 = (int16_t)offset;
if (l1 < 0 && orig >= 0) {
extra = 0x4000;
l1 = (int16_t)(offset - 0x4000);
}
if (l1) {
tcg_out32(s, ADDIS | TAI(rs, base, l1));
base = rs;
}
if (extra) {
tcg_out32(s, ADDIS | TAI(rs, base, extra));
base = rs;
}
if (opi != ADDI || base != rt || l0 != 0) {
tcg_out32(s, opi | TAI(rt & 31, base, l0));
}
}
@@ -1363,52 +1367,53 @@ static void tcg_out_vsldoi(TCGContext *s, TCGReg ret,
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
TCGReg base, intptr_t offset)
{
int shift;
switch (type) {
case TCG_TYPE_I32:
if (ret < TCG_REG_V0) {
tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset);
break;
}
if (have_isa_2_07 && have_vsx) {
tcg_out_mem_long(s, 0, LXSIWZX, ret, base, offset);
break;
}
tcg_debug_assert((offset & 3) == 0);
tcg_out_mem_long(s, 0, LVEWX, ret, base, offset);
shift = (offset - 4) & 0xc;
if (shift) {
tcg_out_vsldoi(s, ret, ret, ret, shift);
}
break;
case TCG_TYPE_I64:
if (ret < TCG_REG_V0) {
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
tcg_out_mem_long(s, LD, LDX, ret, base, offset);
break;
}
/* fallthru */
+ fallthrough;
case TCG_TYPE_V64:
tcg_debug_assert(ret >= TCG_REG_V0);
if (have_vsx) {
tcg_out_mem_long(s, have_isa_3_00 ? LXSD : 0, LXSDX,
ret, base, offset);
break;
}
tcg_debug_assert((offset & 7) == 0);
tcg_out_mem_long(s, 0, LVX, ret, base, offset & -16);
if (offset & 8) {
tcg_out_vsldoi(s, ret, ret, ret, 8);
}
break;
case TCG_TYPE_V128:
tcg_debug_assert(ret >= TCG_REG_V0);
tcg_debug_assert((offset & 15) == 0);
tcg_out_mem_long(s, have_isa_3_00 ? LXV : 0,
LVX, ret, base, offset);
break;
default:
g_assert_not_reached();
}
}
@@ -1416,55 +1421,56 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
TCGReg base, intptr_t offset)
{
int shift;
switch (type) {
case TCG_TYPE_I32:
if (arg < TCG_REG_V0) {
tcg_out_mem_long(s, STW, STWX, arg, base, offset);
break;
}
if (have_isa_2_07 && have_vsx) {
tcg_out_mem_long(s, 0, STXSIWX, arg, base, offset);
break;
}
assert((offset & 3) == 0);
tcg_debug_assert((offset & 3) == 0);
shift = (offset - 4) & 0xc;
if (shift) {
tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, shift);
arg = TCG_VEC_TMP1;
}
tcg_out_mem_long(s, 0, STVEWX, arg, base, offset);
break;
case TCG_TYPE_I64:
if (arg < TCG_REG_V0) {
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
tcg_out_mem_long(s, STD, STDX, arg, base, offset);
break;
}
/* fallthru */
+ fallthrough;
case TCG_TYPE_V64:
tcg_debug_assert(arg >= TCG_REG_V0);
if (have_vsx) {
tcg_out_mem_long(s, have_isa_3_00 ? STXSD : 0,
STXSDX, arg, base, offset);
break;
}
tcg_debug_assert((offset & 7) == 0);
if (offset & 8) {
tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8);
arg = TCG_VEC_TMP1;
}
tcg_out_mem_long(s, 0, STVEWX, arg, base, offset);
tcg_out_mem_long(s, 0, STVEWX, arg, base, offset + 4);
break;
case TCG_TYPE_V128:
tcg_debug_assert(arg >= TCG_REG_V0);
tcg_out_mem_long(s, have_isa_3_00 ? STXV : 0,
STVX, arg, base, offset);
break;
default:
g_assert_not_reached();
}
}
@@ -1618,136 +1624,137 @@ static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
TCGArg arg0, TCGArg arg1, TCGArg arg2,
int const_arg2, bool neg)
{
int sh;
bool inv;
tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
/* Ignore high bits of a potential constant arg2. */
if (type == TCG_TYPE_I32) {
arg2 = (uint32_t)arg2;
}
/* With SETBC/SETBCR, we can always implement with 2 insns. */
if (have_isa_3_10) {
tcg_insn_unit bi, opc;
tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
/* Re-use tcg_to_bc for BI and BO_COND_{TRUE,FALSE}. */
bi = tcg_to_bc[cond] & (0x1f << 16);
if (tcg_to_bc[cond] & BO(8)) {
opc = neg ? SETNBC : SETBC;
} else {
opc = neg ? SETNBCR : SETBCR;
}
tcg_out32(s, opc | RT(arg0) | bi);
return;
}
/* Handle common and trivial cases before handling anything else. */
if (arg2 == 0) {
switch (cond) {
case TCG_COND_EQ:
tcg_out_setcond_eq0(s, type, arg0, arg1, neg);
return;
case TCG_COND_NE:
tcg_out_setcond_ne0(s, type, arg0, arg1, neg);
return;
case TCG_COND_GE:
tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
arg1 = arg0;
/* FALLTHRU */
+ fallthrough;
case TCG_COND_LT:
/* Extract the sign bit. */
if (type == TCG_TYPE_I32) {
if (neg) {
tcg_out_sari32(s, arg0, arg1, 31);
} else {
tcg_out_shri32(s, arg0, arg1, 31);
}
} else {
if (neg) {
tcg_out_sari64(s, arg0, arg1, 63);
} else {
tcg_out_shri64(s, arg0, arg1, 63);
}
}
return;
default:
break;
}
}
/* If we have ISEL, we can implement everything with 3 or 4 insns.
All other cases below are also at least 3 insns, so speed up the
code generator by not considering them and always using ISEL. */
if (have_isel) {
int isel, tab;
tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
isel = tcg_to_isel[cond];
tcg_out_movi(s, type, arg0, neg ? -1 : 1);
if (isel & 1) {
/* arg0 = (bc ? 0 : 1) */
tab = TAB(arg0, 0, arg0);
isel &= ~1;
} else {
/* arg0 = (bc ? 1 : 0) */
tcg_out_movi(s, type, TCG_REG_R0, 0);
tab = TAB(arg0, arg0, TCG_REG_R0);
}
tcg_out32(s, isel | tab);
return;
}
inv = false;
switch (cond) {
case TCG_COND_EQ:
arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
tcg_out_setcond_eq0(s, type, arg0, arg1, neg);
break;
case TCG_COND_NE:
arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
tcg_out_setcond_ne0(s, type, arg0, arg1, neg);
break;
case TCG_COND_LE:
case TCG_COND_LEU:
inv = true;
- /* fall through */
+ fallthrough;
case TCG_COND_GT:
case TCG_COND_GTU:
sh = 30; /* CR7 CR_GT */
goto crtest;
case TCG_COND_GE:
case TCG_COND_GEU:
inv = true;
- /* fall through */
+ fallthrough;
case TCG_COND_LT:
case TCG_COND_LTU:
sh = 29; /* CR7 CR_LT */
goto crtest;
crtest:
tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
if (neg && inv) {
tcg_out32(s, ADDI | TAI(arg0, arg0, -1));
} else if (neg) {
tcg_out32(s, NEG | RT(arg0) | RA(arg0));
} else if (inv) {
tcg_out_xori32(s, arg0, arg0, 1);
}
break;
default:
g_assert_not_reached();
}
}
@@ -2594,599 +2601,601 @@ void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
TCGArg a0, a1, a2;
switch (opc) {
case INDEX_op_goto_ptr:
tcg_out32(s, MTSPR | RS(args[0]) | CTR);
if (USE_REG_TB) {
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]);
}
tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0));
tcg_out32(s, BCCTR | BO_ALWAYS);
break;
case INDEX_op_br:
{
TCGLabel *l = arg_label(args[0]);
uint32_t insn = B;
if (l->has_value) {
insn |= reloc_pc24_val(tcg_splitwx_to_rx(s->code_ptr),
l->u.value_ptr);
} else {
tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0);
}
tcg_out32(s, insn);
}
break;
case INDEX_op_ld8u_i32:
case INDEX_op_ld8u_i64:
tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
break;
case INDEX_op_ld8s_i32:
case INDEX_op_ld8s_i64:
tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
tcg_out_ext8s(s, TCG_TYPE_REG, args[0], args[0]);
break;
case INDEX_op_ld16u_i32:
case INDEX_op_ld16u_i64:
tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
break;
case INDEX_op_ld16s_i32:
case INDEX_op_ld16s_i64:
tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
break;
case INDEX_op_ld_i32:
case INDEX_op_ld32u_i64:
tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
break;
case INDEX_op_ld32s_i64:
tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
break;
case INDEX_op_ld_i64:
tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
break;
case INDEX_op_st8_i32:
case INDEX_op_st8_i64:
tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
break;
case INDEX_op_st16_i32:
case INDEX_op_st16_i64:
tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
break;
case INDEX_op_st_i32:
case INDEX_op_st32_i64:
tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
break;
case INDEX_op_st_i64:
tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
break;
case INDEX_op_add_i32:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
do_addi_32:
tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
} else {
tcg_out32(s, ADD | TAB(a0, a1, a2));
}
break;
case INDEX_op_sub_i32:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[1]) {
if (const_args[2]) {
tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
} else {
tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
}
} else if (const_args[2]) {
a2 = -a2;
goto do_addi_32;
} else {
tcg_out32(s, SUBF | TAB(a0, a2, a1));
}
break;
case INDEX_op_and_i32:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
tcg_out_andi32(s, a0, a1, a2);
} else {
tcg_out32(s, AND | SAB(a1, a0, a2));
}
break;
case INDEX_op_and_i64:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
tcg_out_andi64(s, a0, a1, a2);
} else {
tcg_out32(s, AND | SAB(a1, a0, a2));
}
break;
case INDEX_op_or_i64:
case INDEX_op_or_i32:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
tcg_out_ori32(s, a0, a1, a2);
} else {
tcg_out32(s, OR | SAB(a1, a0, a2));
}
break;
case INDEX_op_xor_i64:
case INDEX_op_xor_i32:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
tcg_out_xori32(s, a0, a1, a2);
} else {
tcg_out32(s, XOR | SAB(a1, a0, a2));
}
break;
case INDEX_op_andc_i32:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
tcg_out_andi32(s, a0, a1, ~a2);
} else {
tcg_out32(s, ANDC | SAB(a1, a0, a2));
}
break;
case INDEX_op_andc_i64:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
tcg_out_andi64(s, a0, a1, ~a2);
} else {
tcg_out32(s, ANDC | SAB(a1, a0, a2));
}
break;
case INDEX_op_orc_i32:
if (const_args[2]) {
tcg_out_ori32(s, args[0], args[1], ~args[2]);
break;
}
/* FALLTHRU */
+ fallthrough;
case INDEX_op_orc_i64:
tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
break;
case INDEX_op_eqv_i32:
if (const_args[2]) {
tcg_out_xori32(s, args[0], args[1], ~args[2]);
break;
}
/* FALLTHRU */
+ fallthrough;
case INDEX_op_eqv_i64:
tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
break;
case INDEX_op_nand_i32:
case INDEX_op_nand_i64:
tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
break;
case INDEX_op_nor_i32:
case INDEX_op_nor_i64:
tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
break;
case INDEX_op_clz_i32:
tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1],
args[2], const_args[2]);
break;
case INDEX_op_ctz_i32:
tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1],
args[2], const_args[2]);
break;
case INDEX_op_ctpop_i32:
tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0));
break;
case INDEX_op_clz_i64:
tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1],
args[2], const_args[2]);
break;
case INDEX_op_ctz_i64:
tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1],
args[2], const_args[2]);
break;
case INDEX_op_ctpop_i64:
tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0));
break;
case INDEX_op_mul_i32:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
tcg_out32(s, MULLI | TAI(a0, a1, a2));
} else {
tcg_out32(s, MULLW | TAB(a0, a1, a2));
}
break;
case INDEX_op_div_i32:
tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
break;
case INDEX_op_divu_i32:
tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
break;
case INDEX_op_rem_i32:
tcg_out32(s, MODSW | TAB(args[0], args[1], args[2]));
break;
case INDEX_op_remu_i32:
tcg_out32(s, MODUW | TAB(args[0], args[1], args[2]));
break;
case INDEX_op_shl_i32:
if (const_args[2]) {
/* Limit immediate shift count lest we create an illegal insn. */
tcg_out_shli32(s, args[0], args[1], args[2] & 31);
} else {
tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
}
break;
case INDEX_op_shr_i32:
if (const_args[2]) {
/* Limit immediate shift count lest we create an illegal insn. */
tcg_out_shri32(s, args[0], args[1], args[2] & 31);
} else {
tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
}
break;
case INDEX_op_sar_i32:
if (const_args[2]) {
tcg_out_sari32(s, args[0], args[1], args[2]);
} else {
tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
}
break;
case INDEX_op_rotl_i32:
if (const_args[2]) {
tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
} else {
tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
| MB(0) | ME(31));
}
break;
case INDEX_op_rotr_i32:
if (const_args[2]) {
tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
} else {
tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
| MB(0) | ME(31));
}
break;
case INDEX_op_brcond_i32:
tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
arg_label(args[3]), TCG_TYPE_I32);
break;
case INDEX_op_brcond_i64:
tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
arg_label(args[3]), TCG_TYPE_I64);
break;
case INDEX_op_brcond2_i32:
tcg_out_brcond2(s, args, const_args);
break;
case INDEX_op_neg_i32:
case INDEX_op_neg_i64:
tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
break;
case INDEX_op_not_i32:
case INDEX_op_not_i64:
tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
break;
case INDEX_op_add_i64:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
do_addi_64:
tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
} else {
tcg_out32(s, ADD | TAB(a0, a1, a2));
}
break;
case INDEX_op_sub_i64:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[1]) {
if (const_args[2]) {
tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
} else {
tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
}
} else if (const_args[2]) {
a2 = -a2;
goto do_addi_64;
} else {
tcg_out32(s, SUBF | TAB(a0, a2, a1));
}
break;
case INDEX_op_shl_i64:
if (const_args[2]) {
/* Limit immediate shift count lest we create an illegal insn. */
tcg_out_shli64(s, args[0], args[1], args[2] & 63);
} else {
tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
}
break;
case INDEX_op_shr_i64:
if (const_args[2]) {
/* Limit immediate shift count lest we create an illegal insn. */
tcg_out_shri64(s, args[0], args[1], args[2] & 63);
} else {
tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
}
break;
case INDEX_op_sar_i64:
if (const_args[2]) {
tcg_out_sari64(s, args[0], args[1], args[2]);
} else {
tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
}
break;
case INDEX_op_rotl_i64:
if (const_args[2]) {
tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
} else {
tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
}
break;
case INDEX_op_rotr_i64:
if (const_args[2]) {
tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
} else {
tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
}
break;
case INDEX_op_mul_i64:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
tcg_out32(s, MULLI | TAI(a0, a1, a2));
} else {
tcg_out32(s, MULLD | TAB(a0, a1, a2));
}
break;
case INDEX_op_div_i64:
tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
break;
case INDEX_op_divu_i64:
tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
break;
case INDEX_op_rem_i64:
tcg_out32(s, MODSD | TAB(args[0], args[1], args[2]));
break;
case INDEX_op_remu_i64:
tcg_out32(s, MODUD | TAB(args[0], args[1], args[2]));
break;
case INDEX_op_qemu_ld_a64_i32:
if (TCG_TARGET_REG_BITS == 32) {
tcg_out_qemu_ld(s, args[0], -1, args[1], args[2],
args[3], TCG_TYPE_I32);
break;
}
- /* fall through */
+ fallthrough;
case INDEX_op_qemu_ld_a32_i32:
tcg_out_qemu_ld(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
break;
case INDEX_op_qemu_ld_a32_i64:
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_qemu_ld(s, args[0], -1, args[1], -1,
args[2], TCG_TYPE_I64);
} else {
tcg_out_qemu_ld(s, args[0], args[1], args[2], -1,
args[3], TCG_TYPE_I64);
}
break;
case INDEX_op_qemu_ld_a64_i64:
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_qemu_ld(s, args[0], -1, args[1], -1,
args[2], TCG_TYPE_I64);
} else {
tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3],
args[4], TCG_TYPE_I64);
}
break;
case INDEX_op_qemu_ld_a32_i128:
case INDEX_op_qemu_ld_a64_i128:
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], true);
break;
case INDEX_op_qemu_st_a64_i32:
if (TCG_TARGET_REG_BITS == 32) {
tcg_out_qemu_st(s, args[0], -1, args[1], args[2],
args[3], TCG_TYPE_I32);
break;
}
- /* fall through */
+ fallthrough;
case INDEX_op_qemu_st_a32_i32:
tcg_out_qemu_st(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
break;
case INDEX_op_qemu_st_a32_i64:
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_qemu_st(s, args[0], -1, args[1], -1,
args[2], TCG_TYPE_I64);
} else {
tcg_out_qemu_st(s, args[0], args[1], args[2], -1,
args[3], TCG_TYPE_I64);
}
break;
case INDEX_op_qemu_st_a64_i64:
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_qemu_st(s, args[0], -1, args[1], -1,
args[2], TCG_TYPE_I64);
} else {
tcg_out_qemu_st(s, args[0], args[1], args[2], args[3],
args[4], TCG_TYPE_I64);
}
break;
case INDEX_op_qemu_st_a32_i128:
case INDEX_op_qemu_st_a64_i128:
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false);
break;
case INDEX_op_setcond_i32:
tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
const_args[2], false);
break;
case INDEX_op_setcond_i64:
tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
const_args[2], false);
break;
case INDEX_op_negsetcond_i32:
tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
const_args[2], true);
break;
case INDEX_op_negsetcond_i64:
tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
const_args[2], true);
break;
case INDEX_op_setcond2_i32:
tcg_out_setcond2(s, args, const_args);
break;
case INDEX_op_bswap16_i32:
case INDEX_op_bswap16_i64:
tcg_out_bswap16(s, args[0], args[1], args[2]);
break;
case INDEX_op_bswap32_i32:
tcg_out_bswap32(s, args[0], args[1], 0);
break;
case INDEX_op_bswap32_i64:
tcg_out_bswap32(s, args[0], args[1], args[2]);
break;
case INDEX_op_bswap64_i64:
tcg_out_bswap64(s, args[0], args[1]);
break;
case INDEX_op_deposit_i32:
if (const_args[2]) {
uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
tcg_out_andi32(s, args[0], args[0], ~mask);
} else {
tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
32 - args[3] - args[4], 31 - args[3]);
}
break;
case INDEX_op_deposit_i64:
if (const_args[2]) {
uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
tcg_out_andi64(s, args[0], args[0], ~mask);
} else {
tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
64 - args[3] - args[4]);
}
break;
case INDEX_op_extract_i32:
tcg_out_rlw(s, RLWINM, args[0], args[1],
32 - args[2], 32 - args[3], 31);
break;
case INDEX_op_extract_i64:
tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]);
break;
case INDEX_op_movcond_i32:
tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
args[3], args[4], const_args[2]);
break;
case INDEX_op_movcond_i64:
tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
args[3], args[4], const_args[2]);
break;
#if TCG_TARGET_REG_BITS == 64
case INDEX_op_add2_i64:
#else
case INDEX_op_add2_i32:
#endif
/* Note that the CA bit is defined based on the word size of the
environment. So in 64-bit mode it's always carry-out of bit 63.
The fallback code using deposit works just as well for 32-bit. */
a0 = args[0], a1 = args[1];
if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
a0 = TCG_REG_R0;
}
if (const_args[4]) {
tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
} else {
tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
}
if (const_args[5]) {
tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
} else {
tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
}
if (a0 != args[0]) {
tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
}
break;
#if TCG_TARGET_REG_BITS == 64
case INDEX_op_sub2_i64:
#else
case INDEX_op_sub2_i32:
#endif
a0 = args[0], a1 = args[1];
if (a0 == args[5] || (!const_args[3] && a0 == args[3])) {
a0 = TCG_REG_R0;
}
if (const_args[2]) {
tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2]));
} else {
tcg_out32(s, SUBFC | TAB(a0, args[4], args[2]));
}
if (const_args[3]) {
tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
} else {
tcg_out32(s, SUBFE | TAB(a1, args[5], args[3]));
}
if (a0 != args[0]) {
tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
}
break;
case INDEX_op_muluh_i32:
tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2]));
break;
case INDEX_op_mulsh_i32:
tcg_out32(s, MULHW | TAB(args[0], args[1], args[2]));
break;
case INDEX_op_muluh_i64:
tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
break;
case INDEX_op_mulsh_i64:
tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
break;
case INDEX_op_mb:
tcg_out_mb(s, args[0]);
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */
case INDEX_op_ext8s_i64:
case INDEX_op_ext8u_i32:
case INDEX_op_ext8u_i64:
case INDEX_op_ext16s_i32:
case INDEX_op_ext16s_i64:
case INDEX_op_ext16u_i32:
case INDEX_op_ext16u_i64:
case INDEX_op_ext32s_i64:
case INDEX_op_ext32u_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
case INDEX_op_extrl_i64_i32:
default:
g_assert_not_reached();
}
}
@@ -3578,49 +3587,49 @@ static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0,
static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
TCGv_vec v1, TCGv_vec v2, TCGCond cond)
{
bool need_swap = false, need_inv = false;
tcg_debug_assert(vece <= MO_32 || have_isa_2_07);
switch (cond) {
case TCG_COND_EQ:
case TCG_COND_GT:
case TCG_COND_GTU:
break;
case TCG_COND_NE:
if (have_isa_3_00 && vece <= MO_32) {
break;
}
- /* fall through */
+ fallthrough;
case TCG_COND_LE:
case TCG_COND_LEU:
need_inv = true;
break;
case TCG_COND_LT:
case TCG_COND_LTU:
need_swap = true;
break;
case TCG_COND_GE:
case TCG_COND_GEU:
need_swap = need_inv = true;
break;
default:
g_assert_not_reached();
}
if (need_inv) {
cond = tcg_invert_cond(cond);
}
if (need_swap) {
TCGv_vec t1;
t1 = v1, v1 = v2, v2 = t1;
cond = tcg_swap_cond(cond);
}
vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0),
tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond);
if (need_inv) {
tcg_gen_not_vec(vece, v0, v0);
}
}
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index d6dbcaf3cb..8b0e7b000c 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -939,37 +939,37 @@ static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
static void tcg_out_negsetcond(TCGContext *s, TCGCond cond, TCGReg ret,
TCGReg arg1, tcg_target_long arg2, bool c2)
{
int tmpflags;
TCGReg tmp;
/* For LT/GE comparison against 0, replicate the sign bit. */
if (c2 && arg2 == 0) {
switch (cond) {
case TCG_COND_GE:
tcg_out_opc_imm(s, OPC_XORI, ret, arg1, -1);
arg1 = ret;
- /* fall through */
+ fallthrough;
case TCG_COND_LT:
tcg_out_opc_imm(s, OPC_SRAI, ret, arg1, TCG_TARGET_REG_BITS - 1);
return;
default:
break;
}
}
tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2);
tmp = tmpflags & ~SETCOND_FLAGS;
/* If intermediate result is zero/non-zero: test != 0. */
if (tmpflags & SETCOND_NEZ) {
tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp);
tmp = ret;
}
/* Produce the 0/-1 result. */
if (tmpflags & SETCOND_INV) {
tcg_out_opc_imm(s, OPC_ADDI, ret, tmp, -1);
} else {
tcg_out_opc_reg(s, OPC_SUB, ret, TCG_REG_ZERO, tmp);
}
}
@@ -1351,35 +1351,36 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val,
TCGReg base, MemOp opc, TCGType type)
{
/* Byte swapping is left to middle-end expansion. */
tcg_debug_assert((opc & MO_BSWAP) == 0);
switch (opc & (MO_SSIZE)) {
case MO_UB:
tcg_out_opc_imm(s, OPC_LBU, val, base, 0);
break;
case MO_SB:
tcg_out_opc_imm(s, OPC_LB, val, base, 0);
break;
case MO_UW:
tcg_out_opc_imm(s, OPC_LHU, val, base, 0);
break;
case MO_SW:
tcg_out_opc_imm(s, OPC_LH, val, base, 0);
break;
case MO_UL:
if (type == TCG_TYPE_I64) {
tcg_out_opc_imm(s, OPC_LWU, val, base, 0);
break;
}
/* FALLTHRU */
+ fallthrough;
case MO_SL:
tcg_out_opc_imm(s, OPC_LW, val, base, 0);
break;
case MO_UQ:
tcg_out_opc_imm(s, OPC_LD, val, base, 0);
break;
default:
g_assert_not_reached();
}
}
@@ -1486,405 +1487,405 @@ void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
TCGArg a0 = args[0];
TCGArg a1 = args[1];
TCGArg a2 = args[2];
int c2 = const_args[2];
switch (opc) {
case INDEX_op_goto_ptr:
tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0);
break;
case INDEX_op_br:
tcg_out_reloc(s, s->code_ptr, R_RISCV_JAL, arg_label(a0), 0);
tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0);
break;
case INDEX_op_ld8u_i32:
case INDEX_op_ld8u_i64:
tcg_out_ldst(s, OPC_LBU, a0, a1, a2);
break;
case INDEX_op_ld8s_i32:
case INDEX_op_ld8s_i64:
tcg_out_ldst(s, OPC_LB, a0, a1, a2);
break;
case INDEX_op_ld16u_i32:
case INDEX_op_ld16u_i64:
tcg_out_ldst(s, OPC_LHU, a0, a1, a2);
break;
case INDEX_op_ld16s_i32:
case INDEX_op_ld16s_i64:
tcg_out_ldst(s, OPC_LH, a0, a1, a2);
break;
case INDEX_op_ld32u_i64:
tcg_out_ldst(s, OPC_LWU, a0, a1, a2);
break;
case INDEX_op_ld_i32:
case INDEX_op_ld32s_i64:
tcg_out_ldst(s, OPC_LW, a0, a1, a2);
break;
case INDEX_op_ld_i64:
tcg_out_ldst(s, OPC_LD, a0, a1, a2);
break;
case INDEX_op_st8_i32:
case INDEX_op_st8_i64:
tcg_out_ldst(s, OPC_SB, a0, a1, a2);
break;
case INDEX_op_st16_i32:
case INDEX_op_st16_i64:
tcg_out_ldst(s, OPC_SH, a0, a1, a2);
break;
case INDEX_op_st_i32:
case INDEX_op_st32_i64:
tcg_out_ldst(s, OPC_SW, a0, a1, a2);
break;
case INDEX_op_st_i64:
tcg_out_ldst(s, OPC_SD, a0, a1, a2);
break;
case INDEX_op_add_i32:
if (c2) {
tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, a2);
} else {
tcg_out_opc_reg(s, OPC_ADDW, a0, a1, a2);
}
break;
case INDEX_op_add_i64:
if (c2) {
tcg_out_opc_imm(s, OPC_ADDI, a0, a1, a2);
} else {
tcg_out_opc_reg(s, OPC_ADD, a0, a1, a2);
}
break;
case INDEX_op_sub_i32:
if (c2) {
tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, -a2);
} else {
tcg_out_opc_reg(s, OPC_SUBW, a0, a1, a2);
}
break;
case INDEX_op_sub_i64:
if (c2) {
tcg_out_opc_imm(s, OPC_ADDI, a0, a1, -a2);
} else {
tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2);
}
break;
case INDEX_op_and_i32:
case INDEX_op_and_i64:
if (c2) {
tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2);
} else {
tcg_out_opc_reg(s, OPC_AND, a0, a1, a2);
}
break;
case INDEX_op_or_i32:
case INDEX_op_or_i64:
if (c2) {
tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2);
} else {
tcg_out_opc_reg(s, OPC_OR, a0, a1, a2);
}
break;
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
if (c2) {
tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2);
} else {
tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2);
}
break;
case INDEX_op_andc_i32:
case INDEX_op_andc_i64:
if (c2) {
tcg_out_opc_imm(s, OPC_ANDI, a0, a1, ~a2);
} else {
tcg_out_opc_reg(s, OPC_ANDN, a0, a1, a2);
}
break;
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
if (c2) {
tcg_out_opc_imm(s, OPC_ORI, a0, a1, ~a2);
} else {
tcg_out_opc_reg(s, OPC_ORN, a0, a1, a2);
}
break;
case INDEX_op_eqv_i32:
case INDEX_op_eqv_i64:
if (c2) {
tcg_out_opc_imm(s, OPC_XORI, a0, a1, ~a2);
} else {
tcg_out_opc_reg(s, OPC_XNOR, a0, a1, a2);
}
break;
case INDEX_op_not_i32:
case INDEX_op_not_i64:
tcg_out_opc_imm(s, OPC_XORI, a0, a1, -1);
break;
case INDEX_op_neg_i32:
tcg_out_opc_reg(s, OPC_SUBW, a0, TCG_REG_ZERO, a1);
break;
case INDEX_op_neg_i64:
tcg_out_opc_reg(s, OPC_SUB, a0, TCG_REG_ZERO, a1);
break;
case INDEX_op_mul_i32:
tcg_out_opc_reg(s, OPC_MULW, a0, a1, a2);
break;
case INDEX_op_mul_i64:
tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
break;
case INDEX_op_div_i32:
tcg_out_opc_reg(s, OPC_DIVW, a0, a1, a2);
break;
case INDEX_op_div_i64:
tcg_out_opc_reg(s, OPC_DIV, a0, a1, a2);
break;
case INDEX_op_divu_i32:
tcg_out_opc_reg(s, OPC_DIVUW, a0, a1, a2);
break;
case INDEX_op_divu_i64:
tcg_out_opc_reg(s, OPC_DIVU, a0, a1, a2);
break;
case INDEX_op_rem_i32:
tcg_out_opc_reg(s, OPC_REMW, a0, a1, a2);
break;
case INDEX_op_rem_i64:
tcg_out_opc_reg(s, OPC_REM, a0, a1, a2);
break;
case INDEX_op_remu_i32:
tcg_out_opc_reg(s, OPC_REMUW, a0, a1, a2);
break;
case INDEX_op_remu_i64:
tcg_out_opc_reg(s, OPC_REMU, a0, a1, a2);
break;
case INDEX_op_shl_i32:
if (c2) {
tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2 & 0x1f);
} else {
tcg_out_opc_reg(s, OPC_SLLW, a0, a1, a2);
}
break;
case INDEX_op_shl_i64:
if (c2) {
tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2 & 0x3f);
} else {
tcg_out_opc_reg(s, OPC_SLL, a0, a1, a2);
}
break;
case INDEX_op_shr_i32:
if (c2) {
tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2 & 0x1f);
} else {
tcg_out_opc_reg(s, OPC_SRLW, a0, a1, a2);
}
break;
case INDEX_op_shr_i64:
if (c2) {
tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2 & 0x3f);
} else {
tcg_out_opc_reg(s, OPC_SRL, a0, a1, a2);
}
break;
case INDEX_op_sar_i32:
if (c2) {
tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2 & 0x1f);
} else {
tcg_out_opc_reg(s, OPC_SRAW, a0, a1, a2);
}
break;
case INDEX_op_sar_i64:
if (c2) {
tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2 & 0x3f);
} else {
tcg_out_opc_reg(s, OPC_SRA, a0, a1, a2);
}
break;
case INDEX_op_rotl_i32:
if (c2) {
tcg_out_opc_imm(s, OPC_RORIW, a0, a1, -a2 & 0x1f);
} else {
tcg_out_opc_reg(s, OPC_ROLW, a0, a1, a2);
}
break;
case INDEX_op_rotl_i64:
if (c2) {
tcg_out_opc_imm(s, OPC_RORI, a0, a1, -a2 & 0x3f);
} else {
tcg_out_opc_reg(s, OPC_ROL, a0, a1, a2);
}
break;
case INDEX_op_rotr_i32:
if (c2) {
tcg_out_opc_imm(s, OPC_RORIW, a0, a1, a2 & 0x1f);
} else {
tcg_out_opc_reg(s, OPC_RORW, a0, a1, a2);
}
break;
case INDEX_op_rotr_i64:
if (c2) {
tcg_out_opc_imm(s, OPC_RORI, a0, a1, a2 & 0x3f);
} else {
tcg_out_opc_reg(s, OPC_ROR, a0, a1, a2);
}
break;
case INDEX_op_bswap64_i64:
tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
break;
case INDEX_op_bswap32_i32:
a2 = 0;
- /* fall through */
+ fallthrough;
case INDEX_op_bswap32_i64:
tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
if (a2 & TCG_BSWAP_OZ) {
tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 32);
} else {
tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 32);
}
break;
case INDEX_op_bswap16_i64:
case INDEX_op_bswap16_i32:
tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
if (a2 & TCG_BSWAP_OZ) {
tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 48);
} else {
tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 48);
}
break;
case INDEX_op_ctpop_i32:
tcg_out_opc_imm(s, OPC_CPOPW, a0, a1, 0);
break;
case INDEX_op_ctpop_i64:
tcg_out_opc_imm(s, OPC_CPOP, a0, a1, 0);
break;
case INDEX_op_clz_i32:
tcg_out_cltz(s, TCG_TYPE_I32, OPC_CLZW, a0, a1, a2, c2);
break;
case INDEX_op_clz_i64:
tcg_out_cltz(s, TCG_TYPE_I64, OPC_CLZ, a0, a1, a2, c2);
break;
case INDEX_op_ctz_i32:
tcg_out_cltz(s, TCG_TYPE_I32, OPC_CTZW, a0, a1, a2, c2);
break;
case INDEX_op_ctz_i64:
tcg_out_cltz(s, TCG_TYPE_I64, OPC_CTZ, a0, a1, a2, c2);
break;
case INDEX_op_add2_i32:
tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
const_args[4], const_args[5], false, true);
break;
case INDEX_op_add2_i64:
tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
const_args[4], const_args[5], false, false);
break;
case INDEX_op_sub2_i32:
tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
const_args[4], const_args[5], true, true);
break;
case INDEX_op_sub2_i64:
tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
const_args[4], const_args[5], true, false);
break;
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
break;
case INDEX_op_setcond_i32:
case INDEX_op_setcond_i64:
tcg_out_setcond(s, args[3], a0, a1, a2, c2);
break;
case INDEX_op_negsetcond_i32:
case INDEX_op_negsetcond_i64:
tcg_out_negsetcond(s, args[3], a0, a1, a2, c2);
break;
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
tcg_out_movcond(s, args[5], a0, a1, a2, c2,
args[3], const_args[3], args[4], const_args[4]);
break;
case INDEX_op_qemu_ld_a32_i32:
case INDEX_op_qemu_ld_a64_i32:
tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
break;
case INDEX_op_qemu_ld_a32_i64:
case INDEX_op_qemu_ld_a64_i64:
tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64);
break;
case INDEX_op_qemu_st_a32_i32:
case INDEX_op_qemu_st_a64_i32:
tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32);
break;
case INDEX_op_qemu_st_a32_i64:
case INDEX_op_qemu_st_a64_i64:
tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64);
break;
case INDEX_op_extrh_i64_i32:
tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32);
break;
case INDEX_op_mulsh_i32:
case INDEX_op_mulsh_i64:
tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2);
break;
case INDEX_op_muluh_i32:
case INDEX_op_muluh_i64:
tcg_out_opc_reg(s, OPC_MULHU, a0, a1, a2);
break;
case INDEX_op_mb:
tcg_out_mb(s, a0);
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */
case INDEX_op_ext8s_i64:
case INDEX_op_ext8u_i32:
case INDEX_op_ext8u_i64:
case INDEX_op_ext16s_i32:
case INDEX_op_ext16s_i64:
case INDEX_op_ext16u_i32:
case INDEX_op_ext16u_i64:
case INDEX_op_ext32s_i64:
case INDEX_op_ext32u_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
case INDEX_op_extrl_i64_i32:
default:
g_assert_not_reached();
}
}
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 4ef9ac3d5b..3656b8ddf0 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -801,37 +801,37 @@ static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest,
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
{
if (src == dst) {
return true;
}
switch (type) {
case TCG_TYPE_I32:
if (likely(is_general_reg(dst) && is_general_reg(src))) {
tcg_out_insn(s, RR, LR, dst, src);
break;
}
- /* fallthru */
+ fallthrough;
case TCG_TYPE_I64:
if (likely(is_general_reg(dst))) {
if (likely(is_general_reg(src))) {
tcg_out_insn(s, RRE, LGR, dst, src);
} else {
tcg_out_insn(s, VRSc, VLGV, dst, 0, 0, src, 3);
}
break;
} else if (is_general_reg(src)) {
tcg_out_insn(s, VRSb, VLVG, dst, 0, 0, src, 3);
break;
}
- /* fallthru */
+ fallthrough;
case TCG_TYPE_V64:
case TCG_TYPE_V128:
tcg_out_insn(s, VRRa, VLR, dst, src, 0);
break;
default:
g_assert_not_reached();
}
return true;
}
@@ -965,33 +965,34 @@ static void tcg_out_vrx_mem(TCGContext *s, S390Opcode opc_vrx,
/* load data without address translation or endianness conversion */
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data,
TCGReg base, intptr_t ofs)
{
switch (type) {
case TCG_TYPE_I32:
if (likely(is_general_reg(data))) {
tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs);
break;
}
tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_32);
break;
case TCG_TYPE_I64:
if (likely(is_general_reg(data))) {
tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs);
break;
}
/* fallthru */
+ fallthrough;
case TCG_TYPE_V64:
tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_64);
break;
case TCG_TYPE_V128:
/* Hint quadword aligned. */
tcg_out_vrx_mem(s, VRX_VL, data, base, TCG_REG_NONE, ofs, 4);
break;
default:
g_assert_not_reached();
}
}
@@ -999,32 +1000,33 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data,
static void tcg_out_st(TCGContext *s, TCGType type, TCGReg data,
TCGReg base, intptr_t ofs)
{
switch (type) {
case TCG_TYPE_I32:
if (likely(is_general_reg(data))) {
tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs);
} else {
tcg_out_vrx_mem(s, VRX_VSTEF, data, base, TCG_REG_NONE, ofs, 1);
}
break;
case TCG_TYPE_I64:
if (likely(is_general_reg(data))) {
tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs);
break;
}
/* fallthru */
+ fallthrough;
case TCG_TYPE_V64:
tcg_out_vrx_mem(s, VRX_VSTEG, data, base, TCG_REG_NONE, ofs, 0);
break;
case TCG_TYPE_V128:
/* Hint quadword aligned. */
tcg_out_vrx_mem(s, VRX_VST, data, base, TCG_REG_NONE, ofs, 4);
break;
default:
g_assert_not_reached();
}
}
@@ -1268,93 +1270,95 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,
static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond,
TCGReg dest, TCGReg c1, TCGArg c2,
bool c2const, bool neg)
{
int cc;
/* With LOC2, we can always emit the minimum 3 insns. */
if (HAVE_FACILITY(LOAD_ON_COND2)) {
/* Emit: d = 0, d = (cc ? 1 : d). */
cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
tcg_out_insn(s, RIEg, LOCGHI, dest, neg ? -1 : 1, cc);
return;
}
switch (cond) {
case TCG_COND_GEU:
case TCG_COND_LTU:
case TCG_COND_LT:
case TCG_COND_GE:
/* Swap operands so that we can use LEU/GTU/GT/LE. */
if (!c2const) {
TCGReg t = c1;
c1 = c2;
c2 = t;
cond = tcg_swap_cond(cond);
}
break;
default:
break;
}
switch (cond) {
case TCG_COND_NE:
/* X != 0 is X > 0. */
if (c2const && c2 == 0) {
cond = TCG_COND_GTU;
} else {
break;
}
/* fallthru */
+ fallthrough;
case TCG_COND_GTU:
case TCG_COND_GT:
/*
* The result of a compare has CC=2 for GT and CC=3 unused.
* ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit.
*/
tgen_cmp(s, type, cond, c1, c2, c2const, true);
tcg_out_movi(s, type, dest, 0);
tcg_out_insn(s, RRE, ALCGR, dest, dest);
if (neg) {
if (type == TCG_TYPE_I32) {
tcg_out_insn(s, RR, LCR, dest, dest);
} else {
tcg_out_insn(s, RRE, LCGR, dest, dest);
}
}
return;
case TCG_COND_EQ:
/* X == 0 is X <= 0. */
if (c2const && c2 == 0) {
cond = TCG_COND_LEU;
} else {
break;
}
/* fallthru */
+ fallthrough;
case TCG_COND_LEU:
case TCG_COND_LE:
/*
* As above, but we're looking for borrow, or !carry.
* The second insn computes d - d - borrow, or -1 for true
* and 0 for false. So we must mask to 1 bit afterward.
*/
tgen_cmp(s, type, cond, c1, c2, c2const, true);
tcg_out_insn(s, RRE, SLBGR, dest, dest);
if (!neg) {
tgen_andi(s, type, dest, 1);
}
return;
default:
g_assert_not_reached();
}
cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
/* Emit: d = 0, t = 1, d = (cc ? t : d). */
tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, neg ? -1 : 1);
tcg_out_insn(s, RRFc, LOCGR, dest, TCG_TMP0, cc);
}
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index feb2d3686b..35e47902f1 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -472,51 +472,51 @@ static TCGType choose_vector_type(const TCGOpcode *list, unsigned vece,
static void do_dup_store(TCGType type, uint32_t dofs, uint32_t oprsz,
uint32_t maxsz, TCGv_vec t_vec)
{
uint32_t i = 0;
tcg_debug_assert(oprsz >= 8);
/*
* This may be expand_clr for the tail of an operation, e.g.
* oprsz == 8 && maxsz == 64. The first 8 bytes of this store
* are misaligned wrt the maximum vector size, so do that first.
*/
if (dofs & 8) {
tcg_gen_stl_vec(t_vec, tcg_env, dofs + i, TCG_TYPE_V64);
i += 8;
}
switch (type) {
case TCG_TYPE_V256:
/*
* Recall that ARM SVE allows vector sizes that are not a
* power of 2, but always a multiple of 16. The intent is
* that e.g. size == 80 would be expanded with 2x32 + 1x16.
*/
for (; i + 32 <= oprsz; i += 32) {
tcg_gen_stl_vec(t_vec, tcg_env, dofs + i, TCG_TYPE_V256);
}
- /* fallthru */
+ fallthrough;
case TCG_TYPE_V128:
for (; i + 16 <= oprsz; i += 16) {
tcg_gen_stl_vec(t_vec, tcg_env, dofs + i, TCG_TYPE_V128);
}
break;
case TCG_TYPE_V64:
for (; i < oprsz; i += 8) {
tcg_gen_stl_vec(t_vec, tcg_env, dofs + i, TCG_TYPE_V64);
}
break;
default:
g_assert_not_reached();
}
if (oprsz < maxsz) {
expand_clr(dofs + oprsz, maxsz - oprsz);
}
}
/* Set OPRSZ bytes at DOFS to replications of IN_32, IN_64 or IN_C.
* Only one of IN_32 or IN_64 may be set;
* IN_C is used if IN_32 and IN_64 are unset.
*/
@@ -1200,484 +1200,484 @@ static void expand_4i_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
/* Expand a vector two-operand operation. */
void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen2 *g)
{
const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
TCGType type;
uint32_t some;
check_size_align(oprsz, maxsz, dofs | aofs);
check_overlap_2(dofs, aofs, maxsz);
type = 0;
if (g->fniv) {
type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
}
switch (type) {
case TCG_TYPE_V256:
/* Recall that ARM SVE allows vector sizes that are not a
* power of 2, but always a multiple of 16. The intent is
* that e.g. size == 80 would be expanded with 2x32 + 1x16.
*/
some = QEMU_ALIGN_DOWN(oprsz, 32);
expand_2_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256,
g->load_dest, g->fniv);
if (some == oprsz) {
break;
}
dofs += some;
aofs += some;
oprsz -= some;
maxsz -= some;
- /* fallthru */
+ fallthrough;
case TCG_TYPE_V128:
expand_2_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128,
g->load_dest, g->fniv);
break;
case TCG_TYPE_V64:
expand_2_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64,
g->load_dest, g->fniv);
break;
case 0:
if (g->fni8 && check_size_impl(oprsz, 8)) {
expand_2_i64(dofs, aofs, oprsz, g->load_dest, g->fni8);
} else if (g->fni4 && check_size_impl(oprsz, 4)) {
expand_2_i32(dofs, aofs, oprsz, g->load_dest, g->fni4);
} else {
assert(g->fno != NULL);
tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, g->data, g->fno);
oprsz = maxsz;
}
break;
default:
g_assert_not_reached();
}
tcg_swap_vecop_list(hold_list);
if (oprsz < maxsz) {
expand_clr(dofs + oprsz, maxsz - oprsz);
}
}
/* Expand a vector operation with two vectors and an immediate. */
void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
uint32_t maxsz, int64_t c, const GVecGen2i *g)
{
const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
TCGType type;
uint32_t some;
check_size_align(oprsz, maxsz, dofs | aofs);
check_overlap_2(dofs, aofs, maxsz);
type = 0;
if (g->fniv) {
type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
}
switch (type) {
case TCG_TYPE_V256:
/* Recall that ARM SVE allows vector sizes that are not a
* power of 2, but always a multiple of 16. The intent is
* that e.g. size == 80 would be expanded with 2x32 + 1x16.
*/
some = QEMU_ALIGN_DOWN(oprsz, 32);
expand_2i_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256,
c, g->load_dest, g->fniv);
if (some == oprsz) {
break;
}
dofs += some;
aofs += some;
oprsz -= some;
maxsz -= some;
- /* fallthru */
+ fallthrough;
case TCG_TYPE_V128:
expand_2i_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128,
c, g->load_dest, g->fniv);
break;
case TCG_TYPE_V64:
expand_2i_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64,
c, g->load_dest, g->fniv);
break;
case 0:
if (g->fni8 && check_size_impl(oprsz, 8)) {
expand_2i_i64(dofs, aofs, oprsz, c, g->load_dest, g->fni8);
} else if (g->fni4 && check_size_impl(oprsz, 4)) {
expand_2i_i32(dofs, aofs, oprsz, c, g->load_dest, g->fni4);
} else {
if (g->fno) {
tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, c, g->fno);
} else {
TCGv_i64 tcg_c = tcg_constant_i64(c);
tcg_gen_gvec_2i_ool(dofs, aofs, tcg_c, oprsz,
maxsz, c, g->fnoi);
}
oprsz = maxsz;
}
break;
default:
g_assert_not_reached();
}
tcg_swap_vecop_list(hold_list);
if (oprsz < maxsz) {
expand_clr(dofs + oprsz, maxsz - oprsz);
}
}
/* Expand a vector operation with two vectors and a scalar. */
void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
uint32_t maxsz, TCGv_i64 c, const GVecGen2s *g)
{
TCGType type;
check_size_align(oprsz, maxsz, dofs | aofs);
check_overlap_2(dofs, aofs, maxsz);
type = 0;
if (g->fniv) {
type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
}
if (type != 0) {
const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
TCGv_vec t_vec = tcg_temp_new_vec(type);
uint32_t some;
tcg_gen_dup_i64_vec(g->vece, t_vec, c);
switch (type) {
case TCG_TYPE_V256:
/* Recall that ARM SVE allows vector sizes that are not a
* power of 2, but always a multiple of 16. The intent is
* that e.g. size == 80 would be expanded with 2x32 + 1x16.
*/
some = QEMU_ALIGN_DOWN(oprsz, 32);
expand_2s_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256,
t_vec, g->scalar_first, g->fniv);
if (some == oprsz) {
break;
}
dofs += some;
aofs += some;
oprsz -= some;
maxsz -= some;
- /* fallthru */
+ fallthrough;
case TCG_TYPE_V128:
expand_2s_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128,
t_vec, g->scalar_first, g->fniv);
break;
case TCG_TYPE_V64:
expand_2s_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64,
t_vec, g->scalar_first, g->fniv);
break;
default:
g_assert_not_reached();
}
tcg_temp_free_vec(t_vec);
tcg_swap_vecop_list(hold_list);
} else if (g->fni8 && check_size_impl(oprsz, 8)) {
TCGv_i64 t64 = tcg_temp_new_i64();
tcg_gen_dup_i64(g->vece, t64, c);
expand_2s_i64(dofs, aofs, oprsz, t64, g->scalar_first, g->fni8);
tcg_temp_free_i64(t64);
} else if (g->fni4 && check_size_impl(oprsz, 4)) {
TCGv_i32 t32 = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(t32, c);
tcg_gen_dup_i32(g->vece, t32, t32);
expand_2s_i32(dofs, aofs, oprsz, t32, g->scalar_first, g->fni4);
tcg_temp_free_i32(t32);
} else {
tcg_gen_gvec_2i_ool(dofs, aofs, c, oprsz, maxsz, 0, g->fno);
return;
}
if (oprsz < maxsz) {
expand_clr(dofs + oprsz, maxsz - oprsz);
}
}
/* Expand a vector three-operand operation. */
void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen3 *g)
{
const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
TCGType type;
uint32_t some;
check_size_align(oprsz, maxsz, dofs | aofs | bofs);
check_overlap_3(dofs, aofs, bofs, maxsz);
type = 0;
if (g->fniv) {
type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
}
switch (type) {
case TCG_TYPE_V256:
/* Recall that ARM SVE allows vector sizes that are not a
* power of 2, but always a multiple of 16. The intent is
* that e.g. size == 80 would be expanded with 2x32 + 1x16.
*/
some = QEMU_ALIGN_DOWN(oprsz, 32);
expand_3_vec(g->vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256,
g->load_dest, g->fniv);
if (some == oprsz) {
break;
}
dofs += some;
aofs += some;
bofs += some;
oprsz -= some;
maxsz -= some;
- /* fallthru */
+ fallthrough;
case TCG_TYPE_V128:
expand_3_vec(g->vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128,
g->load_dest, g->fniv);
break;
case TCG_TYPE_V64:
expand_3_vec(g->vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64,
g->load_dest, g->fniv);
break;
case 0:
if (g->fni8 && check_size_impl(oprsz, 8)) {
expand_3_i64(dofs, aofs, bofs, oprsz, g->load_dest, g->fni8);
} else if (g->fni4 && check_size_impl(oprsz, 4)) {
expand_3_i32(dofs, aofs, bofs, oprsz, g->load_dest, g->fni4);
} else {
assert(g->fno != NULL);
tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz,
maxsz, g->data, g->fno);
oprsz = maxsz;
}
break;
default:
g_assert_not_reached();
}
tcg_swap_vecop_list(hold_list);
if (oprsz < maxsz) {
expand_clr(dofs + oprsz, maxsz - oprsz);
}
}
/* Expand a vector operation with three vectors and an immediate. */
void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t oprsz, uint32_t maxsz, int64_t c,
const GVecGen3i *g)
{
const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
TCGType type;
uint32_t some;
check_size_align(oprsz, maxsz, dofs | aofs | bofs);
check_overlap_3(dofs, aofs, bofs, maxsz);
type = 0;
if (g->fniv) {
type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
}
switch (type) {
case TCG_TYPE_V256:
/*
* Recall that ARM SVE allows vector sizes that are not a
* power of 2, but always a multiple of 16. The intent is
* that e.g. size == 80 would be expanded with 2x32 + 1x16.
*/
some = QEMU_ALIGN_DOWN(oprsz, 32);
expand_3i_vec(g->vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256,
c, g->load_dest, g->fniv);
if (some == oprsz) {
break;
}
dofs += some;
aofs += some;
bofs += some;
oprsz -= some;
maxsz -= some;
- /* fallthru */
+ fallthrough;
case TCG_TYPE_V128:
expand_3i_vec(g->vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128,
c, g->load_dest, g->fniv);
break;
case TCG_TYPE_V64:
expand_3i_vec(g->vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64,
c, g->load_dest, g->fniv);
break;
case 0:
if (g->fni8 && check_size_impl(oprsz, 8)) {
expand_3i_i64(dofs, aofs, bofs, oprsz, c, g->load_dest, g->fni8);
} else if (g->fni4 && check_size_impl(oprsz, 4)) {
expand_3i_i32(dofs, aofs, bofs, oprsz, c, g->load_dest, g->fni4);
} else {
assert(g->fno != NULL);
tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, c, g->fno);
oprsz = maxsz;
}
break;
default:
g_assert_not_reached();
}
tcg_swap_vecop_list(hold_list);
if (oprsz < maxsz) {
expand_clr(dofs + oprsz, maxsz - oprsz);
}
}
/* Expand a vector four-operand operation. */
void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen4 *g)
{
const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
TCGType type;
uint32_t some;
check_size_align(oprsz, maxsz, dofs | aofs | bofs | cofs);
check_overlap_4(dofs, aofs, bofs, cofs, maxsz);
type = 0;
if (g->fniv) {
type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
}
switch (type) {
case TCG_TYPE_V256:
/* Recall that ARM SVE allows vector sizes that are not a
* power of 2, but always a multiple of 16. The intent is
* that e.g. size == 80 would be expanded with 2x32 + 1x16.
*/
some = QEMU_ALIGN_DOWN(oprsz, 32);
expand_4_vec(g->vece, dofs, aofs, bofs, cofs, some,
32, TCG_TYPE_V256, g->write_aofs, g->fniv);
if (some == oprsz) {
break;
}
dofs += some;
aofs += some;
bofs += some;
cofs += some;
oprsz -= some;
maxsz -= some;
- /* fallthru */
+ fallthrough;
case TCG_TYPE_V128:
expand_4_vec(g->vece, dofs, aofs, bofs, cofs, oprsz,
16, TCG_TYPE_V128, g->write_aofs, g->fniv);
break;
case TCG_TYPE_V64:
expand_4_vec(g->vece, dofs, aofs, bofs, cofs, oprsz,
8, TCG_TYPE_V64, g->write_aofs, g->fniv);
break;
case 0:
if (g->fni8 && check_size_impl(oprsz, 8)) {
expand_4_i64(dofs, aofs, bofs, cofs, oprsz,
g->write_aofs, g->fni8);
} else if (g->fni4 && check_size_impl(oprsz, 4)) {
expand_4_i32(dofs, aofs, bofs, cofs, oprsz,
g->write_aofs, g->fni4);
} else {
assert(g->fno != NULL);
tcg_gen_gvec_4_ool(dofs, aofs, bofs, cofs,
oprsz, maxsz, g->data, g->fno);
oprsz = maxsz;
}
break;
default:
g_assert_not_reached();
}
tcg_swap_vecop_list(hold_list);
if (oprsz < maxsz) {
expand_clr(dofs + oprsz, maxsz - oprsz);
}
}
/* Expand a vector four-operand operation. */
void tcg_gen_gvec_4i(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
uint32_t oprsz, uint32_t maxsz, int64_t c,
const GVecGen4i *g)
{
const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
TCGType type;
uint32_t some;
check_size_align(oprsz, maxsz, dofs | aofs | bofs | cofs);
check_overlap_4(dofs, aofs, bofs, cofs, maxsz);
type = 0;
if (g->fniv) {
type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
}
switch (type) {
case TCG_TYPE_V256:
/*
* Recall that ARM SVE allows vector sizes that are not a
* power of 2, but always a multiple of 16. The intent is
* that e.g. size == 80 would be expanded with 2x32 + 1x16.
*/
some = QEMU_ALIGN_DOWN(oprsz, 32);
expand_4i_vec(g->vece, dofs, aofs, bofs, cofs, some,
32, TCG_TYPE_V256, c, g->fniv);
if (some == oprsz) {
break;
}
dofs += some;
aofs += some;
bofs += some;
cofs += some;
oprsz -= some;
maxsz -= some;
- /* fallthru */
+ fallthrough;
case TCG_TYPE_V128:
expand_4i_vec(g->vece, dofs, aofs, bofs, cofs, oprsz,
16, TCG_TYPE_V128, c, g->fniv);
break;
case TCG_TYPE_V64:
expand_4i_vec(g->vece, dofs, aofs, bofs, cofs, oprsz,
8, TCG_TYPE_V64, c, g->fniv);
break;
case 0:
if (g->fni8 && check_size_impl(oprsz, 8)) {
expand_4i_i64(dofs, aofs, bofs, cofs, oprsz, c, g->fni8);
} else if (g->fni4 && check_size_impl(oprsz, 4)) {
expand_4i_i32(dofs, aofs, bofs, cofs, oprsz, c, g->fni4);
} else {
assert(g->fno != NULL);
tcg_gen_gvec_4_ool(dofs, aofs, bofs, cofs,
oprsz, maxsz, c, g->fno);
oprsz = maxsz;
}
break;
default:
g_assert_not_reached();
}
tcg_swap_vecop_list(hold_list);
if (oprsz < maxsz) {
expand_clr(dofs + oprsz, maxsz - oprsz);
}
}
/*
* Expand specific vector operations.
*/
@@ -3151,116 +3151,116 @@ static void
do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift,
uint32_t oprsz, uint32_t maxsz, const GVecGen2sh *g)
{
TCGType type;
uint32_t some;
check_size_align(oprsz, maxsz, dofs | aofs);
check_overlap_2(dofs, aofs, maxsz);
/* If the backend has a scalar expansion, great. */
type = choose_vector_type(g->s_list, vece, oprsz, vece == MO_64);
if (type) {
const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
switch (type) {
case TCG_TYPE_V256:
some = QEMU_ALIGN_DOWN(oprsz, 32);
expand_2sh_vec(vece, dofs, aofs, some, 32,
TCG_TYPE_V256, shift, g->fniv_s);
if (some == oprsz) {
break;
}
dofs += some;
aofs += some;
oprsz -= some;
maxsz -= some;
- /* fallthru */
+ fallthrough;
case TCG_TYPE_V128:
expand_2sh_vec(vece, dofs, aofs, oprsz, 16,
TCG_TYPE_V128, shift, g->fniv_s);
break;
case TCG_TYPE_V64:
expand_2sh_vec(vece, dofs, aofs, oprsz, 8,
TCG_TYPE_V64, shift, g->fniv_s);
break;
default:
g_assert_not_reached();
}
tcg_swap_vecop_list(hold_list);
goto clear_tail;
}
/* If the backend supports variable vector shifts, also cool. */
type = choose_vector_type(g->v_list, vece, oprsz, vece == MO_64);
if (type) {
const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
TCGv_vec v_shift = tcg_temp_new_vec(type);
if (vece == MO_64) {
TCGv_i64 sh64 = tcg_temp_ebb_new_i64();
tcg_gen_extu_i32_i64(sh64, shift);
tcg_gen_dup_i64_vec(MO_64, v_shift, sh64);
tcg_temp_free_i64(sh64);
} else {
tcg_gen_dup_i32_vec(vece, v_shift, shift);
}
switch (type) {
case TCG_TYPE_V256:
some = QEMU_ALIGN_DOWN(oprsz, 32);
expand_2s_vec(vece, dofs, aofs, some, 32, TCG_TYPE_V256,
v_shift, false, g->fniv_v);
if (some == oprsz) {
break;
}
dofs += some;
aofs += some;
oprsz -= some;
maxsz -= some;
- /* fallthru */
+ fallthrough;
case TCG_TYPE_V128:
expand_2s_vec(vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128,
v_shift, false, g->fniv_v);
break;
case TCG_TYPE_V64:
expand_2s_vec(vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64,
v_shift, false, g->fniv_v);
break;
default:
g_assert_not_reached();
}
tcg_temp_free_vec(v_shift);
tcg_swap_vecop_list(hold_list);
goto clear_tail;
}
/* Otherwise fall back to integral... */
if (vece == MO_32 && check_size_impl(oprsz, 4)) {
expand_2s_i32(dofs, aofs, oprsz, shift, false, g->fni4);
} else if (vece == MO_64 && check_size_impl(oprsz, 8)) {
TCGv_i64 sh64 = tcg_temp_ebb_new_i64();
tcg_gen_extu_i32_i64(sh64, shift);
expand_2s_i64(dofs, aofs, oprsz, sh64, false, g->fni8);
tcg_temp_free_i64(sh64);
} else {
TCGv_ptr a0 = tcg_temp_ebb_new_ptr();
TCGv_ptr a1 = tcg_temp_ebb_new_ptr();
TCGv_i32 desc = tcg_temp_ebb_new_i32();
tcg_gen_shli_i32(desc, shift, SIMD_DATA_SHIFT);
tcg_gen_ori_i32(desc, desc, simd_desc(oprsz, maxsz, 0));
tcg_gen_addi_ptr(a0, tcg_env, dofs);
tcg_gen_addi_ptr(a1, tcg_env, aofs);
g->fno[vece](a0, a1, desc);
tcg_temp_free_ptr(a0);
tcg_temp_free_ptr(a1);
tcg_temp_free_i32(desc);
return;
}
clear_tail:
if (oprsz < maxsz) {
expand_clr(dofs + oprsz, maxsz - oprsz);
}
}
@@ -3737,111 +3737,111 @@ static void expand_cmp_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,
uint32_t aofs, uint32_t bofs,
uint32_t oprsz, uint32_t maxsz)
{
static const TCGOpcode cmp_list[] = { INDEX_op_cmp_vec, 0 };
static gen_helper_gvec_3 * const eq_fn[4] = {
gen_helper_gvec_eq8, gen_helper_gvec_eq16,
gen_helper_gvec_eq32, gen_helper_gvec_eq64
};
static gen_helper_gvec_3 * const ne_fn[4] = {
gen_helper_gvec_ne8, gen_helper_gvec_ne16,
gen_helper_gvec_ne32, gen_helper_gvec_ne64
};
static gen_helper_gvec_3 * const lt_fn[4] = {
gen_helper_gvec_lt8, gen_helper_gvec_lt16,
gen_helper_gvec_lt32, gen_helper_gvec_lt64
};
static gen_helper_gvec_3 * const le_fn[4] = {
gen_helper_gvec_le8, gen_helper_gvec_le16,
gen_helper_gvec_le32, gen_helper_gvec_le64
};
static gen_helper_gvec_3 * const ltu_fn[4] = {
gen_helper_gvec_ltu8, gen_helper_gvec_ltu16,
gen_helper_gvec_ltu32, gen_helper_gvec_ltu64
};
static gen_helper_gvec_3 * const leu_fn[4] = {
gen_helper_gvec_leu8, gen_helper_gvec_leu16,
gen_helper_gvec_leu32, gen_helper_gvec_leu64
};
static gen_helper_gvec_3 * const * const fns[16] = {
[TCG_COND_EQ] = eq_fn,
[TCG_COND_NE] = ne_fn,
[TCG_COND_LT] = lt_fn,
[TCG_COND_LE] = le_fn,
[TCG_COND_LTU] = ltu_fn,
[TCG_COND_LEU] = leu_fn,
};
const TCGOpcode *hold_list;
TCGType type;
uint32_t some;
check_size_align(oprsz, maxsz, dofs | aofs | bofs);
check_overlap_3(dofs, aofs, bofs, maxsz);
if (cond == TCG_COND_NEVER || cond == TCG_COND_ALWAYS) {
do_dup(MO_8, dofs, oprsz, maxsz,
NULL, NULL, -(cond == TCG_COND_ALWAYS));
return;
}
/*
* Implement inline with a vector type, if possible.
* Prefer integer when 64-bit host and 64-bit comparison.
*/
hold_list = tcg_swap_vecop_list(cmp_list);
type = choose_vector_type(cmp_list, vece, oprsz,
TCG_TARGET_REG_BITS == 64 && vece == MO_64);
switch (type) {
case TCG_TYPE_V256:
/* Recall that ARM SVE allows vector sizes that are not a
* power of 2, but always a multiple of 16. The intent is
* that e.g. size == 80 would be expanded with 2x32 + 1x16.
*/
some = QEMU_ALIGN_DOWN(oprsz, 32);
expand_cmp_vec(vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256, cond);
if (some == oprsz) {
break;
}
dofs += some;
aofs += some;
bofs += some;
oprsz -= some;
maxsz -= some;
- /* fallthru */
+ fallthrough;
case TCG_TYPE_V128:
expand_cmp_vec(vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128, cond);
break;
case TCG_TYPE_V64:
expand_cmp_vec(vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64, cond);
break;
case 0:
if (vece == MO_64 && check_size_impl(oprsz, 8)) {
expand_cmp_i64(dofs, aofs, bofs, oprsz, cond);
} else if (vece == MO_32 && check_size_impl(oprsz, 4)) {
expand_cmp_i32(dofs, aofs, bofs, oprsz, cond);
} else {
gen_helper_gvec_3 * const *fn = fns[cond];
if (fn == NULL) {
uint32_t tmp;
tmp = aofs, aofs = bofs, bofs = tmp;
cond = tcg_swap_cond(cond);
fn = fns[cond];
assert(fn != NULL);
}
tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, 0, fn[vece]);
oprsz = maxsz;
}
break;
default:
g_assert_not_reached();
}
tcg_swap_vecop_list(hold_list);
if (oprsz < maxsz) {
expand_clr(dofs + oprsz, maxsz - oprsz);
}
}
@@ -3864,125 +3864,125 @@ static void expand_cmps_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
void tcg_gen_gvec_cmps(TCGCond cond, unsigned vece, uint32_t dofs,
uint32_t aofs, TCGv_i64 c,
uint32_t oprsz, uint32_t maxsz)
{
static const TCGOpcode cmp_list[] = { INDEX_op_cmp_vec, 0 };
static gen_helper_gvec_2i * const eq_fn[4] = {
gen_helper_gvec_eqs8, gen_helper_gvec_eqs16,
gen_helper_gvec_eqs32, gen_helper_gvec_eqs64
};
static gen_helper_gvec_2i * const lt_fn[4] = {
gen_helper_gvec_lts8, gen_helper_gvec_lts16,
gen_helper_gvec_lts32, gen_helper_gvec_lts64
};
static gen_helper_gvec_2i * const le_fn[4] = {
gen_helper_gvec_les8, gen_helper_gvec_les16,
gen_helper_gvec_les32, gen_helper_gvec_les64
};
static gen_helper_gvec_2i * const ltu_fn[4] = {
gen_helper_gvec_ltus8, gen_helper_gvec_ltus16,
gen_helper_gvec_ltus32, gen_helper_gvec_ltus64
};
static gen_helper_gvec_2i * const leu_fn[4] = {
gen_helper_gvec_leus8, gen_helper_gvec_leus16,
gen_helper_gvec_leus32, gen_helper_gvec_leus64
};
static gen_helper_gvec_2i * const * const fns[16] = {
[TCG_COND_EQ] = eq_fn,
[TCG_COND_LT] = lt_fn,
[TCG_COND_LE] = le_fn,
[TCG_COND_LTU] = ltu_fn,
[TCG_COND_LEU] = leu_fn,
};
TCGType type;
check_size_align(oprsz, maxsz, dofs | aofs);
check_overlap_2(dofs, aofs, maxsz);
if (cond == TCG_COND_NEVER || cond == TCG_COND_ALWAYS) {
do_dup(MO_8, dofs, oprsz, maxsz,
NULL, NULL, -(cond == TCG_COND_ALWAYS));
return;
}
/*
* Implement inline with a vector type, if possible.
* Prefer integer when 64-bit host and 64-bit comparison.
*/
type = choose_vector_type(cmp_list, vece, oprsz,
TCG_TARGET_REG_BITS == 64 && vece == MO_64);
if (type != 0) {
const TCGOpcode *hold_list = tcg_swap_vecop_list(cmp_list);
TCGv_vec t_vec = tcg_temp_new_vec(type);
uint32_t some;
tcg_gen_dup_i64_vec(vece, t_vec, c);
switch (type) {
case TCG_TYPE_V256:
some = QEMU_ALIGN_DOWN(oprsz, 32);
expand_cmps_vec(vece, dofs, aofs, some, 32,
TCG_TYPE_V256, cond, t_vec);
aofs += some;
dofs += some;
oprsz -= some;
maxsz -= some;
- /* fallthru */
+ fallthrough;
case TCG_TYPE_V128:
some = QEMU_ALIGN_DOWN(oprsz, 16);
expand_cmps_vec(vece, dofs, aofs, some, 16,
TCG_TYPE_V128, cond, t_vec);
break;
case TCG_TYPE_V64:
some = QEMU_ALIGN_DOWN(oprsz, 8);
expand_cmps_vec(vece, dofs, aofs, some, 8,
TCG_TYPE_V64, cond, t_vec);
break;
default:
g_assert_not_reached();
}
tcg_temp_free_vec(t_vec);
tcg_swap_vecop_list(hold_list);
} else if (vece == MO_64 && check_size_impl(oprsz, 8)) {
TCGv_i64 t0 = tcg_temp_ebb_new_i64();
uint32_t i;
for (i = 0; i < oprsz; i += 8) {
tcg_gen_ld_i64(t0, tcg_env, aofs + i);
tcg_gen_negsetcond_i64(cond, t0, t0, c);
tcg_gen_st_i64(t0, tcg_env, dofs + i);
}
tcg_temp_free_i64(t0);
} else if (vece == MO_32 && check_size_impl(oprsz, 4)) {
TCGv_i32 t0 = tcg_temp_ebb_new_i32();
TCGv_i32 t1 = tcg_temp_ebb_new_i32();
uint32_t i;
tcg_gen_extrl_i64_i32(t1, c);
for (i = 0; i < oprsz; i += 8) {
tcg_gen_ld_i32(t0, tcg_env, aofs + i);
tcg_gen_negsetcond_i32(cond, t0, t0, t1);
tcg_gen_st_i32(t0, tcg_env, dofs + i);
}
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);
} else {
gen_helper_gvec_2i * const *fn = fns[cond];
bool inv = false;
if (fn == NULL) {
cond = tcg_invert_cond(cond);
fn = fns[cond];
assert(fn != NULL);
inv = true;
}
tcg_gen_gvec_2i_ool(dofs, aofs, c, oprsz, maxsz, inv, fn[vece]);
return;
}
if (oprsz < maxsz) {
expand_clr(dofs + oprsz, maxsz - oprsz);
}
}
diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c
index df4f22c427..5ad51c8cb8 100644
--- a/tcg/tcg-op-ldst.c
+++ b/tcg/tcg-op-ldst.c
@@ -46,36 +46,36 @@ static void check_max_alignment(unsigned a_bits)
static MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st)
{
unsigned a_bits = get_alignment_bits(op);
check_max_alignment(a_bits);
/* Prefer MO_ALIGN+MO_XX over MO_ALIGN_XX+MO_XX */
if (a_bits == (op & MO_SIZE)) {
op = (op & ~MO_AMASK) | MO_ALIGN;
}
switch (op & MO_SIZE) {
case MO_8:
op &= ~MO_BSWAP;
break;
case MO_16:
break;
case MO_32:
if (!is64) {
op &= ~MO_SIGN;
}
break;
case MO_64:
if (is64) {
op &= ~MO_SIGN;
break;
}
- /* fall through */
+ fallthrough;
default:
g_assert_not_reached();
}
if (st) {
op &= ~MO_SIGN;
}
return op;
}
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 637b9e6870..84e74badcf 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1,64 +1,65 @@
/*
* Tiny Code Generator for QEMU
*
* Copyright (c) 2008 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
+#include "qemu/compiler.h"
/* Define to jump the ELF file used to communicate with GDB. */
#undef DEBUG_JIT
#include "qemu/error-report.h"
#include "qemu/cutils.h"
#include "qemu/host-utils.h"
#include "qemu/qemu-print.h"
#include "qemu/cacheflush.h"
#include "qemu/cacheinfo.h"
#include "qemu/timer.h"
#include "exec/translation-block.h"
#include "exec/tlb-common.h"
#include "tcg/startup.h"
#include "tcg/tcg-op-common.h"
#if UINTPTR_MAX == UINT32_MAX
# define ELF_CLASS ELFCLASS32
#else
# define ELF_CLASS ELFCLASS64
#endif
#if HOST_BIG_ENDIAN
# define ELF_DATA ELFDATA2MSB
#else
# define ELF_DATA ELFDATA2LSB
#endif
#include "elf.h"
#include "exec/log.h"
#include "tcg/tcg-ldst.h"
#include "tcg/tcg-temp-internal.h"
#include "tcg-internal.h"
#include "accel/tcg/perf.h"
#ifdef CONFIG_USER_ONLY
#include "exec/user/guest-base.h"
#endif
/* Forward declarations for functions declared in tcg-target.c.inc and
used here. */
@@ -1106,180 +1107,180 @@ static void layout_arg_by_ref(TCGCumulativeArgs *cum, TCGHelperInfo *info)
static void init_call_layout(TCGHelperInfo *info)
{
int max_reg_slots = ARRAY_SIZE(tcg_target_call_iarg_regs);
int max_stk_slots = TCG_STATIC_CALL_ARGS_SIZE / sizeof(tcg_target_long);
unsigned typemask = info->typemask;
unsigned typecode;
TCGCumulativeArgs cum = { };
/*
* Parse and place any function return value.
*/
typecode = typemask & 7;
switch (typecode) {
case dh_typecode_void:
info->nr_out = 0;
break;
case dh_typecode_i32:
case dh_typecode_s32:
case dh_typecode_ptr:
info->nr_out = 1;
info->out_kind = TCG_CALL_RET_NORMAL;
break;
case dh_typecode_i64:
case dh_typecode_s64:
info->nr_out = 64 / TCG_TARGET_REG_BITS;
info->out_kind = TCG_CALL_RET_NORMAL;
/* Query the last register now to trigger any assert early. */
tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1);
break;
case dh_typecode_i128:
info->nr_out = 128 / TCG_TARGET_REG_BITS;
info->out_kind = TCG_TARGET_CALL_RET_I128;
switch (TCG_TARGET_CALL_RET_I128) {
case TCG_CALL_RET_NORMAL:
/* Query the last register now to trigger any assert early. */
tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1);
break;
case TCG_CALL_RET_BY_VEC:
/* Query the single register now to trigger any assert early. */
tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0);
break;
case TCG_CALL_RET_BY_REF:
/*
* Allocate the first argument to the output.
* We don't need to store this anywhere, just make it
* unavailable for use in the input loop below.
*/
cum.arg_slot = 1;
break;
default:
qemu_build_not_reached();
}
break;
default:
g_assert_not_reached();
}
/*
* Parse and place function arguments.
*/
for (typemask >>= 3; typemask; typemask >>= 3, cum.arg_idx++) {
TCGCallArgumentKind kind;
TCGType type;
typecode = typemask & 7;
switch (typecode) {
case dh_typecode_i32:
case dh_typecode_s32:
type = TCG_TYPE_I32;
break;
case dh_typecode_i64:
case dh_typecode_s64:
type = TCG_TYPE_I64;
break;
case dh_typecode_ptr:
type = TCG_TYPE_PTR;
break;
case dh_typecode_i128:
type = TCG_TYPE_I128;
break;
default:
g_assert_not_reached();
}
switch (type) {
case TCG_TYPE_I32:
switch (TCG_TARGET_CALL_ARG_I32) {
case TCG_CALL_ARG_EVEN:
layout_arg_even(&cum);
- /* fall through */
+ fallthrough;
case TCG_CALL_ARG_NORMAL:
layout_arg_1(&cum, info, TCG_CALL_ARG_NORMAL);
break;
case TCG_CALL_ARG_EXTEND:
kind = TCG_CALL_ARG_EXTEND_U + (typecode & 1);
layout_arg_1(&cum, info, kind);
break;
default:
qemu_build_not_reached();
}
break;
case TCG_TYPE_I64:
switch (TCG_TARGET_CALL_ARG_I64) {
case TCG_CALL_ARG_EVEN:
layout_arg_even(&cum);
- /* fall through */
+ fallthrough;
case TCG_CALL_ARG_NORMAL:
if (TCG_TARGET_REG_BITS == 32) {
layout_arg_normal_n(&cum, info, 2);
} else {
layout_arg_1(&cum, info, TCG_CALL_ARG_NORMAL);
}
break;
default:
qemu_build_not_reached();
}
break;
case TCG_TYPE_I128:
switch (TCG_TARGET_CALL_ARG_I128) {
case TCG_CALL_ARG_EVEN:
layout_arg_even(&cum);
- /* fall through */
+ fallthrough;
case TCG_CALL_ARG_NORMAL:
layout_arg_normal_n(&cum, info, 128 / TCG_TARGET_REG_BITS);
break;
case TCG_CALL_ARG_BY_REF:
layout_arg_by_ref(&cum, info);
break;
default:
qemu_build_not_reached();
}
break;
default:
g_assert_not_reached();
}
}
info->nr_in = cum.info_in_idx;
/* Validate that we didn't overrun the input array. */
assert(cum.info_in_idx <= ARRAY_SIZE(info->in));
/* Validate the backend has enough argument space. */
assert(cum.arg_slot <= max_reg_slots + max_stk_slots);
/*
* Relocate the "ref_slot" area to the end of the parameters.
* Minimizing this stack offset helps code size for x86,
* which has a signed 8-bit offset encoding.
*/
if (cum.ref_slot != 0) {
int ref_base = 0;
if (cum.arg_slot > max_reg_slots) {
int align = __alignof(Int128) / sizeof(tcg_target_long);
ref_base = cum.arg_slot - max_reg_slots;
if (align > 1) {
ref_base = ROUND_UP(ref_base, align);
}
}
assert(ref_base + cum.ref_slot <= max_stk_slots);
ref_base += max_reg_slots;
if (ref_base != 0) {
for (int i = cum.info_in_idx - 1; i >= 0; --i) {
TCGCallArgumentLoc *loc = &info->in[i];
switch (loc->kind) {
case TCG_CALL_ARG_BY_REF:
case TCG_CALL_ARG_BY_REF_N:
loc->ref_slot += ref_base;
break;
default:
break;
}
}
}
}
}
@@ -2283,31 +2284,31 @@ void tcg_gen_call7(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1,
static void tcg_reg_alloc_start(TCGContext *s)
{
int i, n;
for (i = 0, n = s->nb_temps; i < n; i++) {
TCGTemp *ts = &s->temps[i];
TCGTempVal val = TEMP_VAL_MEM;
switch (ts->kind) {
case TEMP_CONST:
val = TEMP_VAL_CONST;
break;
case TEMP_FIXED:
val = TEMP_VAL_REG;
break;
case TEMP_GLOBAL:
break;
case TEMP_EBB:
val = TEMP_VAL_DEAD;
- /* fall through */
+ fallthrough;
case TEMP_TB:
ts->mem_allocated = 0;
break;
default:
g_assert_not_reached();
}
ts->val_type = val;
}
memset(s->reg_to_temp, 0, sizeof(s->reg_to_temp));
}
@@ -3456,340 +3457,340 @@ static void __attribute__((noinline))
liveness_pass_1(TCGContext *s)
{
int nb_globals = s->nb_globals;
int nb_temps = s->nb_temps;
TCGOp *op, *op_prev;
TCGRegSet *prefs;
int i;
prefs = tcg_malloc(sizeof(TCGRegSet) * nb_temps);
for (i = 0; i < nb_temps; ++i) {
s->temps[i].state_ptr = prefs + i;
}
/* ??? Should be redundant with the exit_tb that ends the TB. */
la_func_end(s, nb_globals, nb_temps);
QTAILQ_FOREACH_REVERSE_SAFE(op, &s->ops, link, op_prev) {
int nb_iargs, nb_oargs;
TCGOpcode opc_new, opc_new2;
bool have_opc_new2;
TCGLifeData arg_life = 0;
TCGTemp *ts;
TCGOpcode opc = op->opc;
const TCGOpDef *def = &tcg_op_defs[opc];
switch (opc) {
case INDEX_op_call:
{
const TCGHelperInfo *info = tcg_call_info(op);
int call_flags = tcg_call_flags(op);
nb_oargs = TCGOP_CALLO(op);
nb_iargs = TCGOP_CALLI(op);
/* pure functions can be removed if their result is unused */
if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) {
for (i = 0; i < nb_oargs; i++) {
ts = arg_temp(op->args[i]);
if (ts->state != TS_DEAD) {
goto do_not_remove_call;
}
}
goto do_remove;
}
do_not_remove_call:
/* Output args are dead. */
for (i = 0; i < nb_oargs; i++) {
ts = arg_temp(op->args[i]);
if (ts->state & TS_DEAD) {
arg_life |= DEAD_ARG << i;
}
if (ts->state & TS_MEM) {
arg_life |= SYNC_ARG << i;
}
ts->state = TS_DEAD;
la_reset_pref(ts);
}
/* Not used -- it will be tcg_target_call_oarg_reg(). */
memset(op->output_pref, 0, sizeof(op->output_pref));
if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS |
TCG_CALL_NO_READ_GLOBALS))) {
la_global_kill(s, nb_globals);
} else if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) {
la_global_sync(s, nb_globals);
}
/* Record arguments that die in this helper. */
for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
ts = arg_temp(op->args[i]);
if (ts->state & TS_DEAD) {
arg_life |= DEAD_ARG << i;
}
}
/* For all live registers, remove call-clobbered prefs. */
la_cross_call(s, nb_temps);
/*
* Input arguments are live for preceding opcodes.
*
* For those arguments that die, and will be allocated in
* registers, clear the register set for that arg, to be
* filled in below. For args that will be on the stack,
* reset to any available reg. Process arguments in reverse
* order so that if a temp is used more than once, the stack
* reset to max happens before the register reset to 0.
*/
for (i = nb_iargs - 1; i >= 0; i--) {
const TCGCallArgumentLoc *loc = &info->in[i];
ts = arg_temp(op->args[nb_oargs + i]);
if (ts->state & TS_DEAD) {
switch (loc->kind) {
case TCG_CALL_ARG_NORMAL:
case TCG_CALL_ARG_EXTEND_U:
case TCG_CALL_ARG_EXTEND_S:
if (arg_slot_reg_p(loc->arg_slot)) {
*la_temp_pref(ts) = 0;
break;
}
- /* fall through */
+ fallthrough;
default:
*la_temp_pref(ts) =
tcg_target_available_regs[ts->type];
break;
}
ts->state &= ~TS_DEAD;
}
}
/*
* For each input argument, add its input register to prefs.
* If a temp is used once, this produces a single set bit;
* if a temp is used multiple times, this produces a set.
*/
for (i = 0; i < nb_iargs; i++) {
const TCGCallArgumentLoc *loc = &info->in[i];
ts = arg_temp(op->args[nb_oargs + i]);
switch (loc->kind) {
case TCG_CALL_ARG_NORMAL:
case TCG_CALL_ARG_EXTEND_U:
case TCG_CALL_ARG_EXTEND_S:
if (arg_slot_reg_p(loc->arg_slot)) {
tcg_regset_set_reg(*la_temp_pref(ts),
tcg_target_call_iarg_regs[loc->arg_slot]);
}
break;
default:
break;
}
}
}
break;
case INDEX_op_insn_start:
break;
case INDEX_op_discard:
/* mark the temporary as dead */
ts = arg_temp(op->args[0]);
ts->state = TS_DEAD;
la_reset_pref(ts);
break;
case INDEX_op_add2_i32:
opc_new = INDEX_op_add_i32;
goto do_addsub2;
case INDEX_op_sub2_i32:
opc_new = INDEX_op_sub_i32;
goto do_addsub2;
case INDEX_op_add2_i64:
opc_new = INDEX_op_add_i64;
goto do_addsub2;
case INDEX_op_sub2_i64:
opc_new = INDEX_op_sub_i64;
do_addsub2:
nb_iargs = 4;
nb_oargs = 2;
/* Test if the high part of the operation is dead, but not
the low part. The result can be optimized to a simple
add or sub. This happens often for x86_64 guest when the
cpu mode is set to 32 bit. */
if (arg_temp(op->args[1])->state == TS_DEAD) {
if (arg_temp(op->args[0])->state == TS_DEAD) {
goto do_remove;
}
/* Replace the opcode and adjust the args in place,
leaving 3 unused args at the end. */
op->opc = opc = opc_new;
op->args[1] = op->args[2];
op->args[2] = op->args[4];
/* Fall through and mark the single-word operation live. */
nb_iargs = 2;
nb_oargs = 1;
}
goto do_not_remove;
case INDEX_op_mulu2_i32:
opc_new = INDEX_op_mul_i32;
opc_new2 = INDEX_op_muluh_i32;
have_opc_new2 = TCG_TARGET_HAS_muluh_i32;
goto do_mul2;
case INDEX_op_muls2_i32:
opc_new = INDEX_op_mul_i32;
opc_new2 = INDEX_op_mulsh_i32;
have_opc_new2 = TCG_TARGET_HAS_mulsh_i32;
goto do_mul2;
case INDEX_op_mulu2_i64:
opc_new = INDEX_op_mul_i64;
opc_new2 = INDEX_op_muluh_i64;
have_opc_new2 = TCG_TARGET_HAS_muluh_i64;
goto do_mul2;
case INDEX_op_muls2_i64:
opc_new = INDEX_op_mul_i64;
opc_new2 = INDEX_op_mulsh_i64;
have_opc_new2 = TCG_TARGET_HAS_mulsh_i64;
goto do_mul2;
do_mul2:
nb_iargs = 2;
nb_oargs = 2;
if (arg_temp(op->args[1])->state == TS_DEAD) {
if (arg_temp(op->args[0])->state == TS_DEAD) {
/* Both parts of the operation are dead. */
goto do_remove;
}
/* The high part of the operation is dead; generate the low. */
op->opc = opc = opc_new;
op->args[1] = op->args[2];
op->args[2] = op->args[3];
} else if (arg_temp(op->args[0])->state == TS_DEAD && have_opc_new2) {
/* The low part of the operation is dead; generate the high. */
op->opc = opc = opc_new2;
op->args[0] = op->args[1];
op->args[1] = op->args[2];
op->args[2] = op->args[3];
} else {
goto do_not_remove;
}
/* Mark the single-word operation live. */
nb_oargs = 1;
goto do_not_remove;
default:
/* XXX: optimize by hardcoding common cases (e.g. triadic ops) */
nb_iargs = def->nb_iargs;
nb_oargs = def->nb_oargs;
/* Test if the operation can be removed because all
its outputs are dead. We assume that nb_oargs == 0
implies side effects */
if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) {
for (i = 0; i < nb_oargs; i++) {
if (arg_temp(op->args[i])->state != TS_DEAD) {
goto do_not_remove;
}
}
goto do_remove;
}
goto do_not_remove;
do_remove:
tcg_op_remove(s, op);
break;
do_not_remove:
for (i = 0; i < nb_oargs; i++) {
ts = arg_temp(op->args[i]);
/* Remember the preference of the uses that followed. */
if (i < ARRAY_SIZE(op->output_pref)) {
op->output_pref[i] = *la_temp_pref(ts);
}
/* Output args are dead. */
if (ts->state & TS_DEAD) {
arg_life |= DEAD_ARG << i;
}
if (ts->state & TS_MEM) {
arg_life |= SYNC_ARG << i;
}
ts->state = TS_DEAD;
la_reset_pref(ts);
}
/* If end of basic block, update. */
if (def->flags & TCG_OPF_BB_EXIT) {
la_func_end(s, nb_globals, nb_temps);
} else if (def->flags & TCG_OPF_COND_BRANCH) {
la_bb_sync(s, nb_globals, nb_temps);
} else if (def->flags & TCG_OPF_BB_END) {
la_bb_end(s, nb_globals, nb_temps);
} else if (def->flags & TCG_OPF_SIDE_EFFECTS) {
la_global_sync(s, nb_globals);
if (def->flags & TCG_OPF_CALL_CLOBBER) {
la_cross_call(s, nb_temps);
}
}
/* Record arguments that die in this opcode. */
for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
ts = arg_temp(op->args[i]);
if (ts->state & TS_DEAD) {
arg_life |= DEAD_ARG << i;
}
}
/* Input arguments are live for preceding opcodes. */
for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
ts = arg_temp(op->args[i]);
if (ts->state & TS_DEAD) {
/* For operands that were dead, initially allow
all regs for the type. */
*la_temp_pref(ts) = tcg_target_available_regs[ts->type];
ts->state &= ~TS_DEAD;
}
}
/* Incorporate constraints for this operand. */
switch (opc) {
case INDEX_op_mov_i32:
case INDEX_op_mov_i64:
/* Note that these are TCG_OPF_NOT_PRESENT and do not
have proper constraints. That said, special case
moves to propagate preferences backward. */
if (IS_DEAD_ARG(1)) {
*la_temp_pref(arg_temp(op->args[0]))
= *la_temp_pref(arg_temp(op->args[1]));
}
break;
default:
for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
const TCGArgConstraint *ct = &def->args_ct[i];
TCGRegSet set, *pset;
ts = arg_temp(op->args[i]);
pset = la_temp_pref(ts);
set = *pset;
set &= ct->regs;
if (ct->ialias) {
set &= output_pref(op, ct->alias_index);
}
/* If the combination is not possible, restart. */
if (set == 0) {
set = ct->regs;
}
*pset = set;
}
break;
}
break;
}
op->life = arg_life;
}
}
/* Liveness analysis: Convert indirect regs to direct temporaries. */
@@ -4115,45 +4116,45 @@ static inline void temp_dead(TCGContext *s, TCGTemp *ts)
/* Sync a temporary to memory. 'allocated_regs' is used in case a temporary
registers needs to be allocated to store a constant. If 'free_or_dead'
is non-zero, subsequently release the temporary; if it is positive, the
temp is dead; if it is negative, the temp is free. */
static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs,
TCGRegSet preferred_regs, int free_or_dead)
{
if (!temp_readonly(ts) && !ts->mem_coherent) {
if (!ts->mem_allocated) {
temp_allocate_frame(s, ts);
}
switch (ts->val_type) {
case TEMP_VAL_CONST:
/* If we're going to free the temp immediately, then we won't
require it later in a register, so attempt to store the
constant to memory directly. */
if (free_or_dead
&& tcg_out_sti(s, ts->type, ts->val,
ts->mem_base->reg, ts->mem_offset)) {
break;
}
temp_load(s, ts, tcg_target_available_regs[ts->type],
allocated_regs, preferred_regs);
- /* fallthrough */
+ fallthrough;
case TEMP_VAL_REG:
tcg_out_st(s, ts->type, ts->reg,
ts->mem_base->reg, ts->mem_offset);
break;
case TEMP_VAL_MEM:
break;
case TEMP_VAL_DEAD:
default:
g_assert_not_reached();
}
ts->mem_coherent = 1;
}
if (free_or_dead) {
temp_free_or_dead(s, ts, free_or_dead);
}
}
/* free register 'reg' by spilling the corresponding temporary if necessary */
@@ -4550,110 +4551,110 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op)
/*
* Specialized code generation for INDEX_op_dup_vec.
*/
static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op)
{
const TCGLifeData arg_life = op->life;
TCGRegSet dup_out_regs, dup_in_regs;
TCGTemp *its, *ots;
TCGType itype, vtype;
unsigned vece;
int lowpart_ofs;
bool ok;
ots = arg_temp(op->args[0]);
its = arg_temp(op->args[1]);
/* ENV should not be modified. */
tcg_debug_assert(!temp_readonly(ots));
itype = its->type;
vece = TCGOP_VECE(op);
vtype = TCGOP_VECL(op) + TCG_TYPE_V64;
if (its->val_type == TEMP_VAL_CONST) {
/* Propagate constant via movi -> dupi. */
tcg_target_ulong val = its->val;
if (IS_DEAD_ARG(1)) {
temp_dead(s, its);
}
tcg_reg_alloc_do_movi(s, ots, val, arg_life, output_pref(op, 0));
return;
}
dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs;
dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs;
/* Allocate the output register now. */
if (ots->val_type != TEMP_VAL_REG) {
TCGRegSet allocated_regs = s->reserved_regs;
TCGReg oreg;
if (!IS_DEAD_ARG(1) && its->val_type == TEMP_VAL_REG) {
/* Make sure to not spill the input register. */
tcg_regset_set_reg(allocated_regs, its->reg);
}
oreg = tcg_reg_alloc(s, dup_out_regs, allocated_regs,
output_pref(op, 0), ots->indirect_base);
set_temp_val_reg(s, ots, oreg);
}
switch (its->val_type) {
case TEMP_VAL_REG:
/*
* The dup constriaints must be broad, covering all possible VECE.
* However, tcg_op_dup_vec() gets to see the VECE and we allow it
* to fail, indicating that extra moves are required for that case.
*/
if (tcg_regset_test_reg(dup_in_regs, its->reg)) {
if (tcg_out_dup_vec(s, vtype, vece, ots->reg, its->reg)) {
goto done;
}
/* Try again from memory or a vector input register. */
}
if (!its->mem_coherent) {
/*
* The input register is not synced, and so an extra store
* would be required to use memory. Attempt an integer-vector
* register move first. We do not have a TCGRegSet for this.
*/
if (tcg_out_mov(s, itype, ots->reg, its->reg)) {
break;
}
/* Sync the temp back to its slot and load from there. */
temp_sync(s, its, s->reserved_regs, 0, 0);
}
- /* fall through */
+ fallthrough;
case TEMP_VAL_MEM:
lowpart_ofs = 0;
if (HOST_BIG_ENDIAN) {
lowpart_ofs = tcg_type_size(itype) - (1 << vece);
}
if (tcg_out_dupm_vec(s, vtype, vece, ots->reg, its->mem_base->reg,
its->mem_offset + lowpart_ofs)) {
goto done;
}
/* Load the input into the destination vector register. */
tcg_out_ld(s, itype, ots->reg, its->mem_base->reg, its->mem_offset);
break;
default:
g_assert_not_reached();
}
/* We now have a vector input register, so dup must succeed. */
ok = tcg_out_dup_vec(s, vtype, vece, ots->reg, ots->reg);
tcg_debug_assert(ok);
done:
ots->mem_coherent = 0;
if (IS_DEAD_ARG(1)) {
temp_dead(s, its);
}
if (NEED_SYNC_ARG(0)) {
temp_sync(s, ots, s->reserved_regs, 0, 0);
}
if (IS_DEAD_ARG(0)) {
temp_dead(s, ots);
}
}
@@ -5185,146 +5186,147 @@ static void load_arg_ref(TCGContext *s, unsigned arg_slot, TCGReg ref_base,
static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
{
const int nb_oargs = TCGOP_CALLO(op);
const int nb_iargs = TCGOP_CALLI(op);
const TCGLifeData arg_life = op->life;
const TCGHelperInfo *info = tcg_call_info(op);
TCGRegSet allocated_regs = s->reserved_regs;
int i;
/*
* Move inputs into place in reverse order,
* so that we place stacked arguments first.
*/
for (i = nb_iargs - 1; i >= 0; --i) {
const TCGCallArgumentLoc *loc = &info->in[i];
TCGTemp *ts = arg_temp(op->args[nb_oargs + i]);
switch (loc->kind) {
case TCG_CALL_ARG_NORMAL:
case TCG_CALL_ARG_EXTEND_U:
case TCG_CALL_ARG_EXTEND_S:
load_arg_normal(s, loc, ts, &allocated_regs);
break;
case TCG_CALL_ARG_BY_REF:
load_arg_stk(s, loc->ref_slot, ts, allocated_regs);
load_arg_ref(s, loc->arg_slot, TCG_REG_CALL_STACK,
arg_slot_stk_ofs(loc->ref_slot),
&allocated_regs);
break;
case TCG_CALL_ARG_BY_REF_N:
load_arg_stk(s, loc->ref_slot, ts, allocated_regs);
break;
default:
g_assert_not_reached();
}
}
/* Mark dead temporaries and free the associated registers. */
for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
if (IS_DEAD_ARG(i)) {
temp_dead(s, arg_temp(op->args[i]));
}
}
/* Clobber call registers. */
for (i = 0; i < TCG_TARGET_NB_REGS; i++) {
if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) {
tcg_reg_free(s, i, allocated_regs);
}
}
/*
* Save globals if they might be written by the helper,
* sync them if they might be read.
*/
if (info->flags & TCG_CALL_NO_READ_GLOBALS) {
/* Nothing to do */
} else if (info->flags & TCG_CALL_NO_WRITE_GLOBALS) {
sync_globals(s, allocated_regs);
} else {
save_globals(s, allocated_regs);
}
/*
* If the ABI passes a pointer to the returned struct as the first
* argument, load that now. Pass a pointer to the output home slot.
*/
if (info->out_kind == TCG_CALL_RET_BY_REF) {
TCGTemp *ts = arg_temp(op->args[0]);
if (!ts->mem_allocated) {
temp_allocate_frame(s, ts);
}
load_arg_ref(s, 0, ts->mem_base->reg, ts->mem_offset, &allocated_regs);
}
tcg_out_call(s, tcg_call_func(op), info);
/* Assign output registers and emit moves if needed. */
switch (info->out_kind) {
case TCG_CALL_RET_NORMAL:
for (i = 0; i < nb_oargs; i++) {
TCGTemp *ts = arg_temp(op->args[i]);
TCGReg reg = tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, i);
/* ENV should not be modified. */
tcg_debug_assert(!temp_readonly(ts));
set_temp_val_reg(s, ts, reg);
ts->mem_coherent = 0;
}
break;
case TCG_CALL_RET_BY_VEC:
{
TCGTemp *ts = arg_temp(op->args[0]);
tcg_debug_assert(ts->base_type == TCG_TYPE_I128);
tcg_debug_assert(ts->temp_subindex == 0);
if (!ts->mem_allocated) {
temp_allocate_frame(s, ts);
}
tcg_out_st(s, TCG_TYPE_V128,
tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0),
ts->mem_base->reg, ts->mem_offset);
}
/* fall through to mark all parts in memory */
+ fallthrough;
case TCG_CALL_RET_BY_REF:
/* The callee has performed a write through the reference. */
for (i = 0; i < nb_oargs; i++) {
TCGTemp *ts = arg_temp(op->args[i]);
ts->val_type = TEMP_VAL_MEM;
}
break;
default:
g_assert_not_reached();
}
/* Flush or discard output registers as needed. */
for (i = 0; i < nb_oargs; i++) {
TCGTemp *ts = arg_temp(op->args[i]);
if (NEED_SYNC_ARG(i)) {
temp_sync(s, ts, s->reserved_regs, 0, IS_DEAD_ARG(i));
} else if (IS_DEAD_ARG(i)) {
temp_dead(s, ts);
}
}
}
/**
* atom_and_align_for_opc:
* @s: tcg context
* @opc: memory operation code
* @host_atom: MO_ATOM_{IFALIGN,WITHIN16,SUBALIGN} for host operations
* @allow_two_ops: true if we are prepared to issue two operations
*
* Return the alignment and atomicity to use for the inline fast path
* for the given memory operation. The alignment may be larger than
* that specified in @opc, and the correct alignment will be diagnosed
* by the slow path helper.
*
* If @allow_two_ops, the host is prepared to test for 2x alignment,
* and issue two loads or stores for subalignment.
*/
@@ -5424,85 +5426,85 @@ static int tcg_out_helper_stk_ofs(TCGType type, unsigned slot)
static void tcg_out_helper_load_slots(TCGContext *s,
unsigned nmov, TCGMovExtend *mov,
const TCGLdstHelperParam *parm)
{
unsigned i;
TCGReg dst3;
/*
* Start from the end, storing to the stack first.
* This frees those registers, so we need not consider overlap.
*/
for (i = nmov; i-- > 0; ) {
unsigned slot = mov[i].dst;
if (arg_slot_reg_p(slot)) {
goto found_reg;
}
TCGReg src = mov[i].src;
TCGType dst_type = mov[i].dst_type;
MemOp dst_mo = dst_type == TCG_TYPE_I32 ? MO_32 : MO_64;
/* The argument is going onto the stack; extend into scratch. */
if ((mov[i].src_ext & MO_SIZE) != dst_mo) {
tcg_debug_assert(parm->ntmp != 0);
mov[i].dst = src = parm->tmp[0];
tcg_out_movext1(s, &mov[i]);
}
tcg_out_st(s, dst_type, src, TCG_REG_CALL_STACK,
tcg_out_helper_stk_ofs(dst_type, slot));
}
return;
found_reg:
/*
* The remaining arguments are in registers.
* Convert slot numbers to argument registers.
*/
nmov = i + 1;
for (i = 0; i < nmov; ++i) {
mov[i].dst = tcg_target_call_iarg_regs[mov[i].dst];
}
switch (nmov) {
case 4:
/* The backend must have provided enough temps for the worst case. */
tcg_debug_assert(parm->ntmp >= 2);
dst3 = mov[3].dst;
for (unsigned j = 0; j < 3; ++j) {
if (dst3 == mov[j].src) {
/*
* Conflict. Copy the source to a temporary, perform the
* remaining moves, then the extension from our scratch
* on the way out.
*/
TCGReg scratch = parm->tmp[1];
tcg_out_mov(s, mov[3].src_type, scratch, mov[3].src);
tcg_out_movext3(s, mov, mov + 1, mov + 2, parm->tmp[0]);
tcg_out_movext1_new_src(s, &mov[3], scratch);
break;
}
}
/* No conflicts: perform this move and continue. */
tcg_out_movext1(s, &mov[3]);
- /* fall through */
+ fallthrough;
case 3:
tcg_out_movext3(s, mov, mov + 1, mov + 2,
parm->ntmp ? parm->tmp[0] : -1);
break;
case 2:
tcg_out_movext2(s, mov, mov + 1,
parm->ntmp ? parm->tmp[0] : -1);
break;
case 1:
tcg_out_movext1(s, mov);
break;
default:
g_assert_not_reached();
}
}
@@ -5731,85 +5733,85 @@ static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst,
static void tcg_out_ld_helper_ret(TCGContext *s, const TCGLabelQemuLdst *ldst,
bool load_sign,
const TCGLdstHelperParam *parm)
{
MemOp mop = get_memop(ldst->oi);
TCGMovExtend mov[2];
int ofs_slot0;
switch (ldst->type) {
case TCG_TYPE_I64:
if (TCG_TARGET_REG_BITS == 32) {
break;
}
- /* fall through */
+ fallthrough;
case TCG_TYPE_I32:
mov[0].dst = ldst->datalo_reg;
mov[0].src = tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, 0);
mov[0].dst_type = ldst->type;
mov[0].src_type = TCG_TYPE_REG;
/*
* If load_sign, then we allowed the helper to perform the
* appropriate sign extension to tcg_target_ulong, and all
* we need now is a plain move.
*
* If they do not, then we expect the relevant extension
* instruction to be no more expensive than a move, and
* we thus save the icache etc by only using one of two
* helper functions.
*/
if (load_sign || !(mop & MO_SIGN)) {
if (TCG_TARGET_REG_BITS == 32 || ldst->type == TCG_TYPE_I32) {
mov[0].src_ext = MO_32;
} else {
mov[0].src_ext = MO_64;
}
} else {
mov[0].src_ext = mop & MO_SSIZE;
}
tcg_out_movext1(s, mov);
return;
case TCG_TYPE_I128:
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
ofs_slot0 = TCG_TARGET_CALL_STACK_OFFSET;
switch (TCG_TARGET_CALL_RET_I128) {
case TCG_CALL_RET_NORMAL:
break;
case TCG_CALL_RET_BY_VEC:
tcg_out_st(s, TCG_TYPE_V128,
tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0),
TCG_REG_CALL_STACK, ofs_slot0);
- /* fall through */
+ fallthrough;
case TCG_CALL_RET_BY_REF:
tcg_out_ld(s, TCG_TYPE_I64, ldst->datalo_reg,
TCG_REG_CALL_STACK, ofs_slot0 + 8 * HOST_BIG_ENDIAN);
tcg_out_ld(s, TCG_TYPE_I64, ldst->datahi_reg,
TCG_REG_CALL_STACK, ofs_slot0 + 8 * !HOST_BIG_ENDIAN);
return;
default:
g_assert_not_reached();
}
break;
default:
g_assert_not_reached();
}
mov[0].dst = ldst->datalo_reg;
mov[0].src =
tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, HOST_BIG_ENDIAN);
mov[0].dst_type = TCG_TYPE_REG;
mov[0].src_type = TCG_TYPE_REG;
mov[0].src_ext = TCG_TARGET_REG_BITS == 32 ? MO_32 : MO_64;
mov[1].dst = ldst->datahi_reg;
mov[1].src =
tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, !HOST_BIG_ENDIAN);
mov[1].dst_type = TCG_TYPE_REG;
mov[1].src_type = TCG_TYPE_REG;
mov[1].src_ext = TCG_TARGET_REG_BITS == 32 ? MO_32 : MO_64;
tcg_out_movext2(s, mov, mov + 1, parm->ntmp ? parm->tmp[0] : -1);
}
@@ -5928,195 +5930,195 @@ void tcg_dump_op_count(GString *buf)
int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
{
int i, start_words, num_insns;
TCGOp *op;
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)
&& qemu_log_in_addr_range(pc_start))) {
FILE *logfile = qemu_log_trylock();
if (logfile) {
fprintf(logfile, "OP:\n");
tcg_dump_ops(s, logfile, false);
fprintf(logfile, "\n");
qemu_log_unlock(logfile);
}
}
#ifdef CONFIG_DEBUG_TCG
/* Ensure all labels referenced have been emitted. */
{
TCGLabel *l;
bool error = false;
QSIMPLEQ_FOREACH(l, &s->labels, next) {
if (unlikely(!l->present) && !QSIMPLEQ_EMPTY(&l->branches)) {
qemu_log_mask(CPU_LOG_TB_OP,
"$L%d referenced but not present.\n", l->id);
error = true;
}
}
assert(!error);
}
#endif
tcg_optimize(s);
reachable_code_pass(s);
liveness_pass_0(s);
liveness_pass_1(s);
if (s->nb_indirects > 0) {
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND)
&& qemu_log_in_addr_range(pc_start))) {
FILE *logfile = qemu_log_trylock();
if (logfile) {
fprintf(logfile, "OP before indirect lowering:\n");
tcg_dump_ops(s, logfile, false);
fprintf(logfile, "\n");
qemu_log_unlock(logfile);
}
}
/* Replace indirect temps with direct temps. */
if (liveness_pass_2(s)) {
/* If changes were made, re-run liveness. */
liveness_pass_1(s);
}
}
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT)
&& qemu_log_in_addr_range(pc_start))) {
FILE *logfile = qemu_log_trylock();
if (logfile) {
fprintf(logfile, "OP after optimization and liveness analysis:\n");
tcg_dump_ops(s, logfile, true);
fprintf(logfile, "\n");
qemu_log_unlock(logfile);
}
}
/* Initialize goto_tb jump offsets. */
tb->jmp_reset_offset[0] = TB_JMP_OFFSET_INVALID;
tb->jmp_reset_offset[1] = TB_JMP_OFFSET_INVALID;
tb->jmp_insn_offset[0] = TB_JMP_OFFSET_INVALID;
tb->jmp_insn_offset[1] = TB_JMP_OFFSET_INVALID;
tcg_reg_alloc_start(s);
/*
* Reset the buffer pointers when restarting after overflow.
* TODO: Move this into translate-all.c with the rest of the
* buffer management. Having only this done here is confusing.
*/
s->code_buf = tcg_splitwx_to_rw(tb->tc.ptr);
s->code_ptr = s->code_buf;
#ifdef TCG_TARGET_NEED_LDST_LABELS
QSIMPLEQ_INIT(&s->ldst_labels);
#endif
#ifdef TCG_TARGET_NEED_POOL_LABELS
s->pool_labels = NULL;
#endif
start_words = s->insn_start_words;
s->gen_insn_data =
tcg_malloc(sizeof(uint64_t) * s->gen_tb->icount * start_words);
tcg_out_tb_start(s);
num_insns = -1;
QTAILQ_FOREACH(op, &s->ops, link) {
TCGOpcode opc = op->opc;
switch (opc) {
case INDEX_op_mov_i32:
case INDEX_op_mov_i64:
case INDEX_op_mov_vec:
tcg_reg_alloc_mov(s, op);
break;
case INDEX_op_dup_vec:
tcg_reg_alloc_dup(s, op);
break;
case INDEX_op_insn_start:
if (num_insns >= 0) {
size_t off = tcg_current_code_size(s);
s->gen_insn_end_off[num_insns] = off;
/* Assert that we do not overflow our stored offset. */
assert(s->gen_insn_end_off[num_insns] == off);
}
num_insns++;
for (i = 0; i < start_words; ++i) {
s->gen_insn_data[num_insns * start_words + i] =
tcg_get_insn_start_param(op, i);
}
break;
case INDEX_op_discard:
temp_dead(s, arg_temp(op->args[0]));
break;
case INDEX_op_set_label:
tcg_reg_alloc_bb_end(s, s->reserved_regs);
tcg_out_label(s, arg_label(op->args[0]));
break;
case INDEX_op_call:
tcg_reg_alloc_call(s, op);
break;
case INDEX_op_exit_tb:
tcg_out_exit_tb(s, op->args[0]);
break;
case INDEX_op_goto_tb:
tcg_out_goto_tb(s, op->args[0]);
break;
case INDEX_op_dup2_vec:
if (tcg_reg_alloc_dup2(s, op)) {
break;
}
- /* fall through */
+ fallthrough;
default:
/* Sanity check that we've not introduced any unhandled opcodes. */
tcg_debug_assert(tcg_op_supported(opc));
/* Note: in order to speed up the code, it would be much
faster to have specialized register allocator functions for
some common argument patterns */
tcg_reg_alloc_op(s, op);
break;
}
/* Test for (pending) buffer overflow. The assumption is that any
one operation beginning below the high water mark cannot overrun
the buffer completely. Thus we can test for overflow after
generating code without having to check during generation. */
if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) {
return -1;
}
/* Test for TB overflow, as seen by gen_insn_end_off. */
if (unlikely(tcg_current_code_size(s) > UINT16_MAX)) {
return -2;
}
}
tcg_debug_assert(num_insns + 1 == s->gen_tb->icount);
s->gen_insn_end_off[num_insns] = tcg_current_code_size(s);
/* Generate TB finalization at the end of block */
#ifdef TCG_TARGET_NEED_LDST_LABELS
i = tcg_out_ldst_finalize(s);
if (i < 0) {
return i;
}
#endif
#ifdef TCG_TARGET_NEED_POOL_LABELS
i = tcg_out_pool_finalize(s);
if (i < 0) {
return i;
}
#endif
if (!tcg_resolve_relocs(s)) {
return -2;
}
#ifndef CONFIG_TCG_INTERPRETER
/* flush instruction cache */
flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s->code_buf),
(uintptr_t)s->code_buf,
tcg_ptr_byte_diff(s->code_ptr, s->code_buf));
#endif
return tcg_current_code_size(s);
}
diff --git a/tcg/tci.c b/tcg/tci.c
index 4640902c88..3368941953 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -1053,269 +1053,269 @@ static const char *str_c(TCGCond c)
/* Disassemble TCI bytecode. */
int print_insn_tci(bfd_vma addr, disassemble_info *info)
{
const uint32_t *tb_ptr = (const void *)(uintptr_t)addr;
const TCGOpDef *def;
const char *op_name;
uint32_t insn;
TCGOpcode op;
TCGReg r0, r1, r2, r3, r4, r5;
tcg_target_ulong i1;
int32_t s2;
TCGCond c;
MemOpIdx oi;
uint8_t pos, len;
void *ptr;
/* TCI is always the host, so we don't need to load indirect. */
insn = *tb_ptr++;
info->fprintf_func(info->stream, "%08x ", insn);
op = extract32(insn, 0, 8);
def = &tcg_op_defs[op];
op_name = def->name;
switch (op) {
case INDEX_op_br:
case INDEX_op_exit_tb:
case INDEX_op_goto_tb:
tci_args_l(insn, tb_ptr, &ptr);
info->fprintf_func(info->stream, "%-12s %p", op_name, ptr);
break;
case INDEX_op_goto_ptr:
tci_args_r(insn, &r0);
info->fprintf_func(info->stream, "%-12s %s", op_name, str_r(r0));
break;
case INDEX_op_call:
tci_args_nl(insn, tb_ptr, &len, &ptr);
info->fprintf_func(info->stream, "%-12s %d, %p", op_name, len, ptr);
break;
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
tci_args_rl(insn, tb_ptr, &r0, &ptr);
info->fprintf_func(info->stream, "%-12s %s, 0, ne, %p",
op_name, str_r(r0), ptr);
break;
case INDEX_op_setcond_i32:
case INDEX_op_setcond_i64:
tci_args_rrrc(insn, &r0, &r1, &r2, &c);
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
op_name, str_r(r0), str_r(r1), str_r(r2), str_c(c));
break;
case INDEX_op_tci_movi:
tci_args_ri(insn, &r0, &i1);
info->fprintf_func(info->stream, "%-12s %s, 0x%" TCG_PRIlx,
op_name, str_r(r0), i1);
break;
case INDEX_op_tci_movl:
tci_args_rl(insn, tb_ptr, &r0, &ptr);
info->fprintf_func(info->stream, "%-12s %s, %p",
op_name, str_r(r0), ptr);
break;
case INDEX_op_ld8u_i32:
case INDEX_op_ld8u_i64:
case INDEX_op_ld8s_i32:
case INDEX_op_ld8s_i64:
case INDEX_op_ld16u_i32:
case INDEX_op_ld16u_i64:
case INDEX_op_ld16s_i32:
case INDEX_op_ld16s_i64:
case INDEX_op_ld32u_i64:
case INDEX_op_ld32s_i64:
case INDEX_op_ld_i32:
case INDEX_op_ld_i64:
case INDEX_op_st8_i32:
case INDEX_op_st8_i64:
case INDEX_op_st16_i32:
case INDEX_op_st16_i64:
case INDEX_op_st32_i64:
case INDEX_op_st_i32:
case INDEX_op_st_i64:
tci_args_rrs(insn, &r0, &r1, &s2);
info->fprintf_func(info->stream, "%-12s %s, %s, %d",
op_name, str_r(r0), str_r(r1), s2);
break;
case INDEX_op_mov_i32:
case INDEX_op_mov_i64:
case INDEX_op_ext8s_i32:
case INDEX_op_ext8s_i64:
case INDEX_op_ext8u_i32:
case INDEX_op_ext8u_i64:
case INDEX_op_ext16s_i32:
case INDEX_op_ext16s_i64:
case INDEX_op_ext16u_i32:
case INDEX_op_ext32s_i64:
case INDEX_op_ext32u_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
case INDEX_op_bswap16_i32:
case INDEX_op_bswap16_i64:
case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64:
case INDEX_op_not_i32:
case INDEX_op_not_i64:
case INDEX_op_neg_i32:
case INDEX_op_neg_i64:
case INDEX_op_ctpop_i32:
case INDEX_op_ctpop_i64:
tci_args_rr(insn, &r0, &r1);
info->fprintf_func(info->stream, "%-12s %s, %s",
op_name, str_r(r0), str_r(r1));
break;
case INDEX_op_add_i32:
case INDEX_op_add_i64:
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
case INDEX_op_mul_i32:
case INDEX_op_mul_i64:
case INDEX_op_and_i32:
case INDEX_op_and_i64:
case INDEX_op_or_i32:
case INDEX_op_or_i64:
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
case INDEX_op_andc_i32:
case INDEX_op_andc_i64:
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
case INDEX_op_eqv_i32:
case INDEX_op_eqv_i64:
case INDEX_op_nand_i32:
case INDEX_op_nand_i64:
case INDEX_op_nor_i32:
case INDEX_op_nor_i64:
case INDEX_op_div_i32:
case INDEX_op_div_i64:
case INDEX_op_rem_i32:
case INDEX_op_rem_i64:
case INDEX_op_divu_i32:
case INDEX_op_divu_i64:
case INDEX_op_remu_i32:
case INDEX_op_remu_i64:
case INDEX_op_shl_i32:
case INDEX_op_shl_i64:
case INDEX_op_shr_i32:
case INDEX_op_shr_i64:
case INDEX_op_sar_i32:
case INDEX_op_sar_i64:
case INDEX_op_rotl_i32:
case INDEX_op_rotl_i64:
case INDEX_op_rotr_i32:
case INDEX_op_rotr_i64:
case INDEX_op_clz_i32:
case INDEX_op_clz_i64:
case INDEX_op_ctz_i32:
case INDEX_op_ctz_i64:
tci_args_rrr(insn, &r0, &r1, &r2);
info->fprintf_func(info->stream, "%-12s %s, %s, %s",
op_name, str_r(r0), str_r(r1), str_r(r2));
break;
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %d, %d",
op_name, str_r(r0), str_r(r1), str_r(r2), pos, len);
break;
case INDEX_op_extract_i32:
case INDEX_op_extract_i64:
case INDEX_op_sextract_i32:
case INDEX_op_sextract_i64:
tci_args_rrbb(insn, &r0, &r1, &pos, &len);
info->fprintf_func(info->stream, "%-12s %s,%s,%d,%d",
op_name, str_r(r0), str_r(r1), pos, len);
break;
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
case INDEX_op_setcond2_i32:
tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c);
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s",
op_name, str_r(r0), str_r(r1), str_r(r2),
str_r(r3), str_r(r4), str_c(c));
break;
case INDEX_op_mulu2_i32:
case INDEX_op_mulu2_i64:
case INDEX_op_muls2_i32:
case INDEX_op_muls2_i64:
tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
op_name, str_r(r0), str_r(r1),
str_r(r2), str_r(r3));
break;
case INDEX_op_add2_i32:
case INDEX_op_add2_i64:
case INDEX_op_sub2_i32:
case INDEX_op_sub2_i64:
tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s",
op_name, str_r(r0), str_r(r1), str_r(r2),
str_r(r3), str_r(r4), str_r(r5));
break;
case INDEX_op_qemu_ld_a32_i32:
case INDEX_op_qemu_st_a32_i32:
len = 1 + 1;
goto do_qemu_ldst;
case INDEX_op_qemu_ld_a32_i64:
case INDEX_op_qemu_st_a32_i64:
case INDEX_op_qemu_ld_a64_i32:
case INDEX_op_qemu_st_a64_i32:
len = 1 + DIV_ROUND_UP(64, TCG_TARGET_REG_BITS);
goto do_qemu_ldst;
case INDEX_op_qemu_ld_a64_i64:
case INDEX_op_qemu_st_a64_i64:
len = 2 * DIV_ROUND_UP(64, TCG_TARGET_REG_BITS);
goto do_qemu_ldst;
do_qemu_ldst:
switch (len) {
case 2:
tci_args_rrm(insn, &r0, &r1, &oi);
info->fprintf_func(info->stream, "%-12s %s, %s, %x",
op_name, str_r(r0), str_r(r1), oi);
break;
case 3:
tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
op_name, str_r(r0), str_r(r1),
str_r(r2), str_r(r3));
break;
case 4:
tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s",
op_name, str_r(r0), str_r(r1),
str_r(r2), str_r(r3), str_r(r4));
break;
default:
g_assert_not_reached();
}
break;
case 0:
/* tcg_out_nop_fill uses zeros */
if (insn == 0) {
info->fprintf_func(info->stream, "align");
break;
}
- /* fall through */
+ fallthrough;
default:
info->fprintf_func(info->stream, "illegal opcode %d", op);
break;
}
return sizeof(insn);
}
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 461f4b47ff..f60d0ba037 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -520,26 +520,26 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg ret, tcg_target_long arg)
{
switch (type) {
case TCG_TYPE_I32:
#if TCG_TARGET_REG_BITS == 64
arg = (int32_t)arg;
- /* fall through */
+ fallthrough;
case TCG_TYPE_I64:
#endif
break;
default:
g_assert_not_reached();
}
if (arg == sextract32(arg, 0, 20)) {
tcg_out_op_ri(s, INDEX_op_tci_movi, ret, arg);
} else {
tcg_insn_unit insn = 0;
new_pool_label(s, arg, 20, s->code_ptr, 0);
insn = deposit32(insn, 0, 8, INDEX_op_tci_movl);
insn = deposit32(insn, 8, 4, ret);
tcg_out32(s, insn);
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 07/78] hw/virtio/virtio-balloon.c: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (5 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 06/78] tcg: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 08/78] hw/block: " Emmanouil Pitsidianakis
` (71 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Michael S. Tsirkin, David Hildenbrand
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/virtio/virtio-balloon.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/virtio/virtio-balloon.c b/hw/virtio/virtio-balloon.c
index d004cf29d2..0f0d94bd94 100644
--- a/hw/virtio/virtio-balloon.c
+++ b/hw/virtio/virtio-balloon.c
@@ -636,56 +636,57 @@ static int
virtio_balloon_free_page_hint_notify(NotifierWithReturn *n, void *data)
{
VirtIOBalloon *dev = container_of(n, VirtIOBalloon, free_page_hint_notify);
VirtIODevice *vdev = VIRTIO_DEVICE(dev);
PrecopyNotifyData *pnd = data;
if (!virtio_balloon_free_page_support(dev)) {
/*
* This is an optimization provided to migration, so just return 0 to
* have the normal migration process not affected when this feature is
* not supported.
*/
return 0;
}
/*
* Pages hinted via qemu_guest_free_page_hint() are cleared from the dirty
* bitmap and will not get migrated, especially also not when the postcopy
* destination starts using them and requests migration from the source; the
* faulting thread will stall until postcopy migration finishes and
* all threads are woken up. Let's not start free page hinting if postcopy
* is possible.
*/
if (migrate_postcopy_ram()) {
return 0;
}
switch (pnd->reason) {
case PRECOPY_NOTIFY_BEFORE_BITMAP_SYNC:
virtio_balloon_free_page_stop(dev);
break;
case PRECOPY_NOTIFY_AFTER_BITMAP_SYNC:
if (vdev->vm_running) {
virtio_balloon_free_page_start(dev);
break;
}
/*
* Set S_DONE before migrating the vmstate, so the guest will reuse
* all hinted pages once running on the destination. Fall through.
*/
+ fallthrough;
case PRECOPY_NOTIFY_CLEANUP:
/*
* Especially, if something goes wrong during precopy or if migration
* is canceled, we have to properly communicate S_DONE to the VM.
*/
virtio_balloon_free_page_done(dev);
break;
case PRECOPY_NOTIFY_SETUP:
case PRECOPY_NOTIFY_COMPLETE:
break;
default:
virtio_error(vdev, "%s: %d reason unknown", __func__, pnd->reason);
}
return 0;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 08/78] hw/block: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (6 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 07/78] hw/virtio/virtio-balloon.c: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 09/78] hw/acpi/aml-build.c: " Emmanouil Pitsidianakis
` (70 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Stefan Hajnoczi, Stefano Stabellini,
Anthony Perard, Paul Durrant, Kevin Wolf, Hanna Reitz,
Alistair Francis, Philippe Mathieu-Daudé,
open list:virtio-blk, open list:X86 Xen CPUs
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/block/dataplane/xen-block.c | 4 ++--
hw/block/m25p80.c | 2 +-
hw/block/onenand.c | 2 +-
hw/block/pflash_cfi01.c | 1 +
hw/block/pflash_cfi02.c | 6 ++++--
5 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/hw/block/dataplane/xen-block.c b/hw/block/dataplane/xen-block.c
index 3b6f2b0aa2..1ae25a73b2 100644
--- a/hw/block/dataplane/xen-block.c
+++ b/hw/block/dataplane/xen-block.c
@@ -144,59 +144,59 @@ static void xen_block_complete_request(XenBlockRequest *request)
/*
* translate request into iovec + start offset
* do sanity checks along the way
*/
static int xen_block_parse_request(XenBlockRequest *request)
{
XenBlockDataPlane *dataplane = request->dataplane;
size_t len;
int i;
switch (request->req.operation) {
case BLKIF_OP_READ:
break;
case BLKIF_OP_FLUSH_DISKCACHE:
request->presync = 1;
if (!request->req.nr_segments) {
return 0;
}
- /* fall through */
+ fallthrough;
case BLKIF_OP_WRITE:
break;
case BLKIF_OP_DISCARD:
return 0;
default:
error_report("error: unknown operation (%d)", request->req.operation);
goto err;
};
if (request->req.operation != BLKIF_OP_READ &&
!blk_is_writable(dataplane->blk)) {
error_report("error: write req for ro device");
goto err;
}
request->start = request->req.sector_number * dataplane->sector_size;
for (i = 0; i < request->req.nr_segments; i++) {
if (i == BLKIF_MAX_SEGMENTS_PER_REQUEST) {
error_report("error: nr_segments too big");
goto err;
}
if (request->req.seg[i].first_sect > request->req.seg[i].last_sect) {
error_report("error: first > last sector");
goto err;
}
if (request->req.seg[i].last_sect * dataplane->sector_size >=
XEN_PAGE_SIZE) {
error_report("error: page crossing");
goto err;
}
len = (request->req.seg[i].last_sect -
request->req.seg[i].first_sect + 1) * dataplane->sector_size;
request->size += len;
}
if (request->start + request->size > blk_getlength(dataplane->blk)) {
error_report("error: access beyond end of file");
goto err;
}
return 0;
@@ -257,63 +257,63 @@ static int xen_block_do_aio(XenBlockRequest *request);
static void xen_block_complete_aio(void *opaque, int ret)
{
XenBlockRequest *request = opaque;
XenBlockDataPlane *dataplane = request->dataplane;
aio_context_acquire(dataplane->ctx);
if (ret != 0) {
error_report("%s I/O error",
request->req.operation == BLKIF_OP_READ ?
"read" : "write");
request->aio_errors++;
}
request->aio_inflight--;
if (request->presync) {
request->presync = 0;
xen_block_do_aio(request);
goto done;
}
if (request->aio_inflight > 0) {
goto done;
}
switch (request->req.operation) {
case BLKIF_OP_READ:
/* in case of failure request->aio_errors is increased */
if (ret == 0) {
xen_block_copy_request(request);
}
break;
case BLKIF_OP_WRITE:
case BLKIF_OP_FLUSH_DISKCACHE:
default:
break;
}
request->status = request->aio_errors ? BLKIF_RSP_ERROR : BLKIF_RSP_OKAY;
switch (request->req.operation) {
case BLKIF_OP_WRITE:
case BLKIF_OP_FLUSH_DISKCACHE:
if (!request->req.nr_segments) {
break;
}
- /* fall through */
+ fallthrough;
case BLKIF_OP_READ:
if (request->status == BLKIF_RSP_OKAY) {
block_acct_done(blk_get_stats(dataplane->blk), &request->acct);
} else {
block_acct_failed(blk_get_stats(dataplane->blk), &request->acct);
}
break;
case BLKIF_OP_DISCARD:
default:
break;
}
xen_block_complete_request(request);
if (dataplane->more_work) {
qemu_bh_schedule(dataplane->bh);
}
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index afc3fdf4d6..523c34da71 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -1117,360 +1117,360 @@ static bool is_valid_aai_cmd(uint32_t cmd)
static void decode_new_cmd(Flash *s, uint32_t value)
{
int i;
s->cmd_in_progress = value;
trace_m25p80_command_decoded(s, value);
if (value != RESET_MEMORY) {
s->reset_enable = false;
}
if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) {
qemu_log_mask(LOG_GUEST_ERROR,
"M25P80: Invalid cmd within AAI programming sequence");
}
switch (value) {
case ERASE_4K:
case ERASE4_4K:
case ERASE_32K:
case ERASE4_32K:
case ERASE_SECTOR:
case ERASE4_SECTOR:
case PP:
case PP4:
case DIE_ERASE:
case RDID_90:
case RDID_AB:
s->needed_bytes = get_addr_length(s);
s->pos = 0;
s->len = 0;
s->state = STATE_COLLECTING_DATA;
break;
case READ:
case READ4:
if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) {
s->needed_bytes = get_addr_length(s);
s->pos = 0;
s->len = 0;
s->state = STATE_COLLECTING_DATA;
} else {
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
"DIO or QIO mode\n", s->cmd_in_progress);
}
break;
case DPP:
if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
s->needed_bytes = get_addr_length(s);
s->pos = 0;
s->len = 0;
s->state = STATE_COLLECTING_DATA;
} else {
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
"QIO mode\n", s->cmd_in_progress);
}
break;
case QPP:
case QPP_4:
case PP4_4:
if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
s->needed_bytes = get_addr_length(s);
s->pos = 0;
s->len = 0;
s->state = STATE_COLLECTING_DATA;
} else {
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
"DIO mode\n", s->cmd_in_progress);
}
break;
case FAST_READ:
case FAST_READ4:
decode_fast_read_cmd(s);
break;
case DOR:
case DOR4:
if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
decode_fast_read_cmd(s);
} else {
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
"QIO mode\n", s->cmd_in_progress);
}
break;
case QOR:
case QOR4:
if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
decode_fast_read_cmd(s);
} else {
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
"DIO mode\n", s->cmd_in_progress);
}
break;
case DIOR:
case DIOR4:
if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
decode_dio_read_cmd(s);
} else {
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
"QIO mode\n", s->cmd_in_progress);
}
break;
case QIOR:
case QIOR4:
if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
decode_qio_read_cmd(s);
} else {
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
"DIO mode\n", s->cmd_in_progress);
}
break;
case WRSR:
/*
* If WP# is low and status_register_write_disabled is high,
* status register writes are disabled.
* This is also called "hardware protected mode" (HPM). All other
* combinations of the two states are called "software protected mode"
* (SPM), and status register writes are permitted.
*/
if ((s->wp_level == 0 && s->status_register_write_disabled)
|| !s->write_enable) {
qemu_log_mask(LOG_GUEST_ERROR,
"M25P80: Status register write is disabled!\n");
break;
}
switch (get_man(s)) {
case MAN_SPANSION:
s->needed_bytes = 2;
s->state = STATE_COLLECTING_DATA;
break;
case MAN_MACRONIX:
s->needed_bytes = 2;
s->state = STATE_COLLECTING_VAR_LEN_DATA;
break;
default:
s->needed_bytes = 1;
s->state = STATE_COLLECTING_DATA;
}
s->pos = 0;
break;
case WRDI:
s->write_enable = false;
if (get_man(s) == MAN_SST) {
s->aai_enable = false;
}
break;
case WREN:
s->write_enable = true;
break;
case RDSR:
s->data[0] = (!!s->write_enable) << 1;
s->data[0] |= (!!s->status_register_write_disabled) << 7;
s->data[0] |= (!!s->block_protect0) << 2;
s->data[0] |= (!!s->block_protect1) << 3;
s->data[0] |= (!!s->block_protect2) << 4;
if (s->pi->flags & HAS_SR_TB) {
s->data[0] |= (!!s->top_bottom_bit) << 5;
}
if (s->pi->flags & HAS_SR_BP3_BIT6) {
s->data[0] |= (!!s->block_protect3) << 6;
}
if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) {
s->data[0] |= (!!s->quad_enable) << 6;
}
if (get_man(s) == MAN_SST) {
s->data[0] |= (!!s->aai_enable) << 6;
}
s->pos = 0;
s->len = 1;
s->data_read_loop = true;
s->state = STATE_READING_DATA;
break;
case READ_FSR:
s->data[0] = FSR_FLASH_READY;
if (s->four_bytes_address_mode) {
s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED;
}
s->pos = 0;
s->len = 1;
s->data_read_loop = true;
s->state = STATE_READING_DATA;
break;
case JEDEC_READ:
if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) {
trace_m25p80_populated_jedec(s);
for (i = 0; i < s->pi->id_len; i++) {
s->data[i] = s->pi->id[i];
}
for (; i < SPI_NOR_MAX_ID_LEN; i++) {
s->data[i] = 0;
}
s->len = SPI_NOR_MAX_ID_LEN;
s->pos = 0;
s->state = STATE_READING_DATA;
} else {
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute JEDEC read "
"in DIO or QIO mode\n");
}
break;
case RDCR:
s->data[0] = s->volatile_cfg & 0xFF;
s->data[0] |= (!!s->four_bytes_address_mode) << 5;
s->pos = 0;
s->len = 1;
s->state = STATE_READING_DATA;
break;
case BULK_ERASE_60:
case BULK_ERASE:
if (s->write_enable) {
trace_m25p80_chip_erase(s);
flash_erase(s, 0, BULK_ERASE);
} else {
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
"protect!\n");
}
break;
case NOP:
break;
case EN_4BYTE_ADDR:
s->four_bytes_address_mode = true;
break;
case EX_4BYTE_ADDR:
s->four_bytes_address_mode = false;
break;
case BRRD:
case EXTEND_ADDR_READ:
s->data[0] = s->ear;
s->pos = 0;
s->len = 1;
s->state = STATE_READING_DATA;
break;
case BRWR:
case EXTEND_ADDR_WRITE:
if (s->write_enable) {
s->needed_bytes = 1;
s->pos = 0;
s->len = 0;
s->state = STATE_COLLECTING_DATA;
}
break;
case RNVCR:
s->data[0] = s->nonvolatile_cfg & 0xFF;
s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF;
s->pos = 0;
s->len = 2;
s->state = STATE_READING_DATA;
break;
case WNVCR:
if (s->write_enable && get_man(s) == MAN_NUMONYX) {
s->needed_bytes = 2;
s->pos = 0;
s->len = 0;
s->state = STATE_COLLECTING_DATA;
}
break;
case RVCR:
s->data[0] = s->volatile_cfg & 0xFF;
s->pos = 0;
s->len = 1;
s->state = STATE_READING_DATA;
break;
case WVCR:
if (s->write_enable) {
s->needed_bytes = 1;
s->pos = 0;
s->len = 0;
s->state = STATE_COLLECTING_DATA;
}
break;
case REVCR:
s->data[0] = s->enh_volatile_cfg & 0xFF;
s->pos = 0;
s->len = 1;
s->state = STATE_READING_DATA;
break;
case WEVCR:
if (s->write_enable) {
s->needed_bytes = 1;
s->pos = 0;
s->len = 0;
s->state = STATE_COLLECTING_DATA;
}
break;
case RESET_ENABLE:
s->reset_enable = true;
break;
case RESET_MEMORY:
if (s->reset_enable) {
reset_memory(s);
}
break;
case RDCR_EQIO:
switch (get_man(s)) {
case MAN_SPANSION:
s->data[0] = (!!s->quad_enable) << 1;
s->pos = 0;
s->len = 1;
s->state = STATE_READING_DATA;
break;
case MAN_MACRONIX:
s->quad_enable = true;
break;
default:
break;
}
break;
case RSTQIO:
s->quad_enable = false;
break;
case AAI_WP:
if (get_man(s) == MAN_SST) {
if (s->write_enable) {
if (s->aai_enable) {
s->state = STATE_PAGE_PROGRAM;
} else {
s->aai_enable = true;
s->needed_bytes = get_addr_length(s);
s->state = STATE_COLLECTING_DATA;
}
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"M25P80: AAI_WP with write protect\n");
}
} else {
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
}
break;
case RDSFDP:
if (s->pi->sfdp_read) {
s->needed_bytes = get_addr_length(s) + 1; /* SFDP addr + dummy */
s->pos = 0;
s->len = 0;
s->state = STATE_COLLECTING_DATA;
break;
}
- /* Fallthrough */
+ fallthrough;
default:
s->pos = 0;
s->len = 1;
s->state = STATE_READING_DATA;
s->data_read_loop = true;
s->data[0] = 0;
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
break;
}
}
diff --git a/hw/block/onenand.c b/hw/block/onenand.c
index 50d3d1c985..87583c48a0 100644
--- a/hw/block/onenand.c
+++ b/hw/block/onenand.c
@@ -406,202 +406,202 @@ fail:
static void onenand_command(OneNANDState *s)
{
int b;
int sec;
void *buf;
#define SETADDR(block, page) \
sec = (s->addr[page] & 3) + \
((((s->addr[page] >> 2) & 0x3f) + \
(((s->addr[block] & 0xfff) | \
(s->addr[block] >> 15 ? s->density_mask : 0)) \
<< 6)) \
<< (PAGE_SHIFT - 9));
#define SETBUF_M() \
buf = (s->bufaddr & 8) ? s->data[(s->bufaddr >> 2) & 1][0] : s->boot[0]; \
buf += (s->bufaddr & 3) << 9;
#define SETBUF_S() \
buf = (s->bufaddr & 8) ? \
s->data[(s->bufaddr >> 2) & 1][1] : s->boot[1]; \
buf += (s->bufaddr & 3) << 4;
switch (s->command) {
case 0x00: /* Load single/multiple sector data unit into buffer */
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
SETBUF_M()
if (onenand_load_main(s, sec, s->count, buf))
s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD;
#if 0
SETBUF_S()
if (onenand_load_spare(s, sec, s->count, buf))
s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD;
#endif
/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
* then we need two split the read/write into two chunks.
*/
s->intstatus |= ONEN_INT | ONEN_INT_LOAD;
break;
case 0x13: /* Load single/multiple spare sector into buffer */
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
SETBUF_S()
if (onenand_load_spare(s, sec, s->count, buf))
s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD;
/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
* then we need two split the read/write into two chunks.
*/
s->intstatus |= ONEN_INT | ONEN_INT_LOAD;
break;
case 0x80: /* Program single/multiple sector data unit from buffer */
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
SETBUF_M()
if (onenand_prog_main(s, sec, s->count, buf))
s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
#if 0
SETBUF_S()
if (onenand_prog_spare(s, sec, s->count, buf))
s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
#endif
/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
* then we need two split the read/write into two chunks.
*/
s->intstatus |= ONEN_INT | ONEN_INT_PROG;
break;
case 0x1a: /* Program single/multiple spare area sector from buffer */
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
SETBUF_S()
if (onenand_prog_spare(s, sec, s->count, buf))
s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
* then we need two split the read/write into two chunks.
*/
s->intstatus |= ONEN_INT | ONEN_INT_PROG;
break;
case 0x1b: /* Copy-back program */
SETBUF_S()
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
if (onenand_load_main(s, sec, s->count, buf))
s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
SETADDR(ONEN_BUF_DEST_BLOCK, ONEN_BUF_DEST_PAGE)
if (onenand_prog_main(s, sec, s->count, buf))
s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
/* TODO: spare areas */
s->intstatus |= ONEN_INT | ONEN_INT_PROG;
break;
case 0x23: /* Unlock NAND array block(s) */
s->intstatus |= ONEN_INT;
/* XXX the previous (?) area should be locked automatically */
for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) {
if (b >= s->blocks) {
s->status |= ONEN_ERR_CMD;
break;
}
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
break;
s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED;
}
break;
case 0x27: /* Unlock All NAND array blocks */
s->intstatus |= ONEN_INT;
for (b = 0; b < s->blocks; b ++) {
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
break;
s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED;
}
break;
case 0x2a: /* Lock NAND array block(s) */
s->intstatus |= ONEN_INT;
for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) {
if (b >= s->blocks) {
s->status |= ONEN_ERR_CMD;
break;
}
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
break;
s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKED;
}
break;
case 0x2c: /* Lock-tight NAND array block(s) */
s->intstatus |= ONEN_INT;
for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) {
if (b >= s->blocks) {
s->status |= ONEN_ERR_CMD;
break;
}
if (s->blockwp[b] == ONEN_LOCK_UNLOCKED)
continue;
s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKTIGHTEN;
}
break;
case 0x71: /* Erase-Verify-Read */
s->intstatus |= ONEN_INT;
break;
case 0x95: /* Multi-block erase */
qemu_irq_pulse(s->intr);
- /* Fall through. */
+ fallthrough;
case 0x94: /* Block erase */
sec = ((s->addr[ONEN_BUF_BLOCK] & 0xfff) |
(s->addr[ONEN_BUF_BLOCK] >> 15 ? s->density_mask : 0))
<< (BLOCK_SHIFT - 9);
if (onenand_erase(s, sec, 1 << (BLOCK_SHIFT - 9)))
s->status |= ONEN_ERR_CMD | ONEN_ERR_ERASE;
s->intstatus |= ONEN_INT | ONEN_INT_ERASE;
break;
case 0xb0: /* Erase suspend */
break;
case 0x30: /* Erase resume */
s->intstatus |= ONEN_INT | ONEN_INT_ERASE;
break;
case 0xf0: /* Reset NAND Flash core */
onenand_reset(s, 0);
break;
case 0xf3: /* Reset OneNAND */
onenand_reset(s, 0);
break;
case 0x65: /* OTP Access */
s->intstatus |= ONEN_INT;
s->blk_cur = NULL;
s->current = s->otp;
s->secs_cur = 1 << (BLOCK_SHIFT - 9);
s->addr[ONEN_BUF_BLOCK] = 0;
s->otpmode = 1;
break;
default:
s->status |= ONEN_ERR_CMD;
s->intstatus |= ONEN_INT;
qemu_log_mask(LOG_GUEST_ERROR, "unknown OneNAND command %x\n",
s->command);
}
onenand_intr_update(s);
}
diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c
index 62056b1d74..cb58f08f53 100644
--- a/hw/block/pflash_cfi01.c
+++ b/hw/block/pflash_cfi01.c
@@ -261,123 +261,124 @@ static uint32_t pflash_data_read(PFlashCFI01 *pfl, hwaddr offset,
static uint32_t pflash_read(PFlashCFI01 *pfl, hwaddr offset,
int width, int be)
{
hwaddr boff;
uint32_t ret;
ret = -1;
switch (pfl->cmd) {
default:
/* This should never happen : reset state & treat it as a read */
trace_pflash_read_unknown_state(pfl->name, pfl->cmd);
pfl->wcycle = 0;
/*
* The command 0x00 is not assigned by the CFI open standard,
* but QEMU historically uses it for the READ_ARRAY command (0xff).
*/
pfl->cmd = 0x00;
/* fall through to read code */
+ fallthrough;
case 0x00: /* This model reset value for READ_ARRAY (not CFI compliant) */
/* Flash area read */
ret = pflash_data_read(pfl, offset, width, be);
break;
case 0x10: /* Single byte program */
case 0x20: /* Block erase */
case 0x28: /* Block erase */
case 0x40: /* single byte program */
case 0x50: /* Clear status register */
case 0x60: /* Block /un)lock */
case 0x70: /* Status Register */
case 0xe8: /* Write block */
/*
* Status register read. Return status from each device in
* bank.
*/
ret = pfl->status;
if (pfl->device_width && width > pfl->device_width) {
int shift = pfl->device_width * 8;
while (shift + pfl->device_width * 8 <= width * 8) {
ret |= pfl->status << shift;
shift += pfl->device_width * 8;
}
} else if (!pfl->device_width && width > 2) {
/*
* Handle 32 bit flash cases where device width is not
* set. (Existing behavior before device width added.)
*/
ret |= pfl->status << 16;
}
trace_pflash_read_status(pfl->name, ret);
break;
case 0x90:
if (!pfl->device_width) {
/* Preserve old behavior if device width not specified */
boff = offset & 0xFF;
if (pfl->bank_width == 2) {
boff = boff >> 1;
} else if (pfl->bank_width == 4) {
boff = boff >> 2;
}
switch (boff) {
case 0:
ret = pfl->ident0 << 8 | pfl->ident1;
trace_pflash_manufacturer_id(pfl->name, ret);
break;
case 1:
ret = pfl->ident2 << 8 | pfl->ident3;
trace_pflash_device_id(pfl->name, ret);
break;
default:
trace_pflash_device_info(pfl->name, boff);
ret = 0;
break;
}
} else {
/*
* If we have a read larger than the bank_width, combine multiple
* manufacturer/device ID queries into a single response.
*/
int i;
for (i = 0; i < width; i += pfl->bank_width) {
ret = deposit32(ret, i * 8, pfl->bank_width * 8,
pflash_devid_query(pfl,
offset + i * pfl->bank_width));
}
}
break;
case 0x98: /* Query mode */
if (!pfl->device_width) {
/* Preserve old behavior if device width not specified */
boff = offset & 0xFF;
if (pfl->bank_width == 2) {
boff = boff >> 1;
} else if (pfl->bank_width == 4) {
boff = boff >> 2;
}
if (boff < sizeof(pfl->cfi_table)) {
ret = pfl->cfi_table[boff];
} else {
ret = 0;
}
} else {
/*
* If we have a read larger than the bank_width, combine multiple
* CFI queries into a single response.
*/
int i;
for (i = 0; i < width; i += pfl->bank_width) {
ret = deposit32(ret, i * 8, pfl->bank_width * 8,
pflash_cfi_query(pfl,
offset + i * pfl->bank_width));
}
}
break;
}
trace_pflash_io_read(pfl->name, offset, width, ret, pfl->cmd, pfl->wcycle);
return ret;
}
/* update flash content on disk */
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index 2a99b286b0..711f978d7c 100644
--- a/hw/block/pflash_cfi02.c
+++ b/hw/block/pflash_cfi02.c
@@ -307,87 +307,89 @@ static bool pflash_sector_is_erasing(PFlashCFI02 *pfl, hwaddr offset)
static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width)
{
PFlashCFI02 *pfl = opaque;
hwaddr boff;
uint64_t ret;
/* Lazy reset to ROMD mode after a certain amount of read accesses */
if (!pfl->rom_mode && pfl->wcycle == 0 &&
++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) {
pflash_mode_read_array(pfl);
}
offset &= pfl->chip_len - 1;
boff = offset & 0xFF;
if (pfl->width == 2) {
boff = boff >> 1;
} else if (pfl->width == 4) {
boff = boff >> 2;
}
switch (pfl->cmd) {
default:
/* This should never happen : reset state & treat it as a read*/
trace_pflash_read_unknown_state(pfl->name, pfl->cmd);
pflash_reset_state_machine(pfl);
/* fall through to the read code */
+ fallthrough;
case 0x80: /* Erase (unlock) */
/* We accept reads during second unlock sequence... */
case 0x00:
if (pflash_erase_suspend_mode(pfl) &&
pflash_sector_is_erasing(pfl, offset)) {
/* Toggle bit 2, but not 6. */
toggle_dq2(pfl);
/* Status register read */
ret = pfl->status;
trace_pflash_read_status(pfl->name, ret);
break;
}
/* Flash area read */
ret = pflash_data_read(pfl, offset, width);
break;
case 0x90: /* flash ID read */
switch (boff) {
case 0x00:
case 0x01:
ret = boff & 0x01 ? pfl->ident1 : pfl->ident0;
break;
case 0x02:
ret = 0x00; /* Pretend all sectors are unprotected */
break;
case 0x0E:
case 0x0F:
ret = boff & 0x01 ? pfl->ident3 : pfl->ident2;
if (ret != (uint8_t)-1) {
break;
}
/* Fall through to data read. */
+ fallthrough;
default:
ret = pflash_data_read(pfl, offset, width);
}
trace_pflash_read_done(pfl->name, boff, ret);
break;
case 0x10: /* Chip Erase */
case 0x30: /* Sector Erase */
/* Toggle bit 2 during erase, but not program. */
toggle_dq2(pfl);
- /* fall through */
+ fallthrough;
case 0xA0: /* Program */
/* Toggle bit 6 */
toggle_dq6(pfl);
/* Status register read */
ret = pfl->status;
trace_pflash_read_status(pfl->name, ret);
break;
case 0x98:
/* CFI query mode */
if (boff < sizeof(pfl->cfi_table)) {
ret = pfl->cfi_table[boff];
} else {
ret = 0;
}
break;
}
trace_pflash_io_read(pfl->name, offset, width, ret, pfl->cmd, pfl->wcycle);
return ret;
}
/* update flash content on disk */
@@ -431,277 +433,277 @@ static void pflash_sector_erase(PFlashCFI02 *pfl, hwaddr offset)
static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
unsigned int width)
{
PFlashCFI02 *pfl = opaque;
hwaddr boff;
uint8_t *p;
uint8_t cmd;
trace_pflash_io_write(pfl->name, offset, width, value, pfl->wcycle);
cmd = value;
if (pfl->cmd != 0xA0) {
/* Reset does nothing during chip erase and sector erase. */
if (cmd == 0xF0 && pfl->cmd != 0x10 && pfl->cmd != 0x30) {
if (pfl->wcycle == WCYCLE_AUTOSELECT_CFI) {
/* Return to autoselect mode. */
pfl->wcycle = 3;
pfl->cmd = 0x90;
return;
}
goto reset_flash;
}
}
offset &= pfl->chip_len - 1;
boff = offset;
if (pfl->width == 2) {
boff = boff >> 1;
} else if (pfl->width == 4) {
boff = boff >> 2;
}
/* Only the least-significant 11 bits are used in most cases. */
boff &= 0x7FF;
switch (pfl->wcycle) {
case 0:
/* Set the device in I/O access mode if required */
if (pfl->rom_mode) {
pfl->rom_mode = false;
memory_region_rom_device_set_romd(&pfl->orig_mem, false);
}
pfl->read_counter = 0;
/* We're in read mode */
check_unlock0:
if (boff == 0x55 && cmd == 0x98) {
/* Enter CFI query mode */
pfl->wcycle = WCYCLE_CFI;
pfl->cmd = 0x98;
return;
}
/* Handle erase resume in erase suspend mode, otherwise reset. */
if (cmd == 0x30) { /* Erase Resume */
if (pflash_erase_suspend_mode(pfl)) {
/* Resume the erase. */
timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
pfl->erase_time_remaining);
pfl->erase_time_remaining = 0;
pfl->wcycle = 6;
pfl->cmd = 0x30;
set_dq7(pfl, 0x00);
assert_dq3(pfl);
return;
}
goto reset_flash;
}
/* Ignore erase suspend. */
if (cmd == 0xB0) { /* Erase Suspend */
return;
}
if (boff != pfl->unlock_addr0 || cmd != 0xAA) {
trace_pflash_unlock0_failed(pfl->name, boff,
cmd, pfl->unlock_addr0);
goto reset_flash;
}
trace_pflash_write(pfl->name, "unlock sequence started");
break;
case 1:
/* We started an unlock sequence */
check_unlock1:
if (boff != pfl->unlock_addr1 || cmd != 0x55) {
trace_pflash_unlock1_failed(pfl->name, boff, cmd);
goto reset_flash;
}
trace_pflash_write(pfl->name, "unlock sequence done");
break;
case 2:
/* We finished an unlock sequence */
if (!pfl->bypass && boff != pfl->unlock_addr0) {
trace_pflash_write_failed(pfl->name, boff, cmd);
goto reset_flash;
}
switch (cmd) {
case 0x20:
pfl->bypass = 1;
goto do_bypass;
case 0x80: /* Erase */
case 0x90: /* Autoselect */
case 0xA0: /* Program */
pfl->cmd = cmd;
trace_pflash_write_start(pfl->name, cmd);
break;
default:
trace_pflash_write_unknown(pfl->name, cmd);
goto reset_flash;
}
break;
case 3:
switch (pfl->cmd) {
case 0x80: /* Erase */
/* We need another unlock sequence */
goto check_unlock0;
case 0xA0: /* Program */
if (pflash_erase_suspend_mode(pfl) &&
pflash_sector_is_erasing(pfl, offset)) {
/* Ignore writes to erasing sectors. */
if (pfl->bypass) {
goto do_bypass;
}
goto reset_flash;
}
trace_pflash_data_write(pfl->name, offset, width, value, 0);
if (!pfl->ro) {
p = (uint8_t *)pfl->storage + offset;
if (pfl->be) {
uint64_t current = ldn_be_p(p, width);
stn_be_p(p, width, current & value);
} else {
uint64_t current = ldn_le_p(p, width);
stn_le_p(p, width, current & value);
}
pflash_update(pfl, offset, width);
}
/*
* While programming, status bit DQ7 should hold the opposite
* value from how it was programmed.
*/
set_dq7(pfl, ~value);
/* Let's pretend write is immediate */
if (pfl->bypass)
goto do_bypass;
goto reset_flash;
case 0x90: /* Autoselect */
if (pfl->bypass && cmd == 0x00) {
/* Unlock bypass reset */
goto reset_flash;
}
/*
* We can enter CFI query mode from autoselect mode, but we must
* return to autoselect mode after a reset.
*/
if (boff == 0x55 && cmd == 0x98) {
/* Enter autoselect CFI query mode */
pfl->wcycle = WCYCLE_AUTOSELECT_CFI;
pfl->cmd = 0x98;
return;
}
- /* fall through */
+ fallthrough;
default:
trace_pflash_write_invalid(pfl->name, pfl->cmd);
goto reset_flash;
}
case 4:
switch (pfl->cmd) {
case 0xA0: /* Program */
/* Ignore writes while flash data write is occurring */
/* As we suppose write is immediate, this should never happen */
return;
case 0x80: /* Erase */
goto check_unlock1;
default:
/* Should never happen */
trace_pflash_write_invalid_state(pfl->name, pfl->cmd, 5);
goto reset_flash;
}
break;
case 5:
if (pflash_erase_suspend_mode(pfl)) {
/* Erasing is not supported in erase suspend mode. */
goto reset_flash;
}
switch (cmd) {
case 0x10: /* Chip Erase */
if (boff != pfl->unlock_addr0) {
trace_pflash_chip_erase_invalid(pfl->name, offset);
goto reset_flash;
}
/* Chip erase */
trace_pflash_chip_erase_start(pfl->name);
if (!pfl->ro) {
memset(pfl->storage, 0xff, pfl->chip_len);
pflash_update(pfl, 0, pfl->chip_len);
}
set_dq7(pfl, 0x00);
/* Wait the time specified at CFI address 0x22. */
timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
(1ULL << pfl->cfi_table[0x22]) * SCALE_MS);
break;
case 0x30: /* Sector erase */
pflash_sector_erase(pfl, offset);
break;
default:
trace_pflash_write_invalid_command(pfl->name, cmd);
goto reset_flash;
}
pfl->cmd = cmd;
break;
case 6:
switch (pfl->cmd) {
case 0x10: /* Chip Erase */
/* Ignore writes during chip erase */
return;
case 0x30: /* Sector erase */
if (cmd == 0xB0) {
/*
* If erase suspend happens during the erase timeout (so DQ3 is
* 0), then the device suspends erasing immediately. Set the
* remaining time to be the total time to erase. Otherwise,
* there is a maximum amount of time it can take to enter
* suspend mode. Let's ignore that and suspend immediately and
* set the remaining time to the actual time remaining on the
* timer.
*/
if ((pfl->status & 0x08) == 0) {
pfl->erase_time_remaining = pflash_erase_time(pfl);
} else {
int64_t delta = timer_expire_time_ns(&pfl->timer) -
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
/* Make sure we have a positive time remaining. */
pfl->erase_time_remaining = delta <= 0 ? 1 : delta;
}
reset_dq3(pfl);
timer_del(&pfl->timer);
pflash_reset_state_machine(pfl);
return;
}
/*
* If DQ3 is 0, additional sector erase commands can be
* written and anything else (other than an erase suspend) resets
* the device.
*/
if ((pfl->status & 0x08) == 0) {
if (cmd == 0x30) {
pflash_sector_erase(pfl, offset);
} else {
goto reset_flash;
}
}
/* Ignore writes during the actual erase. */
return;
default:
/* Should never happen */
trace_pflash_write_invalid_state(pfl->name, pfl->cmd, 6);
goto reset_flash;
}
break;
/* Special values for CFI queries */
case WCYCLE_CFI:
case WCYCLE_AUTOSELECT_CFI:
trace_pflash_write(pfl->name, "invalid write in CFI query mode");
goto reset_flash;
default:
/* Should never happen */
trace_pflash_write(pfl->name, "invalid write state (wc 7)");
goto reset_flash;
}
pfl->wcycle++;
return;
/* Reset flash */
reset_flash:
pfl->bypass = 0;
pflash_reset_state_machine(pfl);
return;
do_bypass:
pfl->wcycle = 2;
pfl->cmd = 0;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 09/78] hw/acpi/aml-build.c: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (7 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 08/78] hw/block: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 10/78] hw/ide/atapi.c: " Emmanouil Pitsidianakis
` (69 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Michael S. Tsirkin, Igor Mammedov,
Ani Sinha
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/acpi/aml-build.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index af66bde0f5..b0cf0c6073 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -292,56 +292,55 @@ static void
build_prepend_package_length(GArray *package, unsigned length, bool incl_self)
{
uint8_t byte;
unsigned length_bytes;
if (length + 1 < (1 << PACKAGE_LENGTH_1BYTE_SHIFT)) {
length_bytes = 1;
} else if (length + 2 < (1 << PACKAGE_LENGTH_3BYTE_SHIFT)) {
length_bytes = 2;
} else if (length + 3 < (1 << PACKAGE_LENGTH_4BYTE_SHIFT)) {
length_bytes = 3;
} else {
length_bytes = 4;
}
/*
* NamedField uses PkgLength encoding but it doesn't include length
* of PkgLength itself.
*/
if (incl_self) {
/*
* PkgLength is the length of the inclusive length of the data
* and PkgLength's length itself when used for terms with
* explicit length.
*/
length += length_bytes;
}
switch (length_bytes) {
case 1:
byte = length;
build_prepend_byte(package, byte);
return;
case 4:
byte = length >> PACKAGE_LENGTH_4BYTE_SHIFT;
build_prepend_byte(package, byte);
length &= (1 << PACKAGE_LENGTH_4BYTE_SHIFT) - 1;
- /* fall through */
+ fallthrough;
case 3:
byte = length >> PACKAGE_LENGTH_3BYTE_SHIFT;
build_prepend_byte(package, byte);
length &= (1 << PACKAGE_LENGTH_3BYTE_SHIFT) - 1;
- /* fall through */
+ fallthrough;
case 2:
byte = length >> PACKAGE_LENGTH_2BYTE_SHIFT;
build_prepend_byte(package, byte);
length &= (1 << PACKAGE_LENGTH_2BYTE_SHIFT) - 1;
- /* fall through */
}
/*
* Most significant two bits of byte zero indicate how many following bytes
* are in PkgLength encoding.
*/
byte = ((length_bytes - 1) << PACKAGE_LENGTH_1BYTE_SHIFT) | length;
build_prepend_byte(package, byte);
}
@@ -508,37 +507,38 @@ static void build_buffer(GArray *array, uint8_t op)
void aml_append(Aml *parent_ctx, Aml *child)
{
GArray *buf = build_alloc_array();
build_append_array(buf, child->buf);
switch (child->block_flags) {
case AML_OPCODE:
build_append_byte(parent_ctx->buf, child->op);
break;
case AML_EXT_PACKAGE:
build_extop_package(buf, child->op);
break;
case AML_PACKAGE:
build_package(buf, child->op);
break;
case AML_RES_TEMPLATE:
build_append_byte(buf, 0x79); /* EndTag */
/*
* checksum operations are treated as succeeded if checksum
* field is zero. [ACPI Spec 1.0b, 6.4.2.8 End Tag]
*/
build_append_byte(buf, 0);
/* fall through, to pack resources in buffer */
+ fallthrough;
case AML_BUFFER:
build_buffer(buf, child->op);
break;
case AML_NO_OPCODE:
break;
default:
assert(0);
break;
}
build_append_array(parent_ctx->buf, buf);
build_free_array(buf);
}
/* ACPI 1.0b: 16.2.5.1 Namespace Modifier Objects Encoding: DefScope */
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 10/78] hw/ide/atapi.c: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (8 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 09/78] hw/acpi/aml-build.c: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 11/78] hw/timer: " Emmanouil Pitsidianakis
` (68 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, John Snow, open list:IDE
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/ide/atapi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/ide/atapi.c b/hw/ide/atapi.c
index dcc39df9a4..85c74a5ffe 100644
--- a/hw/ide/atapi.c
+++ b/hw/ide/atapi.c
@@ -1189,53 +1189,54 @@ static void cmd_read_disc_information(IDEState *s, uint8_t* buf)
static void cmd_read_dvd_structure(IDEState *s, uint8_t* buf)
{
int max_len;
int media = buf[1];
int format = buf[7];
int ret;
max_len = lduw_be_p(buf + 8);
if (format < 0xff) {
if (media_is_cd(s)) {
ide_atapi_cmd_error(s, ILLEGAL_REQUEST,
ASC_INCOMPATIBLE_FORMAT);
return;
} else if (!media_present(s)) {
ide_atapi_cmd_error(s, ILLEGAL_REQUEST,
ASC_INV_FIELD_IN_CMD_PACKET);
return;
}
}
memset(buf, 0, max_len > IDE_DMA_BUF_SECTORS * BDRV_SECTOR_SIZE + 4 ?
IDE_DMA_BUF_SECTORS * BDRV_SECTOR_SIZE + 4 : max_len);
switch (format) {
case 0x00 ... 0x7f:
case 0xff:
if (media == 0) {
ret = ide_dvd_read_structure(s, format, buf, buf);
if (ret < 0) {
ide_atapi_cmd_error(s, ILLEGAL_REQUEST, -ret);
} else {
ide_atapi_cmd_reply(s, ret, max_len);
}
break;
}
/* TODO: BD support, fall through for now */
+ fallthrough;
/* Generic disk structures */
case 0x80: /* TODO: AACS volume identifier */
case 0x81: /* TODO: AACS media serial number */
case 0x82: /* TODO: AACS media identifier */
case 0x83: /* TODO: AACS media key block */
case 0x90: /* TODO: List of recognized format layers */
case 0xc0: /* TODO: Write protection status */
default:
ide_atapi_cmd_error(s, ILLEGAL_REQUEST,
ASC_INV_FIELD_IN_CMD_PACKET);
break;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 11/78] hw/timer: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (9 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 10/78] hw/ide/atapi.c: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 12/78] hw/usb: " Emmanouil Pitsidianakis
` (67 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Peter Maydell, Cédric Le Goater,
Andrew Jeffery, Joel Stanley, Yoshinori Sato, Magnus Damm,
open list:ARM cores
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/timer/a9gtimer.c | 8 ++--
hw/timer/aspeed_timer.c | 1 +
hw/timer/pxa2xx_timer.c | 94 ++++++++++++++++++++---------------------
hw/timer/renesas_tmr.c | 2 +-
hw/timer/sh_timer.c | 8 ++--
5 files changed, 57 insertions(+), 56 deletions(-)
diff --git a/hw/timer/a9gtimer.c b/hw/timer/a9gtimer.c
index 5e959b6d09..b83d51da96 100644
--- a/hw/timer/a9gtimer.c
+++ b/hw/timer/a9gtimer.c
@@ -135,40 +135,40 @@ static void a9_gtimer_update_no_sync(void *opaque)
static uint64_t a9_gtimer_read(void *opaque, hwaddr addr, unsigned size)
{
A9GTimerPerCPU *gtb = (A9GTimerPerCPU *)opaque;
A9GTimerState *s = gtb->parent;
A9GTimerUpdate update;
uint64_t ret = 0;
int shift = 0;
switch (addr) {
case R_COUNTER_HI:
shift = 32;
- /* fallthrough */
+ fallthrough;
case R_COUNTER_LO:
update = a9_gtimer_get_update(s);
ret = extract64(update.new, shift, 32);
break;
case R_CONTROL:
ret = s->control | gtb->control;
break;
case R_INTERRUPT_STATUS:
ret = gtb->status;
break;
case R_COMPARATOR_HI:
shift = 32;
- /* fallthrough */
+ fallthrough;
case R_COMPARATOR_LO:
ret = extract64(gtb->compare, shift, 32);
break;
case R_AUTO_INCREMENT:
ret = gtb->inc;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "bad a9gtimer register: %x\n",
(unsigned)addr);
return 0;
}
DB_PRINT("addr:%#x data:%#08" PRIx64 "\n", (unsigned)addr, ret);
return ret;
}
@@ -176,54 +176,54 @@ static uint64_t a9_gtimer_read(void *opaque, hwaddr addr, unsigned size)
static void a9_gtimer_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
A9GTimerPerCPU *gtb = (A9GTimerPerCPU *)opaque;
A9GTimerState *s = gtb->parent;
int shift = 0;
DB_PRINT("addr:%#x data:%#08" PRIx64 "\n", (unsigned)addr, value);
switch (addr) {
case R_COUNTER_HI:
shift = 32;
- /* fallthrough */
+ fallthrough;
case R_COUNTER_LO:
/*
* Keep it simple - ARM docco explicitly says to disable timer before
* modding it, so don't bother trying to do all the difficult on the fly
* timer modifications - (if they even work in real hardware??).
*/
if (s->control & R_CONTROL_TIMER_ENABLE) {
qemu_log_mask(LOG_GUEST_ERROR, "Cannot mod running ARM gtimer\n");
return;
}
s->counter = deposit64(s->counter, shift, 32, value);
return;
case R_CONTROL:
a9_gtimer_update(s, (value ^ s->control) & R_CONTROL_NEEDS_SYNC);
gtb->control = value & R_CONTROL_BANKED;
s->control = value & ~R_CONTROL_BANKED;
break;
case R_INTERRUPT_STATUS:
a9_gtimer_update(s, false);
gtb->status &= ~value;
break;
case R_COMPARATOR_HI:
shift = 32;
- /* fallthrough */
+ fallthrough;
case R_COMPARATOR_LO:
a9_gtimer_update(s, false);
gtb->compare = deposit64(gtb->compare, shift, 32, value);
break;
case R_AUTO_INCREMENT:
gtb->inc = value;
return;
default:
return;
}
a9_gtimer_update(s, false);
}
/* Wrapper functions to implement the "read global timer for
* the current CPU" memory regions.
*/
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
index 72161f07bb..b343b7ab2c 100644
--- a/hw/timer/aspeed_timer.c
+++ b/hw/timer/aspeed_timer.c
@@ -266,53 +266,54 @@ static uint64_t aspeed_timer_read(void *opaque, hwaddr offset, unsigned size)
static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg,
uint32_t value)
{
AspeedTimer *t;
uint32_t old_reload;
trace_aspeed_timer_set_value(timer, reg, value);
t = &s->timers[timer];
switch (reg) {
case TIMER_REG_RELOAD:
old_reload = t->reload;
t->reload = calculate_min_ticks(t, value);
/* If the reload value was not previously set, or zero, and
* the current value is valid, try to start the timer if it is
* enabled.
*/
if (old_reload || !t->reload) {
break;
}
/* fall through to re-enable */
+ fallthrough;
case TIMER_REG_STATUS:
if (timer_enabled(t)) {
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
int64_t delta = (int64_t) value - (int64_t) calculate_ticks(t, now);
uint32_t rate = calculate_rate(t);
if (delta >= 0) {
t->start += muldiv64(delta, NANOSECONDS_PER_SECOND, rate);
} else {
t->start -= muldiv64(-delta, NANOSECONDS_PER_SECOND, rate);
}
aspeed_timer_mod(t);
}
break;
case TIMER_REG_MATCH_FIRST:
case TIMER_REG_MATCH_SECOND:
t->match[reg - 2] = value;
if (timer_enabled(t)) {
aspeed_timer_mod(t);
}
break;
default:
qemu_log_mask(LOG_UNIMP, "%s: Programming error: unexpected reg: %d\n",
__func__, reg);
break;
}
}
/* Control register operations are broken out into helpers that can be
* explicitly called on aspeed_timer_reset(), but also from
* aspeed_timer_ctrl_op().
*/
diff --git a/hw/timer/pxa2xx_timer.c b/hw/timer/pxa2xx_timer.c
index 2ae5ae3212..11863e1a42 100644
--- a/hw/timer/pxa2xx_timer.c
+++ b/hw/timer/pxa2xx_timer.c
@@ -162,109 +162,109 @@ static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
unsigned size)
{
PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
int tm = 0;
switch (offset) {
case OSMR3: tm ++;
- /* fall through */
+ fallthrough;
case OSMR2: tm ++;
- /* fall through */
+ fallthrough;
case OSMR1: tm ++;
- /* fall through */
+ fallthrough;
case OSMR0:
return s->timer[tm].value;
case OSMR11: tm ++;
- /* fall through */
+ fallthrough;
case OSMR10: tm ++;
- /* fall through */
+ fallthrough;
case OSMR9: tm ++;
- /* fall through */
+ fallthrough;
case OSMR8: tm ++;
- /* fall through */
+ fallthrough;
case OSMR7: tm ++;
- /* fall through */
+ fallthrough;
case OSMR6: tm ++;
- /* fall through */
+ fallthrough;
case OSMR5: tm ++;
- /* fall through */
+ fallthrough;
case OSMR4:
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
return s->tm4[tm].tm.value;
case OSCR:
return s->clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
s->lastload, s->freq, NANOSECONDS_PER_SECOND);
case OSCR11: tm ++;
- /* fall through */
+ fallthrough;
case OSCR10: tm ++;
- /* fall through */
+ fallthrough;
case OSCR9: tm ++;
- /* fall through */
+ fallthrough;
case OSCR8: tm ++;
- /* fall through */
+ fallthrough;
case OSCR7: tm ++;
- /* fall through */
+ fallthrough;
case OSCR6: tm ++;
- /* fall through */
+ fallthrough;
case OSCR5: tm ++;
- /* fall through */
+ fallthrough;
case OSCR4:
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
if (s->tm4[tm - 1].freq)
s->snapshot = s->tm4[tm - 1].clock + muldiv64(
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
s->tm4[tm - 1].lastload,
s->tm4[tm - 1].freq, NANOSECONDS_PER_SECOND);
else
s->snapshot = s->tm4[tm - 1].clock;
}
if (!s->tm4[tm].freq)
return s->tm4[tm].clock;
return s->tm4[tm].clock +
muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
s->tm4[tm].lastload, s->tm4[tm].freq,
NANOSECONDS_PER_SECOND);
case OIER:
return s->irq_enabled;
case OSSR: /* Status register */
return s->events;
case OWER:
return s->reset3;
case OMCR11: tm ++;
- /* fall through */
+ fallthrough;
case OMCR10: tm ++;
- /* fall through */
+ fallthrough;
case OMCR9: tm ++;
- /* fall through */
+ fallthrough;
case OMCR8: tm ++;
- /* fall through */
+ fallthrough;
case OMCR7: tm ++;
- /* fall through */
+ fallthrough;
case OMCR6: tm ++;
- /* fall through */
+ fallthrough;
case OMCR5: tm ++;
- /* fall through */
+ fallthrough;
case OMCR4:
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
return s->tm4[tm].control;
case OSNR:
return s->snapshot;
default:
qemu_log_mask(LOG_UNIMP,
"%s: unknown register 0x%02" HWADDR_PRIx "\n",
__func__, offset);
break;
badreg:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: incorrect register 0x%02" HWADDR_PRIx "\n",
__func__, offset);
}
return 0;
}
@@ -272,128 +272,128 @@ static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
static void pxa2xx_timer_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
int i, tm = 0;
PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
switch (offset) {
case OSMR3: tm ++;
- /* fall through */
+ fallthrough;
case OSMR2: tm ++;
- /* fall through */
+ fallthrough;
case OSMR1: tm ++;
- /* fall through */
+ fallthrough;
case OSMR0:
s->timer[tm].value = value;
pxa2xx_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
break;
case OSMR11: tm ++;
- /* fall through */
+ fallthrough;
case OSMR10: tm ++;
- /* fall through */
+ fallthrough;
case OSMR9: tm ++;
- /* fall through */
+ fallthrough;
case OSMR8: tm ++;
- /* fall through */
+ fallthrough;
case OSMR7: tm ++;
- /* fall through */
+ fallthrough;
case OSMR6: tm ++;
- /* fall through */
+ fallthrough;
case OSMR5: tm ++;
- /* fall through */
+ fallthrough;
case OSMR4:
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
s->tm4[tm].tm.value = value;
pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
break;
case OSCR:
s->oldclock = s->clock;
s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
s->clock = value;
pxa2xx_timer_update(s, s->lastload);
break;
case OSCR11: tm ++;
- /* fall through */
+ fallthrough;
case OSCR10: tm ++;
- /* fall through */
+ fallthrough;
case OSCR9: tm ++;
- /* fall through */
+ fallthrough;
case OSCR8: tm ++;
- /* fall through */
+ fallthrough;
case OSCR7: tm ++;
- /* fall through */
+ fallthrough;
case OSCR6: tm ++;
- /* fall through */
+ fallthrough;
case OSCR5: tm ++;
- /* fall through */
+ fallthrough;
case OSCR4:
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
s->tm4[tm].oldclock = s->tm4[tm].clock;
s->tm4[tm].lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
s->tm4[tm].clock = value;
pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
break;
case OIER:
s->irq_enabled = value & 0xfff;
break;
case OSSR: /* Status register */
value &= s->events;
s->events &= ~value;
for (i = 0; i < 4; i ++, value >>= 1)
if (value & 1)
qemu_irq_lower(s->timer[i].irq);
if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
qemu_irq_lower(s->irq4);
break;
case OWER: /* XXX: Reset on OSMR3 match? */
s->reset3 = value;
break;
case OMCR7: tm ++;
- /* fall through */
+ fallthrough;
case OMCR6: tm ++;
- /* fall through */
+ fallthrough;
case OMCR5: tm ++;
- /* fall through */
+ fallthrough;
case OMCR4:
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
s->tm4[tm].control = value & 0x0ff;
/* XXX Stop if running (shouldn't happen) */
if ((value & (1 << 7)) || tm == 0)
s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
else {
s->tm4[tm].freq = 0;
pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
}
break;
case OMCR11: tm ++;
- /* fall through */
+ fallthrough;
case OMCR10: tm ++;
- /* fall through */
+ fallthrough;
case OMCR9: tm ++;
- /* fall through */
+ fallthrough;
case OMCR8: tm += 4;
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
s->tm4[tm].control = value & 0x3ff;
/* XXX Stop if running (shouldn't happen) */
if ((value & (1 << 7)) || !(tm & 1))
s->tm4[tm].freq =
pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)];
else {
s->tm4[tm].freq = 0;
pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
}
break;
default:
qemu_log_mask(LOG_UNIMP,
"%s: unknown register 0x%02" HWADDR_PRIx " "
"(value 0x%08" PRIx64 ")\n", __func__, offset, value);
break;
badreg:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: incorrect register 0x%02" HWADDR_PRIx " "
"(value 0x%08" PRIx64 ")\n", __func__, offset, value);
}
}
diff --git a/hw/timer/renesas_tmr.c b/hw/timer/renesas_tmr.c
index 43b31213bc..a32521e3c3 100644
--- a/hw/timer/renesas_tmr.c
+++ b/hw/timer/renesas_tmr.c
@@ -193,69 +193,69 @@ static uint8_t read_tccr(uint8_t r)
static uint64_t tmr_read(void *opaque, hwaddr addr, unsigned size)
{
RTMRState *tmr = opaque;
int ch = addr & 1;
uint64_t ret;
if (size == 2 && (ch != 0 || addr == A_TCR || addr == A_TCSR)) {
qemu_log_mask(LOG_GUEST_ERROR, "renesas_tmr: Invalid read size 0x%"
HWADDR_PRIX "\n",
addr);
return UINT64_MAX;
}
switch (addr & 0x0e) {
case A_TCR:
ret = 0;
ret = FIELD_DP8(ret, TCR, CCLR,
FIELD_EX8(tmr->tcr[ch], TCR, CCLR));
ret = FIELD_DP8(ret, TCR, OVIE,
FIELD_EX8(tmr->tcr[ch], TCR, OVIE));
ret = FIELD_DP8(ret, TCR, CMIEA,
FIELD_EX8(tmr->tcr[ch], TCR, CMIEA));
ret = FIELD_DP8(ret, TCR, CMIEB,
FIELD_EX8(tmr->tcr[ch], TCR, CMIEB));
return ret;
case A_TCSR:
ret = 0;
ret = FIELD_DP8(ret, TCSR, OSA,
FIELD_EX8(tmr->tcsr[ch], TCSR, OSA));
ret = FIELD_DP8(ret, TCSR, OSB,
FIELD_EX8(tmr->tcsr[ch], TCSR, OSB));
switch (ch) {
case 0:
ret = FIELD_DP8(ret, TCSR, ADTE,
FIELD_EX8(tmr->tcsr[ch], TCSR, ADTE));
break;
case 1: /* CH1 ADTE unimplement always 1 */
ret = FIELD_DP8(ret, TCSR, ADTE, 1);
break;
}
return ret;
case A_TCORA:
if (size == 1) {
return tmr->tcora[ch];
} else if (ch == 0) {
return concat_reg(tmr->tcora);
}
- /* fall through */
+ fallthrough;
case A_TCORB:
if (size == 1) {
return tmr->tcorb[ch];
} else {
return concat_reg(tmr->tcorb);
}
case A_TCNT:
return read_tcnt(tmr, size, ch);
case A_TCCR:
if (size == 1) {
return read_tccr(tmr->tccr[ch]);
} else {
return read_tccr(tmr->tccr[0]) << 8 | read_tccr(tmr->tccr[1]);
}
default:
qemu_log_mask(LOG_UNIMP, "renesas_tmr: Register 0x%" HWADDR_PRIX
" not implemented\n",
addr);
break;
}
return UINT64_MAX;
}
diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c
index 7788939766..6dbfc2595b 100644
--- a/hw/timer/sh_timer.c
+++ b/hw/timer/sh_timer.c
@@ -84,120 +84,120 @@ static uint32_t sh_timer_read(void *opaque, hwaddr offset)
static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value)
{
SHTimerState *s = opaque;
int freq;
switch (offset >> 2) {
case OFFSET_TCOR:
s->tcor = value;
ptimer_transaction_begin(s->timer);
ptimer_set_limit(s->timer, s->tcor, 0);
ptimer_transaction_commit(s->timer);
break;
case OFFSET_TCNT:
s->tcnt = value;
ptimer_transaction_begin(s->timer);
ptimer_set_count(s->timer, s->tcnt);
ptimer_transaction_commit(s->timer);
break;
case OFFSET_TCR:
ptimer_transaction_begin(s->timer);
if (s->enabled) {
/*
* Pause the timer if it is running. This may cause some inaccuracy
* due to rounding, but avoids a whole lot of other messiness
*/
ptimer_stop(s->timer);
}
freq = s->freq;
/* ??? Need to recalculate expiry time after changing divisor. */
switch (value & TIMER_TCR_TPSC) {
case 0:
freq >>= 2;
break;
case 1:
freq >>= 4;
break;
case 2:
freq >>= 6;
break;
case 3:
freq >>= 8;
break;
case 4:
freq >>= 10;
break;
case 6:
case 7:
if (s->feat & TIMER_FEAT_EXTCLK) {
break;
}
- /* fallthrough */
+ fallthrough;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Reserved TPSC value\n", __func__);
}
switch ((value & TIMER_TCR_CKEG) >> 3) {
case 0:
break;
case 1:
case 2:
case 3:
if (s->feat & TIMER_FEAT_EXTCLK) {
break;
}
- /* fallthrough */
+ fallthrough;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Reserved CKEG value\n", __func__);
}
switch ((value & TIMER_TCR_ICPE) >> 6) {
case 0:
break;
case 2:
case 3:
if (s->feat & TIMER_FEAT_CAPT) {
break;
}
- /* fallthrough */
+ fallthrough;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Reserved ICPE value\n", __func__);
}
if ((value & TIMER_TCR_UNF) == 0) {
s->int_level = 0;
}
value &= ~TIMER_TCR_UNF;
if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Reserved ICPF value\n", __func__);
}
value &= ~TIMER_TCR_ICPF; /* capture not supported */
if (value & TIMER_TCR_RESERVED) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Reserved TCR bits set\n", __func__);
}
s->tcr = value;
ptimer_set_limit(s->timer, s->tcor, 0);
ptimer_set_freq(s->timer, freq);
if (s->enabled) {
/* Restart the timer if still enabled. */
ptimer_run(s->timer, 0);
}
ptimer_transaction_commit(s->timer);
break;
case OFFSET_TCPR:
if (s->feat & TIMER_FEAT_CAPT) {
s->tcpr = value;
break;
}
- /* fallthrough */
+ fallthrough;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset);
}
sh_timer_update(s);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 12/78] hw/usb: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (10 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 11/78] hw/timer: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 13/78] hw/adc: " Emmanouil Pitsidianakis
` (66 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Gerd Hoffmann
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/usb/dev-mtp.c | 2 +-
hw/usb/dev-wacom.c | 2 +-
hw/usb/hcd-ehci.c | 4 +++-
hw/usb/hcd-xhci.c | 4 ++--
hw/usb/redirect.c | 4 ++--
hw/usb/tusb6010.c | 2 +-
6 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/hw/usb/dev-mtp.c b/hw/usb/dev-mtp.c
index 1cac1cd435..5cbaabd2b2 100644
--- a/hw/usb/dev-mtp.c
+++ b/hw/usb/dev-mtp.c
@@ -1602,76 +1602,76 @@ static int usb_mtp_update_object(MTPObject *parent, char *name)
static void usb_mtp_write_data(MTPState *s, uint32_t handle)
{
MTPData *d = s->data_out;
MTPObject *parent =
usb_mtp_object_lookup(s, s->dataset.parent_handle);
char *path = NULL;
uint64_t rc;
mode_t mask = 0755;
int ret = 0;
assert(d != NULL);
switch (d->write_status) {
case WRITE_START:
if (!parent || !s->write_pending) {
usb_mtp_queue_result(s, RES_INVALID_OBJECTINFO, d->trans,
0, 0, 0, 0);
return;
}
if (s->dataset.filename) {
path = g_strdup_printf("%s/%s", parent->path, s->dataset.filename);
if (s->dataset.format == FMT_ASSOCIATION) {
ret = g_mkdir(path, mask);
if (!ret) {
usb_mtp_queue_result(s, RES_OK, d->trans, 3,
QEMU_STORAGE_ID,
s->dataset.parent_handle,
handle);
goto close;
}
goto done;
}
d->fd = open(path, O_CREAT | O_WRONLY |
O_CLOEXEC | O_NOFOLLOW, mask & 0666);
if (d->fd == -1) {
ret = 1;
goto done;
}
/* Return success if initiator sent 0 sized data */
if (!s->dataset.size) {
goto done;
}
if (d->length != MTP_WRITE_BUF_SZ && !d->pending) {
d->write_status = WRITE_END;
}
}
- /* fall through */
+ fallthrough;
case WRITE_CONTINUE:
case WRITE_END:
rc = write_retry(d->fd, d->data, d->data_offset,
d->offset - d->data_offset);
if (rc != d->data_offset) {
ret = 1;
goto done;
}
if (d->write_status != WRITE_END) {
g_free(path);
return;
} else {
/*
* Return an incomplete transfer if file size doesn't match
* for < 4G file or if lstat fails which will result in an incorrect
* file size
*/
if ((s->dataset.size != 0xFFFFFFFF &&
d->offset != s->dataset.size) ||
usb_mtp_update_object(parent, s->dataset.filename)) {
usb_mtp_queue_result(s, RES_INCOMPLETE_TRANSFER, d->trans,
0, 0, 0, 0);
goto close;
}
}
}
diff --git a/hw/usb/dev-wacom.c b/hw/usb/dev-wacom.c
index 7177c17f03..bd2a1bae50 100644
--- a/hw/usb/dev-wacom.c
+++ b/hw/usb/dev-wacom.c
@@ -371,27 +371,27 @@ static void usb_wacom_handle_control(USBDevice *dev, USBPacket *p,
static void usb_wacom_handle_data(USBDevice *dev, USBPacket *p)
{
USBWacomState *s = (USBWacomState *) dev;
g_autofree uint8_t *buf = g_malloc(p->iov.size);
int len = 0;
switch (p->pid) {
case USB_TOKEN_IN:
if (p->ep->nr == 1) {
if (!(s->changed || s->idle)) {
p->status = USB_RET_NAK;
return;
}
s->changed = 0;
if (s->mode == WACOM_MODE_HID)
len = usb_mouse_poll(s, buf, p->iov.size);
else if (s->mode == WACOM_MODE_WACOM)
len = usb_wacom_poll(s, buf, p->iov.size);
usb_packet_copy(p, buf, len);
break;
}
- /* Fall through. */
+ fallthrough;
case USB_TOKEN_OUT:
default:
p->status = USB_RET_STALL;
}
}
diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
index 19b4534c20..e29cc21957 100644
--- a/hw/usb/hcd-ehci.c
+++ b/hw/usb/hcd-ehci.c
@@ -1402,116 +1402,116 @@ static int ehci_execute(EHCIPacket *p, const char *action)
static int ehci_process_itd(EHCIState *ehci,
EHCIitd *itd,
uint32_t addr)
{
USBDevice *dev;
USBEndpoint *ep;
uint32_t i, len, pid, dir, devaddr, endp;
uint32_t pg, off, ptr1, ptr2, max, mult;
ehci->periodic_sched_active = PERIODIC_ACTIVE;
dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
for(i = 0; i < 8; i++) {
if (itd->transact[i] & ITD_XACT_ACTIVE) {
pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
len = get_field(itd->transact[i], ITD_XACT_LENGTH);
if (len > max * mult) {
len = max * mult;
}
if (len > BUFF_SIZE || pg > 6) {
return -1;
}
ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);
qemu_sglist_init(&ehci->isgl, ehci->device, 2, ehci->as);
if (off + len > 4096) {
/* transfer crosses page border */
if (pg == 6) {
qemu_sglist_destroy(&ehci->isgl);
return -1; /* avoid page pg + 1 */
}
ptr2 = (itd->bufptr[pg + 1] & ITD_BUFPTR_MASK);
uint32_t len2 = off + len - 4096;
uint32_t len1 = len - len2;
qemu_sglist_add(&ehci->isgl, ptr1 + off, len1);
qemu_sglist_add(&ehci->isgl, ptr2, len2);
} else {
qemu_sglist_add(&ehci->isgl, ptr1 + off, len);
}
dev = ehci_find_device(ehci, devaddr);
if (dev == NULL) {
ehci_trace_guest_bug(ehci, "no device found");
ehci->ipacket.status = USB_RET_NODEV;
ehci->ipacket.actual_length = 0;
} else {
pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT;
ep = usb_ep_get(dev, pid, endp);
if (ep && ep->type == USB_ENDPOINT_XFER_ISOC) {
usb_packet_setup(&ehci->ipacket, pid, ep, 0, addr, false,
(itd->transact[i] & ITD_XACT_IOC) != 0);
if (usb_packet_map(&ehci->ipacket, &ehci->isgl)) {
qemu_sglist_destroy(&ehci->isgl);
return -1;
}
usb_handle_packet(dev, &ehci->ipacket);
usb_packet_unmap(&ehci->ipacket, &ehci->isgl);
} else {
DPRINTF("ISOCH: attempt to address non-iso endpoint\n");
ehci->ipacket.status = USB_RET_NAK;
ehci->ipacket.actual_length = 0;
}
}
qemu_sglist_destroy(&ehci->isgl);
switch (ehci->ipacket.status) {
case USB_RET_SUCCESS:
break;
default:
fprintf(stderr, "Unexpected iso usb result: %d\n",
ehci->ipacket.status);
- /* Fall through */
+ fallthrough;
case USB_RET_IOERROR:
case USB_RET_NODEV:
/* 3.3.2: XACTERR is only allowed on IN transactions */
if (dir) {
itd->transact[i] |= ITD_XACT_XACTERR;
ehci_raise_irq(ehci, USBSTS_ERRINT);
}
break;
case USB_RET_BABBLE:
itd->transact[i] |= ITD_XACT_BABBLE;
ehci_raise_irq(ehci, USBSTS_ERRINT);
break;
case USB_RET_NAK:
/* no data for us, so do a zero-length transfer */
ehci->ipacket.actual_length = 0;
break;
}
if (!dir) {
set_field(&itd->transact[i], len - ehci->ipacket.actual_length,
ITD_XACT_LENGTH); /* OUT */
} else {
set_field(&itd->transact[i], ehci->ipacket.actual_length,
ITD_XACT_LENGTH); /* IN */
}
if (itd->transact[i] & ITD_XACT_IOC) {
ehci_raise_irq(ehci, USBSTS_INT);
}
itd->transact[i] &= ~ITD_XACT_ACTIVE;
}
}
return 0;
}
/* This state is the entry point for asynchronous schedule
* processing. Entry here constitutes a EHCI start event state (4.8.5)
*/
@@ -2132,54 +2132,55 @@ static void ehci_advance_state(EHCIState *ehci, int async)
static void ehci_advance_async_state(EHCIState *ehci)
{
const int async = 1;
switch(ehci_get_state(ehci, async)) {
case EST_INACTIVE:
if (!ehci_async_enabled(ehci)) {
break;
}
ehci_set_state(ehci, async, EST_ACTIVE);
// No break, fall through to ACTIVE
+ fallthrough;
case EST_ACTIVE:
if (!ehci_async_enabled(ehci)) {
ehci_queues_rip_all(ehci, async);
ehci_set_state(ehci, async, EST_INACTIVE);
break;
}
/* make sure guest has acknowledged the doorbell interrupt */
/* TO-DO: is this really needed? */
if (ehci->usbsts & USBSTS_IAA) {
DPRINTF("IAA status bit still set.\n");
break;
}
/* check that address register has been set */
if (ehci->asynclistaddr == 0) {
break;
}
ehci_set_state(ehci, async, EST_WAITLISTHEAD);
ehci_advance_state(ehci, async);
/* If the doorbell is set, the guest wants to make a change to the
* schedule. The host controller needs to release cached data.
* (section 4.8.2)
*/
if (ehci->usbcmd & USBCMD_IAAD) {
/* Remove all unseen qhs from the async qhs queue */
ehci_queues_rip_unseen(ehci, async);
trace_usb_ehci_doorbell_ack();
ehci->usbcmd &= ~USBCMD_IAAD;
ehci_raise_irq(ehci, USBSTS_IAA);
}
break;
default:
/* this should only be due to a developer mistake */
fprintf(stderr, "ehci: Bad asynchronous state %d. "
"Resetting to active\n", ehci->astate);
g_assert_not_reached();
}
}
@@ -2187,49 +2188,50 @@ static void ehci_advance_async_state(EHCIState *ehci)
static void ehci_advance_periodic_state(EHCIState *ehci)
{
uint32_t entry;
uint32_t list;
const int async = 0;
// 4.6
switch(ehci_get_state(ehci, async)) {
case EST_INACTIVE:
if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) {
ehci_set_state(ehci, async, EST_ACTIVE);
// No break, fall through to ACTIVE
+ fallthrough;
} else
break;
case EST_ACTIVE:
if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) {
ehci_queues_rip_all(ehci, async);
ehci_set_state(ehci, async, EST_INACTIVE);
break;
}
list = ehci->periodiclistbase & 0xfffff000;
/* check that register has been set */
if (list == 0) {
break;
}
list |= ((ehci->frindex & 0x1ff8) >> 1);
if (get_dwords(ehci, list, &entry, 1) < 0) {
break;
}
DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
ehci->frindex / 8, list, entry);
ehci_set_fetch_addr(ehci, async,entry);
ehci_set_state(ehci, async, EST_FETCHENTRY);
ehci_advance_state(ehci, async);
ehci_queues_rip_unused(ehci, async);
break;
default:
/* this should only be due to a developer mistake */
fprintf(stderr, "ehci: Bad periodic state %d. "
"Resetting to active\n", ehci->pstate);
g_assert_not_reached();
}
}
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
index 4b60114207..3e9b9c62bd 100644
--- a/hw/usb/hcd-xhci.c
+++ b/hw/usb/hcd-xhci.c
@@ -1438,41 +1438,41 @@ static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
{
XHCIState *xhci = xfer->epctx->xhci;
int i;
xfer->int_req = false;
qemu_sglist_init(&xfer->sgl, DEVICE(xhci), xfer->trb_count, xhci->as);
for (i = 0; i < xfer->trb_count; i++) {
XHCITRB *trb = &xfer->trbs[i];
dma_addr_t addr;
unsigned int chunk = 0;
if (trb->control & TRB_TR_IOC) {
xfer->int_req = true;
}
switch (TRB_TYPE(*trb)) {
case TR_DATA:
if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
DPRINTF("xhci: data direction mismatch for TR_DATA\n");
goto err;
}
- /* fallthrough */
+ fallthrough;
case TR_NORMAL:
case TR_ISOCH:
addr = xhci_mask64(trb->parameter);
chunk = trb->status & 0x1ffff;
if (trb->control & TRB_TR_IDT) {
if (chunk > 8 || in_xfer) {
DPRINTF("xhci: invalid immediate data TRB\n");
goto err;
}
qemu_sglist_add(&xfer->sgl, trb->addr, chunk);
} else {
qemu_sglist_add(&xfer->sgl, addr, chunk);
}
break;
}
}
return 0;
@@ -2666,28 +2666,28 @@ static void xhci_port_update(XHCIPort *port, int is_detach)
static void xhci_port_reset(XHCIPort *port, bool warm_reset)
{
trace_usb_xhci_port_reset(port->portnr, warm_reset);
if (!xhci_port_have_device(port)) {
return;
}
usb_device_reset(port->uport->dev);
switch (port->uport->dev->speed) {
case USB_SPEED_SUPER:
if (warm_reset) {
port->portsc |= PORTSC_WRC;
}
- /* fall through */
+ fallthrough;
case USB_SPEED_LOW:
case USB_SPEED_FULL:
case USB_SPEED_HIGH:
set_field(&port->portsc, PLS_U0, PORTSC_PLS);
trace_usb_xhci_port_link(port->portnr, PLS_U0);
port->portsc |= PORTSC_PED;
break;
}
port->portsc &= ~PORTSC_PR;
xhci_port_notify(port, PORTSC_PRC);
}
diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c
index c9893df867..2531d583ad 100644
--- a/hw/usb/redirect.c
+++ b/hw/usb/redirect.c
@@ -1790,67 +1790,67 @@ static void usbredir_setup_usb_eps(USBRedirDevice *dev)
static void usbredir_ep_info(void *priv,
struct usb_redir_ep_info_header *ep_info)
{
USBRedirDevice *dev = priv;
int i;
assert(dev != NULL);
for (i = 0; i < MAX_ENDPOINTS; i++) {
dev->endpoint[i].type = ep_info->type[i];
dev->endpoint[i].interval = ep_info->interval[i];
dev->endpoint[i].interface = ep_info->interface[i];
if (usbredirparser_peer_has_cap(dev->parser,
usb_redir_cap_ep_info_max_packet_size)) {
dev->endpoint[i].max_packet_size = ep_info->max_packet_size[i];
}
#if USBREDIR_VERSION >= 0x000700
if (usbredirparser_peer_has_cap(dev->parser,
usb_redir_cap_bulk_streams)) {
dev->endpoint[i].max_streams = ep_info->max_streams[i];
}
#endif
switch (dev->endpoint[i].type) {
case usb_redir_type_invalid:
break;
case usb_redir_type_iso:
usbredir_mark_speed_incompatible(dev, USB_SPEED_FULL);
usbredir_mark_speed_incompatible(dev, USB_SPEED_HIGH);
- /* Fall through */
+ fallthrough;
case usb_redir_type_interrupt:
if (!usbredirparser_peer_has_cap(dev->parser,
usb_redir_cap_ep_info_max_packet_size) ||
ep_info->max_packet_size[i] > 64) {
usbredir_mark_speed_incompatible(dev, USB_SPEED_FULL);
}
if (!usbredirparser_peer_has_cap(dev->parser,
usb_redir_cap_ep_info_max_packet_size) ||
ep_info->max_packet_size[i] > 1024) {
usbredir_mark_speed_incompatible(dev, USB_SPEED_HIGH);
}
if (dev->endpoint[i].interval == 0) {
ERROR("Received 0 interval for isoc or irq endpoint\n");
usbredir_reject_device(dev);
return;
}
- /* Fall through */
+ fallthrough;
case usb_redir_type_control:
case usb_redir_type_bulk:
DPRINTF("ep: %02X type: %d interface: %d\n", I2EP(i),
dev->endpoint[i].type, dev->endpoint[i].interface);
break;
default:
ERROR("Received invalid endpoint type\n");
usbredir_reject_device(dev);
return;
}
}
/* The new ep info may have caused a speed incompatibility, recheck */
if (dev->dev.attached &&
!(dev->dev.port->speedmask & dev->dev.speedmask)) {
ERROR("Device no longer matches speed after endpoint info change, "
"disconnecting!\n");
usbredir_reject_device(dev);
return;
}
usbredir_setup_usb_eps(dev);
usbredir_check_bulk_receiving(dev);
}
diff --git a/hw/usb/tusb6010.c b/hw/usb/tusb6010.c
index 1dd4071e68..88c736fad2 100644
--- a/hw/usb/tusb6010.c
+++ b/hw/usb/tusb6010.c
@@ -706,48 +706,48 @@ static void tusb_power_tick(void *opaque)
static void tusb_musb_core_intr(void *opaque, int source, int level)
{
TUSBState *s = (TUSBState *) opaque;
uint16_t otg_status = s->otg_status;
switch (source) {
case musb_set_vbus:
if (level)
otg_status |= TUSB_DEV_OTG_STAT_VBUS_VALID;
else
otg_status &= ~TUSB_DEV_OTG_STAT_VBUS_VALID;
/* XXX: only if TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN set? */
/* XXX: only if TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN set? */
if (s->otg_status != otg_status) {
s->otg_status = otg_status;
s->intr |= TUSB_INT_SRC_VBUS_SENSE_CHNG;
tusb_intr_update(s);
}
break;
case musb_set_session:
/* XXX: only if TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN set? */
/* XXX: only if TUSB_PRCM_MNGMT_OTG_SESS_END_EN set? */
if (level) {
s->otg_status |= TUSB_DEV_OTG_STAT_SESS_VALID;
s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_END;
} else {
s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_VALID;
s->otg_status |= TUSB_DEV_OTG_STAT_SESS_END;
}
/* XXX: some IRQ or anything? */
break;
case musb_irq_tx:
case musb_irq_rx:
s->usbip_intr = musb_core_intr_get(s->musb);
- /* Fall through. */
+ fallthrough;
default:
if (level)
s->intr |= 1 << source;
else
s->intr &= ~(1 << source);
tusb_intr_update(s);
break;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 13/78] hw/adc: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (11 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 12/78] hw/usb: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 14/78] util/error-report.c: " Emmanouil Pitsidianakis
` (65 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Alistair Francis, Peter Maydell,
Cédric Le Goater, Andrew Jeffery, Joel Stanley,
Edgar E. Iglesias, open list:STM32F205
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/adc/aspeed_adc.c | 12 ++++++------
hw/adc/zynq-xadc.c | 2 +-
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/adc/aspeed_adc.c b/hw/adc/aspeed_adc.c
index 0d29663129..f9f5f7bb17 100644
--- a/hw/adc/aspeed_adc.c
+++ b/hw/adc/aspeed_adc.c
@@ -107,59 +107,59 @@ static uint32_t read_channel_sample(AspeedADCEngineState *s, int reg)
static uint64_t aspeed_adc_engine_read(void *opaque, hwaddr addr,
unsigned int size)
{
AspeedADCEngineState *s = ASPEED_ADC_ENGINE(opaque);
int reg = TO_REG(addr);
uint32_t value = 0;
switch (reg) {
case BOUNDS_CHANNEL_8 ... BOUNDS_CHANNEL_15:
if (s->nr_channels <= 8) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: engine[%u]: "
"bounds register %u invalid, only 0...7 valid\n",
__func__, s->engine_id, reg - BOUNDS_CHANNEL_0);
break;
}
- /* fallthrough */
+ fallthrough;
case HYSTERESIS_CHANNEL_8 ... HYSTERESIS_CHANNEL_15:
if (s->nr_channels <= 8) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: engine[%u]: "
"hysteresis register %u invalid, only 0...7 valid\n",
__func__, s->engine_id, reg - HYSTERESIS_CHANNEL_0);
break;
}
- /* fallthrough */
+ fallthrough;
case BOUNDS_CHANNEL_0 ... BOUNDS_CHANNEL_7:
case HYSTERESIS_CHANNEL_0 ... HYSTERESIS_CHANNEL_7:
case ENGINE_CONTROL:
case INTERRUPT_CONTROL:
case VGA_DETECT_CONTROL:
case CLOCK_CONTROL:
case INTERRUPT_SOURCE:
case COMPENSATING_AND_TRIMMING:
value = s->regs[reg];
break;
case DATA_CHANNEL_9_AND_8 ... DATA_CHANNEL_15_AND_14:
if (s->nr_channels <= 8) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: engine[%u]: "
"data register %u invalid, only 0...3 valid\n",
__func__, s->engine_id, reg - DATA_CHANNEL_1_AND_0);
break;
}
- /* fallthrough */
+ fallthrough;
case DATA_CHANNEL_1_AND_0 ... DATA_CHANNEL_7_AND_6:
value = read_channel_sample(s, reg);
/* Allow 16-bit reads of the data registers */
if (addr & 0x2) {
assert(size == 2);
value >>= 16;
}
break;
default:
qemu_log_mask(LOG_UNIMP, "%s: engine[%u]: 0x%" HWADDR_PRIx "\n",
__func__, s->engine_id, addr);
break;
}
trace_aspeed_adc_engine_read(s->engine_id, addr, value);
return value;
}
@@ -167,69 +167,69 @@ static uint64_t aspeed_adc_engine_read(void *opaque, hwaddr addr,
static void aspeed_adc_engine_write(void *opaque, hwaddr addr, uint64_t value,
unsigned int size)
{
AspeedADCEngineState *s = ASPEED_ADC_ENGINE(opaque);
int reg = TO_REG(addr);
uint32_t init = 0;
trace_aspeed_adc_engine_write(s->engine_id, addr, value);
switch (reg) {
case ENGINE_CONTROL:
init = !!(value & ASPEED_ADC_ENGINE_EN);
init *= ASPEED_ADC_ENGINE_INIT;
value &= ~ASPEED_ADC_ENGINE_INIT;
value |= init;
value &= ~ASPEED_ADC_ENGINE_AUTO_COMP;
break;
case INTERRUPT_CONTROL:
case VGA_DETECT_CONTROL:
case CLOCK_CONTROL:
break;
case DATA_CHANNEL_9_AND_8 ... DATA_CHANNEL_15_AND_14:
if (s->nr_channels <= 8) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: engine[%u]: "
"data register %u invalid, only 0...3 valid\n",
__func__, s->engine_id, reg - DATA_CHANNEL_1_AND_0);
return;
}
- /* fallthrough */
+ fallthrough;
case BOUNDS_CHANNEL_8 ... BOUNDS_CHANNEL_15:
if (s->nr_channels <= 8) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: engine[%u]: "
"bounds register %u invalid, only 0...7 valid\n",
__func__, s->engine_id, reg - BOUNDS_CHANNEL_0);
return;
}
- /* fallthrough */
+ fallthrough;
case DATA_CHANNEL_1_AND_0 ... DATA_CHANNEL_7_AND_6:
case BOUNDS_CHANNEL_0 ... BOUNDS_CHANNEL_7:
value &= ASPEED_ADC_LH_MASK;
break;
case HYSTERESIS_CHANNEL_8 ... HYSTERESIS_CHANNEL_15:
if (s->nr_channels <= 8) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: engine[%u]: "
"hysteresis register %u invalid, only 0...7 valid\n",
__func__, s->engine_id, reg - HYSTERESIS_CHANNEL_0);
return;
}
- /* fallthrough */
+ fallthrough;
case HYSTERESIS_CHANNEL_0 ... HYSTERESIS_CHANNEL_7:
value &= (ASPEED_ADC_HYST_EN | ASPEED_ADC_LH_MASK);
break;
case INTERRUPT_SOURCE:
value &= 0xffff;
break;
case COMPENSATING_AND_TRIMMING:
value &= 0xf;
break;
default:
qemu_log_mask(LOG_UNIMP, "%s: engine[%u]: "
"0x%" HWADDR_PRIx " 0x%" PRIx64 "\n",
__func__, s->engine_id, addr, value);
break;
}
s->regs[reg] = value;
}
diff --git a/hw/adc/zynq-xadc.c b/hw/adc/zynq-xadc.c
index 032e19cbd0..a74de3a4fd 100644
--- a/hw/adc/zynq-xadc.c
+++ b/hw/adc/zynq-xadc.c
@@ -189,61 +189,61 @@ static uint64_t zynq_xadc_read(void *opaque, hwaddr offset, unsigned size)
static void zynq_xadc_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
{
ZynqXADCState *s = (ZynqXADCState *)opaque;
int reg = offset / 4;
int xadc_reg;
int xadc_cmd;
int xadc_data;
if (!zynq_xadc_check_offset(reg, false)) {
qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Invalid write access "
"to addr %" HWADDR_PRIx "\n", offset);
return;
}
switch (reg) {
case CFG:
s->regs[CFG] = val;
break;
case INT_STS:
s->regs[INT_STS] &= ~val;
break;
case INT_MASK:
s->regs[INT_MASK] = val & INT_ALL;
break;
case CMDFIFO:
xadc_cmd = extract32(val, 26, 4);
xadc_reg = extract32(val, 16, 10);
xadc_data = extract32(val, 0, 16);
if (s->regs[MCTL] & MCTL_RESET) {
qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Sending command "
"while comm channel held in reset: %" PRIx32 "\n",
(uint32_t) val);
break;
}
if (xadc_reg >= ZYNQ_XADC_NUM_ADC_REGS && xadc_cmd != CMD_NOP) {
qemu_log_mask(LOG_GUEST_ERROR, "read/write op to invalid xadc "
"reg 0x%x\n", xadc_reg);
break;
}
switch (xadc_cmd) {
case CMD_READ:
xadc_push_dfifo(s, s->xadc_regs[xadc_reg]);
break;
case CMD_WRITE:
s->xadc_regs[xadc_reg] = xadc_data;
- /* fallthrough */
+ fallthrough;
case CMD_NOP:
xadc_push_dfifo(s, 0);
break;
}
break;
case MCTL:
s->regs[MCTL] = val & 0x00fffeff;
break;
}
zynq_xadc_update_ints(s);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 14/78] util/error-report.c: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (12 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 13/78] hw/adc: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 15/78] accel/tcg: " Emmanouil Pitsidianakis
` (64 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
util/error-report.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/error-report.c b/util/error-report.c
index 6e44a55732..acb66420de 100644
--- a/util/error-report.c
+++ b/util/error-report.c
@@ -353,36 +353,36 @@ static char *qemu_glog_domains;
static void qemu_log_func(const gchar *log_domain,
GLogLevelFlags log_level,
const gchar *message,
gpointer user_data)
{
switch (log_level & G_LOG_LEVEL_MASK) {
case G_LOG_LEVEL_DEBUG:
case G_LOG_LEVEL_INFO:
/*
* Use same G_MESSAGES_DEBUG logic as glib to enable/disable debug
* messages
*/
if (qemu_glog_domains == NULL) {
break;
}
if (strcmp(qemu_glog_domains, "all") != 0 &&
(log_domain == NULL || !strstr(qemu_glog_domains, log_domain))) {
break;
}
- /* Fall through */
+ fallthrough;
case G_LOG_LEVEL_MESSAGE:
info_report("%s%s%s",
log_domain ?: "", log_domain ? ": " : "", message);
break;
case G_LOG_LEVEL_WARNING:
warn_report("%s%s%s",
log_domain ?: "", log_domain ? ": " : "", message);
break;
case G_LOG_LEVEL_CRITICAL:
case G_LOG_LEVEL_ERROR:
error_report("%s%s%s",
log_domain ?: "", log_domain ? ": " : "", message);
break;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 15/78] accel/tcg: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (13 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 14/78] util/error-report.c: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 16/78] audio: " Emmanouil Pitsidianakis
` (63 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Richard Henderson, Paolo Bonzini
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
accel/tcg/cputlb.c | 4 ++--
accel/tcg/ldst_atomicity.c.inc | 2 +-
accel/tcg/plugin-gen.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index b8c5e345b8..92b7ab529a 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -2209,53 +2209,53 @@ static Int128 do_ld_whole_be16(CPUState *cpu, uintptr_t ra,
/*
* Wrapper for the above.
*/
static uint64_t do_ld_beN(CPUState *cpu, MMULookupPageData *p,
uint64_t ret_be, int mmu_idx, MMUAccessType type,
MemOp mop, uintptr_t ra)
{
MemOp atom;
unsigned tmp, half_size;
if (unlikely(p->flags & TLB_MMIO)) {
return do_ld_mmio_beN(cpu, p->full, ret_be, p->addr, p->size,
mmu_idx, type, ra);
}
/*
* It is a given that we cross a page and therefore there is no
* atomicity for the load as a whole, but subobjects may need attention.
*/
atom = mop & MO_ATOM_MASK;
switch (atom) {
case MO_ATOM_SUBALIGN:
return do_ld_parts_beN(p, ret_be);
case MO_ATOM_IFALIGN_PAIR:
case MO_ATOM_WITHIN16_PAIR:
tmp = mop & MO_SIZE;
tmp = tmp ? tmp - 1 : 0;
half_size = 1 << tmp;
if (atom == MO_ATOM_IFALIGN_PAIR
? p->size == half_size
: p->size >= half_size) {
if (!HAVE_al8_fast && p->size < 4) {
return do_ld_whole_be4(p, ret_be);
} else {
return do_ld_whole_be8(cpu, ra, p, ret_be);
}
}
- /* fall through */
+ fallthrough;
case MO_ATOM_IFALIGN:
case MO_ATOM_WITHIN16:
case MO_ATOM_NONE:
return do_ld_bytes_beN(p, ret_be);
default:
g_assert_not_reached();
}
}
/*
* Wrapper for the above, for 8 < size < 16.
*/
@@ -2625,57 +2625,57 @@ static uint64_t do_st16_mmio_leN(CPUState *cpu, CPUTLBEntryFull *full,
/*
* Wrapper for the above.
*/
static uint64_t do_st_leN(CPUState *cpu, MMULookupPageData *p,
uint64_t val_le, int mmu_idx,
MemOp mop, uintptr_t ra)
{
MemOp atom;
unsigned tmp, half_size;
if (unlikely(p->flags & TLB_MMIO)) {
return do_st_mmio_leN(cpu, p->full, val_le, p->addr,
p->size, mmu_idx, ra);
} else if (unlikely(p->flags & TLB_DISCARD_WRITE)) {
return val_le >> (p->size * 8);
}
/*
* It is a given that we cross a page and therefore there is no atomicity
* for the store as a whole, but subobjects may need attention.
*/
atom = mop & MO_ATOM_MASK;
switch (atom) {
case MO_ATOM_SUBALIGN:
return store_parts_leN(p->haddr, p->size, val_le);
case MO_ATOM_IFALIGN_PAIR:
case MO_ATOM_WITHIN16_PAIR:
tmp = mop & MO_SIZE;
tmp = tmp ? tmp - 1 : 0;
half_size = 1 << tmp;
if (atom == MO_ATOM_IFALIGN_PAIR
? p->size == half_size
: p->size >= half_size) {
if (!HAVE_al8_fast && p->size <= 4) {
return store_whole_le4(p->haddr, p->size, val_le);
} else if (HAVE_al8) {
return store_whole_le8(p->haddr, p->size, val_le);
} else {
cpu_loop_exit_atomic(cpu, ra);
}
}
- /* fall through */
+ fallthrough;
case MO_ATOM_IFALIGN:
case MO_ATOM_WITHIN16:
case MO_ATOM_NONE:
return store_bytes_leN(p->haddr, p->size, val_le);
default:
g_assert_not_reached();
}
}
/*
* Wrapper for the above, for 8 < size < 16.
*/
diff --git a/accel/tcg/ldst_atomicity.c.inc b/accel/tcg/ldst_atomicity.c.inc
index 1cf5b92166..3752f74214 100644
--- a/accel/tcg/ldst_atomicity.c.inc
+++ b/accel/tcg/ldst_atomicity.c.inc
@@ -22,86 +22,86 @@
/**
* required_atomicity:
*
* Return the lg2 bytes of atomicity required by @memop for @p.
* If the operation must be split into two operations to be
* examined separately for atomicity, return -lg2.
*/
static int required_atomicity(CPUState *cpu, uintptr_t p, MemOp memop)
{
MemOp atom = memop & MO_ATOM_MASK;
MemOp size = memop & MO_SIZE;
MemOp half = size ? size - 1 : 0;
unsigned tmp;
int atmax;
switch (atom) {
case MO_ATOM_NONE:
atmax = MO_8;
break;
case MO_ATOM_IFALIGN_PAIR:
size = half;
- /* fall through */
+ fallthrough;
case MO_ATOM_IFALIGN:
tmp = (1 << size) - 1;
atmax = p & tmp ? MO_8 : size;
break;
case MO_ATOM_WITHIN16:
tmp = p & 15;
atmax = (tmp + (1 << size) <= 16 ? size : MO_8);
break;
case MO_ATOM_WITHIN16_PAIR:
tmp = p & 15;
if (tmp + (1 << size) <= 16) {
atmax = size;
} else if (tmp + (1 << half) == 16) {
/*
* The pair exactly straddles the boundary.
* Both halves are naturally aligned and atomic.
*/
atmax = half;
} else {
/*
* One of the pair crosses the boundary, and is non-atomic.
* The other of the pair does not cross, and is atomic.
*/
atmax = -half;
}
break;
case MO_ATOM_SUBALIGN:
/*
* Examine the alignment of p to determine if there are subobjects
* that must be aligned. Note that we only really need ctz4() --
* any more sigificant bits are discarded by the immediately
* following comparison.
*/
tmp = ctz32(p);
atmax = MIN(size, tmp);
break;
default:
g_assert_not_reached();
}
/*
* Here we have the architectural atomicity of the operation.
* However, when executing in a serial context, we need no extra
* host atomicity in order to avoid racing. This reduction
* avoids looping with cpu_loop_exit_atomic.
*/
if (cpu_in_serial_context(cpu)) {
return MO_8;
}
return atmax;
}
/**
* load_atomic2:
* @pv: host address
*
* Atomically load 2 aligned bytes from @pv.
*/
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index d31c9993ea..ba9a8c8789 100644
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -179,23 +179,23 @@ static void gen_wrapped(enum plugin_gen_from from,
static void plugin_gen_empty_callback(enum plugin_gen_from from)
{
switch (from) {
case PLUGIN_GEN_AFTER_INSN:
gen_wrapped(from, PLUGIN_GEN_DISABLE_MEM_HELPER,
gen_empty_mem_helper);
break;
case PLUGIN_GEN_FROM_INSN:
/*
* Note: plugin_gen_inject() relies on ENABLE_MEM_HELPER being
* the first callback of an instruction
*/
gen_wrapped(from, PLUGIN_GEN_ENABLE_MEM_HELPER,
gen_empty_mem_helper);
- /* fall through */
+ fallthrough;
case PLUGIN_GEN_FROM_TB:
gen_wrapped(from, PLUGIN_GEN_CB_UDATA, gen_empty_udata_cb);
gen_wrapped(from, PLUGIN_GEN_CB_INLINE, gen_empty_inline_cb);
break;
default:
g_assert_not_reached();
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 16/78] audio: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (14 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 15/78] accel/tcg: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 17/78] ui/sdl2.c: " Emmanouil Pitsidianakis
` (62 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Gerd Hoffmann, Marc-André Lureau,
Christian Schoenebeck
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
audio/audio.c | 16 ++++++++--------
audio/jackaudio.c | 4 ++--
audio/pwaudio.c | 4 ++--
3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/audio/audio.c b/audio/audio.c
index e9815d6812..ed7c795af7 100644
--- a/audio/audio.c
+++ b/audio/audio.c
@@ -245,39 +245,39 @@ static int audio_validate_settings (struct audsettings *as)
static int audio_pcm_info_eq (struct audio_pcm_info *info, struct audsettings *as)
{
int bits = 8;
bool is_signed = false, is_float = false;
switch (as->fmt) {
case AUDIO_FORMAT_S8:
is_signed = true;
- /* fall through */
+ fallthrough;
case AUDIO_FORMAT_U8:
break;
case AUDIO_FORMAT_S16:
is_signed = true;
- /* fall through */
+ fallthrough;
case AUDIO_FORMAT_U16:
bits = 16;
break;
case AUDIO_FORMAT_F32:
is_float = true;
- /* fall through */
+ fallthrough;
case AUDIO_FORMAT_S32:
is_signed = true;
- /* fall through */
+ fallthrough;
case AUDIO_FORMAT_U32:
bits = 32;
break;
default:
abort();
}
return info->freq == as->freq
&& info->nchannels == as->nchannels
&& info->is_signed == is_signed
&& info->is_float == is_float
&& info->bits == bits
&& info->swap_endianness == (as->endianness != AUDIO_HOST_ENDIANNESS);
}
@@ -285,45 +285,45 @@ static int audio_pcm_info_eq (struct audio_pcm_info *info, struct audsettings *a
void audio_pcm_init_info (struct audio_pcm_info *info, struct audsettings *as)
{
int bits = 8, mul;
bool is_signed = false, is_float = false;
switch (as->fmt) {
case AUDIO_FORMAT_S8:
is_signed = true;
- /* fall through */
+ fallthrough;
case AUDIO_FORMAT_U8:
mul = 1;
break;
case AUDIO_FORMAT_S16:
is_signed = true;
- /* fall through */
+ fallthrough;
case AUDIO_FORMAT_U16:
bits = 16;
mul = 2;
break;
case AUDIO_FORMAT_F32:
is_float = true;
- /* fall through */
+ fallthrough;
case AUDIO_FORMAT_S32:
is_signed = true;
- /* fall through */
+ fallthrough;
case AUDIO_FORMAT_U32:
bits = 32;
mul = 4;
break;
default:
abort();
}
info->freq = as->freq;
info->bits = bits;
info->is_signed = is_signed;
info->is_float = is_float;
info->nchannels = as->nchannels;
info->bytes_per_frame = as->nchannels * mul;
info->bytes_per_second = info->freq * info->bytes_per_frame;
info->swap_endianness = (as->endianness != AUDIO_HOST_ENDIANNESS);
}
diff --git a/audio/jackaudio.c b/audio/jackaudio.c
index 974a3caad3..fc602411cd 100644
--- a/audio/jackaudio.c
+++ b/audio/jackaudio.c
@@ -574,22 +574,22 @@ static int qjack_init_in(HWVoiceIn *hw, struct audsettings *as,
static void qjack_client_fini_locked(QJackClient *c)
{
switch (c->state) {
case QJACK_STATE_RUNNING:
jack_deactivate(c->client);
- /* fallthrough */
+ fallthrough;
case QJACK_STATE_SHUTDOWN:
jack_client_close(c->client);
c->client = NULL;
qjack_buffer_free(&c->fifo);
g_free(c->port);
g_free(c->process_buffers);
c->state = QJACK_STATE_DISCONNECTED;
- /* fallthrough */
+ fallthrough;
case QJACK_STATE_DISCONNECTED:
break;
}
}
diff --git a/audio/pwaudio.c b/audio/pwaudio.c
index bf26fadb06..89b31617a6 100644
--- a/audio/pwaudio.c
+++ b/audio/pwaudio.c
@@ -487,31 +487,31 @@ static void
qpw_set_position(uint32_t channels, uint32_t position[SPA_AUDIO_MAX_CHANNELS])
{
memcpy(position, (uint32_t[SPA_AUDIO_MAX_CHANNELS]) { SPA_AUDIO_CHANNEL_UNKNOWN, },
sizeof(uint32_t) * SPA_AUDIO_MAX_CHANNELS);
/*
* TODO: This currently expects the only frontend supporting more than 2
* channels is the usb-audio. We will need some means to set channel
* order when a new frontend gains multi-channel support.
*/
switch (channels) {
case 8:
position[6] = SPA_AUDIO_CHANNEL_SL;
position[7] = SPA_AUDIO_CHANNEL_SR;
- /* fallthrough */
+ fallthrough;
case 6:
position[2] = SPA_AUDIO_CHANNEL_FC;
position[3] = SPA_AUDIO_CHANNEL_LFE;
position[4] = SPA_AUDIO_CHANNEL_RL;
position[5] = SPA_AUDIO_CHANNEL_RR;
- /* fallthrough */
+ fallthrough;
case 2:
position[0] = SPA_AUDIO_CHANNEL_FL;
position[1] = SPA_AUDIO_CHANNEL_FR;
break;
case 1:
position[0] = SPA_AUDIO_CHANNEL_MONO;
break;
default:
dolog("Internal error: unsupported channel count %d\n", channels);
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 17/78] ui/sdl2.c: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (15 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 16/78] audio: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 18/78] ui/win32-kbd-hook.c: " Emmanouil Pitsidianakis
` (61 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Gerd Hoffmann, Marc-André Lureau
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
ui/sdl2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ui/sdl2.c b/ui/sdl2.c
index fbfdb64e90..3d157a14aa 100644
--- a/ui/sdl2.c
+++ b/ui/sdl2.c
@@ -576,78 +576,78 @@ static void handle_mousewheel(SDL_Event *ev)
static void handle_windowevent(SDL_Event *ev)
{
struct sdl2_console *scon = get_scon_from_window(ev->window.windowID);
bool allow_close = true;
if (!scon) {
return;
}
switch (ev->window.event) {
case SDL_WINDOWEVENT_RESIZED:
{
QemuUIInfo info;
memset(&info, 0, sizeof(info));
info.width = ev->window.data1;
info.height = ev->window.data2;
dpy_set_ui_info(scon->dcl.con, &info, true);
}
sdl2_redraw(scon);
break;
case SDL_WINDOWEVENT_EXPOSED:
sdl2_redraw(scon);
break;
case SDL_WINDOWEVENT_FOCUS_GAINED:
win32_kbd_set_grab(gui_grab);
if (qemu_console_is_graphic(scon->dcl.con)) {
win32_kbd_set_window(sdl2_win32_get_hwnd(scon));
}
- /* fall through */
+ fallthrough;
case SDL_WINDOWEVENT_ENTER:
if (!gui_grab && (qemu_input_is_absolute(scon->dcl.con) || absolute_enabled)) {
absolute_mouse_grab(scon);
}
/* If a new console window opened using a hotkey receives the
* focus, SDL sends another KEYDOWN event to the new window,
* closing the console window immediately after.
*
* Work around this by ignoring further hotkey events until a
* key is released.
*/
scon->ignore_hotkeys = get_mod_state();
break;
case SDL_WINDOWEVENT_FOCUS_LOST:
if (qemu_console_is_graphic(scon->dcl.con)) {
win32_kbd_set_window(NULL);
}
if (gui_grab && !gui_fullscreen) {
sdl_grab_end(scon);
}
break;
case SDL_WINDOWEVENT_RESTORED:
update_displaychangelistener(&scon->dcl, GUI_REFRESH_INTERVAL_DEFAULT);
break;
case SDL_WINDOWEVENT_MINIMIZED:
update_displaychangelistener(&scon->dcl, 500);
break;
case SDL_WINDOWEVENT_CLOSE:
if (qemu_console_is_graphic(scon->dcl.con)) {
if (scon->opts->has_window_close && !scon->opts->window_close) {
allow_close = false;
}
if (allow_close) {
shutdown_action = SHUTDOWN_ACTION_POWEROFF;
qemu_system_shutdown_request(SHUTDOWN_CAUSE_HOST_UI);
}
} else {
SDL_HideWindow(scon->real_window);
scon->hidden = true;
}
break;
case SDL_WINDOWEVENT_SHOWN:
scon->hidden = false;
break;
case SDL_WINDOWEVENT_HIDDEN:
scon->hidden = true;
break;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 18/78] ui/win32-kbd-hook.c: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (16 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 17/78] ui/sdl2.c: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 19/78] target/hppa: " Emmanouil Pitsidianakis
` (60 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Gerd Hoffmann, Marc-André Lureau,
Stefan Weil
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
ui/win32-kbd-hook.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/ui/win32-kbd-hook.c b/ui/win32-kbd-hook.c
index 1ac237db9e..3c5c3fc597 100644
--- a/ui/win32-kbd-hook.c
+++ b/ui/win32-kbd-hook.c
@@ -18,59 +18,52 @@ static DWORD win32_grab;
static LRESULT CALLBACK keyboard_hook_cb(int code, WPARAM wparam, LPARAM lparam)
{
if (win32_window && code == HC_ACTION && win32_window == GetFocus()) {
KBDLLHOOKSTRUCT *hooked = (KBDLLHOOKSTRUCT *)lparam;
if (wparam != WM_KEYUP) {
DWORD dwmsg = (hooked->flags << 24) |
((hooked->scanCode & 0xff) << 16) | 1;
switch (hooked->vkCode) {
case VK_CAPITAL:
- /* fall through */
case VK_SCROLL:
- /* fall through */
case VK_NUMLOCK:
- /* fall through */
case VK_LSHIFT:
- /* fall through */
case VK_RSHIFT:
- /* fall through */
case VK_RCONTROL:
- /* fall through */
case VK_LMENU:
- /* fall through */
case VK_RMENU:
break;
case VK_LCONTROL:
/*
* When pressing AltGr, an extra VK_LCONTROL with a special
* scancode with bit 9 set is sent. Let's ignore the extra
* VK_LCONTROL, as that will make AltGr misbehave.
*/
if (hooked->scanCode & 0x200) {
return 1;
}
break;
default:
if (win32_grab) {
SendMessage(win32_window, wparam, hooked->vkCode, dwmsg);
return 1;
}
break;
}
} else {
switch (hooked->vkCode) {
case VK_LCONTROL:
if (hooked->scanCode & 0x200) {
return 1;
}
break;
}
}
}
return CallNextHookEx(NULL, code, wparam, lparam);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 19/78] target/hppa: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (17 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 18/78] ui/win32-kbd-hook.c: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 20/78] target/mips: " Emmanouil Pitsidianakis
` (59 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Richard Henderson
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
target/hppa/translate.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 9f3ba9f42f..1df81b0fa2 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -480,14 +480,14 @@ static DisasCond cond_make(TCGCond c, TCGv_reg a0, TCGv_reg a1)
static void cond_free(DisasCond *cond)
{
switch (cond->c) {
default:
cond->a0 = NULL;
cond->a1 = NULL;
- /* fallthru */
+ fallthrough;
case TCG_COND_ALWAYS:
cond->c = TCG_COND_NEVER;
break;
case TCG_COND_NEVER:
break;
}
}
@@ -3831,65 +3831,65 @@ static bool trans_fcmp_d(DisasContext *ctx, arg_fclass2 *a)
static bool trans_ftest(DisasContext *ctx, arg_ftest *a)
{
TCGv_reg t;
nullify_over(ctx);
t = get_temp(ctx);
tcg_gen_ld32u_reg(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow));
if (a->y == 1) {
int mask;
bool inv = false;
switch (a->c) {
case 0: /* simple */
tcg_gen_andi_reg(t, t, 0x4000000);
ctx->null_cond = cond_make_0(TCG_COND_NE, t);
goto done;
case 2: /* rej */
inv = true;
- /* fallthru */
+ fallthrough;
case 1: /* acc */
mask = 0x43ff800;
break;
case 6: /* rej8 */
inv = true;
- /* fallthru */
+ fallthrough;
case 5: /* acc8 */
mask = 0x43f8000;
break;
case 9: /* acc6 */
mask = 0x43e0000;
break;
case 13: /* acc4 */
mask = 0x4380000;
break;
case 17: /* acc2 */
mask = 0x4200000;
break;
default:
gen_illegal(ctx);
return true;
}
if (inv) {
TCGv_reg c = load_const(ctx, mask);
tcg_gen_or_reg(t, t, c);
ctx->null_cond = cond_make(TCG_COND_EQ, t, c);
} else {
tcg_gen_andi_reg(t, t, mask);
ctx->null_cond = cond_make_0(TCG_COND_EQ, t);
}
} else {
unsigned cbit = (a->y ^ 1) - 1;
tcg_gen_extract_reg(t, t, 21 - cbit, 1);
ctx->null_cond = cond_make_0(TCG_COND_NE, t);
}
done:
return nullify_end(ctx);
}
/*
* Float class 2
*/
@@ -4219,28 +4219,28 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
DisasJumpType is_jmp = ctx->base.is_jmp;
switch (is_jmp) {
case DISAS_NORETURN:
break;
case DISAS_TOO_MANY:
case DISAS_IAQ_N_STALE:
case DISAS_IAQ_N_STALE_EXIT:
copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f);
copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b);
nullify_save(ctx);
- /* FALLTHRU */
+ fallthrough;
case DISAS_IAQ_N_UPDATED:
if (is_jmp != DISAS_IAQ_N_STALE_EXIT) {
tcg_gen_lookup_and_goto_ptr();
break;
}
- /* FALLTHRU */
+ fallthrough;
case DISAS_EXIT:
tcg_gen_exit_tb(NULL, 0);
break;
default:
g_assert_not_reached();
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 20/78] target/mips: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (18 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 19/78] target/hppa: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 21/78] target/sparc: " Emmanouil Pitsidianakis
` (58 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Huacai Chen, Philippe Mathieu-Daudé,
Aurelien Jarno, Jiaxun Yang, Aleksandar Rikalo
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
target/mips/sysemu/physaddr.c | 2 +-
target/mips/tcg/micromips_translate.c.inc | 4 +-
target/mips/tcg/mips16e_translate.c.inc | 30 ++++-----
target/mips/tcg/mxu_translate.c | 8 +--
target/mips/tcg/nanomips_translate.c.inc | 4 +-
target/mips/tcg/op_helper.c | 2 +-
target/mips/tcg/translate.c | 79 ++++++++++++-----------
7 files changed, 66 insertions(+), 63 deletions(-)
diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c
index 05990aa5bb..ebcaeea1bc 100644
--- a/target/mips/sysemu/physaddr.c
+++ b/target/mips/sysemu/physaddr.c
@@ -24,52 +24,52 @@
static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
{
/*
* Interpret access control mode and mmu_idx.
* AdE? TLB?
* AM K S U E K S U E
* UK 0 0 1 1 0 0 - - 0
* MK 1 0 1 1 0 1 - - !eu
* MSK 2 0 0 1 0 1 1 - !eu
* MUSK 3 0 0 0 0 1 1 1 !eu
* MUSUK 4 0 0 0 0 0 1 1 0
* USK 5 0 0 1 0 0 0 - 0
* - 6 - - - - - - - -
* UUSK 7 0 0 0 0 0 0 0 0
*/
int32_t adetlb_mask;
switch (mmu_idx) {
case 3: /* ERL */
/* If EU is set, always unmapped */
if (eu) {
return 0;
}
- /* fall through */
+ fallthrough;
case MIPS_HFLAG_KM:
/* Never AdE, TLB mapped if AM={1,2,3} */
adetlb_mask = 0x70000000;
goto check_tlb;
case MIPS_HFLAG_SM:
/* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */
adetlb_mask = 0xc0380000;
goto check_ade;
case MIPS_HFLAG_UM:
/* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */
adetlb_mask = 0xe4180000;
/* fall through */
check_ade:
/* does this AM cause AdE in current execution mode */
if ((adetlb_mask << am) < 0) {
return TLBRET_BADADDR;
}
adetlb_mask <<= 8;
/* fall through */
check_tlb:
/* is this AM mapped in current execution mode */
return ((adetlb_mask << am) < 0);
default:
g_assert_not_reached();
};
}
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index 7510831701..00e96ce27a 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -1621,1353 +1621,1353 @@ static void gen_pool32fxf(DisasContext *ctx, int rt, int rs)
static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
{
int32_t offset;
uint16_t insn;
int rt, rs, rd, rr;
int16_t imm;
uint32_t op, minor, minor2, mips32_op;
uint32_t cond, fmt, cc;
insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
ctx->opcode = (ctx->opcode << 16) | insn;
rt = (ctx->opcode >> 21) & 0x1f;
rs = (ctx->opcode >> 16) & 0x1f;
rd = (ctx->opcode >> 11) & 0x1f;
rr = (ctx->opcode >> 6) & 0x1f;
imm = (int16_t) ctx->opcode;
op = (ctx->opcode >> 26) & 0x3f;
switch (op) {
case POOL32A:
minor = ctx->opcode & 0x3f;
switch (minor) {
case 0x00:
minor = (ctx->opcode >> 6) & 0xf;
switch (minor) {
case SLL32:
mips32_op = OPC_SLL;
goto do_shifti;
case SRA:
mips32_op = OPC_SRA;
goto do_shifti;
case SRL32:
mips32_op = OPC_SRL;
goto do_shifti;
case ROTR:
mips32_op = OPC_ROTR;
do_shifti:
gen_shift_imm(ctx, mips32_op, rt, rs, rd);
break;
case SELEQZ:
check_insn(ctx, ISA_MIPS_R6);
gen_cond_move(ctx, OPC_SELEQZ, rd, rs, rt);
break;
case SELNEZ:
check_insn(ctx, ISA_MIPS_R6);
gen_cond_move(ctx, OPC_SELNEZ, rd, rs, rt);
break;
case R6_RDHWR:
check_insn(ctx, ISA_MIPS_R6);
gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3));
break;
default:
goto pool32a_invalid;
}
break;
case 0x10:
minor = (ctx->opcode >> 6) & 0xf;
switch (minor) {
/* Arithmetic */
case ADD:
mips32_op = OPC_ADD;
goto do_arith;
case ADDU32:
mips32_op = OPC_ADDU;
goto do_arith;
case SUB:
mips32_op = OPC_SUB;
goto do_arith;
case SUBU32:
mips32_op = OPC_SUBU;
goto do_arith;
case MUL:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MUL;
do_arith:
gen_arith(ctx, mips32_op, rd, rs, rt);
break;
/* Shifts */
case SLLV:
mips32_op = OPC_SLLV;
goto do_shift;
case SRLV:
mips32_op = OPC_SRLV;
goto do_shift;
case SRAV:
mips32_op = OPC_SRAV;
goto do_shift;
case ROTRV:
mips32_op = OPC_ROTRV;
do_shift:
gen_shift(ctx, mips32_op, rd, rs, rt);
break;
/* Logical operations */
case AND:
mips32_op = OPC_AND;
goto do_logic;
case OR32:
mips32_op = OPC_OR;
goto do_logic;
case NOR:
mips32_op = OPC_NOR;
goto do_logic;
case XOR32:
mips32_op = OPC_XOR;
do_logic:
gen_logic(ctx, mips32_op, rd, rs, rt);
break;
/* Set less than */
case SLT:
mips32_op = OPC_SLT;
goto do_slt;
case SLTU:
mips32_op = OPC_SLTU;
do_slt:
gen_slt(ctx, mips32_op, rd, rs, rt);
break;
default:
goto pool32a_invalid;
}
break;
case 0x18:
minor = (ctx->opcode >> 6) & 0xf;
switch (minor) {
/* Conditional moves */
case MOVN: /* MUL */
if (ctx->insn_flags & ISA_MIPS_R6) {
/* MUL */
gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt);
} else {
/* MOVN */
gen_cond_move(ctx, OPC_MOVN, rd, rs, rt);
}
break;
case MOVZ: /* MUH */
if (ctx->insn_flags & ISA_MIPS_R6) {
/* MUH */
gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt);
} else {
/* MOVZ */
gen_cond_move(ctx, OPC_MOVZ, rd, rs, rt);
}
break;
case MULU:
check_insn(ctx, ISA_MIPS_R6);
gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt);
break;
case MUHU:
check_insn(ctx, ISA_MIPS_R6);
gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt);
break;
case LWXS: /* DIV */
if (ctx->insn_flags & ISA_MIPS_R6) {
/* DIV */
gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt);
} else {
/* LWXS */
gen_ldxs(ctx, rs, rt, rd);
}
break;
case MOD:
check_insn(ctx, ISA_MIPS_R6);
gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt);
break;
case R6_DIVU:
check_insn(ctx, ISA_MIPS_R6);
gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt);
break;
case MODU:
check_insn(ctx, ISA_MIPS_R6);
gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt);
break;
default:
goto pool32a_invalid;
}
break;
case INS:
gen_bitops(ctx, OPC_INS, rt, rs, rr, rd);
return;
case LSA:
check_insn(ctx, ISA_MIPS_R6);
gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2));
break;
case ALIGN:
check_insn(ctx, ISA_MIPS_R6);
gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2));
break;
case EXT:
gen_bitops(ctx, OPC_EXT, rt, rs, rr, rd);
return;
case POOL32AXF:
gen_pool32axf(env, ctx, rt, rs);
break;
case BREAK32:
generate_exception_break(ctx, extract32(ctx->opcode, 6, 20));
break;
case SIGRIE:
check_insn(ctx, ISA_MIPS_R6);
gen_reserved_instruction(ctx);
break;
default:
pool32a_invalid:
MIPS_INVAL("pool32a");
gen_reserved_instruction(ctx);
break;
}
break;
case POOL32B:
minor = (ctx->opcode >> 12) & 0xf;
switch (minor) {
case CACHE:
check_cp0_enabled(ctx);
if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
gen_cache_operation(ctx, rt, rs, imm);
}
break;
case LWC2:
case SWC2:
/* COP2: Not implemented. */
generate_exception_err(ctx, EXCP_CpU, 2);
break;
#ifdef TARGET_MIPS64
case LDP:
case SDP:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
#endif
- /* fall through */
+ fallthrough;
case LWP:
case SWP:
gen_ldst_pair(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
break;
#ifdef TARGET_MIPS64
case LDM:
case SDM:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
#endif
- /* fall through */
+ fallthrough;
case LWM32:
case SWM32:
gen_ldst_multiple(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
break;
default:
MIPS_INVAL("pool32b");
gen_reserved_instruction(ctx);
break;
}
break;
case POOL32F:
if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
minor = ctx->opcode & 0x3f;
check_cp1_enabled(ctx);
switch (minor) {
case ALNV_PS:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_ALNV_PS;
goto do_madd;
case MADD_S:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MADD_S;
goto do_madd;
case MADD_D:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MADD_D;
goto do_madd;
case MADD_PS:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MADD_PS;
goto do_madd;
case MSUB_S:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MSUB_S;
goto do_madd;
case MSUB_D:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MSUB_D;
goto do_madd;
case MSUB_PS:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MSUB_PS;
goto do_madd;
case NMADD_S:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_NMADD_S;
goto do_madd;
case NMADD_D:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_NMADD_D;
goto do_madd;
case NMADD_PS:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_NMADD_PS;
goto do_madd;
case NMSUB_S:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_NMSUB_S;
goto do_madd;
case NMSUB_D:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_NMSUB_D;
goto do_madd;
case NMSUB_PS:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_NMSUB_PS;
do_madd:
gen_flt3_arith(ctx, mips32_op, rd, rr, rs, rt);
break;
case CABS_COND_FMT:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
cond = (ctx->opcode >> 6) & 0xf;
cc = (ctx->opcode >> 13) & 0x7;
fmt = (ctx->opcode >> 10) & 0x3;
switch (fmt) {
case 0x0:
gen_cmpabs_s(ctx, cond, rt, rs, cc);
break;
case 0x1:
gen_cmpabs_d(ctx, cond, rt, rs, cc);
break;
case 0x2:
gen_cmpabs_ps(ctx, cond, rt, rs, cc);
break;
default:
goto pool32f_invalid;
}
break;
case C_COND_FMT:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
cond = (ctx->opcode >> 6) & 0xf;
cc = (ctx->opcode >> 13) & 0x7;
fmt = (ctx->opcode >> 10) & 0x3;
switch (fmt) {
case 0x0:
gen_cmp_s(ctx, cond, rt, rs, cc);
break;
case 0x1:
gen_cmp_d(ctx, cond, rt, rs, cc);
break;
case 0x2:
gen_cmp_ps(ctx, cond, rt, rs, cc);
break;
default:
goto pool32f_invalid;
}
break;
case CMP_CONDN_S:
check_insn(ctx, ISA_MIPS_R6);
gen_r6_cmp_s(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd);
break;
case CMP_CONDN_D:
check_insn(ctx, ISA_MIPS_R6);
gen_r6_cmp_d(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd);
break;
case POOL32FXF:
gen_pool32fxf(ctx, rt, rs);
break;
case 0x00:
/* PLL foo */
switch ((ctx->opcode >> 6) & 0x7) {
case PLL_PS:
mips32_op = OPC_PLL_PS;
goto do_ps;
case PLU_PS:
mips32_op = OPC_PLU_PS;
goto do_ps;
case PUL_PS:
mips32_op = OPC_PUL_PS;
goto do_ps;
case PUU_PS:
mips32_op = OPC_PUU_PS;
goto do_ps;
case CVT_PS_S:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_CVT_PS_S;
do_ps:
gen_farith(ctx, mips32_op, rt, rs, rd, 0);
break;
default:
goto pool32f_invalid;
}
break;
case MIN_FMT:
check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0);
break;
case FMT_SDPS_D:
gen_farith(ctx, OPC_MIN_D, rt, rs, rd, 0);
break;
default:
goto pool32f_invalid;
}
break;
case 0x08:
/* [LS][WDU]XC1 */
switch ((ctx->opcode >> 6) & 0x7) {
case LWXC1:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LWXC1;
goto do_ldst_cp1;
case SWXC1:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SWXC1;
goto do_ldst_cp1;
case LDXC1:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LDXC1;
goto do_ldst_cp1;
case SDXC1:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SDXC1;
goto do_ldst_cp1;
case LUXC1:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LUXC1;
goto do_ldst_cp1;
case SUXC1:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SUXC1;
do_ldst_cp1:
gen_flt3_ldst(ctx, mips32_op, rd, rd, rt, rs);
break;
default:
goto pool32f_invalid;
}
break;
case MAX_FMT:
check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0);
break;
case FMT_SDPS_D:
gen_farith(ctx, OPC_MAX_D, rt, rs, rd, 0);
break;
default:
goto pool32f_invalid;
}
break;
case 0x18:
/* 3D insns */
check_insn_opc_removed(ctx, ISA_MIPS_R6);
fmt = (ctx->opcode >> 9) & 0x3;
switch ((ctx->opcode >> 6) & 0x7) {
case RSQRT2_FMT:
switch (fmt) {
case FMT_SDPS_S:
mips32_op = OPC_RSQRT2_S;
goto do_3d;
case FMT_SDPS_D:
mips32_op = OPC_RSQRT2_D;
goto do_3d;
case FMT_SDPS_PS:
mips32_op = OPC_RSQRT2_PS;
goto do_3d;
default:
goto pool32f_invalid;
}
break;
case RECIP2_FMT:
switch (fmt) {
case FMT_SDPS_S:
mips32_op = OPC_RECIP2_S;
goto do_3d;
case FMT_SDPS_D:
mips32_op = OPC_RECIP2_D;
goto do_3d;
case FMT_SDPS_PS:
mips32_op = OPC_RECIP2_PS;
goto do_3d;
default:
goto pool32f_invalid;
}
break;
case ADDR_PS:
mips32_op = OPC_ADDR_PS;
goto do_3d;
case MULR_PS:
mips32_op = OPC_MULR_PS;
do_3d:
gen_farith(ctx, mips32_op, rt, rs, rd, 0);
break;
default:
goto pool32f_invalid;
}
break;
case 0x20:
/* MOV[FT].fmt, PREFX, RINT.fmt, CLASS.fmt*/
cc = (ctx->opcode >> 13) & 0x7;
fmt = (ctx->opcode >> 9) & 0x3;
switch ((ctx->opcode >> 6) & 0x7) {
case MOVF_FMT: /* RINT_FMT */
if (ctx->insn_flags & ISA_MIPS_R6) {
/* RINT_FMT */
switch (fmt) {
case FMT_SDPS_S:
gen_farith(ctx, OPC_RINT_S, 0, rt, rs, 0);
break;
case FMT_SDPS_D:
gen_farith(ctx, OPC_RINT_D, 0, rt, rs, 0);
break;
default:
goto pool32f_invalid;
}
} else {
/* MOVF_FMT */
switch (fmt) {
case FMT_SDPS_S:
gen_movcf_s(ctx, rs, rt, cc, 0);
break;
case FMT_SDPS_D:
gen_movcf_d(ctx, rs, rt, cc, 0);
break;
case FMT_SDPS_PS:
check_ps(ctx);
gen_movcf_ps(ctx, rs, rt, cc, 0);
break;
default:
goto pool32f_invalid;
}
}
break;
case MOVT_FMT: /* CLASS_FMT */
if (ctx->insn_flags & ISA_MIPS_R6) {
/* CLASS_FMT */
switch (fmt) {
case FMT_SDPS_S:
gen_farith(ctx, OPC_CLASS_S, 0, rt, rs, 0);
break;
case FMT_SDPS_D:
gen_farith(ctx, OPC_CLASS_D, 0, rt, rs, 0);
break;
default:
goto pool32f_invalid;
}
} else {
/* MOVT_FMT */
switch (fmt) {
case FMT_SDPS_S:
gen_movcf_s(ctx, rs, rt, cc, 1);
break;
case FMT_SDPS_D:
gen_movcf_d(ctx, rs, rt, cc, 1);
break;
case FMT_SDPS_PS:
check_ps(ctx);
gen_movcf_ps(ctx, rs, rt, cc, 1);
break;
default:
goto pool32f_invalid;
}
}
break;
case PREFX:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
break;
default:
goto pool32f_invalid;
}
break;
#define FINSN_3ARG_SDPS(prfx) \
switch ((ctx->opcode >> 8) & 0x3) { \
case FMT_SDPS_S: \
mips32_op = OPC_##prfx##_S; \
goto do_fpop; \
case FMT_SDPS_D: \
mips32_op = OPC_##prfx##_D; \
goto do_fpop; \
case FMT_SDPS_PS: \
check_ps(ctx); \
mips32_op = OPC_##prfx##_PS; \
goto do_fpop; \
default: \
goto pool32f_invalid; \
}
case MINA_FMT:
check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0);
break;
case FMT_SDPS_D:
gen_farith(ctx, OPC_MINA_D, rt, rs, rd, 0);
break;
default:
goto pool32f_invalid;
}
break;
case MAXA_FMT:
check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0);
break;
case FMT_SDPS_D:
gen_farith(ctx, OPC_MAXA_D, rt, rs, rd, 0);
break;
default:
goto pool32f_invalid;
}
break;
case 0x30:
/* regular FP ops */
switch ((ctx->opcode >> 6) & 0x3) {
case ADD_FMT:
FINSN_3ARG_SDPS(ADD);
break;
case SUB_FMT:
FINSN_3ARG_SDPS(SUB);
break;
case MUL_FMT:
FINSN_3ARG_SDPS(MUL);
break;
case DIV_FMT:
fmt = (ctx->opcode >> 8) & 0x3;
if (fmt == 1) {
mips32_op = OPC_DIV_D;
} else if (fmt == 0) {
mips32_op = OPC_DIV_S;
} else {
goto pool32f_invalid;
}
goto do_fpop;
default:
goto pool32f_invalid;
}
break;
case 0x38:
/* cmovs */
switch ((ctx->opcode >> 6) & 0x7) {
case MOVN_FMT: /* SELEQZ_FMT */
if (ctx->insn_flags & ISA_MIPS_R6) {
/* SELEQZ_FMT */
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs);
break;
case FMT_SDPS_D:
gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs);
break;
default:
goto pool32f_invalid;
}
} else {
/* MOVN_FMT */
FINSN_3ARG_SDPS(MOVN);
}
break;
case MOVN_FMT_04:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
FINSN_3ARG_SDPS(MOVN);
break;
case MOVZ_FMT: /* SELNEZ_FMT */
if (ctx->insn_flags & ISA_MIPS_R6) {
/* SELNEZ_FMT */
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs);
break;
case FMT_SDPS_D:
gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs);
break;
default:
goto pool32f_invalid;
}
} else {
/* MOVZ_FMT */
FINSN_3ARG_SDPS(MOVZ);
}
break;
case MOVZ_FMT_05:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
FINSN_3ARG_SDPS(MOVZ);
break;
case SEL_FMT:
check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs);
break;
case FMT_SDPS_D:
gen_sel_d(ctx, OPC_SEL_D, rd, rt, rs);
break;
default:
goto pool32f_invalid;
}
break;
case MADDF_FMT:
check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
mips32_op = OPC_MADDF_S;
goto do_fpop;
case FMT_SDPS_D:
mips32_op = OPC_MADDF_D;
goto do_fpop;
default:
goto pool32f_invalid;
}
break;
case MSUBF_FMT:
check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
mips32_op = OPC_MSUBF_S;
goto do_fpop;
case FMT_SDPS_D:
mips32_op = OPC_MSUBF_D;
goto do_fpop;
default:
goto pool32f_invalid;
}
break;
default:
goto pool32f_invalid;
}
break;
do_fpop:
gen_farith(ctx, mips32_op, rt, rs, rd, 0);
break;
default:
pool32f_invalid:
MIPS_INVAL("pool32f");
gen_reserved_instruction(ctx);
break;
}
} else {
generate_exception_err(ctx, EXCP_CpU, 1);
}
break;
case POOL32I:
minor = (ctx->opcode >> 21) & 0x1f;
switch (minor) {
case BLTZ:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BLTZ, 4, rs, -1, imm << 1, 4);
break;
case BLTZAL:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 4);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break;
case BLTZALS:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 2);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break;
case BGEZ:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BGEZ, 4, rs, -1, imm << 1, 4);
break;
case BGEZAL:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 4);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break;
case BGEZALS:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 2);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break;
case BLEZ:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BLEZ, 4, rs, -1, imm << 1, 4);
break;
case BGTZ:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BGTZ, 4, rs, -1, imm << 1, 4);
break;
/* Traps */
case TLTI: /* BC1EQZC */
if (ctx->insn_flags & ISA_MIPS_R6) {
/* BC1EQZC */
check_cp1_enabled(ctx);
gen_compute_branch1_r6(ctx, OPC_BC1EQZ, rs, imm << 1, 0);
} else {
/* TLTI */
mips32_op = OPC_TLTI;
goto do_trapi;
}
break;
case TGEI: /* BC1NEZC */
if (ctx->insn_flags & ISA_MIPS_R6) {
/* BC1NEZC */
check_cp1_enabled(ctx);
gen_compute_branch1_r6(ctx, OPC_BC1NEZ, rs, imm << 1, 0);
} else {
/* TGEI */
mips32_op = OPC_TGEI;
goto do_trapi;
}
break;
case TLTIU:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_TLTIU;
goto do_trapi;
case TGEIU:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_TGEIU;
goto do_trapi;
case TNEI: /* SYNCI */
if (ctx->insn_flags & ISA_MIPS_R6) {
/* SYNCI */
/*
* Break the TB to be able to sync copied instructions
* immediately.
*/
ctx->base.is_jmp = DISAS_STOP;
} else {
/* TNEI */
mips32_op = OPC_TNEI;
goto do_trapi;
}
break;
case TEQI:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_TEQI;
do_trapi:
gen_trap(ctx, mips32_op, rs, -1, imm, 0);
break;
case BNEZC:
case BEQZC:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, minor == BNEZC ? OPC_BNE : OPC_BEQ,
4, rs, 0, imm << 1, 0);
/*
* Compact branches don't have a delay slot, so just let
* the normal delay slot handling take us to the branch
* target.
*/
break;
case LUI:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_logic_imm(ctx, OPC_LUI, rs, 0, imm);
break;
case SYNCI:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
/*
* Break the TB to be able to sync copied instructions
* immediately.
*/
ctx->base.is_jmp = DISAS_STOP;
break;
case BC2F:
case BC2T:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* COP2: Not implemented. */
generate_exception_err(ctx, EXCP_CpU, 2);
break;
case BC1F:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1FANY2 : OPC_BC1F;
goto do_cp1branch;
case BC1T:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1TANY2 : OPC_BC1T;
goto do_cp1branch;
case BC1ANY4F:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_BC1FANY4;
goto do_cp1mips3d;
case BC1ANY4T:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_BC1TANY4;
do_cp1mips3d:
check_cop1x(ctx);
check_insn(ctx, ASE_MIPS3D);
/* Fall through */
do_cp1branch:
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
gen_compute_branch1(ctx, mips32_op,
(ctx->opcode >> 18) & 0x7, imm << 1);
} else {
generate_exception_err(ctx, EXCP_CpU, 1);
}
break;
default:
MIPS_INVAL("pool32i");
gen_reserved_instruction(ctx);
break;
}
break;
case POOL32C:
minor = (ctx->opcode >> 12) & 0xf;
offset = sextract32(ctx->opcode, 0,
(ctx->insn_flags & ISA_MIPS_R6) ? 9 : 12);
switch (minor) {
case LWL:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LWL;
goto do_ld_lr;
case SWL:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SWL;
goto do_st_lr;
case LWR:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LWR;
goto do_ld_lr;
case SWR:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SWR;
goto do_st_lr;
#if defined(TARGET_MIPS64)
case LDL:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LDL;
goto do_ld_lr;
case SDL:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SDL;
goto do_st_lr;
case LDR:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LDR;
goto do_ld_lr;
case SDR:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SDR;
goto do_st_lr;
case LWU:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
mips32_op = OPC_LWU;
goto do_ld_lr;
case LLD:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
mips32_op = OPC_LLD;
goto do_ld_lr;
#endif
case LL:
mips32_op = OPC_LL;
goto do_ld_lr;
do_ld_lr:
gen_ld(ctx, mips32_op, rt, rs, offset);
break;
do_st_lr:
gen_st(ctx, mips32_op, rt, rs, offset);
break;
case SC:
gen_st_cond(ctx, rt, rs, offset, MO_TESL, false);
break;
#if defined(TARGET_MIPS64)
case SCD:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_st_cond(ctx, rt, rs, offset, MO_TEUQ, false);
break;
#endif
case LD_EVA:
if (!ctx->eva) {
MIPS_INVAL("pool32c ld-eva");
gen_reserved_instruction(ctx);
break;
}
check_cp0_enabled(ctx);
minor2 = (ctx->opcode >> 9) & 0x7;
offset = sextract32(ctx->opcode, 0, 9);
switch (minor2) {
case LBUE:
mips32_op = OPC_LBUE;
goto do_ld_lr;
case LHUE:
mips32_op = OPC_LHUE;
goto do_ld_lr;
case LWLE:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LWLE;
goto do_ld_lr;
case LWRE:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LWRE;
goto do_ld_lr;
case LBE:
mips32_op = OPC_LBE;
goto do_ld_lr;
case LHE:
mips32_op = OPC_LHE;
goto do_ld_lr;
case LLE:
mips32_op = OPC_LLE;
goto do_ld_lr;
case LWE:
mips32_op = OPC_LWE;
goto do_ld_lr;
};
break;
case ST_EVA:
if (!ctx->eva) {
MIPS_INVAL("pool32c st-eva");
gen_reserved_instruction(ctx);
break;
}
check_cp0_enabled(ctx);
minor2 = (ctx->opcode >> 9) & 0x7;
offset = sextract32(ctx->opcode, 0, 9);
switch (minor2) {
case SWLE:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SWLE;
goto do_st_lr;
case SWRE:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SWRE;
goto do_st_lr;
case PREFE:
/* Treat as no-op */
if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >= 24)) {
/* hint codes 24-31 are reserved and signal RI */
generate_exception(ctx, EXCP_RI);
}
break;
case CACHEE:
/* Treat as no-op */
if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
gen_cache_operation(ctx, rt, rs, offset);
}
break;
case SBE:
mips32_op = OPC_SBE;
goto do_st_lr;
case SHE:
mips32_op = OPC_SHE;
goto do_st_lr;
case SCE:
gen_st_cond(ctx, rt, rs, offset, MO_TESL, true);
break;
case SWE:
mips32_op = OPC_SWE;
goto do_st_lr;
};
break;
case PREF:
/* Treat as no-op */
if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >= 24)) {
/* hint codes 24-31 are reserved and signal RI */
generate_exception(ctx, EXCP_RI);
}
break;
default:
MIPS_INVAL("pool32c");
gen_reserved_instruction(ctx);
break;
}
break;
case ADDI32: /* AUI, LUI */
if (ctx->insn_flags & ISA_MIPS_R6) {
/* AUI, LUI */
gen_logic_imm(ctx, OPC_LUI, rt, rs, imm);
} else {
/* ADDI32 */
mips32_op = OPC_ADDI;
goto do_addi;
}
break;
case ADDIU32:
mips32_op = OPC_ADDIU;
do_addi:
gen_arith_imm(ctx, mips32_op, rt, rs, imm);
break;
/* Logical operations */
case ORI32:
mips32_op = OPC_ORI;
goto do_logici;
case XORI32:
mips32_op = OPC_XORI;
goto do_logici;
case ANDI32:
mips32_op = OPC_ANDI;
do_logici:
gen_logic_imm(ctx, mips32_op, rt, rs, imm);
break;
/* Set less than immediate */
case SLTI32:
mips32_op = OPC_SLTI;
goto do_slti;
case SLTIU32:
mips32_op = OPC_SLTIU;
do_slti:
gen_slt_imm(ctx, mips32_op, rt, rs, imm);
break;
case JALX32:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
gen_compute_branch(ctx, OPC_JALX, 4, rt, rs, offset, 4);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break;
case JALS32: /* BOVC, BEQC, BEQZALC */
if (ctx->insn_flags & ISA_MIPS_R6) {
if (rs >= rt) {
/* BOVC */
mips32_op = OPC_BOVC;
} else if (rs < rt && rs == 0) {
/* BEQZALC */
mips32_op = OPC_BEQZALC;
} else {
/* BEQC */
mips32_op = OPC_BEQC;
}
gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
} else {
/* JALS32 */
offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 1;
gen_compute_branch(ctx, OPC_JAL, 4, rt, rs, offset, 2);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
}
break;
case BEQ32: /* BC */
if (ctx->insn_flags & ISA_MIPS_R6) {
/* BC */
gen_compute_compact_branch(ctx, OPC_BC, 0, 0,
sextract32(ctx->opcode << 1, 0, 27));
} else {
/* BEQ32 */
gen_compute_branch(ctx, OPC_BEQ, 4, rt, rs, imm << 1, 4);
}
break;
case BNE32: /* BALC */
if (ctx->insn_flags & ISA_MIPS_R6) {
/* BALC */
gen_compute_compact_branch(ctx, OPC_BALC, 0, 0,
sextract32(ctx->opcode << 1, 0, 27));
} else {
/* BNE32 */
gen_compute_branch(ctx, OPC_BNE, 4, rt, rs, imm << 1, 4);
}
break;
case J32: /* BGTZC, BLTZC, BLTC */
if (ctx->insn_flags & ISA_MIPS_R6) {
if (rs == 0 && rt != 0) {
/* BGTZC */
mips32_op = OPC_BGTZC;
} else if (rs != 0 && rt != 0 && rs == rt) {
/* BLTZC */
mips32_op = OPC_BLTZC;
} else {
/* BLTC */
mips32_op = OPC_BLTC;
}
gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
} else {
/* J32 */
gen_compute_branch(ctx, OPC_J, 4, rt, rs,
(int32_t)(ctx->opcode & 0x3FFFFFF) << 1, 4);
}
break;
case JAL32: /* BLEZC, BGEZC, BGEC */
if (ctx->insn_flags & ISA_MIPS_R6) {
if (rs == 0 && rt != 0) {
/* BLEZC */
mips32_op = OPC_BLEZC;
} else if (rs != 0 && rt != 0 && rs == rt) {
/* BGEZC */
mips32_op = OPC_BGEZC;
} else {
/* BGEC */
mips32_op = OPC_BGEC;
}
gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
} else {
/* JAL32 */
gen_compute_branch(ctx, OPC_JAL, 4, rt, rs,
(int32_t)(ctx->opcode & 0x3FFFFFF) << 1, 4);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
}
break;
/* Floating point (COP1) */
case LWC132:
mips32_op = OPC_LWC1;
goto do_cop1;
case LDC132:
mips32_op = OPC_LDC1;
goto do_cop1;
case SWC132:
mips32_op = OPC_SWC1;
goto do_cop1;
case SDC132:
mips32_op = OPC_SDC1;
do_cop1:
gen_cop1_ldst(ctx, mips32_op, rt, rs, imm);
break;
case ADDIUPC: /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
if (ctx->insn_flags & ISA_MIPS_R6) {
/* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
switch ((ctx->opcode >> 16) & 0x1f) {
case ADDIUPC_00:
case ADDIUPC_01:
case ADDIUPC_02:
case ADDIUPC_03:
case ADDIUPC_04:
case ADDIUPC_05:
case ADDIUPC_06:
case ADDIUPC_07:
gen_pcrel(ctx, OPC_ADDIUPC, ctx->base.pc_next & ~0x3, rt);
break;
case AUIPC:
gen_pcrel(ctx, OPC_AUIPC, ctx->base.pc_next, rt);
break;
case ALUIPC:
gen_pcrel(ctx, OPC_ALUIPC, ctx->base.pc_next, rt);
break;
case LWPC_08:
case LWPC_09:
case LWPC_0A:
case LWPC_0B:
case LWPC_0C:
case LWPC_0D:
case LWPC_0E:
case LWPC_0F:
gen_pcrel(ctx, R6_OPC_LWPC, ctx->base.pc_next & ~0x3, rt);
break;
default:
generate_exception(ctx, EXCP_RI);
break;
}
} else {
/* ADDIUPC */
int reg = mmreg(ZIMM(ctx->opcode, 23, 3));
offset = SIMM(ctx->opcode, 0, 23) << 2;
gen_addiupc(ctx, reg, offset, 0, 0);
}
break;
case BNVC: /* BNEC, BNEZALC */
check_insn(ctx, ISA_MIPS_R6);
if (rs >= rt) {
/* BNVC */
mips32_op = OPC_BNVC;
} else if (rs < rt && rs == 0) {
/* BNEZALC */
mips32_op = OPC_BNEZALC;
} else {
/* BNEC */
mips32_op = OPC_BNEC;
}
gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
break;
case R6_BNEZC: /* JIALC */
check_insn(ctx, ISA_MIPS_R6);
if (rt != 0) {
/* BNEZC */
gen_compute_compact_branch(ctx, OPC_BNEZC, rt, 0,
sextract32(ctx->opcode << 1, 0, 22));
} else {
/* JIALC */
gen_compute_compact_branch(ctx, OPC_JIALC, 0, rs, imm);
}
break;
case R6_BEQZC: /* JIC */
check_insn(ctx, ISA_MIPS_R6);
if (rt != 0) {
/* BEQZC */
gen_compute_compact_branch(ctx, OPC_BEQZC, rt, 0,
sextract32(ctx->opcode << 1, 0, 22));
} else {
/* JIC */
gen_compute_compact_branch(ctx, OPC_JIC, 0, rs, imm);
}
break;
case BLEZALC: /* BGEZALC, BGEUC */
check_insn(ctx, ISA_MIPS_R6);
if (rs == 0 && rt != 0) {
/* BLEZALC */
mips32_op = OPC_BLEZALC;
} else if (rs != 0 && rt != 0 && rs == rt) {
/* BGEZALC */
mips32_op = OPC_BGEZALC;
} else {
/* BGEUC */
mips32_op = OPC_BGEUC;
}
gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
break;
case BGTZALC: /* BLTZALC, BLTUC */
check_insn(ctx, ISA_MIPS_R6);
if (rs == 0 && rt != 0) {
/* BGTZALC */
mips32_op = OPC_BGTZALC;
} else if (rs != 0 && rt != 0 && rs == rt) {
/* BLTZALC */
mips32_op = OPC_BLTZALC;
} else {
/* BLTUC */
mips32_op = OPC_BLTUC;
}
gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
break;
/* Loads and stores */
case LB32:
mips32_op = OPC_LB;
goto do_ld;
case LBU32:
mips32_op = OPC_LBU;
goto do_ld;
case LH32:
mips32_op = OPC_LH;
goto do_ld;
case LHU32:
mips32_op = OPC_LHU;
goto do_ld;
case LW32:
mips32_op = OPC_LW;
goto do_ld;
#ifdef TARGET_MIPS64
case LD32:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
mips32_op = OPC_LD;
goto do_ld;
case SD32:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
mips32_op = OPC_SD;
goto do_st;
#endif
case SB32:
mips32_op = OPC_SB;
goto do_st;
case SH32:
mips32_op = OPC_SH;
goto do_st;
case SW32:
mips32_op = OPC_SW;
goto do_st;
do_ld:
gen_ld(ctx, mips32_op, rt, rs, imm);
break;
do_st:
gen_st(ctx, mips32_op, rt, rs, imm);
break;
default:
gen_reserved_instruction(ctx);
break;
}
}
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
index 5cffe0e412..b8bdd6a7f2 100644
--- a/target/mips/tcg/mips16e_translate.c.inc
+++ b/target/mips/tcg/mips16e_translate.c.inc
@@ -130,159 +130,159 @@ static int xlat(int r)
static void gen_mips16_save(DisasContext *ctx,
int xsregs, int aregs,
int do_ra, int do_s0, int do_s1,
int framesize)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
int args, astatic;
switch (aregs) {
case 0:
case 1:
case 2:
case 3:
case 11:
args = 0;
break;
case 4:
case 5:
case 6:
case 7:
args = 1;
break;
case 8:
case 9:
case 10:
args = 2;
break;
case 12:
case 13:
args = 3;
break;
case 14:
args = 4;
break;
default:
gen_reserved_instruction(ctx);
return;
}
switch (args) {
case 4:
gen_base_offset_addr(ctx, t0, 29, 12);
gen_load_gpr(t1, 7);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
ctx->default_tcg_memop_mask);
- /* Fall through */
+ fallthrough;
case 3:
gen_base_offset_addr(ctx, t0, 29, 8);
gen_load_gpr(t1, 6);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
ctx->default_tcg_memop_mask);
- /* Fall through */
+ fallthrough;
case 2:
gen_base_offset_addr(ctx, t0, 29, 4);
gen_load_gpr(t1, 5);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
ctx->default_tcg_memop_mask);
- /* Fall through */
+ fallthrough;
case 1:
gen_base_offset_addr(ctx, t0, 29, 0);
gen_load_gpr(t1, 4);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
ctx->default_tcg_memop_mask);
}
gen_load_gpr(t0, 29);
#define DECR_AND_STORE(reg) do { \
tcg_gen_movi_tl(t2, -4); \
gen_op_addr_add(ctx, t0, t0, t2); \
gen_load_gpr(t1, reg); \
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | \
ctx->default_tcg_memop_mask); \
} while (0)
if (do_ra) {
DECR_AND_STORE(31);
}
switch (xsregs) {
case 7:
DECR_AND_STORE(30);
- /* Fall through */
+ fallthrough;
case 6:
DECR_AND_STORE(23);
- /* Fall through */
+ fallthrough;
case 5:
DECR_AND_STORE(22);
- /* Fall through */
+ fallthrough;
case 4:
DECR_AND_STORE(21);
- /* Fall through */
+ fallthrough;
case 3:
DECR_AND_STORE(20);
- /* Fall through */
+ fallthrough;
case 2:
DECR_AND_STORE(19);
- /* Fall through */
+ fallthrough;
case 1:
DECR_AND_STORE(18);
}
if (do_s1) {
DECR_AND_STORE(17);
}
if (do_s0) {
DECR_AND_STORE(16);
}
switch (aregs) {
case 0:
case 4:
case 8:
case 12:
case 14:
astatic = 0;
break;
case 1:
case 5:
case 9:
case 13:
astatic = 1;
break;
case 2:
case 6:
case 10:
astatic = 2;
break;
case 3:
case 7:
astatic = 3;
break;
case 11:
astatic = 4;
break;
default:
gen_reserved_instruction(ctx);
return;
}
if (astatic > 0) {
DECR_AND_STORE(7);
if (astatic > 1) {
DECR_AND_STORE(6);
if (astatic > 2) {
DECR_AND_STORE(5);
if (astatic > 3) {
DECR_AND_STORE(4);
}
}
}
}
#undef DECR_AND_STORE
tcg_gen_movi_tl(t2, -framesize);
gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
}
@@ -290,105 +290,105 @@ static void gen_mips16_save(DisasContext *ctx,
static void gen_mips16_restore(DisasContext *ctx,
int xsregs, int aregs,
int do_ra, int do_s0, int do_s1,
int framesize)
{
int astatic;
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
tcg_gen_movi_tl(t2, framesize);
gen_op_addr_add(ctx, t0, cpu_gpr[29], t2);
#define DECR_AND_LOAD(reg) do { \
tcg_gen_movi_tl(t2, -4); \
gen_op_addr_add(ctx, t0, t0, t2); \
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL | \
ctx->default_tcg_memop_mask); \
gen_store_gpr(t1, reg); \
} while (0)
if (do_ra) {
DECR_AND_LOAD(31);
}
switch (xsregs) {
case 7:
DECR_AND_LOAD(30);
- /* Fall through */
+ fallthrough;
case 6:
DECR_AND_LOAD(23);
- /* Fall through */
+ fallthrough;
case 5:
DECR_AND_LOAD(22);
- /* Fall through */
+ fallthrough;
case 4:
DECR_AND_LOAD(21);
- /* Fall through */
+ fallthrough;
case 3:
DECR_AND_LOAD(20);
- /* Fall through */
+ fallthrough;
case 2:
DECR_AND_LOAD(19);
- /* Fall through */
+ fallthrough;
case 1:
DECR_AND_LOAD(18);
}
if (do_s1) {
DECR_AND_LOAD(17);
}
if (do_s0) {
DECR_AND_LOAD(16);
}
switch (aregs) {
case 0:
case 4:
case 8:
case 12:
case 14:
astatic = 0;
break;
case 1:
case 5:
case 9:
case 13:
astatic = 1;
break;
case 2:
case 6:
case 10:
astatic = 2;
break;
case 3:
case 7:
astatic = 3;
break;
case 11:
astatic = 4;
break;
default:
gen_reserved_instruction(ctx);
return;
}
if (astatic > 0) {
DECR_AND_LOAD(7);
if (astatic > 1) {
DECR_AND_LOAD(6);
if (astatic > 2) {
DECR_AND_LOAD(5);
if (astatic > 3) {
DECR_AND_LOAD(4);
}
}
}
}
#undef DECR_AND_LOAD
tcg_gen_movi_tl(t2, framesize);
gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
}
#if defined(TARGET_MIPS64)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index c517258ac5..3811ac0d54 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -4564,19 +4564,19 @@ static void decode_opc_mxu__pool05(DisasContext *ctx)
static void decode_opc_mxu__pool06(DisasContext *ctx)
{
uint32_t opcode = extract32(ctx->opcode, 10, 4);
uint32_t strd2 = extract32(ctx->opcode, 14, 2);
switch (opcode) {
case OPC_MXU_S32LDST:
case OPC_MXU_S32LDSTR:
if (strd2 <= 2) {
gen_mxu_s32ldxvx(ctx, opcode, false, strd2);
break;
}
- /* fallthrough */
+ fallthrough;
default:
MIPS_INVAL("decode_opc_mxu");
gen_reserved_instruction(ctx);
break;
}
}
@@ -4584,19 +4584,19 @@ static void decode_opc_mxu__pool06(DisasContext *ctx)
static void decode_opc_mxu__pool07(DisasContext *ctx)
{
uint32_t opcode = extract32(ctx->opcode, 10, 4);
uint32_t strd2 = extract32(ctx->opcode, 14, 2);
switch (opcode) {
case OPC_MXU_S32LDST:
case OPC_MXU_S32LDSTR:
if (strd2 <= 2) {
gen_mxu_s32stxvx(ctx, opcode, false, strd2);
break;
}
- /* fallthrough */
+ fallthrough;
default:
MIPS_INVAL("decode_opc_mxu");
gen_reserved_instruction(ctx);
break;
}
}
@@ -4630,19 +4630,19 @@ static void decode_opc_mxu__pool09(DisasContext *ctx)
static void decode_opc_mxu__pool10(DisasContext *ctx)
{
uint32_t opcode = extract32(ctx->opcode, 10, 4);
uint32_t strd2 = extract32(ctx->opcode, 14, 2);
switch (opcode) {
case OPC_MXU_S32LDST:
case OPC_MXU_S32LDSTR:
if (strd2 <= 2) {
gen_mxu_s32ldxvx(ctx, opcode, true, strd2);
break;
}
- /* fallthrough */
+ fallthrough;
default:
MIPS_INVAL("decode_opc_mxu");
gen_reserved_instruction(ctx);
break;
}
}
@@ -4650,19 +4650,19 @@ static void decode_opc_mxu__pool10(DisasContext *ctx)
static void decode_opc_mxu__pool11(DisasContext *ctx)
{
uint32_t opcode = extract32(ctx->opcode, 10, 4);
uint32_t strd2 = extract32(ctx->opcode, 14, 2);
switch (opcode) {
case OPC_MXU_S32LDST:
case OPC_MXU_S32LDSTR:
if (strd2 <= 2) {
gen_mxu_s32stxvx(ctx, opcode, true, strd2);
break;
}
- /* fallthrough */
+ fallthrough;
default:
MIPS_INVAL("decode_opc_mxu");
gen_reserved_instruction(ctx);
break;
}
}
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index b4b746d418..3e5f4f4e58 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -2604,121 +2604,121 @@ static void gen_compute_branch_cp1_nm(DisasContext *ctx, uint32_t op,
static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
{
TCGv t0, t1;
t0 = tcg_temp_new();
t1 = tcg_temp_new();
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
if ((extract32(ctx->opcode, 6, 1)) == 1) {
/* PP.LSXS instructions require shifting */
switch (extract32(ctx->opcode, 7, 4)) {
case NM_SHXS:
check_nms(ctx);
- /* fall through */
+ fallthrough;
case NM_LHXS:
case NM_LHUXS:
tcg_gen_shli_tl(t0, t0, 1);
break;
case NM_SWXS:
check_nms(ctx);
- /* fall through */
+ fallthrough;
case NM_LWXS:
case NM_LWC1XS:
case NM_SWC1XS:
tcg_gen_shli_tl(t0, t0, 2);
break;
case NM_LDC1XS:
case NM_SDC1XS:
tcg_gen_shli_tl(t0, t0, 3);
break;
default:
gen_reserved_instruction(ctx);
return;
}
}
gen_op_addr_add(ctx, t0, t0, t1);
switch (extract32(ctx->opcode, 7, 4)) {
case NM_LBX:
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB);
gen_store_gpr(t0, rd);
break;
case NM_LHX:
/*case NM_LHXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
MO_TESW | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd);
break;
case NM_LWX:
/*case NM_LWXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
MO_TESL | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd);
break;
case NM_LBUX:
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB);
gen_store_gpr(t0, rd);
break;
case NM_LHUX:
/*case NM_LHUXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
MO_TEUW | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd);
break;
case NM_SBX:
check_nms(ctx);
gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_8);
break;
case NM_SHX:
/*case NM_SHXS:*/
check_nms(ctx);
gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
MO_TEUW | ctx->default_tcg_memop_mask);
break;
case NM_SWX:
/*case NM_SWXS:*/
check_nms(ctx);
gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
MO_TEUL | ctx->default_tcg_memop_mask);
break;
case NM_LWC1X:
/*case NM_LWC1XS:*/
case NM_LDC1X:
/*case NM_LDC1XS:*/
case NM_SWC1X:
/*case NM_SWC1XS:*/
case NM_SDC1X:
/*case NM_SDC1XS:*/
if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
switch (extract32(ctx->opcode, 7, 4)) {
case NM_LWC1X:
/*case NM_LWC1XS:*/
gen_flt_ldst(ctx, OPC_LWC1, rd, t0);
break;
case NM_LDC1X:
/*case NM_LDC1XS:*/
gen_flt_ldst(ctx, OPC_LDC1, rd, t0);
break;
case NM_SWC1X:
/*case NM_SWC1XS:*/
gen_flt_ldst(ctx, OPC_SWC1, rd, t0);
break;
case NM_SDC1X:
/*case NM_SDC1XS:*/
gen_flt_ldst(ctx, OPC_SDC1, rd, t0);
break;
}
} else {
generate_exception_err(ctx, EXCP_CpU, 1);
}
break;
default:
gen_reserved_instruction(ctx);
break;
}
}
diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c
index 98935b5e64..b53f4fa694 100644
--- a/target/mips/tcg/op_helper.c
+++ b/target/mips/tcg/op_helper.c
@@ -233,28 +233,28 @@ target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
void helper_pmon(CPUMIPSState *env, int function)
{
function /= 2;
switch (function) {
case 2: /* TODO: char inbyte(int waitflag); */
if (env->active_tc.gpr[4] == 0) {
env->active_tc.gpr[2] = -1;
}
- /* Fall through */
+ fallthrough;
case 11: /* TODO: char inbyte (void); */
env->active_tc.gpr[2] = -1;
break;
case 3:
case 12:
printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
break;
case 17:
break;
case 158:
{
unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
printf("%s", fmt);
}
break;
}
}
#ifdef TARGET_MIPS64
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 13e43fa3b6..c6cbc05400 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -2054,191 +2054,191 @@ static void gen_lxr(DisasContext *ctx, TCGv reg, TCGv addr,
/* Load */
static void gen_ld(DisasContext *ctx, uint32_t opc,
int rt, int base, int offset)
{
TCGv t0, t1;
int mem_idx = ctx->mem_idx;
if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F |
INSN_LOONGSON3A)) {
/*
* Loongson CPU uses a load to zero register for prefetch.
* We emulate it as a NOP. On other CPU we must perform the
* actual memory access.
*/
return;
}
t0 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, base, offset);
switch (opc) {
#if defined(TARGET_MIPS64)
case OPC_LWU:
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
case OPC_LD:
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
case OPC_LLD:
case R6_OPC_LLD:
op_ld_lld(t0, t0, mem_idx, ctx);
gen_store_gpr(t0, rt);
break;
case OPC_LDL:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
gen_lxl(ctx, t1, t0, mem_idx, MO_TEUQ);
gen_store_gpr(t1, rt);
break;
case OPC_LDR:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
gen_lxr(ctx, t1, t0, mem_idx, MO_TEUQ);
gen_store_gpr(t1, rt);
break;
case OPC_LDPC:
t1 = tcg_constant_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ);
gen_store_gpr(t0, rt);
break;
#endif
case OPC_LWPC:
t1 = tcg_constant_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL);
gen_store_gpr(t0, rt);
break;
case OPC_LWE:
mem_idx = MIPS_HFLAG_UM;
- /* fall through */
+ fallthrough;
case OPC_LW:
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
case OPC_LHE:
mem_idx = MIPS_HFLAG_UM;
- /* fall through */
+ fallthrough;
case OPC_LH:
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESW |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
case OPC_LHUE:
mem_idx = MIPS_HFLAG_UM;
- /* fall through */
+ fallthrough;
case OPC_LHU:
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUW |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
case OPC_LBE:
mem_idx = MIPS_HFLAG_UM;
- /* fall through */
+ fallthrough;
case OPC_LB:
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_SB);
gen_store_gpr(t0, rt);
break;
case OPC_LBUE:
mem_idx = MIPS_HFLAG_UM;
- /* fall through */
+ fallthrough;
case OPC_LBU:
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_UB);
gen_store_gpr(t0, rt);
break;
case OPC_LWLE:
mem_idx = MIPS_HFLAG_UM;
- /* fall through */
+ fallthrough;
case OPC_LWL:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
gen_lxl(ctx, t1, t0, mem_idx, MO_TEUL);
tcg_gen_ext32s_tl(t1, t1);
gen_store_gpr(t1, rt);
break;
case OPC_LWRE:
mem_idx = MIPS_HFLAG_UM;
- /* fall through */
+ fallthrough;
case OPC_LWR:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
gen_lxr(ctx, t1, t0, mem_idx, MO_TEUL);
tcg_gen_ext32s_tl(t1, t1);
gen_store_gpr(t1, rt);
break;
case OPC_LLE:
mem_idx = MIPS_HFLAG_UM;
- /* fall through */
+ fallthrough;
case OPC_LL:
case R6_OPC_LL:
op_ld_ll(t0, t0, mem_idx, ctx);
gen_store_gpr(t0, rt);
break;
}
}
/* Store */
static void gen_st(DisasContext *ctx, uint32_t opc, int rt,
int base, int offset)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
int mem_idx = ctx->mem_idx;
gen_base_offset_addr(ctx, t0, base, offset);
gen_load_gpr(t1, rt);
switch (opc) {
#if defined(TARGET_MIPS64)
case OPC_SD:
tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUQ |
ctx->default_tcg_memop_mask);
break;
case OPC_SDL:
gen_helper_0e2i(sdl, t1, t0, mem_idx);
break;
case OPC_SDR:
gen_helper_0e2i(sdr, t1, t0, mem_idx);
break;
#endif
case OPC_SWE:
mem_idx = MIPS_HFLAG_UM;
- /* fall through */
+ fallthrough;
case OPC_SW:
tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUL |
ctx->default_tcg_memop_mask);
break;
case OPC_SHE:
mem_idx = MIPS_HFLAG_UM;
- /* fall through */
+ fallthrough;
case OPC_SH:
tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUW |
ctx->default_tcg_memop_mask);
break;
case OPC_SBE:
mem_idx = MIPS_HFLAG_UM;
- /* fall through */
+ fallthrough;
case OPC_SB:
tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_8);
break;
case OPC_SWLE:
mem_idx = MIPS_HFLAG_UM;
- /* fall through */
+ fallthrough;
case OPC_SWL:
gen_helper_0e2i(swl, t1, t0, mem_idx);
break;
case OPC_SWRE:
mem_idx = MIPS_HFLAG_UM;
- /* fall through */
+ fallthrough;
case OPC_SWR:
gen_helper_0e2i(swr, t1, t0, mem_idx);
break;
}
}
/* Store conditional */
@@ -2321,22 +2321,22 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
int rs, int16_t imm)
{
TCGv t0 = tcg_temp_new();
if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
switch (op) {
case OPC_LDC1:
case OPC_SDC1:
check_insn(ctx, ISA_MIPS2);
- /* Fallthrough */
+ fallthrough;
default:
gen_base_offset_addr(ctx, t0, rs, imm);
gen_flt_ldst(ctx, op, rt, t0);
}
} else {
generate_exception_err(ctx, EXCP_CpU, 1);
}
}
/* Arithmetic with immediate operand */
@@ -3441,119 +3441,119 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
/*
* These MULT[U] and MADD[U] instructions implemented in for example
* the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
* architectures are special three-operand variants with the syntax
*
* MULT[U][1] rd, rs, rt
*
* such that
*
* (rd, LO, HI) <- rs * rt
*
* and
*
* MADD[U][1] rd, rs, rt
*
* such that
*
* (rd, LO, HI) <- (LO, HI) + rs * rt
*
* where the low-order 32-bits of the result is placed into both the
* GPR rd and the special register LO. The high-order 32-bits of the
* result is placed into the special register HI.
*
* If the GPR rd is omitted in assembly language, it is taken to be 0,
* which is the zero register that always reads as 0.
*/
static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
int rd, int rs, int rt)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
int acc = 0;
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
switch (opc) {
case MMI_OPC_MULT1:
acc = 1;
- /* Fall through */
+ fallthrough;
case OPC_MULT:
{
TCGv_i32 t2 = tcg_temp_new_i32();
TCGv_i32 t3 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(t2, t0);
tcg_gen_trunc_tl_i32(t3, t1);
tcg_gen_muls2_i32(t2, t3, t2, t3);
if (rd) {
tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
}
tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
}
break;
case MMI_OPC_MULTU1:
acc = 1;
- /* Fall through */
+ fallthrough;
case OPC_MULTU:
{
TCGv_i32 t2 = tcg_temp_new_i32();
TCGv_i32 t3 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(t2, t0);
tcg_gen_trunc_tl_i32(t3, t1);
tcg_gen_mulu2_i32(t2, t3, t2, t3);
if (rd) {
tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
}
tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
}
break;
case MMI_OPC_MADD1:
acc = 1;
- /* Fall through */
+ fallthrough;
case MMI_OPC_MADD:
{
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
tcg_gen_ext_tl_i64(t2, t0);
tcg_gen_ext_tl_i64(t3, t1);
tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
tcg_gen_add_i64(t2, t2, t3);
gen_move_low32(cpu_LO[acc], t2);
gen_move_high32(cpu_HI[acc], t2);
if (rd) {
gen_move_low32(cpu_gpr[rd], t2);
}
}
break;
case MMI_OPC_MADDU1:
acc = 1;
- /* Fall through */
+ fallthrough;
case MMI_OPC_MADDU:
{
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_extu_tl_i64(t2, t0);
tcg_gen_extu_tl_i64(t3, t1);
tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
tcg_gen_add_i64(t2, t2, t3);
gen_move_low32(cpu_LO[acc], t2);
gen_move_high32(cpu_HI[acc], t2);
if (rd) {
gen_move_low32(cpu_gpr[rd], t2);
}
}
break;
default:
MIPS_INVAL("mul/madd TXx9");
gen_reserved_instruction(ctx);
break;
}
}
@@ -3782,363 +3782,364 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
/* Loongson multimedia instructions */
static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
{
uint32_t opc, shift_max;
TCGv_i64 t0, t1;
TCGCond cond;
opc = MASK_LMMI(ctx->opcode);
check_cp1_enabled(ctx);
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, t0, rs);
gen_load_fpr64(ctx, t1, rt);
switch (opc) {
case OPC_PADDSH:
gen_helper_paddsh(t0, t0, t1);
break;
case OPC_PADDUSH:
gen_helper_paddush(t0, t0, t1);
break;
case OPC_PADDH:
gen_helper_paddh(t0, t0, t1);
break;
case OPC_PADDW:
gen_helper_paddw(t0, t0, t1);
break;
case OPC_PADDSB:
gen_helper_paddsb(t0, t0, t1);
break;
case OPC_PADDUSB:
gen_helper_paddusb(t0, t0, t1);
break;
case OPC_PADDB:
gen_helper_paddb(t0, t0, t1);
break;
case OPC_PSUBSH:
gen_helper_psubsh(t0, t0, t1);
break;
case OPC_PSUBUSH:
gen_helper_psubush(t0, t0, t1);
break;
case OPC_PSUBH:
gen_helper_psubh(t0, t0, t1);
break;
case OPC_PSUBW:
gen_helper_psubw(t0, t0, t1);
break;
case OPC_PSUBSB:
gen_helper_psubsb(t0, t0, t1);
break;
case OPC_PSUBUSB:
gen_helper_psubusb(t0, t0, t1);
break;
case OPC_PSUBB:
gen_helper_psubb(t0, t0, t1);
break;
case OPC_PSHUFH:
gen_helper_pshufh(t0, t0, t1);
break;
case OPC_PACKSSWH:
gen_helper_packsswh(t0, t0, t1);
break;
case OPC_PACKSSHB:
gen_helper_packsshb(t0, t0, t1);
break;
case OPC_PACKUSHB:
gen_helper_packushb(t0, t0, t1);
break;
case OPC_PUNPCKLHW:
gen_helper_punpcklhw(t0, t0, t1);
break;
case OPC_PUNPCKHHW:
gen_helper_punpckhhw(t0, t0, t1);
break;
case OPC_PUNPCKLBH:
gen_helper_punpcklbh(t0, t0, t1);
break;
case OPC_PUNPCKHBH:
gen_helper_punpckhbh(t0, t0, t1);
break;
case OPC_PUNPCKLWD:
gen_helper_punpcklwd(t0, t0, t1);
break;
case OPC_PUNPCKHWD:
gen_helper_punpckhwd(t0, t0, t1);
break;
case OPC_PAVGH:
gen_helper_pavgh(t0, t0, t1);
break;
case OPC_PAVGB:
gen_helper_pavgb(t0, t0, t1);
break;
case OPC_PMAXSH:
gen_helper_pmaxsh(t0, t0, t1);
break;
case OPC_PMINSH:
gen_helper_pminsh(t0, t0, t1);
break;
case OPC_PMAXUB:
gen_helper_pmaxub(t0, t0, t1);
break;
case OPC_PMINUB:
gen_helper_pminub(t0, t0, t1);
break;
case OPC_PCMPEQW:
gen_helper_pcmpeqw(t0, t0, t1);
break;
case OPC_PCMPGTW:
gen_helper_pcmpgtw(t0, t0, t1);
break;
case OPC_PCMPEQH:
gen_helper_pcmpeqh(t0, t0, t1);
break;
case OPC_PCMPGTH:
gen_helper_pcmpgth(t0, t0, t1);
break;
case OPC_PCMPEQB:
gen_helper_pcmpeqb(t0, t0, t1);
break;
case OPC_PCMPGTB:
gen_helper_pcmpgtb(t0, t0, t1);
break;
case OPC_PSLLW:
gen_helper_psllw(t0, t0, t1);
break;
case OPC_PSLLH:
gen_helper_psllh(t0, t0, t1);
break;
case OPC_PSRLW:
gen_helper_psrlw(t0, t0, t1);
break;
case OPC_PSRLH:
gen_helper_psrlh(t0, t0, t1);
break;
case OPC_PSRAW:
gen_helper_psraw(t0, t0, t1);
break;
case OPC_PSRAH:
gen_helper_psrah(t0, t0, t1);
break;
case OPC_PMULLH:
gen_helper_pmullh(t0, t0, t1);
break;
case OPC_PMULHH:
gen_helper_pmulhh(t0, t0, t1);
break;
case OPC_PMULHUH:
gen_helper_pmulhuh(t0, t0, t1);
break;
case OPC_PMADDHW:
gen_helper_pmaddhw(t0, t0, t1);
break;
case OPC_PASUBUB:
gen_helper_pasubub(t0, t0, t1);
break;
case OPC_BIADD:
gen_helper_biadd(t0, t0);
break;
case OPC_PMOVMSKB:
gen_helper_pmovmskb(t0, t0);
break;
case OPC_PADDD:
tcg_gen_add_i64(t0, t0, t1);
break;
case OPC_PSUBD:
tcg_gen_sub_i64(t0, t0, t1);
break;
case OPC_XOR_CP2:
tcg_gen_xor_i64(t0, t0, t1);
break;
case OPC_NOR_CP2:
tcg_gen_nor_i64(t0, t0, t1);
break;
case OPC_AND_CP2:
tcg_gen_and_i64(t0, t0, t1);
break;
case OPC_OR_CP2:
tcg_gen_or_i64(t0, t0, t1);
break;
case OPC_PANDN:
tcg_gen_andc_i64(t0, t1, t0);
break;
case OPC_PINSRH_0:
tcg_gen_deposit_i64(t0, t0, t1, 0, 16);
break;
case OPC_PINSRH_1:
tcg_gen_deposit_i64(t0, t0, t1, 16, 16);
break;
case OPC_PINSRH_2:
tcg_gen_deposit_i64(t0, t0, t1, 32, 16);
break;
case OPC_PINSRH_3:
tcg_gen_deposit_i64(t0, t0, t1, 48, 16);
break;
case OPC_PEXTRH:
tcg_gen_andi_i64(t1, t1, 3);
tcg_gen_shli_i64(t1, t1, 4);
tcg_gen_shr_i64(t0, t0, t1);
tcg_gen_ext16u_i64(t0, t0);
break;
case OPC_ADDU_CP2:
tcg_gen_add_i64(t0, t0, t1);
tcg_gen_ext32s_i64(t0, t0);
break;
case OPC_SUBU_CP2:
tcg_gen_sub_i64(t0, t0, t1);
tcg_gen_ext32s_i64(t0, t0);
break;
case OPC_SLL_CP2:
shift_max = 32;
goto do_shift;
case OPC_SRL_CP2:
shift_max = 32;
goto do_shift;
case OPC_SRA_CP2:
shift_max = 32;
goto do_shift;
case OPC_DSLL_CP2:
shift_max = 64;
goto do_shift;
case OPC_DSRL_CP2:
shift_max = 64;
goto do_shift;
case OPC_DSRA_CP2:
shift_max = 64;
goto do_shift;
do_shift:
/* Make sure shift count isn't TCG undefined behaviour. */
tcg_gen_andi_i64(t1, t1, shift_max - 1);
switch (opc) {
case OPC_SLL_CP2:
case OPC_DSLL_CP2:
tcg_gen_shl_i64(t0, t0, t1);
break;
case OPC_SRA_CP2:
case OPC_DSRA_CP2:
/*
* Since SRA is UndefinedResult without sign-extended inputs,
* we can treat SRA and DSRA the same.
*/
tcg_gen_sar_i64(t0, t0, t1);
break;
case OPC_SRL_CP2:
/* We want to shift in zeros for SRL; zero-extend first. */
tcg_gen_ext32u_i64(t0, t0);
/* FALLTHRU */
+ fallthrough;
case OPC_DSRL_CP2:
tcg_gen_shr_i64(t0, t0, t1);
break;
}
if (shift_max == 32) {
tcg_gen_ext32s_i64(t0, t0);
}
/* Shifts larger than MAX produce zero. */
tcg_gen_setcondi_i64(TCG_COND_LTU, t1, t1, shift_max);
tcg_gen_neg_i64(t1, t1);
tcg_gen_and_i64(t0, t0, t1);
break;
case OPC_ADD_CP2:
case OPC_DADD_CP2:
{
TCGv_i64 t2 = tcg_temp_new_i64();
TCGLabel *lab = gen_new_label();
tcg_gen_mov_i64(t2, t0);
tcg_gen_add_i64(t0, t1, t2);
if (opc == OPC_ADD_CP2) {
tcg_gen_ext32s_i64(t0, t0);
}
tcg_gen_xor_i64(t1, t1, t2);
tcg_gen_xor_i64(t2, t2, t0);
tcg_gen_andc_i64(t1, t2, t1);
tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab);
generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(lab);
break;
}
case OPC_SUB_CP2:
case OPC_DSUB_CP2:
{
TCGv_i64 t2 = tcg_temp_new_i64();
TCGLabel *lab = gen_new_label();
tcg_gen_mov_i64(t2, t0);
tcg_gen_sub_i64(t0, t1, t2);
if (opc == OPC_SUB_CP2) {
tcg_gen_ext32s_i64(t0, t0);
}
tcg_gen_xor_i64(t1, t1, t2);
tcg_gen_xor_i64(t2, t2, t0);
tcg_gen_and_i64(t1, t1, t2);
tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab);
generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(lab);
break;
}
case OPC_PMULUW:
tcg_gen_ext32u_i64(t0, t0);
tcg_gen_ext32u_i64(t1, t1);
tcg_gen_mul_i64(t0, t0, t1);
break;
case OPC_SEQU_CP2:
case OPC_SEQ_CP2:
cond = TCG_COND_EQ;
goto do_cc_cond;
break;
case OPC_SLTU_CP2:
cond = TCG_COND_LTU;
goto do_cc_cond;
break;
case OPC_SLT_CP2:
cond = TCG_COND_LT;
goto do_cc_cond;
break;
case OPC_SLEU_CP2:
cond = TCG_COND_LEU;
goto do_cc_cond;
break;
case OPC_SLE_CP2:
cond = TCG_COND_LE;
do_cc_cond:
{
int cc = (ctx->opcode >> 8) & 0x7;
TCGv_i64 t64 = tcg_temp_new_i64();
TCGv_i32 t32 = tcg_temp_new_i32();
tcg_gen_setcond_i64(cond, t64, t0, t1);
tcg_gen_extrl_i64_i32(t32, t64);
tcg_gen_deposit_i32(fpu_fcr31, fpu_fcr31, t32,
get_fp_bit(cc), 1);
}
return;
default:
MIPS_INVAL("loongson_cp2");
gen_reserved_instruction(ctx);
return;
}
gen_store_fpr64(ctx, t0, rd);
}
@@ -4574,324 +4575,326 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
/* Branches (before delay slot) */
static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
int insn_bytes,
int rs, int rt, int32_t offset,
int delayslot_size)
{
target_ulong btgt = -1;
int blink = 0;
int bcond_compute = 0;
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
if (ctx->hflags & MIPS_HFLAG_BMASK) {
#ifdef MIPS_DEBUG_DISAS
LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
TARGET_FMT_lx "\n", ctx->base.pc_next);
#endif
gen_reserved_instruction(ctx);
goto out;
}
/* Load needed operands */
switch (opc) {
case OPC_BEQ:
case OPC_BEQL:
case OPC_BNE:
case OPC_BNEL:
/* Compare two registers */
if (rs != rt) {
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
bcond_compute = 1;
}
btgt = ctx->base.pc_next + insn_bytes + offset;
break;
case OPC_BGEZ:
case OPC_BGEZAL:
case OPC_BGEZALL:
case OPC_BGEZL:
case OPC_BGTZ:
case OPC_BGTZL:
case OPC_BLEZ:
case OPC_BLEZL:
case OPC_BLTZ:
case OPC_BLTZAL:
case OPC_BLTZALL:
case OPC_BLTZL:
/* Compare to zero */
if (rs != 0) {
gen_load_gpr(t0, rs);
bcond_compute = 1;
}
btgt = ctx->base.pc_next + insn_bytes + offset;
break;
case OPC_BPOSGE32:
#if defined(TARGET_MIPS64)
case OPC_BPOSGE64:
tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F);
#else
tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F);
#endif
bcond_compute = 1;
btgt = ctx->base.pc_next + insn_bytes + offset;
break;
case OPC_J:
case OPC_JAL:
{
/* Jump to immediate */
int jal_mask = ctx->hflags & MIPS_HFLAG_M16 ? 0xF8000000
: 0xF0000000;
btgt = ((ctx->base.pc_next + insn_bytes) & jal_mask)
| (uint32_t)offset;
break;
}
case OPC_JALX:
/* Jump to immediate */
btgt = ((ctx->base.pc_next + insn_bytes) & (int32_t)0xF0000000) |
(uint32_t)offset;
break;
case OPC_JR:
case OPC_JALR:
/* Jump to register */
if (offset != 0 && offset != 16) {
/*
* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
* others are reserved.
*/
MIPS_INVAL("jump hint");
gen_reserved_instruction(ctx);
goto out;
}
gen_load_gpr(btarget, rs);
break;
default:
MIPS_INVAL("branch/jump");
gen_reserved_instruction(ctx);
goto out;
}
if (bcond_compute == 0) {
/* No condition to be computed */
switch (opc) {
case OPC_BEQ: /* rx == rx */
case OPC_BEQL: /* rx == rx likely */
case OPC_BGEZ: /* 0 >= 0 */
case OPC_BGEZL: /* 0 >= 0 likely */
case OPC_BLEZ: /* 0 <= 0 */
case OPC_BLEZL: /* 0 <= 0 likely */
/* Always take */
ctx->hflags |= MIPS_HFLAG_B;
break;
case OPC_BGEZAL: /* 0 >= 0 */
case OPC_BGEZALL: /* 0 >= 0 likely */
/* Always take and link */
blink = 31;
ctx->hflags |= MIPS_HFLAG_B;
break;
case OPC_BNE: /* rx != rx */
case OPC_BGTZ: /* 0 > 0 */
case OPC_BLTZ: /* 0 < 0 */
/* Treat as NOP. */
goto out;
case OPC_BLTZAL: /* 0 < 0 */
/*
* Handle as an unconditional branch to get correct delay
* slot checking.
*/
blink = 31;
btgt = ctx->base.pc_next + insn_bytes + delayslot_size;
ctx->hflags |= MIPS_HFLAG_B;
break;
case OPC_BLTZALL: /* 0 < 0 likely */
tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 8);
/* Skip the instruction in the delay slot */
ctx->base.pc_next += 4;
goto out;
case OPC_BNEL: /* rx != rx likely */
case OPC_BGTZL: /* 0 > 0 likely */
case OPC_BLTZL: /* 0 < 0 likely */
/* Skip the instruction in the delay slot */
ctx->base.pc_next += 4;
goto out;
case OPC_J:
ctx->hflags |= MIPS_HFLAG_B;
break;
case OPC_JALX:
ctx->hflags |= MIPS_HFLAG_BX;
- /* Fallthrough */
+ fallthrough;
case OPC_JAL:
blink = 31;
ctx->hflags |= MIPS_HFLAG_B;
break;
case OPC_JR:
ctx->hflags |= MIPS_HFLAG_BR;
break;
case OPC_JALR:
blink = rt;
ctx->hflags |= MIPS_HFLAG_BR;
break;
default:
MIPS_INVAL("branch/jump");
gen_reserved_instruction(ctx);
goto out;
}
} else {
switch (opc) {
case OPC_BEQ:
tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
goto not_likely;
case OPC_BEQL:
tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
goto likely;
case OPC_BNE:
tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
goto not_likely;
case OPC_BNEL:
tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
goto likely;
case OPC_BGEZ:
tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
goto not_likely;
case OPC_BGEZL:
tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
goto likely;
case OPC_BGEZAL:
tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
blink = 31;
goto not_likely;
case OPC_BGEZALL:
tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
blink = 31;
goto likely;
case OPC_BGTZ:
tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0);
goto not_likely;
case OPC_BGTZL:
tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0);
goto likely;
case OPC_BLEZ:
tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0);
goto not_likely;
case OPC_BLEZL:
tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0);
goto likely;
case OPC_BLTZ:
tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
goto not_likely;
case OPC_BLTZL:
tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
goto likely;
case OPC_BPOSGE32:
tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32);
goto not_likely;
#if defined(TARGET_MIPS64)
case OPC_BPOSGE64:
tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 64);
goto not_likely;
#endif
case OPC_BLTZAL:
tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
blink = 31;
not_likely:
ctx->hflags |= MIPS_HFLAG_BC;
break;
case OPC_BLTZALL:
tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
blink = 31;
likely:
ctx->hflags |= MIPS_HFLAG_BL;
break;
default:
MIPS_INVAL("conditional branch/jump");
gen_reserved_instruction(ctx);
goto out;
}
}
ctx->btarget = btgt;
switch (delayslot_size) {
case 2:
ctx->hflags |= MIPS_HFLAG_BDS16;
break;
case 4:
ctx->hflags |= MIPS_HFLAG_BDS32;
break;
}
if (blink > 0) {
int post_delay = insn_bytes + delayslot_size;
int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16);
tcg_gen_movi_tl(cpu_gpr[blink],
ctx->base.pc_next + post_delay + lowbit);
}
out:
if (insn_bytes == 2) {
ctx->hflags |= MIPS_HFLAG_B16;
}
}
/* special3 bitfield operations */
static void gen_bitops(DisasContext *ctx, uint32_t opc, int rt,
int rs, int lsb, int msb)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
gen_load_gpr(t1, rs);
switch (opc) {
case OPC_EXT:
if (lsb + msb > 31) {
goto fail;
}
if (msb != 31) {
tcg_gen_extract_tl(t0, t1, lsb, msb + 1);
} else {
/*
* The two checks together imply that lsb == 0,
* so this is a simple sign-extension.
*/
tcg_gen_ext32s_tl(t0, t1);
}
break;
#if defined(TARGET_MIPS64)
case OPC_DEXTU:
lsb += 32;
goto do_dext;
case OPC_DEXTM:
msb += 32;
goto do_dext;
case OPC_DEXT:
do_dext:
if (lsb + msb > 63) {
goto fail;
}
tcg_gen_extract_tl(t0, t1, lsb, msb + 1);
break;
#endif
case OPC_INS:
if (lsb > msb) {
goto fail;
}
gen_load_gpr(t0, rt);
tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
tcg_gen_ext32s_tl(t0, t0);
break;
#if defined(TARGET_MIPS64)
case OPC_DINSU:
lsb += 32;
/* FALLTHRU */
+ fallthrough;
case OPC_DINSM:
msb += 32;
/* FALLTHRU */
+ fallthrough;
case OPC_DINS:
if (lsb > msb) {
goto fail;
}
gen_load_gpr(t0, rt);
tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
break;
#endif
default:
@@ -8343,218 +8346,218 @@ cp0_unimplemented:
static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
int u, int sel, int h)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
TCGv t0 = tcg_temp_new();
if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
(env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) {
tcg_gen_movi_tl(t0, -1);
} else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
(env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) {
tcg_gen_movi_tl(t0, -1);
} else if (u == 0) {
switch (rt) {
case 1:
switch (sel) {
case 1:
gen_helper_mftc0_vpecontrol(t0, tcg_env);
break;
case 2:
gen_helper_mftc0_vpeconf0(t0, tcg_env);
break;
default:
goto die;
break;
}
break;
case 2:
switch (sel) {
case 1:
gen_helper_mftc0_tcstatus(t0, tcg_env);
break;
case 2:
gen_helper_mftc0_tcbind(t0, tcg_env);
break;
case 3:
gen_helper_mftc0_tcrestart(t0, tcg_env);
break;
case 4:
gen_helper_mftc0_tchalt(t0, tcg_env);
break;
case 5:
gen_helper_mftc0_tccontext(t0, tcg_env);
break;
case 6:
gen_helper_mftc0_tcschedule(t0, tcg_env);
break;
case 7:
gen_helper_mftc0_tcschefback(t0, tcg_env);
break;
default:
gen_mfc0(ctx, t0, rt, sel);
break;
}
break;
case 10:
switch (sel) {
case 0:
gen_helper_mftc0_entryhi(t0, tcg_env);
break;
default:
gen_mfc0(ctx, t0, rt, sel);
break;
}
break;
case 12:
switch (sel) {
case 0:
gen_helper_mftc0_status(t0, tcg_env);
break;
default:
gen_mfc0(ctx, t0, rt, sel);
break;
}
break;
case 13:
switch (sel) {
case 0:
gen_helper_mftc0_cause(t0, tcg_env);
break;
default:
goto die;
break;
}
break;
case 14:
switch (sel) {
case 0:
gen_helper_mftc0_epc(t0, tcg_env);
break;
default:
goto die;
break;
}
break;
case 15:
switch (sel) {
case 1:
gen_helper_mftc0_ebase(t0, tcg_env);
break;
default:
goto die;
break;
}
break;
case 16:
switch (sel) {
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
gen_helper_mftc0_configx(t0, tcg_env, tcg_constant_tl(sel));
break;
default:
goto die;
break;
}
break;
case 23:
switch (sel) {
case 0:
gen_helper_mftc0_debug(t0, tcg_env);
break;
default:
gen_mfc0(ctx, t0, rt, sel);
break;
}
break;
default:
gen_mfc0(ctx, t0, rt, sel);
}
} else {
switch (sel) {
/* GPR registers. */
case 0:
gen_helper_1e0i(mftgpr, t0, rt);
break;
/* Auxiliary CPU registers */
case 1:
switch (rt) {
case 0:
gen_helper_1e0i(mftlo, t0, 0);
break;
case 1:
gen_helper_1e0i(mfthi, t0, 0);
break;
case 2:
gen_helper_1e0i(mftacx, t0, 0);
break;
case 4:
gen_helper_1e0i(mftlo, t0, 1);
break;
case 5:
gen_helper_1e0i(mfthi, t0, 1);
break;
case 6:
gen_helper_1e0i(mftacx, t0, 1);
break;
case 8:
gen_helper_1e0i(mftlo, t0, 2);
break;
case 9:
gen_helper_1e0i(mfthi, t0, 2);
break;
case 10:
gen_helper_1e0i(mftacx, t0, 2);
break;
case 12:
gen_helper_1e0i(mftlo, t0, 3);
break;
case 13:
gen_helper_1e0i(mfthi, t0, 3);
break;
case 14:
gen_helper_1e0i(mftacx, t0, 3);
break;
case 16:
gen_helper_mftdsp(t0, tcg_env);
break;
default:
goto die;
}
break;
/* Floating point (COP1). */
case 2:
/* XXX: For now we support only a single FPU context. */
if (h == 0) {
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, rt);
tcg_gen_ext_i32_tl(t0, fp0);
} else {
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32h(ctx, fp0, rt);
tcg_gen_ext_i32_tl(t0, fp0);
}
break;
case 3:
/* XXX: For now we support only a single FPU context. */
gen_helper_1e0i(cfc1, t0, rt);
break;
/* COP2: Not implemented. */
case 4:
case 5:
- /* fall through */
+ fallthrough;
default:
goto die;
}
}
trace_mips_translate_tr("mftr", rt, u, sel, h);
gen_store_gpr(t0, rd);
return;
@@ -8567,195 +8570,195 @@ die:
static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
int u, int sel, int h)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
TCGv t0 = tcg_temp_new();
gen_load_gpr(t0, rt);
if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
(env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) {
/* NOP */
;
} else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
(env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) {
/* NOP */
;
} else if (u == 0) {
switch (rd) {
case 1:
switch (sel) {
case 1:
gen_helper_mttc0_vpecontrol(tcg_env, t0);
break;
case 2:
gen_helper_mttc0_vpeconf0(tcg_env, t0);
break;
default:
goto die;
break;
}
break;
case 2:
switch (sel) {
case 1:
gen_helper_mttc0_tcstatus(tcg_env, t0);
break;
case 2:
gen_helper_mttc0_tcbind(tcg_env, t0);
break;
case 3:
gen_helper_mttc0_tcrestart(tcg_env, t0);
break;
case 4:
gen_helper_mttc0_tchalt(tcg_env, t0);
break;
case 5:
gen_helper_mttc0_tccontext(tcg_env, t0);
break;
case 6:
gen_helper_mttc0_tcschedule(tcg_env, t0);
break;
case 7:
gen_helper_mttc0_tcschefback(tcg_env, t0);
break;
default:
gen_mtc0(ctx, t0, rd, sel);
break;
}
break;
case 10:
switch (sel) {
case 0:
gen_helper_mttc0_entryhi(tcg_env, t0);
break;
default:
gen_mtc0(ctx, t0, rd, sel);
break;
}
break;
case 12:
switch (sel) {
case 0:
gen_helper_mttc0_status(tcg_env, t0);
break;
default:
gen_mtc0(ctx, t0, rd, sel);
break;
}
break;
case 13:
switch (sel) {
case 0:
gen_helper_mttc0_cause(tcg_env, t0);
break;
default:
goto die;
break;
}
break;
case 15:
switch (sel) {
case 1:
gen_helper_mttc0_ebase(tcg_env, t0);
break;
default:
goto die;
break;
}
break;
case 23:
switch (sel) {
case 0:
gen_helper_mttc0_debug(tcg_env, t0);
break;
default:
gen_mtc0(ctx, t0, rd, sel);
break;
}
break;
default:
gen_mtc0(ctx, t0, rd, sel);
}
} else {
switch (sel) {
/* GPR registers. */
case 0:
gen_helper_0e1i(mttgpr, t0, rd);
break;
/* Auxiliary CPU registers */
case 1:
switch (rd) {
case 0:
gen_helper_0e1i(mttlo, t0, 0);
break;
case 1:
gen_helper_0e1i(mtthi, t0, 0);
break;
case 2:
gen_helper_0e1i(mttacx, t0, 0);
break;
case 4:
gen_helper_0e1i(mttlo, t0, 1);
break;
case 5:
gen_helper_0e1i(mtthi, t0, 1);
break;
case 6:
gen_helper_0e1i(mttacx, t0, 1);
break;
case 8:
gen_helper_0e1i(mttlo, t0, 2);
break;
case 9:
gen_helper_0e1i(mtthi, t0, 2);
break;
case 10:
gen_helper_0e1i(mttacx, t0, 2);
break;
case 12:
gen_helper_0e1i(mttlo, t0, 3);
break;
case 13:
gen_helper_0e1i(mtthi, t0, 3);
break;
case 14:
gen_helper_0e1i(mttacx, t0, 3);
break;
case 16:
gen_helper_mttdsp(tcg_env, t0);
break;
default:
goto die;
}
break;
/* Floating point (COP1). */
case 2:
/* XXX: For now we support only a single FPU context. */
if (h == 0) {
TCGv_i32 fp0 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32(ctx, fp0, rd);
} else {
TCGv_i32 fp0 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32h(ctx, fp0, rd);
}
break;
case 3:
/* XXX: For now we support only a single FPU context. */
gen_helper_0e2i(ctc1, t0, tcg_constant_i32(rd), rt);
/* Stop translation as we may have changed hflags */
ctx->base.is_jmp = DISAS_STOP;
break;
/* COP2: Not implemented. */
case 4:
case 5:
- /* fall through */
+ fallthrough;
default:
goto die;
}
}
trace_mips_translate_tr("mttr", rd, u, sel, h);
return;
@@ -11266,224 +11269,224 @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
/* Compact Branches */
static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
int rs, int rt, int32_t offset)
{
int bcond_compute = 0;
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
int m16_lowbit = (ctx->hflags & MIPS_HFLAG_M16) != 0;
if (ctx->hflags & MIPS_HFLAG_BMASK) {
#ifdef MIPS_DEBUG_DISAS
LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
"\n", ctx->base.pc_next);
#endif
gen_reserved_instruction(ctx);
return;
}
/* Load needed operands and calculate btarget */
switch (opc) {
/* compact branch */
case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */
case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
bcond_compute = 1;
ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
if (rs <= rt && rs == 0) {
/* OPC_BEQZALC, OPC_BNEZALC */
tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
}
break;
case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */
case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
bcond_compute = 1;
ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
break;
case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */
case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */
if (rs == 0 || rs == rt) {
/* OPC_BLEZALC, OPC_BGEZALC */
/* OPC_BGTZALC, OPC_BLTZALC */
tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
}
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
bcond_compute = 1;
ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
break;
case OPC_BC:
case OPC_BALC:
ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
break;
case OPC_BEQZC:
case OPC_BNEZC:
if (rs != 0) {
/* OPC_BEQZC, OPC_BNEZC */
gen_load_gpr(t0, rs);
bcond_compute = 1;
ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
} else {
/* OPC_JIC, OPC_JIALC */
TCGv tbase = tcg_temp_new();
TCGv toffset = tcg_constant_tl(offset);
gen_load_gpr(tbase, rt);
gen_op_addr_add(ctx, btarget, tbase, toffset);
}
break;
default:
MIPS_INVAL("Compact branch/jump");
gen_reserved_instruction(ctx);
return;
}
if (bcond_compute == 0) {
/* Unconditional compact branch */
switch (opc) {
case OPC_JIALC:
tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
- /* Fallthrough */
+ fallthrough;
case OPC_JIC:
ctx->hflags |= MIPS_HFLAG_BR;
break;
case OPC_BALC:
tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
- /* Fallthrough */
+ fallthrough;
case OPC_BC:
ctx->hflags |= MIPS_HFLAG_B;
break;
default:
MIPS_INVAL("Compact branch/jump");
gen_reserved_instruction(ctx);
return;
}
/* Generating branch here as compact branches don't have delay slot */
gen_branch(ctx, 4);
} else {
/* Conditional compact branch */
TCGLabel *fs = gen_new_label();
save_cpu_state(ctx, 0);
switch (opc) {
case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */
if (rs == 0 && rt != 0) {
/* OPC_BLEZALC */
tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs);
} else if (rs != 0 && rt != 0 && rs == rt) {
/* OPC_BGEZALC */
tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs);
} else {
/* OPC_BGEUC */
tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU), t0, t1, fs);
}
break;
case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */
if (rs == 0 && rt != 0) {
/* OPC_BGTZALC */
tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs);
} else if (rs != 0 && rt != 0 && rs == rt) {
/* OPC_BLTZALC */
tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs);
} else {
/* OPC_BLTUC */
tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU), t0, t1, fs);
}
break;
case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */
if (rs == 0 && rt != 0) {
/* OPC_BLEZC */
tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs);
} else if (rs != 0 && rt != 0 && rs == rt) {
/* OPC_BGEZC */
tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs);
} else {
/* OPC_BGEC */
tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE), t0, t1, fs);
}
break;
case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */
if (rs == 0 && rt != 0) {
/* OPC_BGTZC */
tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs);
} else if (rs != 0 && rt != 0 && rs == rt) {
/* OPC_BLTZC */
tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs);
} else {
/* OPC_BLTC */
tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT), t0, t1, fs);
}
break;
case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */
case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
if (rs >= rt) {
/* OPC_BOVC, OPC_BNVC */
TCGv t2 = tcg_temp_new();
TCGv t3 = tcg_temp_new();
TCGv t4 = tcg_temp_new();
TCGv input_overflow = tcg_temp_new();
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
tcg_gen_ext32s_tl(t2, t0);
tcg_gen_setcond_tl(TCG_COND_NE, input_overflow, t2, t0);
tcg_gen_ext32s_tl(t3, t1);
tcg_gen_setcond_tl(TCG_COND_NE, t4, t3, t1);
tcg_gen_or_tl(input_overflow, input_overflow, t4);
tcg_gen_add_tl(t4, t2, t3);
tcg_gen_ext32s_tl(t4, t4);
tcg_gen_xor_tl(t2, t2, t3);
tcg_gen_xor_tl(t3, t4, t3);
tcg_gen_andc_tl(t2, t3, t2);
tcg_gen_setcondi_tl(TCG_COND_LT, t4, t2, 0);
tcg_gen_or_tl(t4, t4, input_overflow);
if (opc == OPC_BOVC) {
/* OPC_BOVC */
tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t4, 0, fs);
} else {
/* OPC_BNVC */
tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t4, 0, fs);
}
} else if (rs < rt && rs == 0) {
/* OPC_BEQZALC, OPC_BNEZALC */
if (opc == OPC_BEQZALC) {
/* OPC_BEQZALC */
tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t1, 0, fs);
} else {
/* OPC_BNEZALC */
tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t1, 0, fs);
}
} else {
/* OPC_BEQC, OPC_BNEC */
if (opc == OPC_BEQC) {
/* OPC_BEQC */
tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ), t0, t1, fs);
} else {
/* OPC_BNEC */
tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE), t0, t1, fs);
}
}
break;
case OPC_BEQZC:
tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t0, 0, fs);
break;
case OPC_BNEZC:
tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t0, 0, fs);
break;
default:
MIPS_INVAL("Compact conditional branch/jump");
gen_reserved_instruction(ctx);
return;
}
/* Generating branch here as compact branches don't have delay slot */
gen_goto_tb(ctx, 1, ctx->btarget);
gen_set_label(fs);
ctx->hflags |= MIPS_HFLAG_FBNSLOT;
}
}
@@ -13486,198 +13489,198 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
{
int rs, rt, rd, sa;
uint32_t op1;
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
rd = (ctx->opcode >> 11) & 0x1f;
sa = (ctx->opcode >> 6) & 0x1f;
op1 = MASK_SPECIAL(ctx->opcode);
switch (op1) {
case OPC_SLL: /* Shift with immediate */
if (sa == 5 && rd == 0 &&
rs == 0 && rt == 0) { /* PAUSE */
if ((ctx->insn_flags & ISA_MIPS_R6) &&
(ctx->hflags & MIPS_HFLAG_BMASK)) {
gen_reserved_instruction(ctx);
break;
}
}
- /* Fallthrough */
+ fallthrough;
case OPC_SRA:
gen_shift_imm(ctx, op1, rd, rt, sa);
break;
case OPC_SRL:
switch ((ctx->opcode >> 21) & 0x1f) {
case 1:
/* rotr is decoded as srl on non-R2 CPUs */
if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_ROTR;
}
- /* Fallthrough */
+ fallthrough;
case 0:
gen_shift_imm(ctx, op1, rd, rt, sa);
break;
default:
gen_reserved_instruction(ctx);
break;
}
break;
case OPC_ADD:
case OPC_ADDU:
case OPC_SUB:
case OPC_SUBU:
gen_arith(ctx, op1, rd, rs, rt);
break;
case OPC_SLLV: /* Shifts */
case OPC_SRAV:
gen_shift(ctx, op1, rd, rs, rt);
break;
case OPC_SRLV:
switch ((ctx->opcode >> 6) & 0x1f) {
case 1:
/* rotrv is decoded as srlv on non-R2 CPUs */
if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_ROTRV;
}
- /* Fallthrough */
+ fallthrough;
case 0:
gen_shift(ctx, op1, rd, rs, rt);
break;
default:
gen_reserved_instruction(ctx);
break;
}
break;
case OPC_SLT: /* Set on less than */
case OPC_SLTU:
gen_slt(ctx, op1, rd, rs, rt);
break;
case OPC_AND: /* Logic*/
case OPC_OR:
case OPC_NOR:
case OPC_XOR:
gen_logic(ctx, op1, rd, rs, rt);
break;
case OPC_JALR:
gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4);
break;
case OPC_TGE: /* Traps */
case OPC_TGEU:
case OPC_TLT:
case OPC_TLTU:
case OPC_TEQ:
case OPC_TNE:
check_insn(ctx, ISA_MIPS2);
gen_trap(ctx, op1, rs, rt, -1, extract32(ctx->opcode, 6, 10));
break;
case OPC_PMON:
/* Pmon entry point, also R4010 selsl */
#ifdef MIPS_STRICT_STANDARD
MIPS_INVAL("PMON / selsl");
gen_reserved_instruction(ctx);
#else
gen_helper_pmon(tcg_env, tcg_constant_i32(sa));
#endif
break;
case OPC_SYSCALL:
generate_exception_end(ctx, EXCP_SYSCALL);
break;
case OPC_BREAK:
generate_exception_break(ctx, extract32(ctx->opcode, 6, 20));
break;
case OPC_SYNC:
check_insn(ctx, ISA_MIPS2);
gen_sync(extract32(ctx->opcode, 6, 5));
break;
#if defined(TARGET_MIPS64)
/* MIPS64 specific opcodes */
case OPC_DSLL:
case OPC_DSRA:
case OPC_DSLL32:
case OPC_DSRA32:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_shift_imm(ctx, op1, rd, rt, sa);
break;
case OPC_DSRL:
switch ((ctx->opcode >> 21) & 0x1f) {
case 1:
/* drotr is decoded as dsrl on non-R2 CPUs */
if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_DROTR;
}
- /* Fallthrough */
+ fallthrough;
case 0:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_shift_imm(ctx, op1, rd, rt, sa);
break;
default:
gen_reserved_instruction(ctx);
break;
}
break;
case OPC_DSRL32:
switch ((ctx->opcode >> 21) & 0x1f) {
case 1:
/* drotr32 is decoded as dsrl32 on non-R2 CPUs */
if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_DROTR32;
}
- /* Fallthrough */
+ fallthrough;
case 0:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_shift_imm(ctx, op1, rd, rt, sa);
break;
default:
gen_reserved_instruction(ctx);
break;
}
break;
case OPC_DADD:
case OPC_DADDU:
case OPC_DSUB:
case OPC_DSUBU:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_arith(ctx, op1, rd, rs, rt);
break;
case OPC_DSLLV:
case OPC_DSRAV:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_shift(ctx, op1, rd, rs, rt);
break;
case OPC_DSRLV:
switch ((ctx->opcode >> 6) & 0x1f) {
case 1:
/* drotrv is decoded as dsrlv on non-R2 CPUs */
if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_DROTRV;
}
- /* Fallthrough */
+ fallthrough;
case 0:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_shift(ctx, op1, rd, rs, rt);
break;
default:
gen_reserved_instruction(ctx);
break;
}
break;
#endif
default:
if (ctx->insn_flags & ISA_MIPS_R6) {
decode_opc_special_r6(env, ctx);
} else if (ctx->insn_flags & INSN_R5900) {
decode_opc_special_tx79(env, ctx);
} else {
decode_opc_special_legacy(env, ctx);
}
}
}
@@ -14621,700 +14624,700 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
{
int32_t offset;
int rs, rt, rd, sa;
uint32_t op, op1;
int16_t imm;
op = MASK_OP_MAJOR(ctx->opcode);
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
rd = (ctx->opcode >> 11) & 0x1f;
sa = (ctx->opcode >> 6) & 0x1f;
imm = (int16_t)ctx->opcode;
switch (op) {
case OPC_SPECIAL:
decode_opc_special(env, ctx);
break;
case OPC_SPECIAL2:
#if defined(TARGET_MIPS64)
if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
decode_mmi(env, ctx);
break;
}
#endif
if (TARGET_LONG_BITS == 32 && (ctx->insn_flags & ASE_MXU)) {
if (decode_ase_mxu(ctx, ctx->opcode)) {
break;
}
}
decode_opc_special2_legacy(env, ctx);
break;
case OPC_SPECIAL3:
#if defined(TARGET_MIPS64)
if (ctx->insn_flags & INSN_R5900) {
decode_mmi_sq(env, ctx); /* MMI_OPC_SQ */
} else {
decode_opc_special3(env, ctx);
}
#else
decode_opc_special3(env, ctx);
#endif
break;
case OPC_REGIMM:
op1 = MASK_REGIMM(ctx->opcode);
switch (op1) {
case OPC_BLTZL: /* REGIMM branches */
case OPC_BGEZL:
case OPC_BLTZALL:
case OPC_BGEZALL:
check_insn(ctx, ISA_MIPS2);
check_insn_opc_removed(ctx, ISA_MIPS_R6);
- /* Fallthrough */
+ fallthrough;
case OPC_BLTZ:
case OPC_BGEZ:
gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
break;
case OPC_BLTZAL:
case OPC_BGEZAL:
if (ctx->insn_flags & ISA_MIPS_R6) {
if (rs == 0) {
/* OPC_NAL, OPC_BAL */
gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4);
} else {
gen_reserved_instruction(ctx);
}
} else {
gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
}
break;
case OPC_TGEI: /* REGIMM traps */
case OPC_TGEIU:
case OPC_TLTI:
case OPC_TLTIU:
case OPC_TEQI:
case OPC_TNEI:
check_insn(ctx, ISA_MIPS2);
check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_trap(ctx, op1, rs, -1, imm, 0);
break;
case OPC_SIGRIE:
check_insn(ctx, ISA_MIPS_R6);
gen_reserved_instruction(ctx);
break;
case OPC_SYNCI:
check_insn(ctx, ISA_MIPS_R2);
/*
* Break the TB to be able to sync copied instructions
* immediately.
*/
ctx->base.is_jmp = DISAS_STOP;
break;
case OPC_BPOSGE32: /* MIPS DSP branch */
#if defined(TARGET_MIPS64)
case OPC_BPOSGE64:
#endif
check_dsp(ctx);
gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2, 4);
break;
#if defined(TARGET_MIPS64)
case OPC_DAHI:
check_insn(ctx, ISA_MIPS_R6);
check_mips_64(ctx);
if (rs != 0) {
tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 32);
}
break;
case OPC_DATI:
check_insn(ctx, ISA_MIPS_R6);
check_mips_64(ctx);
if (rs != 0) {
tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 48);
}
break;
#endif
default: /* Invalid */
MIPS_INVAL("regimm");
gen_reserved_instruction(ctx);
break;
}
break;
case OPC_CP0:
check_cp0_enabled(ctx);
op1 = MASK_CP0(ctx->opcode);
switch (op1) {
case OPC_MFC0:
case OPC_MTC0:
case OPC_MFTR:
case OPC_MTTR:
case OPC_MFHC0:
case OPC_MTHC0:
#if defined(TARGET_MIPS64)
case OPC_DMFC0:
case OPC_DMTC0:
#endif
#ifndef CONFIG_USER_ONLY
gen_cp0(env, ctx, op1, rt, rd);
#endif /* !CONFIG_USER_ONLY */
break;
case OPC_C0:
case OPC_C0_1:
case OPC_C0_2:
case OPC_C0_3:
case OPC_C0_4:
case OPC_C0_5:
case OPC_C0_6:
case OPC_C0_7:
case OPC_C0_8:
case OPC_C0_9:
case OPC_C0_A:
case OPC_C0_B:
case OPC_C0_C:
case OPC_C0_D:
case OPC_C0_E:
case OPC_C0_F:
#ifndef CONFIG_USER_ONLY
gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
#endif /* !CONFIG_USER_ONLY */
break;
case OPC_MFMC0:
#ifndef CONFIG_USER_ONLY
{
uint32_t op2;
TCGv t0 = tcg_temp_new();
op2 = MASK_MFMC0(ctx->opcode);
switch (op2) {
case OPC_DMT:
check_cp0_mt(ctx);
gen_helper_dmt(t0);
gen_store_gpr(t0, rt);
break;
case OPC_EMT:
check_cp0_mt(ctx);
gen_helper_emt(t0);
gen_store_gpr(t0, rt);
break;
case OPC_DVPE:
check_cp0_mt(ctx);
gen_helper_dvpe(t0, tcg_env);
gen_store_gpr(t0, rt);
break;
case OPC_EVPE:
check_cp0_mt(ctx);
gen_helper_evpe(t0, tcg_env);
gen_store_gpr(t0, rt);
break;
case OPC_DVP:
check_insn(ctx, ISA_MIPS_R6);
if (ctx->vp) {
gen_helper_dvp(t0, tcg_env);
gen_store_gpr(t0, rt);
}
break;
case OPC_EVP:
check_insn(ctx, ISA_MIPS_R6);
if (ctx->vp) {
gen_helper_evp(t0, tcg_env);
gen_store_gpr(t0, rt);
}
break;
case OPC_DI:
check_insn(ctx, ISA_MIPS_R2);
save_cpu_state(ctx, 1);
gen_helper_di(t0, tcg_env);
gen_store_gpr(t0, rt);
/*
* Stop translation as we may have switched
* the execution mode.
*/
ctx->base.is_jmp = DISAS_STOP;
break;
case OPC_EI:
check_insn(ctx, ISA_MIPS_R2);
save_cpu_state(ctx, 1);
gen_helper_ei(t0, tcg_env);
gen_store_gpr(t0, rt);
/*
* DISAS_STOP isn't sufficient, we need to ensure we break
* out of translated code to check for pending interrupts.
*/
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
break;
default: /* Invalid */
MIPS_INVAL("mfmc0");
gen_reserved_instruction(ctx);
break;
}
}
#endif /* !CONFIG_USER_ONLY */
break;
case OPC_RDPGPR:
check_insn(ctx, ISA_MIPS_R2);
gen_load_srsgpr(rt, rd);
break;
case OPC_WRPGPR:
check_insn(ctx, ISA_MIPS_R2);
gen_store_srsgpr(rt, rd);
break;
default:
MIPS_INVAL("cp0");
gen_reserved_instruction(ctx);
break;
}
break;
case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC, OPC_ADDI */
if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_BOVC, OPC_BEQZALC, OPC_BEQC */
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
} else {
/* OPC_ADDI */
/* Arithmetic with immediate opcode */
gen_arith_imm(ctx, op, rt, rs, imm);
}
break;
case OPC_ADDIU:
gen_arith_imm(ctx, op, rt, rs, imm);
break;
case OPC_SLTI: /* Set on less than with immediate opcode */
case OPC_SLTIU:
gen_slt_imm(ctx, op, rt, rs, imm);
break;
case OPC_ANDI: /* Arithmetic with immediate opcode */
case OPC_LUI: /* OPC_AUI */
case OPC_ORI:
case OPC_XORI:
gen_logic_imm(ctx, op, rt, rs, imm);
break;
case OPC_J: /* Jump */
case OPC_JAL:
offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
break;
/* Branch */
case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */
if (ctx->insn_flags & ISA_MIPS_R6) {
if (rt == 0) {
gen_reserved_instruction(ctx);
break;
}
/* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
} else {
/* OPC_BLEZL */
gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
}
break;
case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */
if (ctx->insn_flags & ISA_MIPS_R6) {
if (rt == 0) {
gen_reserved_instruction(ctx);
break;
}
/* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
} else {
/* OPC_BGTZL */
gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
}
break;
case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC, OPC_BLEZ */
if (rt == 0) {
/* OPC_BLEZ */
gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
} else {
check_insn(ctx, ISA_MIPS_R6);
/* OPC_BLEZALC, OPC_BGEZALC, OPC_BGEUC */
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
}
break;
case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC, OPC_BGTZ */
if (rt == 0) {
/* OPC_BGTZ */
gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
} else {
check_insn(ctx, ISA_MIPS_R6);
/* OPC_BGTZALC, OPC_BLTZALC, OPC_BLTUC */
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
}
break;
case OPC_BEQL:
case OPC_BNEL:
check_insn(ctx, ISA_MIPS2);
check_insn_opc_removed(ctx, ISA_MIPS_R6);
- /* Fallthrough */
+ fallthrough;
case OPC_BEQ:
case OPC_BNE:
gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
break;
case OPC_LL: /* Load and stores */
check_insn(ctx, ISA_MIPS2);
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
- /* Fallthrough */
+ fallthrough;
case OPC_LWL:
case OPC_LWR:
case OPC_LB:
case OPC_LH:
case OPC_LW:
case OPC_LWPC:
case OPC_LBU:
case OPC_LHU:
gen_ld(ctx, op, rt, rs, imm);
break;
case OPC_SWL:
case OPC_SWR:
case OPC_SB:
case OPC_SH:
case OPC_SW:
gen_st(ctx, op, rt, rs, imm);
break;
case OPC_SC:
check_insn(ctx, ISA_MIPS2);
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
gen_st_cond(ctx, rt, rs, imm, MO_TESL, false);
break;
case OPC_CACHE:
check_cp0_enabled(ctx);
check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1);
if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
gen_cache_operation(ctx, rt, rs, imm);
}
/* Treat as NOP. */
break;
case OPC_PREF:
check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | INSN_R5900);
/* Treat as NOP. */
break;
/* Floating point (COP1). */
case OPC_LWC1:
case OPC_LDC1:
case OPC_SWC1:
case OPC_SDC1:
gen_cop1_ldst(ctx, op, rt, rs, imm);
break;
case OPC_CP1:
op1 = MASK_CP1(ctx->opcode);
switch (op1) {
case OPC_MFHC1:
case OPC_MTHC1:
check_cp1_enabled(ctx);
check_insn(ctx, ISA_MIPS_R2);
- /* fall through */
+ fallthrough;
case OPC_MFC1:
case OPC_CFC1:
case OPC_MTC1:
case OPC_CTC1:
check_cp1_enabled(ctx);
gen_cp1(ctx, op1, rt, rd);
break;
#if defined(TARGET_MIPS64)
case OPC_DMFC1:
case OPC_DMTC1:
check_cp1_enabled(ctx);
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_cp1(ctx, op1, rt, rd);
break;
#endif
case OPC_BC1EQZ: /* OPC_BC1ANY2 */
check_cp1_enabled(ctx);
if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_BC1EQZ */
gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode),
rt, imm << 2, 4);
} else {
/* OPC_BC1ANY2 */
check_cop1x(ctx);
check_insn(ctx, ASE_MIPS3D);
gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
(rt >> 2) & 0x7, imm << 2);
}
break;
case OPC_BC1NEZ:
check_cp1_enabled(ctx);
check_insn(ctx, ISA_MIPS_R6);
gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode),
rt, imm << 2, 4);
break;
case OPC_BC1ANY4:
check_cp1_enabled(ctx);
check_insn_opc_removed(ctx, ISA_MIPS_R6);
check_cop1x(ctx);
check_insn(ctx, ASE_MIPS3D);
- /* fall through */
+ fallthrough;
case OPC_BC1:
check_cp1_enabled(ctx);
check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
(rt >> 2) & 0x7, imm << 2);
break;
case OPC_PS_FMT:
check_ps(ctx);
- /* fall through */
+ fallthrough;
case OPC_S_FMT:
case OPC_D_FMT:
check_cp1_enabled(ctx);
gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa,
(imm >> 8) & 0x7);
break;
case OPC_W_FMT:
case OPC_L_FMT:
{
int r6_op = ctx->opcode & FOP(0x3f, 0x1f);
check_cp1_enabled(ctx);
if (ctx->insn_flags & ISA_MIPS_R6) {
switch (r6_op) {
case R6_OPC_CMP_AF_S:
case R6_OPC_CMP_UN_S:
case R6_OPC_CMP_EQ_S:
case R6_OPC_CMP_UEQ_S:
case R6_OPC_CMP_LT_S:
case R6_OPC_CMP_ULT_S:
case R6_OPC_CMP_LE_S:
case R6_OPC_CMP_ULE_S:
case R6_OPC_CMP_SAF_S:
case R6_OPC_CMP_SUN_S:
case R6_OPC_CMP_SEQ_S:
case R6_OPC_CMP_SEUQ_S:
case R6_OPC_CMP_SLT_S:
case R6_OPC_CMP_SULT_S:
case R6_OPC_CMP_SLE_S:
case R6_OPC_CMP_SULE_S:
case R6_OPC_CMP_OR_S:
case R6_OPC_CMP_UNE_S:
case R6_OPC_CMP_NE_S:
case R6_OPC_CMP_SOR_S:
case R6_OPC_CMP_SUNE_S:
case R6_OPC_CMP_SNE_S:
gen_r6_cmp_s(ctx, ctx->opcode & 0x1f, rt, rd, sa);
break;
case R6_OPC_CMP_AF_D:
case R6_OPC_CMP_UN_D:
case R6_OPC_CMP_EQ_D:
case R6_OPC_CMP_UEQ_D:
case R6_OPC_CMP_LT_D:
case R6_OPC_CMP_ULT_D:
case R6_OPC_CMP_LE_D:
case R6_OPC_CMP_ULE_D:
case R6_OPC_CMP_SAF_D:
case R6_OPC_CMP_SUN_D:
case R6_OPC_CMP_SEQ_D:
case R6_OPC_CMP_SEUQ_D:
case R6_OPC_CMP_SLT_D:
case R6_OPC_CMP_SULT_D:
case R6_OPC_CMP_SLE_D:
case R6_OPC_CMP_SULE_D:
case R6_OPC_CMP_OR_D:
case R6_OPC_CMP_UNE_D:
case R6_OPC_CMP_NE_D:
case R6_OPC_CMP_SOR_D:
case R6_OPC_CMP_SUNE_D:
case R6_OPC_CMP_SNE_D:
gen_r6_cmp_d(ctx, ctx->opcode & 0x1f, rt, rd, sa);
break;
default:
gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f),
rt, rd, sa, (imm >> 8) & 0x7);
break;
}
} else {
gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa,
(imm >> 8) & 0x7);
}
break;
}
default:
MIPS_INVAL("cp1");
gen_reserved_instruction(ctx);
break;
}
break;
/* Compact branches [R6] and COP2 [non-R6] */
case OPC_BC: /* OPC_LWC2 */
case OPC_BALC: /* OPC_SWC2 */
if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_BC, OPC_BALC */
gen_compute_compact_branch(ctx, op, 0, 0,
sextract32(ctx->opcode << 2, 0, 28));
} else if (ctx->insn_flags & ASE_LEXT) {
gen_loongson_lswc2(ctx, rt, rs, rd);
} else {
/* OPC_LWC2, OPC_SWC2 */
/* COP2: Not implemented. */
generate_exception_err(ctx, EXCP_CpU, 2);
}
break;
case OPC_BEQZC: /* OPC_JIC, OPC_LDC2 */
case OPC_BNEZC: /* OPC_JIALC, OPC_SDC2 */
if (ctx->insn_flags & ISA_MIPS_R6) {
if (rs != 0) {
/* OPC_BEQZC, OPC_BNEZC */
gen_compute_compact_branch(ctx, op, rs, 0,
sextract32(ctx->opcode << 2, 0, 23));
} else {
/* OPC_JIC, OPC_JIALC */
gen_compute_compact_branch(ctx, op, 0, rt, imm);
}
} else if (ctx->insn_flags & ASE_LEXT) {
gen_loongson_lsdc2(ctx, rt, rs, rd);
} else {
/* OPC_LWC2, OPC_SWC2 */
/* COP2: Not implemented. */
generate_exception_err(ctx, EXCP_CpU, 2);
}
break;
case OPC_CP2:
check_insn(ctx, ASE_LMMI);
/* Note that these instructions use different fields. */
gen_loongson_multimedia(ctx, sa, rd, rt);
break;
case OPC_CP3:
if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
op1 = MASK_CP3(ctx->opcode);
switch (op1) {
case OPC_LUXC1:
case OPC_SUXC1:
check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2);
- /* Fallthrough */
+ fallthrough;
case OPC_LWXC1:
case OPC_LDXC1:
case OPC_SWXC1:
case OPC_SDXC1:
check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
gen_flt3_ldst(ctx, op1, sa, rd, rs, rt);
break;
case OPC_PREFX:
check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
/* Treat as NOP. */
break;
case OPC_ALNV_PS:
check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2);
- /* Fallthrough */
+ fallthrough;
case OPC_MADD_S:
case OPC_MADD_D:
case OPC_MADD_PS:
case OPC_MSUB_S:
case OPC_MSUB_D:
case OPC_MSUB_PS:
case OPC_NMADD_S:
case OPC_NMADD_D:
case OPC_NMADD_PS:
case OPC_NMSUB_S:
case OPC_NMSUB_D:
case OPC_NMSUB_PS:
check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
gen_flt3_arith(ctx, op1, sa, rs, rd, rt);
break;
default:
MIPS_INVAL("cp3");
gen_reserved_instruction(ctx);
break;
}
} else {
generate_exception_err(ctx, EXCP_CpU, 1);
}
break;
#if defined(TARGET_MIPS64)
/* MIPS64 opcodes */
case OPC_LLD:
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
- /* fall through */
+ fallthrough;
case OPC_LDL:
case OPC_LDR:
case OPC_LWU:
case OPC_LD:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_ld(ctx, op, rt, rs, imm);
break;
case OPC_SDL:
case OPC_SDR:
case OPC_SD:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_st(ctx, op, rt, rs, imm);
break;
case OPC_SCD:
check_insn(ctx, ISA_MIPS3);
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
check_mips_64(ctx);
gen_st_cond(ctx, rt, rs, imm, MO_TEUQ, false);
break;
case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */
if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
} else {
/* OPC_DADDI */
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_arith_imm(ctx, op, rt, rs, imm);
}
break;
case OPC_DADDIU:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_arith_imm(ctx, op, rt, rs, imm);
break;
#else
case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
if (ctx->insn_flags & ISA_MIPS_R6) {
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
} else {
MIPS_INVAL("major opcode");
gen_reserved_instruction(ctx);
}
break;
#endif
case OPC_DAUI: /* OPC_JALX */
if (ctx->insn_flags & ISA_MIPS_R6) {
#if defined(TARGET_MIPS64)
/* OPC_DAUI */
check_mips_64(ctx);
if (rs == 0) {
generate_exception(ctx, EXCP_RI);
} else if (rt != 0) {
TCGv t0 = tcg_temp_new();
gen_load_gpr(t0, rs);
tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16);
}
#else
gen_reserved_instruction(ctx);
MIPS_INVAL("major opcode");
#endif
} else {
/* OPC_JALX */
check_insn(ctx, ASE_MIPS16 | ASE_MICROMIPS);
offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
}
break;
case OPC_MDMX:
/* MDMX: Not implemented. */
break;
case OPC_PCREL:
check_insn(ctx, ISA_MIPS_R6);
gen_pcrel(ctx, ctx->opcode, ctx->base.pc_next, rs);
break;
default: /* Invalid */
MIPS_INVAL("major opcode");
return false;
}
return true;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 21/78] target/sparc: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (19 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 20/78] target/mips: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 22/78] target/ppc: " Emmanouil Pitsidianakis
` (57 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Mark Cave-Ayland, Artyom Tarasenko
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
target/sparc/ldst_helper.c | 4 ++--
target/sparc/mmu_helper.c | 6 +++---
target/sparc/translate.c | 3 ++-
target/sparc/win_helper.c | 1 +
4 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 78b03308ae..b233e40da5 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -1296,294 +1296,294 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
int asi, uint32_t memop)
{
int size = 1 << (memop & MO_SIZE);
int sign = memop & MO_SIGN;
CPUState *cs = env_cpu(env);
uint64_t ret = 0;
#if defined(DEBUG_ASI)
target_ulong last_addr = addr;
#endif
asi &= 0xff;
do_check_asi(env, asi, GETPC());
do_check_align(env, addr, size - 1, GETPC());
addr = asi_address_mask(env, asi, addr);
switch (asi) {
case ASI_PNF:
case ASI_PNFL:
case ASI_SNF:
case ASI_SNFL:
{
MemOpIdx oi;
int idx = (env->pstate & PS_PRIV
? (asi & 1 ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX)
: (asi & 1 ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX));
if (cpu_get_phys_page_nofault(env, addr, idx) == -1ULL) {
#ifdef DEBUG_ASI
dump_asi("read ", last_addr, asi, size, ret);
#endif
/* exception_index is set in get_physical_address_data. */
cpu_raise_exception_ra(env, cs->exception_index, GETPC());
}
oi = make_memop_idx(memop, idx);
switch (size) {
case 1:
ret = cpu_ldb_mmu(env, addr, oi, GETPC());
break;
case 2:
ret = cpu_ldw_mmu(env, addr, oi, GETPC());
break;
case 4:
ret = cpu_ldl_mmu(env, addr, oi, GETPC());
break;
case 8:
ret = cpu_ldq_mmu(env, addr, oi, GETPC());
break;
default:
g_assert_not_reached();
}
}
break;
case ASI_AIUP: /* As if user primary */
case ASI_AIUS: /* As if user secondary */
case ASI_AIUPL: /* As if user primary LE */
case ASI_AIUSL: /* As if user secondary LE */
case ASI_P: /* Primary */
case ASI_S: /* Secondary */
case ASI_PL: /* Primary LE */
case ASI_SL: /* Secondary LE */
case ASI_REAL: /* Bypass */
case ASI_REAL_IO: /* Bypass, non-cacheable */
case ASI_REAL_L: /* Bypass LE */
case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
case ASI_N: /* Nucleus */
case ASI_NL: /* Nucleus Little Endian (LE) */
case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */
case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */
case ASI_TWINX_AIUP: /* As if user primary, twinx */
case ASI_TWINX_AIUS: /* As if user secondary, twinx */
case ASI_TWINX_REAL: /* Real address, twinx */
case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */
case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */
case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
case ASI_TWINX_N: /* Nucleus, twinx */
case ASI_TWINX_NL: /* Nucleus, twinx, LE */
/* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */
case ASI_TWINX_P: /* Primary, twinx */
case ASI_TWINX_PL: /* Primary, twinx, LE */
case ASI_TWINX_S: /* Secondary, twinx */
case ASI_TWINX_SL: /* Secondary, twinx, LE */
/* These are always handled inline. */
g_assert_not_reached();
case ASI_UPA_CONFIG: /* UPA config */
/* XXX */
break;
case ASI_LSU_CONTROL: /* LSU */
ret = env->lsu;
break;
case ASI_IMMU: /* I-MMU regs */
{
int reg = (addr >> 3) & 0xf;
switch (reg) {
case 0:
/* 0x00 I-TSB Tag Target register */
ret = ultrasparc_tag_target(env->immu.tag_access);
break;
case 3: /* SFSR */
ret = env->immu.sfsr;
break;
case 5: /* TSB access */
ret = env->immu.tsb;
break;
case 6:
/* 0x30 I-TSB Tag Access register */
ret = env->immu.tag_access;
break;
default:
sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC());
ret = 0;
}
break;
}
case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer */
{
/* env->immuregs[5] holds I-MMU TSB register value
env->immuregs[6] holds I-MMU Tag Access register value */
ret = ultrasparc_tsb_pointer(env, &env->immu, 0);
break;
}
case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer */
{
/* env->immuregs[5] holds I-MMU TSB register value
env->immuregs[6] holds I-MMU Tag Access register value */
ret = ultrasparc_tsb_pointer(env, &env->immu, 1);
break;
}
case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */
{
int reg = (addr >> 3) & 0x3f;
ret = env->itlb[reg].tte;
break;
}
case ASI_ITLB_TAG_READ: /* I-MMU tag read */
{
int reg = (addr >> 3) & 0x3f;
ret = env->itlb[reg].tag;
break;
}
case ASI_DMMU: /* D-MMU regs */
{
int reg = (addr >> 3) & 0xf;
switch (reg) {
case 0:
/* 0x00 D-TSB Tag Target register */
ret = ultrasparc_tag_target(env->dmmu.tag_access);
break;
case 1: /* 0x08 Primary Context */
ret = env->dmmu.mmu_primary_context;
break;
case 2: /* 0x10 Secondary Context */
ret = env->dmmu.mmu_secondary_context;
break;
case 3: /* SFSR */
ret = env->dmmu.sfsr;
break;
case 4: /* 0x20 SFAR */
ret = env->dmmu.sfar;
break;
case 5: /* 0x28 TSB access */
ret = env->dmmu.tsb;
break;
case 6: /* 0x30 D-TSB Tag Access register */
ret = env->dmmu.tag_access;
break;
case 7:
ret = env->dmmu.virtual_watchpoint;
break;
case 8:
ret = env->dmmu.physical_watchpoint;
break;
default:
sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC());
ret = 0;
}
break;
}
case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer */
{
/* env->dmmuregs[5] holds D-MMU TSB register value
env->dmmuregs[6] holds D-MMU Tag Access register value */
ret = ultrasparc_tsb_pointer(env, &env->dmmu, 0);
break;
}
case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer */
{
/* env->dmmuregs[5] holds D-MMU TSB register value
env->dmmuregs[6] holds D-MMU Tag Access register value */
ret = ultrasparc_tsb_pointer(env, &env->dmmu, 1);
break;
}
case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */
{
int reg = (addr >> 3) & 0x3f;
ret = env->dtlb[reg].tte;
break;
}
case ASI_DTLB_TAG_READ: /* D-MMU tag read */
{
int reg = (addr >> 3) & 0x3f;
ret = env->dtlb[reg].tag;
break;
}
case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */
break;
case ASI_INTR_RECEIVE: /* Interrupt data receive */
ret = env->ivec_status;
break;
case ASI_INTR_R: /* Incoming interrupt vector, RO */
{
int reg = (addr >> 4) & 0x3;
if (reg < 3) {
ret = env->ivec_data[reg];
}
break;
}
case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */
if (unlikely((addr >= 0x20) && (addr < 0x30))) {
/* Hyperprivileged access only */
sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC());
}
- /* fall through */
+ fallthrough;
case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */
{
unsigned int i = (addr >> 3) & 0x7;
ret = env->scratch[i];
break;
}
case ASI_MMU: /* UA2005 Context ID registers */
switch ((addr >> 3) & 0x3) {
case 1:
ret = env->dmmu.mmu_primary_context;
break;
case 2:
ret = env->dmmu.mmu_secondary_context;
break;
default:
sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
}
break;
case ASI_DCACHE_DATA: /* D-cache data */
case ASI_DCACHE_TAG: /* D-cache tag access */
case ASI_ESTATE_ERROR_EN: /* E-cache error enable */
case ASI_AFSR: /* E-cache asynchronous fault status */
case ASI_AFAR: /* E-cache asynchronous fault address */
case ASI_EC_TAG_DATA: /* E-cache tag data */
case ASI_IC_INSTR: /* I-cache instruction access */
case ASI_IC_TAG: /* I-cache tag access */
case ASI_IC_PRE_DECODE: /* I-cache predecode */
case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */
case ASI_EC_W: /* E-cache tag */
case ASI_EC_R: /* E-cache tag */
break;
case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer */
case ASI_ITLB_DATA_IN: /* I-MMU data in, WO */
case ASI_IMMU_DEMAP: /* I-MMU demap, WO */
case ASI_DTLB_DATA_IN: /* D-MMU data in, WO */
case ASI_DMMU_DEMAP: /* D-MMU demap, WO */
case ASI_INTR_W: /* Interrupt vector, WO */
default:
sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC());
ret = 0;
break;
}
/* Convert to signed number */
if (sign) {
switch (size) {
case 1:
ret = (int8_t) ret;
break;
case 2:
ret = (int16_t) ret;
break;
case 4:
ret = (int32_t) ret;
break;
default:
break;
}
}
#ifdef DEBUG_ASI
dump_asi("read ", last_addr, asi, size, ret);
#endif
return ret;
}
@@ -1591,341 +1591,341 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
int asi, uint32_t memop)
{
int size = 1 << (memop & MO_SIZE);
CPUState *cs = env_cpu(env);
#ifdef DEBUG_ASI
dump_asi("write", addr, asi, size, val);
#endif
asi &= 0xff;
do_check_asi(env, asi, GETPC());
do_check_align(env, addr, size - 1, GETPC());
addr = asi_address_mask(env, asi, addr);
switch (asi) {
case ASI_AIUP: /* As if user primary */
case ASI_AIUS: /* As if user secondary */
case ASI_AIUPL: /* As if user primary LE */
case ASI_AIUSL: /* As if user secondary LE */
case ASI_P: /* Primary */
case ASI_S: /* Secondary */
case ASI_PL: /* Primary LE */
case ASI_SL: /* Secondary LE */
case ASI_REAL: /* Bypass */
case ASI_REAL_IO: /* Bypass, non-cacheable */
case ASI_REAL_L: /* Bypass LE */
case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
case ASI_N: /* Nucleus */
case ASI_NL: /* Nucleus Little Endian (LE) */
case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */
case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */
case ASI_TWINX_AIUP: /* As if user primary, twinx */
case ASI_TWINX_AIUS: /* As if user secondary, twinx */
case ASI_TWINX_REAL: /* Real address, twinx */
case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */
case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */
case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
case ASI_TWINX_N: /* Nucleus, twinx */
case ASI_TWINX_NL: /* Nucleus, twinx, LE */
/* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */
case ASI_TWINX_P: /* Primary, twinx */
case ASI_TWINX_PL: /* Primary, twinx, LE */
case ASI_TWINX_S: /* Secondary, twinx */
case ASI_TWINX_SL: /* Secondary, twinx, LE */
/* These are always handled inline. */
g_assert_not_reached();
/* these ASIs have different functions on UltraSPARC-IIIi
* and UA2005 CPUs. Use the explicit numbers to avoid confusion
*/
case 0x31:
case 0x32:
case 0x39:
case 0x3a:
if (cpu_has_hypervisor(env)) {
/* UA2005
* ASI_DMMU_CTX_ZERO_TSB_BASE_PS0
* ASI_DMMU_CTX_ZERO_TSB_BASE_PS1
* ASI_DMMU_CTX_NONZERO_TSB_BASE_PS0
* ASI_DMMU_CTX_NONZERO_TSB_BASE_PS1
*/
int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2);
env->dmmu.sun4v_tsb_pointers[idx] = val;
} else {
helper_raise_exception(env, TT_ILL_INSN);
}
break;
case 0x33:
case 0x3b:
if (cpu_has_hypervisor(env)) {
/* UA2005
* ASI_DMMU_CTX_ZERO_CONFIG
* ASI_DMMU_CTX_NONZERO_CONFIG
*/
env->dmmu.sun4v_ctx_config[(asi & 8) >> 3] = val;
} else {
helper_raise_exception(env, TT_ILL_INSN);
}
break;
case 0x35:
case 0x36:
case 0x3d:
case 0x3e:
if (cpu_has_hypervisor(env)) {
/* UA2005
* ASI_IMMU_CTX_ZERO_TSB_BASE_PS0
* ASI_IMMU_CTX_ZERO_TSB_BASE_PS1
* ASI_IMMU_CTX_NONZERO_TSB_BASE_PS0
* ASI_IMMU_CTX_NONZERO_TSB_BASE_PS1
*/
int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2);
env->immu.sun4v_tsb_pointers[idx] = val;
} else {
helper_raise_exception(env, TT_ILL_INSN);
}
break;
case 0x37:
case 0x3f:
if (cpu_has_hypervisor(env)) {
/* UA2005
* ASI_IMMU_CTX_ZERO_CONFIG
* ASI_IMMU_CTX_NONZERO_CONFIG
*/
env->immu.sun4v_ctx_config[(asi & 8) >> 3] = val;
} else {
helper_raise_exception(env, TT_ILL_INSN);
}
break;
case ASI_UPA_CONFIG: /* UPA config */
/* XXX */
return;
case ASI_LSU_CONTROL: /* LSU */
env->lsu = val & (DMMU_E | IMMU_E);
return;
case ASI_IMMU: /* I-MMU regs */
{
int reg = (addr >> 3) & 0xf;
uint64_t oldreg;
oldreg = env->immu.mmuregs[reg];
switch (reg) {
case 0: /* RO */
return;
case 1: /* Not in I-MMU */
case 2:
return;
case 3: /* SFSR */
if ((val & 1) == 0) {
val = 0; /* Clear SFSR */
}
env->immu.sfsr = val;
break;
case 4: /* RO */
return;
case 5: /* TSB access */
DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
PRIx64 "\n", env->immu.tsb, val);
env->immu.tsb = val;
break;
case 6: /* Tag access */
env->immu.tag_access = val;
break;
case 7:
case 8:
return;
default:
sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
break;
}
if (oldreg != env->immu.mmuregs[reg]) {
DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
}
#ifdef DEBUG_MMU
dump_mmu(env);
#endif
return;
}
case ASI_ITLB_DATA_IN: /* I-MMU data in */
/* ignore real translation entries */
if (!(addr & TLB_UST1_IS_REAL_BIT)) {
replace_tlb_1bit_lru(env->itlb, env->immu.tag_access,
val, "immu", env, addr);
}
return;
case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */
{
/* TODO: auto demap */
unsigned int i = (addr >> 3) & 0x3f;
/* ignore real translation entries */
if (!(addr & TLB_UST1_IS_REAL_BIT)) {
replace_tlb_entry(&env->itlb[i], env->immu.tag_access,
sun4v_tte_to_sun4u(env, addr, val), env);
}
#ifdef DEBUG_MMU
DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
dump_mmu(env);
#endif
return;
}
case ASI_IMMU_DEMAP: /* I-MMU demap */
demap_tlb(env->itlb, addr, "immu", env);
return;
case ASI_DMMU: /* D-MMU regs */
{
int reg = (addr >> 3) & 0xf;
uint64_t oldreg;
oldreg = env->dmmu.mmuregs[reg];
switch (reg) {
case 0: /* RO */
case 4:
return;
case 3: /* SFSR */
if ((val & 1) == 0) {
val = 0; /* Clear SFSR, Fault address */
env->dmmu.sfar = 0;
}
env->dmmu.sfsr = val;
break;
case 1: /* Primary context */
env->dmmu.mmu_primary_context = val;
/* can be optimized to only flush MMU_USER_IDX
and MMU_KERNEL_IDX entries */
tlb_flush(cs);
break;
case 2: /* Secondary context */
env->dmmu.mmu_secondary_context = val;
/* can be optimized to only flush MMU_USER_SECONDARY_IDX
and MMU_KERNEL_SECONDARY_IDX entries */
tlb_flush(cs);
break;
case 5: /* TSB access */
DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
PRIx64 "\n", env->dmmu.tsb, val);
env->dmmu.tsb = val;
break;
case 6: /* Tag access */
env->dmmu.tag_access = val;
break;
case 7: /* Virtual Watchpoint */
env->dmmu.virtual_watchpoint = val;
break;
case 8: /* Physical Watchpoint */
env->dmmu.physical_watchpoint = val;
break;
default:
sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
break;
}
if (oldreg != env->dmmu.mmuregs[reg]) {
DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
}
#ifdef DEBUG_MMU
dump_mmu(env);
#endif
return;
}
case ASI_DTLB_DATA_IN: /* D-MMU data in */
/* ignore real translation entries */
if (!(addr & TLB_UST1_IS_REAL_BIT)) {
replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access,
val, "dmmu", env, addr);
}
return;
case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */
{
unsigned int i = (addr >> 3) & 0x3f;
/* ignore real translation entries */
if (!(addr & TLB_UST1_IS_REAL_BIT)) {
replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access,
sun4v_tte_to_sun4u(env, addr, val), env);
}
#ifdef DEBUG_MMU
DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
dump_mmu(env);
#endif
return;
}
case ASI_DMMU_DEMAP: /* D-MMU demap */
demap_tlb(env->dtlb, addr, "dmmu", env);
return;
case ASI_INTR_RECEIVE: /* Interrupt data receive */
env->ivec_status = val & 0x20;
return;
case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */
if (unlikely((addr >= 0x20) && (addr < 0x30))) {
/* Hyperprivileged access only */
sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
}
- /* fall through */
+ fallthrough;
case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */
{
unsigned int i = (addr >> 3) & 0x7;
env->scratch[i] = val;
return;
}
case ASI_MMU: /* UA2005 Context ID registers */
{
switch ((addr >> 3) & 0x3) {
case 1:
env->dmmu.mmu_primary_context = val;
env->immu.mmu_primary_context = val;
tlb_flush_by_mmuidx(cs,
(1 << MMU_USER_IDX) | (1 << MMU_KERNEL_IDX));
break;
case 2:
env->dmmu.mmu_secondary_context = val;
env->immu.mmu_secondary_context = val;
tlb_flush_by_mmuidx(cs,
(1 << MMU_USER_SECONDARY_IDX) |
(1 << MMU_KERNEL_SECONDARY_IDX));
break;
default:
sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
}
}
return;
case ASI_QUEUE: /* UA2005 CPU mondo queue */
case ASI_DCACHE_DATA: /* D-cache data */
case ASI_DCACHE_TAG: /* D-cache tag access */
case ASI_ESTATE_ERROR_EN: /* E-cache error enable */
case ASI_AFSR: /* E-cache asynchronous fault status */
case ASI_AFAR: /* E-cache asynchronous fault address */
case ASI_EC_TAG_DATA: /* E-cache tag data */
case ASI_IC_INSTR: /* I-cache instruction access */
case ASI_IC_TAG: /* I-cache tag access */
case ASI_IC_PRE_DECODE: /* I-cache predecode */
case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */
case ASI_EC_W: /* E-cache tag */
case ASI_EC_R: /* E-cache tag */
return;
case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer, RO */
case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer, RO */
case ASI_ITLB_TAG_READ: /* I-MMU tag read, RO */
case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer, RO */
case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer, RO */
case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer, RO */
case ASI_DTLB_TAG_READ: /* D-MMU tag read, RO */
case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */
case ASI_INTR_R: /* Incoming interrupt vector, RO */
case ASI_PNF: /* Primary no-fault, RO */
case ASI_SNF: /* Secondary no-fault, RO */
case ASI_PNFL: /* Primary no-fault LE, RO */
case ASI_SNFL: /* Secondary no-fault LE, RO */
default:
sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
return;
}
}
#endif /* CONFIG_USER_ONLY */
#endif /* TARGET_SPARC64 */
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index 453498c670..13f0430c5d 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -545,99 +545,99 @@ static uint64_t build_sfsr(CPUSPARCState *env, int mmu_idx, int rw)
static int get_physical_address_data(CPUSPARCState *env, CPUTLBEntryFull *full,
target_ulong address, int rw, int mmu_idx)
{
CPUState *cs = env_cpu(env);
unsigned int i;
uint64_t sfsr;
uint64_t context;
bool is_user = false;
sfsr = build_sfsr(env, mmu_idx, rw);
switch (mmu_idx) {
case MMU_PHYS_IDX:
g_assert_not_reached();
case MMU_USER_IDX:
is_user = true;
- /* fallthru */
+ fallthrough;
case MMU_KERNEL_IDX:
context = env->dmmu.mmu_primary_context & 0x1fff;
break;
case MMU_USER_SECONDARY_IDX:
is_user = true;
- /* fallthru */
+ fallthrough;
case MMU_KERNEL_SECONDARY_IDX:
context = env->dmmu.mmu_secondary_context & 0x1fff;
break;
default:
context = 0;
break;
}
for (i = 0; i < 64; i++) {
/* ctx match, vaddr match, valid? */
if (ultrasparc_tag_match(&env->dtlb[i], address, context,
&full->phys_addr)) {
int do_fault = 0;
if (TTE_IS_IE(env->dtlb[i].tte)) {
full->attrs.byte_swap = true;
}
/* access ok? */
/* multiple bits in SFSR.FT may be set on TT_DFAULT */
if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) {
do_fault = 1;
sfsr |= SFSR_FT_PRIV_BIT; /* privilege violation */
trace_mmu_helper_dfault(address, context, mmu_idx, env->tl);
}
if (rw == 4) {
if (TTE_IS_SIDEEFFECT(env->dtlb[i].tte)) {
do_fault = 1;
sfsr |= SFSR_FT_NF_E_BIT;
}
} else {
if (TTE_IS_NFO(env->dtlb[i].tte)) {
do_fault = 1;
sfsr |= SFSR_FT_NFO_BIT;
}
}
if (do_fault) {
/* faults above are reported with TT_DFAULT. */
cs->exception_index = TT_DFAULT;
} else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) {
do_fault = 1;
cs->exception_index = TT_DPROT;
trace_mmu_helper_dprot(address, context, mmu_idx, env->tl);
}
if (!do_fault) {
full->prot = PAGE_READ;
if (TTE_IS_W_OK(env->dtlb[i].tte)) {
full->prot |= PAGE_WRITE;
}
TTE_SET_USED(env->dtlb[i].tte);
return 0;
}
env->dmmu.sfsr = sfsr;
env->dmmu.sfar = address; /* Fault address register */
env->dmmu.tag_access = (address & ~0x1fffULL) | context;
return 1;
}
}
trace_mmu_helper_dmiss(address, context);
/*
* On MMU misses:
* - UltraSPARC IIi: SFSR and SFAR unmodified
* - JPS1: SFAR updated and some fields of SFSR updated
*/
env->dmmu.tag_access = (address & ~0x1fffULL) | context;
cs->exception_index = TT_DMISS;
return 1;
}
@@ -645,75 +645,75 @@ static int get_physical_address_data(CPUSPARCState *env, CPUTLBEntryFull *full,
static int get_physical_address_code(CPUSPARCState *env, CPUTLBEntryFull *full,
target_ulong address, int mmu_idx)
{
CPUState *cs = env_cpu(env);
unsigned int i;
uint64_t context;
bool is_user = false;
switch (mmu_idx) {
case MMU_PHYS_IDX:
case MMU_USER_SECONDARY_IDX:
case MMU_KERNEL_SECONDARY_IDX:
g_assert_not_reached();
case MMU_USER_IDX:
is_user = true;
- /* fallthru */
+ fallthrough;
case MMU_KERNEL_IDX:
context = env->dmmu.mmu_primary_context & 0x1fff;
break;
default:
context = 0;
break;
}
if (env->tl == 0) {
/* PRIMARY context */
context = env->dmmu.mmu_primary_context & 0x1fff;
} else {
/* NUCLEUS context */
context = 0;
}
for (i = 0; i < 64; i++) {
/* ctx match, vaddr match, valid? */
if (ultrasparc_tag_match(&env->itlb[i],
address, context, &full->phys_addr)) {
/* access ok? */
if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) {
/* Fault status register */
if (env->immu.sfsr & SFSR_VALID_BIT) {
env->immu.sfsr = SFSR_OW_BIT; /* overflow (not read before
another fault) */
} else {
env->immu.sfsr = 0;
}
if (env->pstate & PS_PRIV) {
env->immu.sfsr |= SFSR_PR_BIT;
}
if (env->tl > 0) {
env->immu.sfsr |= SFSR_CT_NUCLEUS;
}
/* FIXME: ASI field in SFSR must be set */
env->immu.sfsr |= SFSR_FT_PRIV_BIT | SFSR_VALID_BIT;
cs->exception_index = TT_TFAULT;
env->immu.tag_access = (address & ~0x1fffULL) | context;
trace_mmu_helper_tfault(address, context);
return 1;
}
full->prot = PAGE_EXEC;
TTE_SET_USED(env->itlb[i].tte);
return 0;
}
}
trace_mmu_helper_tmiss(address, context);
/* Context is stored in DMMU (dmmuregs[1]) also for IMMU */
env->immu.tag_access = (address & ~0x1fffULL) | context;
cs->exception_index = TT_TMISS;
return 1;
}
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index f92ff80ac8..4f179473d7 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -1020,167 +1020,168 @@ static void gen_op_next_insn(void)
static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
DisasContext *dc)
{
static int subcc_cond[16] = {
TCG_COND_NEVER,
TCG_COND_EQ,
TCG_COND_LE,
TCG_COND_LT,
TCG_COND_LEU,
TCG_COND_LTU,
-1, /* neg */
-1, /* overflow */
TCG_COND_ALWAYS,
TCG_COND_NE,
TCG_COND_GT,
TCG_COND_GE,
TCG_COND_GTU,
TCG_COND_GEU,
-1, /* pos */
-1, /* no overflow */
};
static int logic_cond[16] = {
TCG_COND_NEVER,
TCG_COND_EQ, /* eq: Z */
TCG_COND_LE, /* le: Z | (N ^ V) -> Z | N */
TCG_COND_LT, /* lt: N ^ V -> N */
TCG_COND_EQ, /* leu: C | Z -> Z */
TCG_COND_NEVER, /* ltu: C -> 0 */
TCG_COND_LT, /* neg: N */
TCG_COND_NEVER, /* vs: V -> 0 */
TCG_COND_ALWAYS,
TCG_COND_NE, /* ne: !Z */
TCG_COND_GT, /* gt: !(Z | (N ^ V)) -> !(Z | N) */
TCG_COND_GE, /* ge: !(N ^ V) -> !N */
TCG_COND_NE, /* gtu: !(C | Z) -> !Z */
TCG_COND_ALWAYS, /* geu: !C -> 1 */
TCG_COND_GE, /* pos: !N */
TCG_COND_ALWAYS, /* vc: !V -> 1 */
};
TCGv_i32 r_src;
TCGv r_dst;
#ifdef TARGET_SPARC64
if (xcc) {
r_src = cpu_xcc;
} else {
r_src = cpu_psr;
}
#else
r_src = cpu_psr;
#endif
switch (dc->cc_op) {
case CC_OP_LOGIC:
cmp->cond = logic_cond[cond];
do_compare_dst_0:
cmp->is_bool = false;
cmp->c2 = tcg_constant_tl(0);
#ifdef TARGET_SPARC64
if (!xcc) {
cmp->c1 = tcg_temp_new();
tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst);
break;
}
#endif
cmp->c1 = cpu_cc_dst;
break;
case CC_OP_SUB:
switch (cond) {
case 6: /* neg */
case 14: /* pos */
cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE);
goto do_compare_dst_0;
case 7: /* overflow */
case 15: /* !overflow */
goto do_dynamic;
default:
cmp->cond = subcc_cond[cond];
cmp->is_bool = false;
#ifdef TARGET_SPARC64
if (!xcc) {
/* Note that sign-extension works for unsigned compares as
long as both operands are sign-extended. */
cmp->c1 = tcg_temp_new();
cmp->c2 = tcg_temp_new();
tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src);
tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2);
break;
}
#endif
cmp->c1 = cpu_cc_src;
cmp->c2 = cpu_cc_src2;
break;
}
break;
default:
do_dynamic:
gen_helper_compute_psr(tcg_env);
dc->cc_op = CC_OP_FLAGS;
/* FALLTHRU */
+ fallthrough;
case CC_OP_FLAGS:
/* We're going to generate a boolean result. */
cmp->cond = TCG_COND_NE;
cmp->is_bool = true;
cmp->c1 = r_dst = tcg_temp_new();
cmp->c2 = tcg_constant_tl(0);
switch (cond) {
case 0x0:
gen_op_eval_bn(r_dst);
break;
case 0x1:
gen_op_eval_be(r_dst, r_src);
break;
case 0x2:
gen_op_eval_ble(r_dst, r_src);
break;
case 0x3:
gen_op_eval_bl(r_dst, r_src);
break;
case 0x4:
gen_op_eval_bleu(r_dst, r_src);
break;
case 0x5:
gen_op_eval_bcs(r_dst, r_src);
break;
case 0x6:
gen_op_eval_bneg(r_dst, r_src);
break;
case 0x7:
gen_op_eval_bvs(r_dst, r_src);
break;
case 0x8:
gen_op_eval_ba(r_dst);
break;
case 0x9:
gen_op_eval_bne(r_dst, r_src);
break;
case 0xa:
gen_op_eval_bg(r_dst, r_src);
break;
case 0xb:
gen_op_eval_bge(r_dst, r_src);
break;
case 0xc:
gen_op_eval_bgu(r_dst, r_src);
break;
case 0xd:
gen_op_eval_bcc(r_dst, r_src);
break;
case 0xe:
gen_op_eval_bpos(r_dst, r_src);
break;
case 0xf:
gen_op_eval_bvc(r_dst, r_src);
break;
}
break;
}
}
@@ -2186,75 +2187,75 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
int insn, MemOp memop)
{
DisasASI da = get_asi(dc, insn, memop);
switch (da.type) {
case GET_ASI_EXCP:
break;
case GET_ASI_DTWINX: /* Reserved for stda. */
#ifndef TARGET_SPARC64
gen_exception(dc, TT_ILL_INSN);
break;
#else
if (!(dc->def->features & CPU_FEATURE_HYPV)) {
/* Pre OpenSPARC CPUs don't have these */
gen_exception(dc, TT_ILL_INSN);
return;
}
/* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions
* are ST_BLKINIT_ ASIs */
#endif
- /* fall through */
+ fallthrough;
case GET_ASI_DIRECT:
gen_address_mask(dc, addr);
tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop | MO_ALIGN);
break;
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
case GET_ASI_BCOPY:
/* Copy 32 bytes from the address in SRC to ADDR. */
/* ??? The original qemu code suggests 4-byte alignment, dropping
the low bits, but the only place I can see this used is in the
Linux kernel with 32 byte alignment, which would make more sense
as a cacheline-style operation. */
{
TCGv saddr = tcg_temp_new();
TCGv daddr = tcg_temp_new();
TCGv four = tcg_constant_tl(4);
TCGv_i32 tmp = tcg_temp_new_i32();
int i;
tcg_gen_andi_tl(saddr, src, -4);
tcg_gen_andi_tl(daddr, addr, -4);
for (i = 0; i < 32; i += 4) {
/* Since the loads and stores are paired, allow the
copy to happen in the host endianness. */
tcg_gen_qemu_ld_i32(tmp, saddr, da.mem_idx, MO_UL);
tcg_gen_qemu_st_i32(tmp, daddr, da.mem_idx, MO_UL);
tcg_gen_add_tl(saddr, saddr, four);
tcg_gen_add_tl(daddr, daddr, four);
}
}
break;
#endif
default:
{
TCGv_i32 r_asi = tcg_constant_i32(da.asi);
TCGv_i32 r_mop = tcg_constant_i32(memop | MO_ALIGN);
save_state(dc);
#ifdef TARGET_SPARC64
gen_helper_st_asi(tcg_env, addr, src, r_asi, r_mop);
#else
{
TCGv_i64 t64 = tcg_temp_new_i64();
tcg_gen_extu_tl_i64(t64, src);
gen_helper_st_asi(tcg_env, addr, t64, r_asi, r_mop);
}
#endif
/* A write to a TLB register may alter page maps. End the TB. */
dc->npc = DYNAMIC_PC;
}
break;
}
}
diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
index 3a7c0ff943..0c54b63938 100644
--- a/target/sparc/win_helper.c
+++ b/target/sparc/win_helper.c
@@ -296,20 +296,21 @@ void helper_wrcwp(CPUSPARCState *env, target_ulong new_cwp)
static inline uint64_t *get_gregset(CPUSPARCState *env, uint32_t pstate)
{
if (env->def.features & CPU_FEATURE_GL) {
return env->glregs + (env->gl & 7) * 8;
}
switch (pstate) {
default:
trace_win_helper_gregset_error(pstate);
/* fall through to normal set of global registers */
+ fallthrough;
case 0:
return env->bgregs;
case PS_AG:
return env->agregs;
case PS_MG:
return env->mgregs;
case PS_IG:
return env->igregs;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 22/78] target/ppc: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (20 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 21/78] target/sparc: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 23/78] target/arm: " Emmanouil Pitsidianakis
` (56 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Nicholas Piggin, Daniel Henrique Barboza,
Cédric Le Goater, open list:PowerPC TCG CPUs
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
target/ppc/cpu_init.c | 8 ++++----
target/ppc/excp_helper.c | 6 +++---
target/ppc/mmu-radix64.c | 6 +++---
target/ppc/mmu_common.c | 12 ++++++------
target/ppc/translate.c | 6 +++---
5 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 40fe14a6c2..7a7bd4d824 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -840,84 +840,84 @@ static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
/* BookE 2.06 storage control registers */
static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
uint32_t *tlbncfg, uint32_t mmucfg)
{
#if !defined(CONFIG_USER_ONLY)
const char *mas_names[8] = {
"MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
};
int mas_sprn[8] = {
SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
};
int i;
/* TLB assist registers */
for (i = 0; i < 8; i++) {
if (mas_mask & (1 << i)) {
spr_register(env, mas_sprn[i], mas_names[i],
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic,
(i == 2 && (env->insns_flags & PPC_64B))
? &spr_write_generic : &spr_write_generic32,
0x00000000);
}
}
if (env->nb_pids > 1) {
spr_register(env, SPR_BOOKE_PID1, "PID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_booke_pid,
0x00000000);
}
if (env->nb_pids > 2) {
spr_register(env, SPR_BOOKE_PID2, "PID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_booke_pid,
0x00000000);
}
spr_register(env, SPR_BOOKE_EPLC, "EPLC",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_eplc,
0x00000000);
spr_register(env, SPR_BOOKE_EPSC, "EPSC",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_epsc,
0x00000000);
spr_register(env, SPR_MMUCFG, "MMUCFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
mmucfg);
switch (env->nb_ways) {
case 4:
spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
tlbncfg[3]);
- /* Fallthru */
+ fallthrough;
case 3:
spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
tlbncfg[2]);
- /* Fallthru */
+ fallthrough;
case 2:
spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
tlbncfg[1]);
- /* Fallthru */
+ fallthrough;
case 1:
spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
tlbncfg[0]);
- /* Fallthru */
+ fallthrough;
case 0:
default:
break;
}
#endif
}
/* SPR specific to PowerPC 440 implementation */
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 7926114d5c..b8be34051c 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1311,51 +1311,51 @@ static bool is_prefix_insn(CPUPPCState *env, uint32_t insn)
static bool is_prefix_insn_excp(PowerPCCPU *cpu, int excp)
{
CPUPPCState *env = &cpu->env;
if (!tcg_enabled()) {
/*
* This does not load instructions and set the prefix bit correctly
* for injected interrupts with KVM. That may have to be discovered
* and set by the KVM layer before injecting.
*/
return false;
}
switch (excp) {
case POWERPC_EXCP_HDSI:
/* HDSI PRTABLE_FAULT has the originating access type in error_code */
if ((env->spr[SPR_HDSISR] & DSISR_PRTABLE_FAULT) &&
(env->error_code == MMU_INST_FETCH)) {
/*
* Fetch failed due to partition scope translation, so prefix
* indication is not relevant (and attempting to load the
* instruction at NIP would cause recursive faults with the same
* translation).
*/
break;
}
- /* fall through */
+ fallthrough;
case POWERPC_EXCP_MCHECK:
case POWERPC_EXCP_DSI:
case POWERPC_EXCP_DSEG:
case POWERPC_EXCP_ALIGN:
case POWERPC_EXCP_PROGRAM:
case POWERPC_EXCP_FPU:
case POWERPC_EXCP_TRACE:
case POWERPC_EXCP_HV_EMU:
case POWERPC_EXCP_VPU:
case POWERPC_EXCP_VSXU:
case POWERPC_EXCP_FU:
case POWERPC_EXCP_HV_FU: {
uint32_t insn = ppc_ldl_code(env, env->nip);
if (is_prefix_insn(env, insn)) {
return true;
}
break;
}
default:
break;
}
return false;
}
#else
@@ -1368,324 +1368,324 @@ static bool is_prefix_insn_excp(PowerPCCPU *cpu, int excp)
static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
int srr0, srr1, lev = -1;
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
/*
* new interrupt handler msr preserves existing HV and ME unless
* explicitly overridden
*/
new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
/* target registers */
srr0 = SPR_SRR0;
srr1 = SPR_SRR1;
/*
* check for special resume at 0x100 from doze/nap/sleep/winkle on
* P7/P8/P9
*/
if (env->resume_as_sreset) {
excp = powerpc_reset_wakeup(env, excp, &msr);
}
/*
* We don't want to generate a Hypervisor Emulation Assistance
* Interrupt if we don't have HVB in msr_mask (PAPR mode),
* unless running a nested-hv guest, in which case the L1
* kernel wants the interrupt.
*/
if (excp == POWERPC_EXCP_HV_EMU && !(env->msr_mask & MSR_HVB) &&
!books_vhyp_handles_hv_excp(cpu)) {
excp = POWERPC_EXCP_PROGRAM;
}
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
cpu_abort(cs, "Raised an exception without defined vector %d\n",
excp);
}
vector |= env->excp_prefix;
if (is_prefix_insn_excp(cpu, excp)) {
msr |= PPC_BIT(34);
}
switch (excp) {
case POWERPC_EXCP_MCHECK: /* Machine check exception */
powerpc_mcheck_checkstop(env);
if (env->msr_mask & MSR_HVB) {
/*
* ISA specifies HV, but can be delivered to guest with HV
* clear (e.g., see FWNMI in PAPR).
*/
new_msr |= (target_ulong)MSR_HVB;
}
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
msr |= env->error_code;
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
break;
case POWERPC_EXCP_ISI: /* Instruction storage exception */
trace_ppc_excp_isi(msr, env->nip);
msr |= env->error_code;
break;
case POWERPC_EXCP_EXTERNAL: /* External input */
{
bool lpes0;
/*
* LPES0 is only taken into consideration if we support HV
* mode for this CPU.
*/
if (!env->has_hv_mode) {
break;
}
lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
if (!lpes0) {
new_msr |= (target_ulong)MSR_HVB;
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
}
break;
}
case POWERPC_EXCP_ALIGN: /* Alignment exception */
/* Optional DSISR update was removed from ISA v3.0 */
if (!(env->insns_flags2 & PPC2_ISA300)) {
/* Get rS/rD and rA from faulting opcode */
/*
* Note: the opcode fields will not be set properly for a
* direct store load/store, but nobody cares as nobody
* actually uses direct store segments.
*/
env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
}
break;
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
return;
}
/*
* FP exceptions always have NIP pointing to the faulting
* instruction, so always use store_next and claim we are
* precise in the MSR.
*/
msr |= 0x00100000;
break;
case POWERPC_EXCP_INVAL:
trace_ppc_excp_inval(env->nip);
msr |= 0x00080000;
break;
case POWERPC_EXCP_PRIV:
msr |= 0x00040000;
break;
case POWERPC_EXCP_TRAP:
msr |= 0x00020000;
break;
default:
/* Should never occur */
cpu_abort(cs, "Invalid program exception %d. Aborting\n",
env->error_code);
break;
}
break;
case POWERPC_EXCP_SYSCALL: /* System call exception */
lev = env->error_code;
if (lev == 1 && cpu->vhyp) {
dump_hcall(env);
} else {
dump_syscall(env);
}
/*
* We need to correct the NIP which in this case is supposed
* to point to the next instruction
*/
env->nip += 4;
/* "PAPR mode" built-in hypercall emulation */
if (lev == 1 && books_vhyp_handles_hcall(cpu)) {
PPCVirtualHypervisorClass *vhc =
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
vhc->hypercall(cpu->vhyp, cpu);
powerpc_reset_excp_state(cpu);
return;
}
if (env->insns_flags2 & PPC2_ISA310) {
/* ISAv3.1 puts LEV into SRR1 */
msr |= lev << 20;
}
if (lev == 1) {
new_msr |= (target_ulong)MSR_HVB;
}
break;
case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
lev = env->error_code;
dump_syscall(env);
env->nip += 4;
new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
vector += lev * 0x20;
env->lr = env->nip;
env->ctr = msr;
break;
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
case POWERPC_EXCP_DECR: /* Decrementer exception */
break;
case POWERPC_EXCP_RESET: /* System reset exception */
/* A power-saving exception sets ME, otherwise it is unchanged */
if (FIELD_EX64(env->msr, MSR, POW)) {
/* indicate that we resumed from power save mode */
msr |= 0x10000;
new_msr |= ((target_ulong)1 << MSR_ME);
}
if (env->msr_mask & MSR_HVB) {
/*
* ISA specifies HV, but can be delivered to guest with HV
* clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
*/
new_msr |= (target_ulong)MSR_HVB;
} else {
if (FIELD_EX64(env->msr, MSR, POW)) {
cpu_abort(cs, "Trying to deliver power-saving system reset "
"exception %d with no HV support\n", excp);
}
}
break;
case POWERPC_EXCP_TRACE: /* Trace exception */
msr |= env->error_code;
- /* fall through */
+ fallthrough;
case POWERPC_EXCP_DSEG: /* Data segment exception */
case POWERPC_EXCP_ISEG: /* Instruction segment exception */
case POWERPC_EXCP_SDOOR: /* Doorbell interrupt */
case POWERPC_EXCP_PERFM: /* Performance monitor interrupt */
break;
case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
msr |= env->error_code;
- /* fall through */
+ fallthrough;
case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
new_msr |= (target_ulong)MSR_HVB;
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
break;
#ifdef CONFIG_TCG
case POWERPC_EXCP_HV_EMU: {
uint32_t insn = ppc_ldl_code(env, env->nip);
env->spr[SPR_HEIR] = insn;
if (is_prefix_insn(env, insn)) {
uint32_t insn2 = ppc_ldl_code(env, env->nip + 4);
env->spr[SPR_HEIR] <<= 32;
env->spr[SPR_HEIR] |= insn2;
}
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
new_msr |= (target_ulong)MSR_HVB;
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
break;
}
#endif
case POWERPC_EXCP_VPU: /* Vector unavailable exception */
case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
case POWERPC_EXCP_FU: /* Facility unavailable exception */
env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
break;
case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
new_msr |= (target_ulong)MSR_HVB;
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
break;
case POWERPC_EXCP_PERFM_EBB: /* Performance Monitor EBB Exception */
case POWERPC_EXCP_EXTERNAL_EBB: /* External EBB Exception */
env->spr[SPR_BESCR] &= ~BESCR_GE;
/*
* Save NIP for rfebb insn in SPR_EBBRR. Next nip is
* stored in the EBB Handler SPR_EBBHR.
*/
env->spr[SPR_EBBRR] = env->nip;
powerpc_set_excp_state(cpu, env->spr[SPR_EBBHR], env->msr);
/*
* This exception is handled in userspace. No need to proceed.
*/
return;
case POWERPC_EXCP_THERM: /* Thermal interrupt */
case POWERPC_EXCP_VPUA: /* Vector assist exception */
case POWERPC_EXCP_MAINT: /* Maintenance exception */
case POWERPC_EXCP_HV_MAINT: /* Hypervisor Maintenance exception */
cpu_abort(cs, "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
break;
}
/*
* Sort out endianness of interrupt, this differs depending on the
* CPU, the HV mode, etc...
*/
if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
new_msr |= (target_ulong)1 << MSR_LE;
}
new_msr |= (target_ulong)1 << MSR_SF;
if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
/* Save PC */
env->spr[srr0] = env->nip;
/* Save MSR */
env->spr[srr1] = msr;
}
if ((new_msr & MSR_HVB) && books_vhyp_handles_hv_excp(cpu)) {
PPCVirtualHypervisorClass *vhc =
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
/* Deliver interrupt to L1 by returning from the H_ENTER_NESTED call */
vhc->deliver_hv_excp(cpu, excp);
powerpc_reset_excp_state(cpu);
} else {
/* Sanity check */
if (!(env->msr_mask & MSR_HVB) && srr0 == SPR_HSRR0) {
cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
"no HV support\n", excp);
}
/* This can update new_msr and vector if AIL applies */
ppc_excp_apply_ail(cpu, excp, msr, &new_msr, &vector);
powerpc_set_excp_state(cpu, vector, new_msr);
}
}
#else
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index 5823e039e6..a85bd614bf 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -111,30 +111,30 @@ static inline const char *access_str(MMUAccessType access_type)
static void ppc_radix64_raise_si(PowerPCCPU *cpu, MMUAccessType access_type,
vaddr eaddr, uint32_t cause)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
qemu_log_mask(CPU_LOG_MMU, "%s for %s @0x%"VADDR_PRIx" cause %08x\n",
__func__, access_str(access_type),
eaddr, cause);
switch (access_type) {
case MMU_INST_FETCH:
/* Instruction Storage Interrupt */
cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = cause;
break;
case MMU_DATA_STORE:
cause |= DSISR_ISSTORE;
- /* fall through */
+ fallthrough;
case MMU_DATA_LOAD:
/* Data Storage Interrupt */
cs->exception_index = POWERPC_EXCP_DSI;
env->spr[SPR_DSISR] = cause;
env->spr[SPR_DAR] = eaddr;
env->error_code = 0;
break;
default:
g_assert_not_reached();
}
}
@@ -142,39 +142,39 @@ static void ppc_radix64_raise_si(PowerPCCPU *cpu, MMUAccessType access_type,
static void ppc_radix64_raise_hsi(PowerPCCPU *cpu, MMUAccessType access_type,
vaddr eaddr, hwaddr g_raddr, uint32_t cause)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
env->error_code = 0;
if (cause & DSISR_PRTABLE_FAULT) {
/* HDSI PRTABLE_FAULT gets the originating access type in error_code */
env->error_code = access_type;
access_type = MMU_DATA_LOAD;
}
qemu_log_mask(CPU_LOG_MMU, "%s for %s @0x%"VADDR_PRIx" 0x%"
HWADDR_PRIx" cause %08x\n",
__func__, access_str(access_type),
eaddr, g_raddr, cause);
switch (access_type) {
case MMU_INST_FETCH:
/* H Instruction Storage Interrupt */
cs->exception_index = POWERPC_EXCP_HISI;
env->spr[SPR_ASDR] = g_raddr;
env->error_code = cause;
break;
case MMU_DATA_STORE:
cause |= DSISR_ISSTORE;
- /* fall through */
+ fallthrough;
case MMU_DATA_LOAD:
/* H Data Storage Interrupt */
cs->exception_index = POWERPC_EXCP_HDSI;
env->spr[SPR_HDSISR] = cause;
env->spr[SPR_HDAR] = eaddr;
env->spr[SPR_ASDR] = g_raddr;
break;
default:
g_assert_not_reached();
}
}
@@ -222,20 +222,20 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, MMUAccessType access_type,
static int ppc_radix64_check_rc(MMUAccessType access_type, uint64_t pte)
{
switch (access_type) {
case MMU_DATA_STORE:
if (!(pte & R_PTE_C)) {
break;
}
- /* fall through */
+ fallthrough;
case MMU_INST_FETCH:
case MMU_DATA_LOAD:
if (!(pte & R_PTE_R)) {
break;
}
/* R/C bits are already set appropriately for this access */
return 0;
}
return 1;
}
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 6ca5d12207..dd44befe6f 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -67,37 +67,37 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
static int pp_check(int key, int pp, int nx)
{
int access;
/* Compute access rights */
access = 0;
if (key == 0) {
switch (pp) {
case 0x0:
case 0x1:
case 0x2:
access |= PAGE_WRITE;
- /* fall through */
+ fallthrough;
case 0x3:
access |= PAGE_READ;
break;
}
} else {
switch (pp) {
case 0x0:
access = 0;
break;
case 0x1:
case 0x3:
access = PAGE_READ;
break;
case 0x2:
access = PAGE_READ | PAGE_WRITE;
break;
}
}
if (nx == 0) {
access |= PAGE_EXEC;
}
return access;
}
@@ -534,68 +534,68 @@ int ppcemb_tlb_search(CPUPPCState *env, target_ulong address, uint32_t pid)
static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
target_ulong address,
MMUAccessType access_type)
{
ppcemb_tlb_t *tlb;
hwaddr raddr;
int i, ret, zsel, zpr, pr;
ret = -1;
raddr = (hwaddr)-1ULL;
pr = FIELD_EX64(env->msr, MSR, PR);
for (i = 0; i < env->nb_tlb; i++) {
tlb = &env->tlb.tlbe[i];
if (!ppcemb_tlb_check(env, tlb, &raddr, address,
env->spr[SPR_40x_PID], i)) {
continue;
}
zsel = (tlb->attr >> 4) & 0xF;
zpr = (env->spr[SPR_40x_ZPR] >> (30 - (2 * zsel))) & 0x3;
qemu_log_mask(CPU_LOG_MMU,
"%s: TLB %d zsel %d zpr %d ty %d attr %08x\n",
__func__, i, zsel, zpr, access_type, tlb->attr);
/* Check execute enable bit */
switch (zpr) {
case 0x2:
if (pr != 0) {
goto check_perms;
}
- /* fall through */
+ fallthrough;
case 0x3:
/* All accesses granted */
ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
ret = 0;
break;
case 0x0:
if (pr != 0) {
/* Raise Zone protection fault. */
env->spr[SPR_40x_ESR] = 1 << 22;
ctx->prot = 0;
ret = -2;
break;
}
- /* fall through */
+ fallthrough;
case 0x1:
check_perms:
/* Check from TLB entry */
ctx->prot = tlb->prot;
ret = check_prot(ctx->prot, access_type);
if (ret == -2) {
env->spr[SPR_40x_ESR] = 0;
}
break;
}
if (ret >= 0) {
ctx->raddr = raddr;
qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx
" => " HWADDR_FMT_plx
" %d %d\n", __func__, address, ctx->raddr, ctx->prot,
ret);
return 0;
}
}
qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
" => " HWADDR_FMT_plx
" %d %d\n", __func__, address, raddr, ctx->prot, ret);
return ret;
}
@@ -1299,222 +1299,222 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
/* Perform address translation */
/* TODO: Split this by mmu_model. */
static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
MMUAccessType access_type,
hwaddr *raddrp, int *psizep, int *protp,
int mmu_idx, bool guest_visible)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
mmu_ctx_t ctx;
int type;
int ret;
if (access_type == MMU_INST_FETCH) {
/* code access */
type = ACCESS_CODE;
} else if (guest_visible) {
/* data access */
type = env->access_type;
} else {
type = ACCESS_INT;
}
ret = get_physical_address_wtlb(env, &ctx, eaddr, access_type,
type, mmu_idx);
if (ret == 0) {
*raddrp = ctx.raddr;
*protp = ctx.prot;
*psizep = TARGET_PAGE_BITS;
return true;
}
if (guest_visible) {
log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
if (type == ACCESS_CODE) {
switch (ret) {
case -1:
/* No matches in page tables or TLB */
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_6xx:
cs->exception_index = POWERPC_EXCP_IFTLB;
env->error_code = 1 << 18;
env->spr[SPR_IMISS] = eaddr;
env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
goto tlb_miss;
case POWERPC_MMU_SOFT_4xx:
cs->exception_index = POWERPC_EXCP_ITLB;
env->error_code = 0;
env->spr[SPR_40x_DEAR] = eaddr;
env->spr[SPR_40x_ESR] = 0x00000000;
break;
case POWERPC_MMU_BOOKE206:
booke206_update_mas_tlb_miss(env, eaddr, 2, mmu_idx);
- /* fall through */
+ fallthrough;
case POWERPC_MMU_BOOKE:
cs->exception_index = POWERPC_EXCP_ITLB;
env->error_code = 0;
env->spr[SPR_BOOKE_DEAR] = eaddr;
env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, MMU_DATA_LOAD);
break;
case POWERPC_MMU_MPC8xx:
cpu_abort(cs, "MPC8xx MMU model is not implemented\n");
case POWERPC_MMU_REAL:
cpu_abort(cs, "PowerPC in real mode should never raise "
"any MMU exceptions\n");
default:
cpu_abort(cs, "Unknown or invalid MMU model\n");
}
break;
case -2:
/* Access rights violation */
cs->exception_index = POWERPC_EXCP_ISI;
if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
(env->mmu_model == POWERPC_MMU_BOOKE206)) {
env->error_code = 0;
} else {
env->error_code = 0x08000000;
}
break;
case -3:
/* No execute protection violation */
if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
(env->mmu_model == POWERPC_MMU_BOOKE206)) {
env->spr[SPR_BOOKE_ESR] = 0x00000000;
env->error_code = 0;
} else {
env->error_code = 0x10000000;
}
cs->exception_index = POWERPC_EXCP_ISI;
break;
case -4:
/* Direct store exception */
/* No code fetch is allowed in direct-store areas */
cs->exception_index = POWERPC_EXCP_ISI;
if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
(env->mmu_model == POWERPC_MMU_BOOKE206)) {
env->error_code = 0;
} else {
env->error_code = 0x10000000;
}
break;
}
} else {
switch (ret) {
case -1:
/* No matches in page tables or TLB */
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_6xx:
if (access_type == MMU_DATA_STORE) {
cs->exception_index = POWERPC_EXCP_DSTLB;
env->error_code = 1 << 16;
} else {
cs->exception_index = POWERPC_EXCP_DLTLB;
env->error_code = 0;
}
env->spr[SPR_DMISS] = eaddr;
env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
tlb_miss:
env->error_code |= ctx.key << 19;
env->spr[SPR_HASH1] = ppc_hash32_hpt_base(cpu) +
get_pteg_offset32(cpu, ctx.hash[0]);
env->spr[SPR_HASH2] = ppc_hash32_hpt_base(cpu) +
get_pteg_offset32(cpu, ctx.hash[1]);
break;
case POWERPC_MMU_SOFT_4xx:
cs->exception_index = POWERPC_EXCP_DTLB;
env->error_code = 0;
env->spr[SPR_40x_DEAR] = eaddr;
if (access_type == MMU_DATA_STORE) {
env->spr[SPR_40x_ESR] = 0x00800000;
} else {
env->spr[SPR_40x_ESR] = 0x00000000;
}
break;
case POWERPC_MMU_MPC8xx:
/* XXX: TODO */
cpu_abort(cs, "MPC8xx MMU model is not implemented\n");
case POWERPC_MMU_BOOKE206:
booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
- /* fall through */
+ fallthrough;
case POWERPC_MMU_BOOKE:
cs->exception_index = POWERPC_EXCP_DTLB;
env->error_code = 0;
env->spr[SPR_BOOKE_DEAR] = eaddr;
env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
break;
case POWERPC_MMU_REAL:
cpu_abort(cs, "PowerPC in real mode should never raise "
"any MMU exceptions\n");
default:
cpu_abort(cs, "Unknown or invalid MMU model\n");
}
break;
case -2:
/* Access rights violation */
cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
if (env->mmu_model == POWERPC_MMU_SOFT_4xx) {
env->spr[SPR_40x_DEAR] = eaddr;
if (access_type == MMU_DATA_STORE) {
env->spr[SPR_40x_ESR] |= 0x00800000;
}
} else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
(env->mmu_model == POWERPC_MMU_BOOKE206)) {
env->spr[SPR_BOOKE_DEAR] = eaddr;
env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
} else {
env->spr[SPR_DAR] = eaddr;
if (access_type == MMU_DATA_STORE) {
env->spr[SPR_DSISR] = 0x0A000000;
} else {
env->spr[SPR_DSISR] = 0x08000000;
}
}
break;
case -4:
/* Direct store exception */
switch (type) {
case ACCESS_FLOAT:
/* Floating point load/store */
cs->exception_index = POWERPC_EXCP_ALIGN;
env->error_code = POWERPC_EXCP_ALIGN_FP;
env->spr[SPR_DAR] = eaddr;
break;
case ACCESS_RES:
/* lwarx, ldarx or stwcx. */
cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
env->spr[SPR_DAR] = eaddr;
if (access_type == MMU_DATA_STORE) {
env->spr[SPR_DSISR] = 0x06000000;
} else {
env->spr[SPR_DSISR] = 0x04000000;
}
break;
case ACCESS_EXT:
/* eciwx or ecowx */
cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
env->spr[SPR_DAR] = eaddr;
if (access_type == MMU_DATA_STORE) {
env->spr[SPR_DSISR] = 0x06100000;
} else {
env->spr[SPR_DSISR] = 0x04100000;
}
break;
default:
printf("DSI: invalid exception (%d)\n", ret);
cs->exception_index = POWERPC_EXCP_PROGRAM;
env->error_code =
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
env->spr[SPR_DAR] = eaddr;
break;
}
break;
}
}
}
return false;
}
/*****************************************************************************/
@@ -1522,29 +1522,29 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
hwaddr *raddrp, int *psizep, int *protp,
int mmu_idx, bool guest_visible)
{
switch (cpu->env.mmu_model) {
#if defined(TARGET_PPC64)
case POWERPC_MMU_3_00:
if (ppc64_v3_radix(cpu)) {
return ppc_radix64_xlate(cpu, eaddr, access_type, raddrp,
psizep, protp, mmu_idx, guest_visible);
}
- /* fall through */
+ fallthrough;
case POWERPC_MMU_64B:
case POWERPC_MMU_2_03:
case POWERPC_MMU_2_06:
case POWERPC_MMU_2_07:
return ppc_hash64_xlate(cpu, eaddr, access_type,
raddrp, psizep, protp, mmu_idx, guest_visible);
#endif
case POWERPC_MMU_32B:
return ppc_hash32_xlate(cpu, eaddr, access_type, raddrp,
psizep, protp, mmu_idx, guest_visible);
default:
return ppc_jumbo_xlate(cpu, eaddr, access_type, raddrp,
psizep, protp, mmu_idx, guest_visible);
}
}
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 329da4d518..a67b77258d 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7427,76 +7427,76 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
DisasJumpType is_jmp = ctx->base.is_jmp;
target_ulong nip = ctx->base.pc_next;
if (is_jmp == DISAS_NORETURN) {
/* We have already exited the TB. */
return;
}
/* Honor single stepping. */
if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)) {
bool rfi_type = false;
switch (is_jmp) {
case DISAS_TOO_MANY:
case DISAS_EXIT_UPDATE:
case DISAS_CHAIN_UPDATE:
gen_update_nip(ctx, nip);
break;
case DISAS_EXIT:
case DISAS_CHAIN:
/*
* This is a heuristic, to put it kindly. The rfi class of
* instructions are among the few outside branches that change
* NIP without taking an interrupt. Single step trace interrupts
* do not fire on completion of these instructions.
*/
rfi_type = true;
break;
default:
g_assert_not_reached();
}
gen_debug_exception(ctx, rfi_type);
return;
}
switch (is_jmp) {
case DISAS_TOO_MANY:
if (use_goto_tb(ctx, nip)) {
pmu_count_insns(ctx);
tcg_gen_goto_tb(0);
gen_update_nip(ctx, nip);
tcg_gen_exit_tb(ctx->base.tb, 0);
break;
}
- /* fall through */
+ fallthrough;
case DISAS_CHAIN_UPDATE:
gen_update_nip(ctx, nip);
- /* fall through */
+ fallthrough;
case DISAS_CHAIN:
/*
* tcg_gen_lookup_and_goto_ptr will exit the TB if
* CF_NO_GOTO_PTR is set. Count insns now.
*/
if (ctx->base.tb->flags & CF_NO_GOTO_PTR) {
pmu_count_insns(ctx);
}
tcg_gen_lookup_and_goto_ptr();
break;
case DISAS_EXIT_UPDATE:
gen_update_nip(ctx, nip);
- /* fall through */
+ fallthrough;
case DISAS_EXIT:
pmu_count_insns(ctx);
tcg_gen_exit_tb(NULL, 0);
break;
default:
g_assert_not_reached();
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 23/78] target/arm: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (21 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 22/78] target/ppc: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 24/78] target/alpha: " Emmanouil Pitsidianakis
` (55 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Peter Maydell, open list:ARM TCG CPUs
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
target/arm/helper.c | 34 +++++++-------
target/arm/ptw.c | 10 ++--
target/arm/tcg/psci.c | 2 +-
target/arm/tcg/translate-a64.c | 76 +++++++++++++++----------------
target/arm/tcg/translate-m-nocp.c | 2 +-
target/arm/tcg/translate-vfp.c | 2 +-
target/arm/tcg/translate.c | 8 ++--
7 files changed, 68 insertions(+), 66 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 74fbb6e1d7..e2d1426cf4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2507,42 +2507,42 @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
bool isread)
{
unsigned int cur_el = arm_current_el(env);
bool has_el2 = arm_is_el2_enabled(env);
uint64_t hcr = arm_hcr_el2_eff(env);
switch (cur_el) {
case 0:
if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
/* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1)
? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2);
}
/*
* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
* EL0 if EL0[PV]TEN is zero.
*/
if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
return CP_ACCESS_TRAP;
}
- /* fall through */
+ fallthrough;
case 1:
if (has_el2 && timeridx == GTIMER_PHYS) {
if (hcr & HCR_E2H) {
/* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
if (!extract32(env->cp15.cnthctl_el2, 11, 1)) {
return CP_ACCESS_TRAP_EL2;
}
} else {
/* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
if (!extract32(env->cp15.cnthctl_el2, 1, 1)) {
return CP_ACCESS_TRAP_EL2;
}
}
}
break;
}
return CP_ACCESS_OK;
}
@@ -3573,69 +3573,69 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
#ifdef CONFIG_TCG
MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
uint64_t par64;
ARMMMUIdx mmu_idx;
int el = arm_current_el(env);
ARMSecuritySpace ss = arm_security_space(env);
switch (ri->opc2 & 6) {
case 0:
/* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
switch (el) {
case 3:
mmu_idx = ARMMMUIdx_E3;
break;
case 2:
g_assert(ss != ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit only */
- /* fall through */
+ fallthrough;
case 1:
if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) {
mmu_idx = ARMMMUIdx_Stage1_E1_PAN;
} else {
mmu_idx = ARMMMUIdx_Stage1_E1;
}
break;
default:
g_assert_not_reached();
}
break;
case 2:
/* stage 1 current state PL0: ATS1CUR, ATS1CUW */
switch (el) {
case 3:
mmu_idx = ARMMMUIdx_E10_0;
break;
case 2:
g_assert(ss != ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit only */
mmu_idx = ARMMMUIdx_Stage1_E0;
break;
case 1:
mmu_idx = ARMMMUIdx_Stage1_E0;
break;
default:
g_assert_not_reached();
}
break;
case 4:
/* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
mmu_idx = ARMMMUIdx_E10_1;
ss = ARMSS_NonSecure;
break;
case 6:
/* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
mmu_idx = ARMMMUIdx_E10_0;
ss = ARMSS_NonSecure;
break;
default:
g_assert_not_reached();
}
par64 = do_ats_write(env, value, access_type, mmu_idx, ss);
A32_BANKED_CURRENT_REG_SET(env, par, par64);
#else
/* Handled by hardware accelerator. */
g_assert_not_reached();
#endif /* CONFIG_TCG */
}
@@ -4649,21 +4649,21 @@ static const ARMCPRegInfo ssbs_reginfo = {
static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
const ARMCPRegInfo *ri,
bool isread)
{
/* Cache invalidate/clean to Point of Coherency or Persistence... */
switch (arm_current_el(env)) {
case 0:
/* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
if (!(arm_sctlr(env, 0) & SCTLR_UCI)) {
return CP_ACCESS_TRAP;
}
- /* fall through */
+ fallthrough;
case 1:
/* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
if (arm_hcr_el2_eff(env) & HCR_TPCP) {
return CP_ACCESS_TRAP_EL2;
}
break;
}
return CP_ACCESS_OK;
}
@@ -4671,19 +4671,19 @@ static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
static CPAccessResult do_cacheop_pou_access(CPUARMState *env, uint64_t hcrflags)
{
/* Cache invalidate/clean to Point of Unification... */
switch (arm_current_el(env)) {
case 0:
/* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
if (!(arm_sctlr(env, 0) & SCTLR_UCI)) {
return CP_ACCESS_TRAP;
}
- /* fall through */
+ fallthrough;
case 1:
/* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */
if (arm_hcr_el2_eff(env) & hcrflags) {
return CP_ACCESS_TRAP_EL2;
}
break;
}
return CP_ACCESS_OK;
}
@@ -6741,107 +6741,107 @@ static const ARMCPRegInfo minimal_ras_reginfo[] = {
/*
* Return the exception level to which exceptions should be taken
* via SVEAccessTrap. This excludes the check for whether the exception
* should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily
* be found by testing 0 < fp_exception_el < sve_exception_el.
*
* C.f. the ARM pseudocode function CheckSVEEnabled. Note that the
* pseudocode does *not* separate out the FP trap checks, but has them
* all in one function.
*/
int sve_exception_el(CPUARMState *env, int el)
{
#ifndef CONFIG_USER_ONLY
if (el <= 1 && !el_is_in_host(env, el)) {
switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, ZEN)) {
case 1:
if (el != 0) {
break;
}
- /* fall through */
+ fallthrough;
case 0:
case 2:
return 1;
}
}
if (el <= 2 && arm_is_el2_enabled(env)) {
/* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
if (env->cp15.hcr_el2 & HCR_E2H) {
switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, ZEN)) {
case 1:
if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) {
break;
}
- /* fall through */
+ fallthrough;
case 0:
case 2:
return 2;
}
} else {
if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TZ)) {
return 2;
}
}
}
/* CPTR_EL3. Since EZ is negative we must check for EL3. */
if (arm_feature(env, ARM_FEATURE_EL3)
&& !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, EZ)) {
return 3;
}
#endif
return 0;
}
/*
* Return the exception level to which exceptions should be taken for SME.
* C.f. the ARM pseudocode function CheckSMEAccess.
*/
int sme_exception_el(CPUARMState *env, int el)
{
#ifndef CONFIG_USER_ONLY
if (el <= 1 && !el_is_in_host(env, el)) {
switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, SMEN)) {
case 1:
if (el != 0) {
break;
}
- /* fall through */
+ fallthrough;
case 0:
case 2:
return 1;
}
}
if (el <= 2 && arm_is_el2_enabled(env)) {
/* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
if (env->cp15.hcr_el2 & HCR_E2H) {
switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, SMEN)) {
case 1:
if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) {
break;
}
- /* fall through */
+ fallthrough;
case 0:
case 2:
return 2;
}
} else {
if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TSM)) {
return 2;
}
}
}
/* CPTR_EL3. Since ESM is negative we must check for EL3. */
if (arm_feature(env, ARM_FEATURE_EL3)
&& !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) {
return 3;
}
#endif
return 0;
}
/*
* Given that SVE is enabled, return the vector length for EL.
*/
@@ -9678,182 +9678,182 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
const ARMCPRegInfo *r, void *opaque)
{
/*
* Define implementations of coprocessor registers.
* We store these in a hashtable because typically
* there are less than 150 registers in a space which
* is 16*16*16*8*8 = 262144 in size.
* Wildcarding is supported for the crm, opc1 and opc2 fields.
* If a register is defined twice then the second definition is
* used, so this can be used to define some generic registers and
* then override them with implementation specific variations.
* At least one of the original and the second definition should
* include ARM_CP_OVERRIDE in its type bits -- this is just a guard
* against accidental use.
*
* The state field defines whether the register is to be
* visible in the AArch32 or AArch64 execution state. If the
* state is set to ARM_CP_STATE_BOTH then we synthesise a
* reginfo structure for the AArch32 view, which sees the lower
* 32 bits of the 64 bit register.
*
* Only registers visible in AArch64 may set r->opc0; opc0 cannot
* be wildcarded. AArch64 registers are always considered to be 64
* bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
* the register, if any.
*/
int crm, opc1, opc2;
int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
CPState state;
/* 64 bit registers have only CRm and Opc1 fields */
assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
/* op0 only exists in the AArch64 encodings */
assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
/* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
/*
* This API is only for Arm's system coprocessors (14 and 15) or
* (M-profile or v7A-and-earlier only) for implementation defined
* coprocessors in the range 0..7. Our decode assumes this, since
* 8..13 can be used for other insns including VFP and Neon. See
* valid_cp() in translate.c. Assert here that we haven't tried
* to use an invalid coprocessor number.
*/
switch (r->state) {
case ARM_CP_STATE_BOTH:
/* 0 has a special meaning, but otherwise the same rules as AA32. */
if (r->cp == 0) {
break;
}
- /* fall through */
+ fallthrough;
case ARM_CP_STATE_AA32:
if (arm_feature(&cpu->env, ARM_FEATURE_V8) &&
!arm_feature(&cpu->env, ARM_FEATURE_M)) {
assert(r->cp >= 14 && r->cp <= 15);
} else {
assert(r->cp < 8 || (r->cp >= 14 && r->cp <= 15));
}
break;
case ARM_CP_STATE_AA64:
assert(r->cp == 0 || r->cp == CP_REG_ARM64_SYSREG_CP);
break;
default:
g_assert_not_reached();
}
/*
* The AArch64 pseudocode CheckSystemAccess() specifies that op1
* encodes a minimum access level for the register. We roll this
* runtime check into our general permission check code, so check
* here that the reginfo's specified permissions are strict enough
* to encompass the generic architectural permission check.
*/
if (r->state != ARM_CP_STATE_AA32) {
CPAccessRights mask;
switch (r->opc1) {
case 0:
/* min_EL EL1, but some accessible to EL0 via kernel ABI */
mask = PL0U_R | PL1_RW;
break;
case 1: case 2:
/* min_EL EL1 */
mask = PL1_RW;
break;
case 3:
/* min_EL EL0 */
mask = PL0_RW;
break;
case 4:
case 5:
/* min_EL EL2 */
mask = PL2_RW;
break;
case 6:
/* min_EL EL3 */
mask = PL3_RW;
break;
case 7:
/* min_EL EL1, secure mode only (we don't check the latter) */
mask = PL1_RW;
break;
default:
/* broken reginfo with out-of-range opc1 */
g_assert_not_reached();
}
/* assert our permissions are not too lax (stricter is fine) */
assert((r->access & ~mask) == 0);
}
/*
* Check that the register definition has enough info to handle
* reads and writes if they are permitted.
*/
if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) {
if (r->access & PL3_R) {
assert((r->fieldoffset ||
(r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
r->readfn);
}
if (r->access & PL3_W) {
assert((r->fieldoffset ||
(r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
r->writefn);
}
}
for (crm = crmmin; crm <= crmmax; crm++) {
for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
for (state = ARM_CP_STATE_AA32;
state <= ARM_CP_STATE_AA64; state++) {
if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
continue;
}
if (state == ARM_CP_STATE_AA32) {
/*
* Under AArch32 CP registers can be common
* (same for secure and non-secure world) or banked.
*/
char *name;
switch (r->secure) {
case ARM_CP_SECSTATE_S:
case ARM_CP_SECSTATE_NS:
add_cpreg_to_hashtable(cpu, r, opaque, state,
r->secure, crm, opc1, opc2,
r->name);
break;
case ARM_CP_SECSTATE_BOTH:
name = g_strdup_printf("%s_S", r->name);
add_cpreg_to_hashtable(cpu, r, opaque, state,
ARM_CP_SECSTATE_S,
crm, opc1, opc2, name);
g_free(name);
add_cpreg_to_hashtable(cpu, r, opaque, state,
ARM_CP_SECSTATE_NS,
crm, opc1, opc2, r->name);
break;
default:
g_assert_not_reached();
}
} else {
/*
* AArch64 registers get mapped to non-secure instance
* of AArch32
*/
add_cpreg_to_hashtable(cpu, r, opaque, state,
ARM_CP_SECSTATE_NS,
crm, opc1, opc2, r->name);
}
}
}
}
}
}
/* Define a whole list of registers */
@@ -10609,79 +10609,79 @@ void aarch64_sync_64_to_32(CPUARMState *env)
static void take_aarch32_exception(CPUARMState *env, int new_mode,
uint32_t mask, uint32_t offset,
uint32_t newpc)
{
int new_el;
/* Change the CPU state so as to actually take the exception. */
switch_mode(env, new_mode);
/*
* For exceptions taken to AArch32 we must clear the SS bit in both
* PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
*/
env->pstate &= ~PSTATE_SS;
env->spsr = cpsr_read(env);
/* Clear IT bits. */
env->condexec_bits = 0;
/* Switch to the new mode, and to the correct instruction set. */
env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
/* This must be after mode switching. */
new_el = arm_current_el(env);
/* Set new mode endianness */
env->uncached_cpsr &= ~CPSR_E;
if (env->cp15.sctlr_el[new_el] & SCTLR_EE) {
env->uncached_cpsr |= CPSR_E;
}
/* J and IL must always be cleared for exception entry */
env->uncached_cpsr &= ~(CPSR_IL | CPSR_J);
env->daif |= mask;
if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) {
if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) {
env->uncached_cpsr |= CPSR_SSBS;
} else {
env->uncached_cpsr &= ~CPSR_SSBS;
}
}
if (new_mode == ARM_CPU_MODE_HYP) {
env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0;
env->elr_el[2] = env->regs[15];
} else {
/* CPSR.PAN is normally preserved preserved unless... */
if (cpu_isar_feature(aa32_pan, env_archcpu(env))) {
switch (new_el) {
case 3:
if (!arm_is_secure_below_el3(env)) {
/* ... the target is EL3, from non-secure state. */
env->uncached_cpsr &= ~CPSR_PAN;
break;
}
/* ... the target is EL3, from secure state ... */
- /* fall through */
+ fallthrough;
case 1:
/* ... the target is EL1 and SCTLR.SPAN is 0. */
if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) {
env->uncached_cpsr |= CPSR_PAN;
}
break;
}
}
/*
* this is a lie, as there was no c1_sys on V4T/V5, but who cares
* and we should just guard the thumb mode on V4
*/
if (arm_feature(env, ARM_FEATURE_V4T)) {
env->thumb =
(A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
}
env->regs[14] = env->regs[15] + offset;
}
env->regs[15] = newpc;
if (tcg_enabled()) {
arm_rebuild_hflags(env);
}
}
@@ -10689,90 +10689,91 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs)
{
/*
* Handle exception entry to Hyp mode; this is sufficiently
* different to entry to other AArch32 modes that we handle it
* separately here.
*
* The vector table entry used is always the 0x14 Hyp mode entry point,
* unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp.
* The offset applied to the preferred return address is always zero
* (see DDI0487C.a section G1.12.3).
* PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
*/
uint32_t addr, mask;
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
switch (cs->exception_index) {
case EXCP_UDEF:
addr = 0x04;
break;
case EXCP_SWI:
addr = 0x08;
break;
case EXCP_BKPT:
/* Fall through to prefetch abort. */
+ fallthrough;
case EXCP_PREFETCH_ABORT:
env->cp15.ifar_s = env->exception.vaddress;
qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n",
(uint32_t)env->exception.vaddress);
addr = 0x0c;
break;
case EXCP_DATA_ABORT:
env->cp15.dfar_s = env->exception.vaddress;
qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n",
(uint32_t)env->exception.vaddress);
addr = 0x10;
break;
case EXCP_IRQ:
addr = 0x18;
break;
case EXCP_FIQ:
addr = 0x1c;
break;
case EXCP_HVC:
addr = 0x08;
break;
case EXCP_HYP_TRAP:
addr = 0x14;
break;
default:
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
}
if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) {
if (!arm_feature(env, ARM_FEATURE_V8)) {
/*
* QEMU syndrome values are v8-style. v7 has the IL bit
* UNK/SBZP for "field not valid" cases, where v8 uses RES1.
* If this is a v7 CPU, squash the IL bit in those cases.
*/
if (cs->exception_index == EXCP_PREFETCH_ABORT ||
(cs->exception_index == EXCP_DATA_ABORT &&
!(env->exception.syndrome & ARM_EL_ISV)) ||
syn_get_ec(env->exception.syndrome) == EC_UNCATEGORIZED) {
env->exception.syndrome &= ~ARM_EL_IL;
}
}
env->cp15.esr_el[2] = env->exception.syndrome;
}
if (arm_current_el(env) != 2 && addr < 0x14) {
addr = 0x14;
}
mask = 0;
if (!(env->cp15.scr_el3 & SCR_EA)) {
mask |= CPSR_A;
}
if (!(env->cp15.scr_el3 & SCR_IRQ)) {
mask |= CPSR_I;
}
if (!(env->cp15.scr_el3 & SCR_FIQ)) {
mask |= CPSR_F;
}
addr += env->cp15.hvbar;
take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr);
}
@@ -10780,175 +10781,176 @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs)
static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
uint32_t addr;
uint32_t mask;
int new_mode;
uint32_t offset;
uint32_t moe;
/* If this is a debug exception we must update the DBGDSCR.MOE bits */
switch (syn_get_ec(env->exception.syndrome)) {
case EC_BREAKPOINT:
case EC_BREAKPOINT_SAME_EL:
moe = 1;
break;
case EC_WATCHPOINT:
case EC_WATCHPOINT_SAME_EL:
moe = 10;
break;
case EC_AA32_BKPT:
moe = 3;
break;
case EC_VECTORCATCH:
moe = 5;
break;
default:
moe = 0;
break;
}
if (moe) {
env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
}
if (env->exception.target_el == 2) {
arm_cpu_do_interrupt_aarch32_hyp(cs);
return;
}
switch (cs->exception_index) {
case EXCP_UDEF:
new_mode = ARM_CPU_MODE_UND;
addr = 0x04;
mask = CPSR_I;
if (env->thumb) {
offset = 2;
} else {
offset = 4;
}
break;
case EXCP_SWI:
new_mode = ARM_CPU_MODE_SVC;
addr = 0x08;
mask = CPSR_I;
/* The PC already points to the next instruction. */
offset = 0;
break;
case EXCP_BKPT:
/* Fall through to prefetch abort. */
+ fallthrough;
case EXCP_PREFETCH_ABORT:
A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
env->exception.fsr, (uint32_t)env->exception.vaddress);
new_mode = ARM_CPU_MODE_ABT;
addr = 0x0c;
mask = CPSR_A | CPSR_I;
offset = 4;
break;
case EXCP_DATA_ABORT:
A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
env->exception.fsr,
(uint32_t)env->exception.vaddress);
new_mode = ARM_CPU_MODE_ABT;
addr = 0x10;
mask = CPSR_A | CPSR_I;
offset = 8;
break;
case EXCP_IRQ:
new_mode = ARM_CPU_MODE_IRQ;
addr = 0x18;
/* Disable IRQ and imprecise data aborts. */
mask = CPSR_A | CPSR_I;
offset = 4;
if (env->cp15.scr_el3 & SCR_IRQ) {
/* IRQ routed to monitor mode */
new_mode = ARM_CPU_MODE_MON;
mask |= CPSR_F;
}
break;
case EXCP_FIQ:
new_mode = ARM_CPU_MODE_FIQ;
addr = 0x1c;
/* Disable FIQ, IRQ and imprecise data aborts. */
mask = CPSR_A | CPSR_I | CPSR_F;
if (env->cp15.scr_el3 & SCR_FIQ) {
/* FIQ routed to monitor mode */
new_mode = ARM_CPU_MODE_MON;
}
offset = 4;
break;
case EXCP_VIRQ:
new_mode = ARM_CPU_MODE_IRQ;
addr = 0x18;
/* Disable IRQ and imprecise data aborts. */
mask = CPSR_A | CPSR_I;
offset = 4;
break;
case EXCP_VFIQ:
new_mode = ARM_CPU_MODE_FIQ;
addr = 0x1c;
/* Disable FIQ, IRQ and imprecise data aborts. */
mask = CPSR_A | CPSR_I | CPSR_F;
offset = 4;
break;
case EXCP_VSERR:
{
/*
* Note that this is reported as a data abort, but the DFAR
* has an UNKNOWN value. Construct the SError syndrome from
* AET and ExT fields.
*/
ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, };
if (extended_addresses_enabled(env)) {
env->exception.fsr = arm_fi_to_lfsc(&fi);
} else {
env->exception.fsr = arm_fi_to_sfsc(&fi);
}
env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000;
A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n",
env->exception.fsr);
new_mode = ARM_CPU_MODE_ABT;
addr = 0x10;
mask = CPSR_A | CPSR_I;
offset = 8;
}
break;
case EXCP_SMC:
new_mode = ARM_CPU_MODE_MON;
addr = 0x08;
mask = CPSR_A | CPSR_I | CPSR_F;
offset = 0;
break;
default:
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
return; /* Never happens. Keep compiler happy. */
}
if (new_mode == ARM_CPU_MODE_MON) {
addr += env->cp15.mvbar;
} else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
/* High vectors. When enabled, base address cannot be remapped. */
addr += 0xffff0000;
} else {
/*
* ARM v7 architectures provide a vector base address register to remap
* the interrupt vector table.
* This register is only followed in non-monitor mode, and is banked.
* Note: only bits 31:5 are valid.
*/
addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
}
if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
env->cp15.scr_el3 &= ~SCR_NS;
}
take_aarch32_exception(env, new_mode, mask, offset, addr);
}
@@ -11056,209 +11058,209 @@ static bool syndrome_is_sync_extabt(uint32_t syndrome)
/* Handle exception entry to a target EL which is using AArch64 */
static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
unsigned int new_el = env->exception.target_el;
target_ulong addr = env->cp15.vbar_el[new_el];
unsigned int new_mode = aarch64_pstate_mode(new_el, true);
unsigned int old_mode;
unsigned int cur_el = arm_current_el(env);
int rt;
if (tcg_enabled()) {
/*
* Note that new_el can never be 0. If cur_el is 0, then
* el0_a64 is is_a64(), else el0_a64 is ignored.
*/
aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
}
if (cur_el < new_el) {
/*
* Entry vector offset depends on whether the implemented EL
* immediately lower than the target level is using AArch32 or AArch64
*/
bool is_aa64;
uint64_t hcr;
switch (new_el) {
case 3:
is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0;
break;
case 2:
hcr = arm_hcr_el2_eff(env);
if ((hcr & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
is_aa64 = (hcr & HCR_RW) != 0;
break;
}
- /* fall through */
+ fallthrough;
case 1:
is_aa64 = is_a64(env);
break;
default:
g_assert_not_reached();
}
if (is_aa64) {
addr += 0x400;
} else {
addr += 0x600;
}
} else if (pstate_read(env) & PSTATE_SP) {
addr += 0x200;
}
switch (cs->exception_index) {
case EXCP_GPC:
qemu_log_mask(CPU_LOG_INT, "...with MFAR 0x%" PRIx64 "\n",
env->cp15.mfar_el3);
- /* fall through */
+ fallthrough;
case EXCP_PREFETCH_ABORT:
case EXCP_DATA_ABORT:
/*
* FEAT_DoubleFault allows synchronous external aborts taken to EL3
* to be taken to the SError vector entrypoint.
*/
if (new_el == 3 && (env->cp15.scr_el3 & SCR_EASE) &&
syndrome_is_sync_extabt(env->exception.syndrome)) {
addr += 0x180;
}
env->cp15.far_el[new_el] = env->exception.vaddress;
qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
env->cp15.far_el[new_el]);
- /* fall through */
+ fallthrough;
case EXCP_BKPT:
case EXCP_UDEF:
case EXCP_SWI:
case EXCP_HVC:
case EXCP_HYP_TRAP:
case EXCP_SMC:
switch (syn_get_ec(env->exception.syndrome)) {
case EC_ADVSIMDFPACCESSTRAP:
/*
* QEMU internal FP/SIMD syndromes from AArch32 include the
* TA and coproc fields which are only exposed if the exception
* is taken to AArch32 Hyp mode. Mask them out to get a valid
* AArch64 format syndrome.
*/
env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20);
break;
case EC_CP14RTTRAP:
case EC_CP15RTTRAP:
case EC_CP14DTTRAP:
/*
* For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
* the raw register field from the insn; when taking this to
* AArch64 we must convert it to the AArch64 view of the register
* number. Notice that we read a 4-bit AArch32 register number and
* write back a 5-bit AArch64 one.
*/
rt = extract32(env->exception.syndrome, 5, 4);
rt = aarch64_regnum(env, rt);
env->exception.syndrome = deposit32(env->exception.syndrome,
5, 5, rt);
break;
case EC_CP15RRTTRAP:
case EC_CP14RRTTRAP:
/* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
rt = extract32(env->exception.syndrome, 5, 4);
rt = aarch64_regnum(env, rt);
env->exception.syndrome = deposit32(env->exception.syndrome,
5, 5, rt);
rt = extract32(env->exception.syndrome, 10, 4);
rt = aarch64_regnum(env, rt);
env->exception.syndrome = deposit32(env->exception.syndrome,
10, 5, rt);
break;
}
env->cp15.esr_el[new_el] = env->exception.syndrome;
break;
case EXCP_IRQ:
case EXCP_VIRQ:
addr += 0x80;
break;
case EXCP_FIQ:
case EXCP_VFIQ:
addr += 0x100;
break;
case EXCP_VSERR:
addr += 0x180;
/* Construct the SError syndrome from IDS and ISS fields. */
env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff);
env->cp15.esr_el[new_el] = env->exception.syndrome;
break;
default:
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
}
if (is_a64(env)) {
old_mode = pstate_read(env);
aarch64_save_sp(env, arm_current_el(env));
env->elr_el[new_el] = env->pc;
} else {
old_mode = cpsr_read_for_spsr_elx(env);
env->elr_el[new_el] = env->regs[15];
aarch64_sync_32_to_64(env);
env->condexec_bits = 0;
}
env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode;
qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
env->elr_el[new_el]);
if (cpu_isar_feature(aa64_pan, cpu)) {
/* The value of PSTATE.PAN is normally preserved, except when ... */
new_mode |= old_mode & PSTATE_PAN;
switch (new_el) {
case 2:
/* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE))
!= (HCR_E2H | HCR_TGE)) {
break;
}
- /* fall through */
+ fallthrough;
case 1:
/* ... the target is EL1 ... */
/* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) == 0) {
new_mode |= PSTATE_PAN;
}
break;
}
}
if (cpu_isar_feature(aa64_mte, cpu)) {
new_mode |= PSTATE_TCO;
}
if (cpu_isar_feature(aa64_ssbs, cpu)) {
if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) {
new_mode |= PSTATE_SSBS;
} else {
new_mode &= ~PSTATE_SSBS;
}
}
pstate_write(env, PSTATE_DAIF | new_mode);
env->aarch64 = true;
aarch64_restore_sp(env, new_el);
if (tcg_enabled()) {
helper_rebuild_hflags_a64(env, new_el);
}
env->pc = addr;
qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n",
new_el, env->pc, pstate_read(env));
}
/*
* Do semihosting call and set the appropriate return value. All the
* permission and validity checks have been done at translate time.
*
* We only see semihosting exceptions in TCG only as they are not
* trapped to the hypervisor in KVM.
*/
#ifdef CONFIG_TCG
@@ -11909,111 +11911,111 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
/*
* Return the exception level to which FP-disabled exceptions should
* be taken, or 0 if FP is enabled.
*/
int fp_exception_el(CPUARMState *env, int cur_el)
{
#ifndef CONFIG_USER_ONLY
uint64_t hcr_el2;
/*
* CPACR and the CPTR registers don't exist before v6, so FP is
* always accessible
*/
if (!arm_feature(env, ARM_FEATURE_V6)) {
return 0;
}
if (arm_feature(env, ARM_FEATURE_M)) {
/* CPACR can cause a NOCP UsageFault taken to current security state */
if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) {
return 1;
}
if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) {
if (!extract32(env->v7m.nsacr, 10, 1)) {
/* FP insns cause a NOCP UsageFault taken to Secure */
return 3;
}
}
return 0;
}
hcr_el2 = arm_hcr_el2_eff(env);
/*
* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
* 0, 2 : trap EL0 and EL1/PL1 accesses
* 1 : trap only EL0 accesses
* 3 : trap no accesses
* This register is ignored if E2H+TGE are both set.
*/
if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
int fpen = FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN);
switch (fpen) {
case 1:
if (cur_el != 0) {
break;
}
- /* fall through */
+ fallthrough;
case 0:
case 2:
/* Trap from Secure PL0 or PL1 to Secure PL1. */
if (!arm_el_is_aa64(env, 3)
&& (cur_el == 3 || arm_is_secure_below_el3(env))) {
return 3;
}
if (cur_el <= 1) {
return 1;
}
break;
}
}
/*
* The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
* to control non-secure access to the FPU. It doesn't have any
* effect if EL3 is AArch64 or if EL3 doesn't exist at all.
*/
if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
cur_el <= 2 && !arm_is_secure_below_el3(env))) {
if (!extract32(env->cp15.nsacr, 10, 1)) {
/* FP insns act as UNDEF */
return cur_el == 2 ? 2 : 1;
}
}
/*
* CPTR_EL2 is present in v7VE or v8, and changes format
* with HCR_EL2.E2H (regardless of TGE).
*/
if (cur_el <= 2) {
if (hcr_el2 & HCR_E2H) {
switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) {
case 1:
if (cur_el != 0 || !(hcr_el2 & HCR_TGE)) {
break;
}
- /* fall through */
+ fallthrough;
case 0:
case 2:
return 2;
}
} else if (arm_is_el2_enabled(env)) {
if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) {
return 2;
}
}
}
/* CPTR_EL3 : present in v8 */
if (FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TFP)) {
/* Trap all FP ops to EL3 */
return 3;
}
#endif
return 0;
}
/* Return the exception level we're running at if this is our mmu_idx */
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 95db9ec4c3..3f6783c100 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -2240,192 +2240,192 @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
static bool get_phys_addr_pmsav7(CPUARMState *env,
S1Translate *ptw,
uint32_t address,
MMUAccessType access_type,
GetPhysAddrResult *result,
ARMMMUFaultInfo *fi)
{
ARMCPU *cpu = env_archcpu(env);
int n;
ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
bool is_user = regime_is_user(env, mmu_idx);
bool secure = arm_space_is_secure(ptw->in_space);
result->f.phys_addr = address;
result->f.lg_page_size = TARGET_PAGE_BITS;
result->f.prot = 0;
if (regime_translation_disabled(env, mmu_idx, ptw->in_space) ||
m_is_ppb_region(env, address)) {
/*
* MPU disabled or M profile PPB access: use default memory map.
* The other case which uses the default memory map in the
* v7M ARM ARM pseudocode is exception vector reads from the vector
* table. In QEMU those accesses are done in arm_v7m_load_vector(),
* which always does a direct read using address_space_ldl(), rather
* than going via this function, so we don't need to check that here.
*/
get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.prot);
} else { /* MPU enabled */
for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
/* region search */
uint32_t base = env->pmsav7.drbar[n];
uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
uint32_t rmask;
bool srdis = false;
if (!(env->pmsav7.drsr[n] & 0x1)) {
continue;
}
if (!rsize) {
qemu_log_mask(LOG_GUEST_ERROR,
"DRSR[%d]: Rsize field cannot be 0\n", n);
continue;
}
rsize++;
rmask = (1ull << rsize) - 1;
if (base & rmask) {
qemu_log_mask(LOG_GUEST_ERROR,
"DRBAR[%d]: 0x%" PRIx32 " misaligned "
"to DRSR region size, mask = 0x%" PRIx32 "\n",
n, base, rmask);
continue;
}
if (address < base || address > base + rmask) {
/*
* Address not in this region. We must check whether the
* region covers addresses in the same page as our address.
* In that case we must not report a size that covers the
* whole page for a subsequent hit against a different MPU
* region or the background region, because it would result in
* incorrect TLB hits for subsequent accesses to addresses that
* are in this MPU region.
*/
if (ranges_overlap(base, rmask,
address & TARGET_PAGE_MASK,
TARGET_PAGE_SIZE)) {
result->f.lg_page_size = 0;
}
continue;
}
/* Region matched */
if (rsize >= 8) { /* no subregions for regions < 256 bytes */
int i, snd;
uint32_t srdis_mask;
rsize -= 3; /* sub region size (power of 2) */
snd = ((address - base) >> rsize) & 0x7;
srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
srdis_mask = srdis ? 0x3 : 0x0;
for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
/*
* This will check in groups of 2, 4 and then 8, whether
* the subregion bits are consistent. rsize is incremented
* back up to give the region size, considering consistent
* adjacent subregions as one region. Stop testing if rsize
* is already big enough for an entire QEMU page.
*/
int snd_rounded = snd & ~(i - 1);
uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
snd_rounded + 8, i);
if (srdis_mask ^ srdis_multi) {
break;
}
srdis_mask = (srdis_mask << i) | srdis_mask;
rsize++;
}
}
if (srdis) {
continue;
}
if (rsize < TARGET_PAGE_BITS) {
result->f.lg_page_size = rsize;
}
break;
}
if (n == -1) { /* no hits */
if (!pmsav7_use_background_region(cpu, mmu_idx, secure, is_user)) {
/* background fault */
fi->type = ARMFault_Background;
return true;
}
get_phys_addr_pmsav7_default(env, mmu_idx, address,
&result->f.prot);
} else { /* a MPU hit! */
uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1);
if (m_is_system_region(env, address)) {
/* System space is always execute never */
xn = 1;
}
if (is_user) { /* User mode AP bit decoding */
switch (ap) {
case 0:
case 1:
case 5:
break; /* no access */
case 3:
result->f.prot |= PAGE_WRITE;
- /* fall through */
+ fallthrough;
case 2:
case 6:
result->f.prot |= PAGE_READ | PAGE_EXEC;
break;
case 7:
/* for v7M, same as 6; for R profile a reserved value */
if (arm_feature(env, ARM_FEATURE_M)) {
result->f.prot |= PAGE_READ | PAGE_EXEC;
break;
}
- /* fall through */
+ fallthrough;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"DRACR[%d]: Bad value for AP bits: 0x%"
PRIx32 "\n", n, ap);
}
} else { /* Priv. mode AP bits decoding */
switch (ap) {
case 0:
break; /* no access */
case 1:
case 2:
case 3:
result->f.prot |= PAGE_WRITE;
- /* fall through */
+ fallthrough;
case 5:
case 6:
result->f.prot |= PAGE_READ | PAGE_EXEC;
break;
case 7:
/* for v7M, same as 6; for R profile a reserved value */
if (arm_feature(env, ARM_FEATURE_M)) {
result->f.prot |= PAGE_READ | PAGE_EXEC;
break;
}
- /* fall through */
+ fallthrough;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"DRACR[%d]: Bad value for AP bits: 0x%"
PRIx32 "\n", n, ap);
}
}
/* execute never */
if (xn) {
result->f.prot &= ~PAGE_EXEC;
}
}
}
fi->type = ARMFault_Permission;
fi->level = 1;
return !(result->f.prot & (1 << access_type));
}
@@ -3269,136 +3269,136 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw,
target_ulong address,
MMUAccessType access_type,
GetPhysAddrResult *result,
ARMMMUFaultInfo *fi)
{
ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
ARMMMUIdx s1_mmu_idx;
/*
* The page table entries may downgrade Secure to NonSecure, but
* cannot upgrade a NonSecure translation regime's attributes
* to Secure or Realm.
*/
result->f.attrs.space = ptw->in_space;
result->f.attrs.secure = arm_space_is_secure(ptw->in_space);
switch (mmu_idx) {
case ARMMMUIdx_Phys_S:
case ARMMMUIdx_Phys_NS:
case ARMMMUIdx_Phys_Root:
case ARMMMUIdx_Phys_Realm:
/* Checking Phys early avoids special casing later vs regime_el. */
return get_phys_addr_disabled(env, ptw, address, access_type,
result, fi);
case ARMMMUIdx_Stage1_E0:
case ARMMMUIdx_Stage1_E1:
case ARMMMUIdx_Stage1_E1_PAN:
/*
* First stage lookup uses second stage for ptw; only
* Secure has both S and NS IPA and starts with Stage2_S.
*/
ptw->in_ptw_idx = (ptw->in_space == ARMSS_Secure) ?
ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
break;
case ARMMMUIdx_Stage2:
case ARMMMUIdx_Stage2_S:
/*
* Second stage lookup uses physical for ptw; whether this is S or
* NS may depend on the SW/NSW bits if this is a stage 2 lookup for
* the Secure EL2&0 regime.
*/
ptw->in_ptw_idx = ptw_idx_for_stage_2(env, mmu_idx);
break;
case ARMMMUIdx_E10_0:
s1_mmu_idx = ARMMMUIdx_Stage1_E0;
goto do_twostage;
case ARMMMUIdx_E10_1:
s1_mmu_idx = ARMMMUIdx_Stage1_E1;
goto do_twostage;
case ARMMMUIdx_E10_1_PAN:
s1_mmu_idx = ARMMMUIdx_Stage1_E1_PAN;
do_twostage:
/*
* Call ourselves recursively to do the stage 1 and then stage 2
* translations if mmu_idx is a two-stage regime, and EL2 present.
* Otherwise, a stage1+stage2 translation is just stage 1.
*/
ptw->in_mmu_idx = mmu_idx = s1_mmu_idx;
if (arm_feature(env, ARM_FEATURE_EL2) &&
!regime_translation_disabled(env, ARMMMUIdx_Stage2, ptw->in_space)) {
return get_phys_addr_twostage(env, ptw, address, access_type,
result, fi);
}
- /* fall through */
+ fallthrough;
default:
/* Single stage uses physical for ptw. */
ptw->in_ptw_idx = arm_space_to_phys(ptw->in_space);
break;
}
result->f.attrs.user = regime_is_user(env, mmu_idx);
/*
* Fast Context Switch Extension. This doesn't exist at all in v8.
* In v7 and earlier it affects all stage 1 translations.
*/
if (address < 0x02000000 && mmu_idx != ARMMMUIdx_Stage2
&& !arm_feature(env, ARM_FEATURE_V8)) {
if (regime_el(env, mmu_idx) == 3) {
address += env->cp15.fcseidr_s;
} else {
address += env->cp15.fcseidr_ns;
}
}
if (arm_feature(env, ARM_FEATURE_PMSA)) {
bool ret;
result->f.lg_page_size = TARGET_PAGE_BITS;
if (arm_feature(env, ARM_FEATURE_V8)) {
/* PMSAv8 */
ret = get_phys_addr_pmsav8(env, ptw, address, access_type,
result, fi);
} else if (arm_feature(env, ARM_FEATURE_V7)) {
/* PMSAv7 */
ret = get_phys_addr_pmsav7(env, ptw, address, access_type,
result, fi);
} else {
/* Pre-v7 MPU */
ret = get_phys_addr_pmsav5(env, ptw, address, access_type,
result, fi);
}
qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
" mmu_idx %u -> %s (prot %c%c%c)\n",
access_type == MMU_DATA_LOAD ? "reading" :
(access_type == MMU_DATA_STORE ? "writing" : "execute"),
(uint32_t)address, mmu_idx,
ret ? "Miss" : "Hit",
result->f.prot & PAGE_READ ? 'r' : '-',
result->f.prot & PAGE_WRITE ? 'w' : '-',
result->f.prot & PAGE_EXEC ? 'x' : '-');
return ret;
}
/* Definitely a real MMU, not an MPU */
if (regime_translation_disabled(env, mmu_idx, ptw->in_space)) {
return get_phys_addr_disabled(env, ptw, address, access_type,
result, fi);
}
if (regime_using_lpae_format(env, mmu_idx)) {
return get_phys_addr_lpae(env, ptw, address, access_type, result, fi);
} else if (arm_feature(env, ARM_FEATURE_V7) ||
regime_sctlr(env, mmu_idx) & SCTLR_XP) {
return get_phys_addr_v6(env, ptw, address, access_type, result, fi);
} else {
return get_phys_addr_v5(env, ptw, address, access_type, result, fi);
}
}
diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c
index 6c1239bb96..dafc39c3d7 100644
--- a/target/arm/tcg/psci.c
+++ b/target/arm/tcg/psci.c
@@ -56,152 +56,152 @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
void arm_handle_psci_call(ARMCPU *cpu)
{
/*
* This function partially implements the logic for dispatching Power State
* Coordination Interface (PSCI) calls (as described in ARM DEN 0022D.b),
* to the extent required for bringing up and taking down secondary cores,
* and for handling reset and poweroff requests.
* Additional information about the calling convention used is available in
* the document 'SMC Calling Convention' (ARM DEN 0028)
*/
CPUARMState *env = &cpu->env;
uint64_t param[4];
uint64_t context_id, mpidr;
target_ulong entry;
int32_t ret = 0;
int i;
for (i = 0; i < 4; i++) {
/*
* All PSCI functions take explicit 32-bit or native int sized
* arguments so we can simply zero-extend all arguments regardless
* of which exact function we are about to call.
*/
param[i] = is_a64(env) ? env->xregs[i] : env->regs[i];
}
if ((param[0] & QEMU_PSCI_0_2_64BIT) && !is_a64(env)) {
ret = QEMU_PSCI_RET_NOT_SUPPORTED;
goto err;
}
switch (param[0]) {
CPUState *target_cpu_state;
ARMCPU *target_cpu;
case QEMU_PSCI_0_2_FN_PSCI_VERSION:
ret = QEMU_PSCI_VERSION_1_1;
break;
case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */
break;
case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
mpidr = param[1];
switch (param[2]) {
case 0:
target_cpu_state = arm_get_cpu_by_id(mpidr);
if (!target_cpu_state) {
ret = QEMU_PSCI_RET_INVALID_PARAMS;
break;
}
target_cpu = ARM_CPU(target_cpu_state);
g_assert(qemu_mutex_iothread_locked());
ret = target_cpu->power_state;
break;
default:
/* Everything above affinity level 0 is always on. */
ret = 0;
}
break;
case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
/* QEMU reset and shutdown are async requests, but PSCI
* mandates that we never return from the reset/shutdown
* call, so power the CPU off now so it doesn't execute
* anything further.
*/
goto cpu_off;
case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
goto cpu_off;
case QEMU_PSCI_0_1_FN_CPU_ON:
case QEMU_PSCI_0_2_FN_CPU_ON:
case QEMU_PSCI_0_2_FN64_CPU_ON:
{
/* The PSCI spec mandates that newly brought up CPUs start
* in the highest exception level which exists and is enabled
* on the calling CPU. Since the QEMU PSCI implementation is
* acting as a "fake EL3" or "fake EL2" firmware, this for us
* means that we want to start at the highest NS exception level
* that we are providing to the guest.
* The execution mode should be that which is currently in use
* by the same exception level on the calling CPU.
* The CPU should be started with the context_id value
* in x0 (if AArch64) or r0 (if AArch32).
*/
int target_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1;
bool target_aarch64 = arm_el_is_aa64(env, target_el);
mpidr = param[1];
entry = param[2];
context_id = param[3];
ret = arm_set_cpu_on(mpidr, entry, context_id,
target_el, target_aarch64);
break;
}
case QEMU_PSCI_0_1_FN_CPU_OFF:
case QEMU_PSCI_0_2_FN_CPU_OFF:
goto cpu_off;
case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
/* Affinity levels are not supported in QEMU */
if (param[1] & 0xfffe0000) {
ret = QEMU_PSCI_RET_INVALID_PARAMS;
break;
}
/* Powerdown is not supported, we always go into WFI */
if (is_a64(env)) {
env->xregs[0] = 0;
} else {
env->regs[0] = 0;
}
helper_wfi(env, 4);
break;
case QEMU_PSCI_1_0_FN_PSCI_FEATURES:
switch (param[1]) {
case QEMU_PSCI_0_2_FN_PSCI_VERSION:
case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
case QEMU_PSCI_0_1_FN_CPU_ON:
case QEMU_PSCI_0_2_FN_CPU_ON:
case QEMU_PSCI_0_2_FN64_CPU_ON:
case QEMU_PSCI_0_1_FN_CPU_OFF:
case QEMU_PSCI_0_2_FN_CPU_OFF:
case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
case QEMU_PSCI_1_0_FN_PSCI_FEATURES:
if (!(param[1] & QEMU_PSCI_0_2_64BIT) || is_a64(env)) {
ret = 0;
break;
}
- /* fallthrough */
+ fallthrough;
case QEMU_PSCI_0_1_FN_MIGRATE:
case QEMU_PSCI_0_2_FN_MIGRATE:
default:
ret = QEMU_PSCI_RET_NOT_SUPPORTED;
break;
}
break;
case QEMU_PSCI_0_1_FN_MIGRATE:
case QEMU_PSCI_0_2_FN_MIGRATE:
default:
ret = QEMU_PSCI_RET_NOT_SUPPORTED;
break;
}
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 10e8dcf743..ee97219acb 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -5725,176 +5725,176 @@ static void handle_fp_compare(DisasContext *s, int size,
/* Floating point compare
* 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
* +---+---+---+-----------+------+---+------+-----+---------+------+-------+
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
* +---+---+---+-----------+------+---+------+-----+---------+------+-------+
*/
static void disas_fp_compare(DisasContext *s, uint32_t insn)
{
unsigned int mos, type, rm, op, rn, opc, op2r;
int size;
mos = extract32(insn, 29, 3);
type = extract32(insn, 22, 2);
rm = extract32(insn, 16, 5);
op = extract32(insn, 14, 2);
rn = extract32(insn, 5, 5);
opc = extract32(insn, 3, 2);
op2r = extract32(insn, 0, 3);
if (mos || op || op2r) {
unallocated_encoding(s);
return;
}
switch (type) {
case 0:
size = MO_32;
break;
case 1:
size = MO_64;
break;
case 3:
size = MO_16;
if (dc_isar_feature(aa64_fp16, s)) {
break;
}
- /* fallthru */
+ fallthrough;
default:
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2);
}
/* Floating point conditional compare
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
* +---+---+---+-----------+------+---+------+------+-----+------+----+------+
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
* +---+---+---+-----------+------+---+------+------+-----+------+----+------+
*/
static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
{
unsigned int mos, type, rm, cond, rn, op, nzcv;
TCGLabel *label_continue = NULL;
int size;
mos = extract32(insn, 29, 3);
type = extract32(insn, 22, 2);
rm = extract32(insn, 16, 5);
cond = extract32(insn, 12, 4);
rn = extract32(insn, 5, 5);
op = extract32(insn, 4, 1);
nzcv = extract32(insn, 0, 4);
if (mos) {
unallocated_encoding(s);
return;
}
switch (type) {
case 0:
size = MO_32;
break;
case 1:
size = MO_64;
break;
case 3:
size = MO_16;
if (dc_isar_feature(aa64_fp16, s)) {
break;
}
- /* fallthru */
+ fallthrough;
default:
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
if (cond < 0x0e) { /* not always */
TCGLabel *label_match = gen_new_label();
label_continue = gen_new_label();
arm_gen_test_cc(cond, label_match);
/* nomatch: */
gen_set_nzcv(tcg_constant_i64(nzcv << 28));
tcg_gen_br(label_continue);
gen_set_label(label_match);
}
handle_fp_compare(s, size, rn, rm, false, op);
if (cond < 0x0e) {
gen_set_label(label_continue);
}
}
/* Floating point conditional select
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
* +---+---+---+-----------+------+---+------+------+-----+------+------+
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
* +---+---+---+-----------+------+---+------+------+-----+------+------+
*/
static void disas_fp_csel(DisasContext *s, uint32_t insn)
{
unsigned int mos, type, rm, cond, rn, rd;
TCGv_i64 t_true, t_false;
DisasCompare64 c;
MemOp sz;
mos = extract32(insn, 29, 3);
type = extract32(insn, 22, 2);
rm = extract32(insn, 16, 5);
cond = extract32(insn, 12, 4);
rn = extract32(insn, 5, 5);
rd = extract32(insn, 0, 5);
if (mos) {
unallocated_encoding(s);
return;
}
switch (type) {
case 0:
sz = MO_32;
break;
case 1:
sz = MO_64;
break;
case 3:
sz = MO_16;
if (dc_isar_feature(aa64_fp16, s)) {
break;
}
- /* fallthru */
+ fallthrough;
default:
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
/* Zero extend sreg & hreg inputs to 64 bits now. */
t_true = tcg_temp_new_i64();
t_false = tcg_temp_new_i64();
read_vec_element(s, t_true, rn, 0, sz);
read_vec_element(s, t_false, rm, 0, sz);
a64_test_cc(&c, cond);
tcg_gen_movcond_i64(c.cond, t_true, c.value, tcg_constant_i64(0),
t_true, t_false);
/* Note that sregs & hregs write back zeros to the high bits,
and we've already done the zero-extension. */
write_fp_dreg(s, rd, t_true);
}
/* Floating-point data-processing (1 source) - half precision */
@@ -6159,95 +6159,95 @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
/* Floating point data-processing (1 source)
* 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
* +---+---+---+-----------+------+---+--------+-----------+------+------+
* | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
* +---+---+---+-----------+------+---+--------+-----------+------+------+
*/
static void disas_fp_1src(DisasContext *s, uint32_t insn)
{
int mos = extract32(insn, 29, 3);
int type = extract32(insn, 22, 2);
int opcode = extract32(insn, 15, 6);
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
if (mos) {
goto do_unallocated;
}
switch (opcode) {
case 0x4: case 0x5: case 0x7:
{
/* FCVT between half, single and double precision */
int dtype = extract32(opcode, 0, 2);
if (type == 2 || dtype == type) {
goto do_unallocated;
}
if (!fp_access_check(s)) {
return;
}
handle_fp_fcvt(s, opcode, rd, rn, dtype, type);
break;
}
case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
if (type > 1 || !dc_isar_feature(aa64_frint, s)) {
goto do_unallocated;
}
- /* fall through */
+ fallthrough;
case 0x0 ... 0x3:
case 0x8 ... 0xc:
case 0xe ... 0xf:
/* 32-to-32 and 64-to-64 ops */
switch (type) {
case 0:
if (!fp_access_check(s)) {
return;
}
handle_fp_1src_single(s, opcode, rd, rn);
break;
case 1:
if (!fp_access_check(s)) {
return;
}
handle_fp_1src_double(s, opcode, rd, rn);
break;
case 3:
if (!dc_isar_feature(aa64_fp16, s)) {
goto do_unallocated;
}
if (!fp_access_check(s)) {
return;
}
handle_fp_1src_half(s, opcode, rd, rn);
break;
default:
goto do_unallocated;
}
break;
case 0x6:
switch (type) {
case 1: /* BFCVT */
if (!dc_isar_feature(aa64_bf16, s)) {
goto do_unallocated;
}
if (!fp_access_check(s)) {
return;
}
handle_fp_1src_single(s, opcode, rd, rn);
break;
default:
goto do_unallocated;
}
break;
default:
do_unallocated:
unallocated_encoding(s);
break;
}
}
/* Floating-point data-processing (2 source) - single precision */
@@ -6593,52 +6593,52 @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
/* Floating point immediate
* 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
* +---+---+---+-----------+------+---+------------+-------+------+------+
* | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
* +---+---+---+-----------+------+---+------------+-------+------+------+
*/
static void disas_fp_imm(DisasContext *s, uint32_t insn)
{
int rd = extract32(insn, 0, 5);
int imm5 = extract32(insn, 5, 5);
int imm8 = extract32(insn, 13, 8);
int type = extract32(insn, 22, 2);
int mos = extract32(insn, 29, 3);
uint64_t imm;
MemOp sz;
if (mos || imm5) {
unallocated_encoding(s);
return;
}
switch (type) {
case 0:
sz = MO_32;
break;
case 1:
sz = MO_64;
break;
case 3:
sz = MO_16;
if (dc_isar_feature(aa64_fp16, s)) {
break;
}
- /* fallthru */
+ fallthrough;
default:
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
imm = vfp_expand_imm(sz, imm8);
write_fp_dreg(s, rd, tcg_constant_i64(imm));
}
/* Handle floating point <=> fixed point conversions. Note that we can
* also deal with fp <=> integer conversions as a special case (scale == 64)
* OPTME: consider handling that special case specially or at least skipping
* the call to scalbn in the helpers for zero shifts.
*/
@@ -6803,57 +6803,57 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
/* Floating point <-> fixed point conversions
* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
* +----+---+---+-----------+------+---+-------+--------+-------+------+------+
* | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
* +----+---+---+-----------+------+---+-------+--------+-------+------+------+
*/
static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
{
int rd = extract32(insn, 0, 5);
int rn = extract32(insn, 5, 5);
int scale = extract32(insn, 10, 6);
int opcode = extract32(insn, 16, 3);
int rmode = extract32(insn, 19, 2);
int type = extract32(insn, 22, 2);
bool sbit = extract32(insn, 29, 1);
bool sf = extract32(insn, 31, 1);
bool itof;
if (sbit || (!sf && scale < 32)) {
unallocated_encoding(s);
return;
}
switch (type) {
case 0: /* float32 */
case 1: /* float64 */
break;
case 3: /* float16 */
if (dc_isar_feature(aa64_fp16, s)) {
break;
}
- /* fallthru */
+ fallthrough;
default:
unallocated_encoding(s);
return;
}
switch ((rmode << 3) | opcode) {
case 0x2: /* SCVTF */
case 0x3: /* UCVTF */
itof = true;
break;
case 0x18: /* FCVTZS */
case 0x19: /* FCVTZU */
itof = false;
break;
default:
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
handle_fpfpcvt(s, rd, rn, opcode, itof, FPROUNDING_ZERO, scale, sf, type);
}
@@ -6936,98 +6936,98 @@ static void handle_fjcvtzs(DisasContext *s, int rd, int rn)
/* Floating point <-> integer conversions
* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
* +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
* | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
* +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
*/
static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
{
int rd = extract32(insn, 0, 5);
int rn = extract32(insn, 5, 5);
int opcode = extract32(insn, 16, 3);
int rmode = extract32(insn, 19, 2);
int type = extract32(insn, 22, 2);
bool sbit = extract32(insn, 29, 1);
bool sf = extract32(insn, 31, 1);
bool itof = false;
if (sbit) {
goto do_unallocated;
}
switch (opcode) {
case 2: /* SCVTF */
case 3: /* UCVTF */
itof = true;
- /* fallthru */
+ fallthrough;
case 4: /* FCVTAS */
case 5: /* FCVTAU */
if (rmode != 0) {
goto do_unallocated;
}
- /* fallthru */
+ fallthrough;
case 0: /* FCVT[NPMZ]S */
case 1: /* FCVT[NPMZ]U */
switch (type) {
case 0: /* float32 */
case 1: /* float64 */
break;
case 3: /* float16 */
if (!dc_isar_feature(aa64_fp16, s)) {
goto do_unallocated;
}
break;
default:
goto do_unallocated;
}
if (!fp_access_check(s)) {
return;
}
handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type);
break;
default:
switch (sf << 7 | type << 5 | rmode << 3 | opcode) {
case 0b01100110: /* FMOV half <-> 32-bit int */
case 0b01100111:
case 0b11100110: /* FMOV half <-> 64-bit int */
case 0b11100111:
if (!dc_isar_feature(aa64_fp16, s)) {
goto do_unallocated;
}
- /* fallthru */
+ fallthrough;
case 0b00000110: /* FMOV 32-bit */
case 0b00000111:
case 0b10100110: /* FMOV 64-bit */
case 0b10100111:
case 0b11001110: /* FMOV top half of 128-bit */
case 0b11001111:
if (!fp_access_check(s)) {
return;
}
itof = opcode & 1;
handle_fmov(s, rd, rn, type, itof);
break;
case 0b00111110: /* FJCVTZS */
if (!dc_isar_feature(aa64_jscvt, s)) {
goto do_unallocated;
} else if (fp_access_check(s)) {
handle_fjcvtzs(s, rd, rn);
}
break;
default:
do_unallocated:
unallocated_encoding(s);
return;
}
break;
}
}
/* FP-specific subcases of table C3-6 (SIMD and FP data processing)
* 31 30 29 28 25 24 0
* +---+---+---+---------+-----------------------------+
* | | 0 | | 1 1 1 1 | |
* +---+---+---+---------+-----------------------------+
*/
@@ -7362,159 +7362,159 @@ static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn,
/* AdvSIMD across lanes
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
* | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
*/
static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
{
int rd = extract32(insn, 0, 5);
int rn = extract32(insn, 5, 5);
int size = extract32(insn, 22, 2);
int opcode = extract32(insn, 12, 5);
bool is_q = extract32(insn, 30, 1);
bool is_u = extract32(insn, 29, 1);
bool is_fp = false;
bool is_min = false;
int esize;
int elements;
int i;
TCGv_i64 tcg_res, tcg_elt;
switch (opcode) {
case 0x1b: /* ADDV */
if (is_u) {
unallocated_encoding(s);
return;
}
- /* fall through */
+ fallthrough;
case 0x3: /* SADDLV, UADDLV */
case 0xa: /* SMAXV, UMAXV */
case 0x1a: /* SMINV, UMINV */
if (size == 3 || (size == 2 && !is_q)) {
unallocated_encoding(s);
return;
}
break;
case 0xc: /* FMAXNMV, FMINNMV */
case 0xf: /* FMAXV, FMINV */
/* Bit 1 of size field encodes min vs max and the actual size
* depends on the encoding of the U bit. If not set (and FP16
* enabled) then we do half-precision float instead of single
* precision.
*/
is_min = extract32(size, 1, 1);
is_fp = true;
if (!is_u && dc_isar_feature(aa64_fp16, s)) {
size = 1;
} else if (!is_u || !is_q || extract32(size, 0, 1)) {
unallocated_encoding(s);
return;
} else {
size = 2;
}
break;
default:
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
esize = 8 << size;
elements = (is_q ? 128 : 64) / esize;
tcg_res = tcg_temp_new_i64();
tcg_elt = tcg_temp_new_i64();
/* These instructions operate across all lanes of a vector
* to produce a single result. We can guarantee that a 64
* bit intermediate is sufficient:
* + for [US]ADDLV the maximum element size is 32 bits, and
* the result type is 64 bits
* + for FMAX*V, FMIN*V, ADDV the intermediate type is the
* same as the element size, which is 32 bits at most
* For the integer operations we can choose to work at 64
* or 32 bits and truncate at the end; for simplicity
* we use 64 bits always. The floating point
* ops do require 32 bit intermediates, though.
*/
if (!is_fp) {
read_vec_element(s, tcg_res, rn, 0, size | (is_u ? 0 : MO_SIGN));
for (i = 1; i < elements; i++) {
read_vec_element(s, tcg_elt, rn, i, size | (is_u ? 0 : MO_SIGN));
switch (opcode) {
case 0x03: /* SADDLV / UADDLV */
case 0x1b: /* ADDV */
tcg_gen_add_i64(tcg_res, tcg_res, tcg_elt);
break;
case 0x0a: /* SMAXV / UMAXV */
if (is_u) {
tcg_gen_umax_i64(tcg_res, tcg_res, tcg_elt);
} else {
tcg_gen_smax_i64(tcg_res, tcg_res, tcg_elt);
}
break;
case 0x1a: /* SMINV / UMINV */
if (is_u) {
tcg_gen_umin_i64(tcg_res, tcg_res, tcg_elt);
} else {
tcg_gen_smin_i64(tcg_res, tcg_res, tcg_elt);
}
break;
default:
g_assert_not_reached();
}
}
} else {
/* Floating point vector reduction ops which work across 32
* bit (single) or 16 bit (half-precision) intermediates.
* Note that correct NaN propagation requires that we do these
* operations in exactly the order specified by the pseudocode.
*/
TCGv_ptr fpst = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
int fpopcode = opcode | is_min << 4 | is_u << 5;
int vmap = (1 << elements) - 1;
TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize,
(is_q ? 128 : 64), vmap, fpst);
tcg_gen_extu_i32_i64(tcg_res, tcg_res32);
}
/* Now truncate the result to the width required for the final output */
if (opcode == 0x03) {
/* SADDLV, UADDLV: result is 2*esize */
size++;
}
switch (size) {
case 0:
tcg_gen_ext8u_i64(tcg_res, tcg_res);
break;
case 1:
tcg_gen_ext16u_i64(tcg_res, tcg_res);
break;
case 2:
tcg_gen_ext32u_i64(tcg_res, tcg_res);
break;
case 3:
break;
default:
g_assert_not_reached();
}
write_fp_dreg(s, rd, tcg_res);
}
/* DUP (Element, Vector)
*
* 31 30 29 21 20 16 15 10 9 5 4 0
* +---+---+-------------------+--------+-------------+------+------+
* | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
* +---+---+-------------------+--------+-------------+------+------+
*
* size: encoded in imm5 (see ARM ARM LowestSetBit())
*/
@@ -8269,111 +8269,111 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
/* SQSHLU, UQSHL, SQSHL: saturating left shifts */
static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
bool src_unsigned, bool dst_unsigned,
int immh, int immb, int rn, int rd)
{
int immhb = immh << 3 | immb;
int size = 32 - clz32(immh) - 1;
int shift = immhb - (8 << size);
int pass;
assert(immh != 0);
assert(!(scalar && is_q));
if (!scalar) {
if (!is_q && extract32(immh, 3, 1)) {
unallocated_encoding(s);
return;
}
/* Since we use the variable-shift helpers we must
* replicate the shift count into each element of
* the tcg_shift value.
*/
switch (size) {
case 0:
shift |= shift << 8;
- /* fall through */
+ fallthrough;
case 1:
shift |= shift << 16;
break;
case 2:
case 3:
break;
default:
g_assert_not_reached();
}
}
if (!fp_access_check(s)) {
return;
}
if (size == 3) {
TCGv_i64 tcg_shift = tcg_constant_i64(shift);
static NeonGenTwo64OpEnvFn * const fns[2][2] = {
{ gen_helper_neon_qshl_s64, gen_helper_neon_qshlu_s64 },
{ NULL, gen_helper_neon_qshl_u64 },
};
NeonGenTwo64OpEnvFn *genfn = fns[src_unsigned][dst_unsigned];
int maxpass = is_q ? 2 : 1;
for (pass = 0; pass < maxpass; pass++) {
TCGv_i64 tcg_op = tcg_temp_new_i64();
read_vec_element(s, tcg_op, rn, pass, MO_64);
genfn(tcg_op, tcg_env, tcg_op, tcg_shift);
write_vec_element(s, tcg_op, rd, pass, MO_64);
}
clear_vec_high(s, is_q, rd);
} else {
TCGv_i32 tcg_shift = tcg_constant_i32(shift);
static NeonGenTwoOpEnvFn * const fns[2][2][3] = {
{
{ gen_helper_neon_qshl_s8,
gen_helper_neon_qshl_s16,
gen_helper_neon_qshl_s32 },
{ gen_helper_neon_qshlu_s8,
gen_helper_neon_qshlu_s16,
gen_helper_neon_qshlu_s32 }
}, {
{ NULL, NULL, NULL },
{ gen_helper_neon_qshl_u8,
gen_helper_neon_qshl_u16,
gen_helper_neon_qshl_u32 }
}
};
NeonGenTwoOpEnvFn *genfn = fns[src_unsigned][dst_unsigned][size];
MemOp memop = scalar ? size : MO_32;
int maxpass = scalar ? 1 : is_q ? 4 : 2;
for (pass = 0; pass < maxpass; pass++) {
TCGv_i32 tcg_op = tcg_temp_new_i32();
read_vec_element_i32(s, tcg_op, rn, pass, memop);
genfn(tcg_op, tcg_env, tcg_op, tcg_shift);
if (scalar) {
switch (size) {
case 0:
tcg_gen_ext8u_i32(tcg_op, tcg_op);
break;
case 1:
tcg_gen_ext16u_i32(tcg_op, tcg_op);
break;
case 2:
break;
default:
g_assert_not_reached();
}
write_fp_sreg(s, rd, tcg_op);
} else {
write_vec_element_i32(s, tcg_op, rd, pass, MO_32);
}
}
if (!scalar) {
clear_vec_high(s, is_q, rd);
}
}
}
/* Common vector code for handling integer to FP conversion */
@@ -8614,170 +8614,170 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
/* AdvSIMD scalar shift by immediate
* 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
* +-----+---+-------------+------+------+--------+---+------+------+
* | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
* +-----+---+-------------+------+------+--------+---+------+------+
*
* This is the scalar version so it works on a fixed sized registers
*/
static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
{
int rd = extract32(insn, 0, 5);
int rn = extract32(insn, 5, 5);
int opcode = extract32(insn, 11, 5);
int immb = extract32(insn, 16, 3);
int immh = extract32(insn, 19, 4);
bool is_u = extract32(insn, 29, 1);
if (immh == 0) {
unallocated_encoding(s);
return;
}
switch (opcode) {
case 0x08: /* SRI */
if (!is_u) {
unallocated_encoding(s);
return;
}
- /* fall through */
+ fallthrough;
case 0x00: /* SSHR / USHR */
case 0x02: /* SSRA / USRA */
case 0x04: /* SRSHR / URSHR */
case 0x06: /* SRSRA / URSRA */
handle_scalar_simd_shri(s, is_u, immh, immb, opcode, rn, rd);
break;
case 0x0a: /* SHL / SLI */
handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd);
break;
case 0x1c: /* SCVTF, UCVTF */
handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb,
opcode, rn, rd);
break;
case 0x10: /* SQSHRUN, SQSHRUN2 */
case 0x11: /* SQRSHRUN, SQRSHRUN2 */
if (!is_u) {
unallocated_encoding(s);
return;
}
handle_vec_simd_sqshrn(s, true, false, false, true,
immh, immb, opcode, rn, rd);
break;
case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
handle_vec_simd_sqshrn(s, true, false, is_u, is_u,
immh, immb, opcode, rn, rd);
break;
case 0xc: /* SQSHLU */
if (!is_u) {
unallocated_encoding(s);
return;
}
handle_simd_qshl(s, true, false, false, true, immh, immb, rn, rd);
break;
case 0xe: /* SQSHL, UQSHL */
handle_simd_qshl(s, true, false, is_u, is_u, immh, immb, rn, rd);
break;
case 0x1f: /* FCVTZS, FCVTZU */
handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn, rd);
break;
default:
unallocated_encoding(s);
break;
}
}
/* AdvSIMD scalar three different
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
* +-----+---+-----------+------+---+------+--------+-----+------+------+
* | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
* +-----+---+-----------+------+---+------+--------+-----+------+------+
*/
static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
{
bool is_u = extract32(insn, 29, 1);
int size = extract32(insn, 22, 2);
int opcode = extract32(insn, 12, 4);
int rm = extract32(insn, 16, 5);
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
if (is_u) {
unallocated_encoding(s);
return;
}
switch (opcode) {
case 0x9: /* SQDMLAL, SQDMLAL2 */
case 0xb: /* SQDMLSL, SQDMLSL2 */
case 0xd: /* SQDMULL, SQDMULL2 */
if (size == 0 || size == 3) {
unallocated_encoding(s);
return;
}
break;
default:
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
if (size == 2) {
TCGv_i64 tcg_op1 = tcg_temp_new_i64();
TCGv_i64 tcg_op2 = tcg_temp_new_i64();
TCGv_i64 tcg_res = tcg_temp_new_i64();
read_vec_element(s, tcg_op1, rn, 0, MO_32 | MO_SIGN);
read_vec_element(s, tcg_op2, rm, 0, MO_32 | MO_SIGN);
tcg_gen_mul_i64(tcg_res, tcg_op1, tcg_op2);
gen_helper_neon_addl_saturate_s64(tcg_res, tcg_env, tcg_res, tcg_res);
switch (opcode) {
case 0xd: /* SQDMULL, SQDMULL2 */
break;
case 0xb: /* SQDMLSL, SQDMLSL2 */
tcg_gen_neg_i64(tcg_res, tcg_res);
- /* fall through */
+ fallthrough;
case 0x9: /* SQDMLAL, SQDMLAL2 */
read_vec_element(s, tcg_op1, rd, 0, MO_64);
gen_helper_neon_addl_saturate_s64(tcg_res, tcg_env,
tcg_res, tcg_op1);
break;
default:
g_assert_not_reached();
}
write_fp_dreg(s, rd, tcg_res);
} else {
TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
TCGv_i64 tcg_res = tcg_temp_new_i64();
gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
gen_helper_neon_addl_saturate_s32(tcg_res, tcg_env, tcg_res, tcg_res);
switch (opcode) {
case 0xd: /* SQDMULL, SQDMULL2 */
break;
case 0xb: /* SQDMLSL, SQDMLSL2 */
gen_helper_neon_negl_u32(tcg_res, tcg_res);
- /* fall through */
+ fallthrough;
case 0x9: /* SQDMLAL, SQDMLAL2 */
{
TCGv_i64 tcg_op3 = tcg_temp_new_i64();
read_vec_element(s, tcg_op3, rd, 0, MO_32);
gen_helper_neon_addl_saturate_s32(tcg_res, tcg_env,
tcg_res, tcg_op3);
break;
}
default:
g_assert_not_reached();
}
tcg_gen_ext32u_i64(tcg_res, tcg_res);
write_fp_dreg(s, rd, tcg_res);
}
}
@@ -8866,183 +8866,183 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
/* Handle the 3-same-operands float operations; shared by the scalar
* and vector encodings. The caller must filter out any encodings
* not allocated for the encoding it is dealing with.
*/
static void handle_3same_float(DisasContext *s, int size, int elements,
int fpopcode, int rd, int rn, int rm)
{
int pass;
TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
for (pass = 0; pass < elements; pass++) {
if (size) {
/* Double */
TCGv_i64 tcg_op1 = tcg_temp_new_i64();
TCGv_i64 tcg_op2 = tcg_temp_new_i64();
TCGv_i64 tcg_res = tcg_temp_new_i64();
read_vec_element(s, tcg_op1, rn, pass, MO_64);
read_vec_element(s, tcg_op2, rm, pass, MO_64);
switch (fpopcode) {
case 0x39: /* FMLS */
/* As usual for ARM, separate negation for fused multiply-add */
gen_helper_vfp_negd(tcg_op1, tcg_op1);
- /* fall through */
+ fallthrough;
case 0x19: /* FMLA */
read_vec_element(s, tcg_res, rd, pass, MO_64);
gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2,
tcg_res, fpst);
break;
case 0x18: /* FMAXNM */
gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x1a: /* FADD */
gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x1b: /* FMULX */
gen_helper_vfp_mulxd(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x1c: /* FCMEQ */
gen_helper_neon_ceq_f64(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x1e: /* FMAX */
gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x1f: /* FRECPS */
gen_helper_recpsf_f64(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x38: /* FMINNM */
gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x3a: /* FSUB */
gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x3e: /* FMIN */
gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x3f: /* FRSQRTS */
gen_helper_rsqrtsf_f64(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x5b: /* FMUL */
gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x5c: /* FCMGE */
gen_helper_neon_cge_f64(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x5d: /* FACGE */
gen_helper_neon_acge_f64(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x5f: /* FDIV */
gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x7a: /* FABD */
gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst);
gen_helper_vfp_absd(tcg_res, tcg_res);
break;
case 0x7c: /* FCMGT */
gen_helper_neon_cgt_f64(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x7d: /* FACGT */
gen_helper_neon_acgt_f64(tcg_res, tcg_op1, tcg_op2, fpst);
break;
default:
g_assert_not_reached();
}
write_vec_element(s, tcg_res, rd, pass, MO_64);
} else {
/* Single */
TCGv_i32 tcg_op1 = tcg_temp_new_i32();
TCGv_i32 tcg_op2 = tcg_temp_new_i32();
TCGv_i32 tcg_res = tcg_temp_new_i32();
read_vec_element_i32(s, tcg_op1, rn, pass, MO_32);
read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);
switch (fpopcode) {
case 0x39: /* FMLS */
/* As usual for ARM, separate negation for fused multiply-add */
gen_helper_vfp_negs(tcg_op1, tcg_op1);
- /* fall through */
+ fallthrough;
case 0x19: /* FMLA */
read_vec_element_i32(s, tcg_res, rd, pass, MO_32);
gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2,
tcg_res, fpst);
break;
case 0x1a: /* FADD */
gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x1b: /* FMULX */
gen_helper_vfp_mulxs(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x1c: /* FCMEQ */
gen_helper_neon_ceq_f32(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x1e: /* FMAX */
gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x1f: /* FRECPS */
gen_helper_recpsf_f32(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x18: /* FMAXNM */
gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x38: /* FMINNM */
gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x3a: /* FSUB */
gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x3e: /* FMIN */
gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x3f: /* FRSQRTS */
gen_helper_rsqrtsf_f32(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x5b: /* FMUL */
gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x5c: /* FCMGE */
gen_helper_neon_cge_f32(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x5d: /* FACGE */
gen_helper_neon_acge_f32(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x5f: /* FDIV */
gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x7a: /* FABD */
gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst);
gen_helper_vfp_abss(tcg_res, tcg_res);
break;
case 0x7c: /* FCMGT */
gen_helper_neon_cgt_f32(tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x7d: /* FACGT */
gen_helper_neon_acgt_f32(tcg_res, tcg_op1, tcg_op2, fpst);
break;
default:
g_assert_not_reached();
}
if (elements == 1) {
/* scalar single so clear high part */
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
tcg_gen_extu_i32_i64(tcg_tmp, tcg_res);
write_vec_element(s, tcg_tmp, rd, pass, MO_64);
} else {
write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
}
}
}
clear_vec_high(s, elements * (size ? 8 : 4) > 8, rd);
}
/* AdvSIMD scalar three same
* 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
* +-----+---+-----------+------+---+------+--------+---+------+------+
* | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
* +-----+---+-----------+------+---+------+--------+---+------+------+
*/
@@ -9468,128 +9468,128 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
bool is_scalar, bool is_u, bool is_q,
int size, int rn, int rd)
{
bool is_double = (size == MO_64);
TCGv_ptr fpst;
if (!fp_access_check(s)) {
return;
}
fpst = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
if (is_double) {
TCGv_i64 tcg_op = tcg_temp_new_i64();
TCGv_i64 tcg_zero = tcg_constant_i64(0);
TCGv_i64 tcg_res = tcg_temp_new_i64();
NeonGenTwoDoubleOpFn *genfn;
bool swap = false;
int pass;
switch (opcode) {
case 0x2e: /* FCMLT (zero) */
swap = true;
- /* fallthrough */
+ fallthrough;
case 0x2c: /* FCMGT (zero) */
genfn = gen_helper_neon_cgt_f64;
break;
case 0x2d: /* FCMEQ (zero) */
genfn = gen_helper_neon_ceq_f64;
break;
case 0x6d: /* FCMLE (zero) */
swap = true;
- /* fall through */
+ fallthrough;
case 0x6c: /* FCMGE (zero) */
genfn = gen_helper_neon_cge_f64;
break;
default:
g_assert_not_reached();
}
for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
read_vec_element(s, tcg_op, rn, pass, MO_64);
if (swap) {
genfn(tcg_res, tcg_zero, tcg_op, fpst);
} else {
genfn(tcg_res, tcg_op, tcg_zero, fpst);
}
write_vec_element(s, tcg_res, rd, pass, MO_64);
}
clear_vec_high(s, !is_scalar, rd);
} else {
TCGv_i32 tcg_op = tcg_temp_new_i32();
TCGv_i32 tcg_zero = tcg_constant_i32(0);
TCGv_i32 tcg_res = tcg_temp_new_i32();
NeonGenTwoSingleOpFn *genfn;
bool swap = false;
int pass, maxpasses;
if (size == MO_16) {
switch (opcode) {
case 0x2e: /* FCMLT (zero) */
swap = true;
- /* fall through */
+ fallthrough;
case 0x2c: /* FCMGT (zero) */
genfn = gen_helper_advsimd_cgt_f16;
break;
case 0x2d: /* FCMEQ (zero) */
genfn = gen_helper_advsimd_ceq_f16;
break;
case 0x6d: /* FCMLE (zero) */
swap = true;
- /* fall through */
+ fallthrough;
case 0x6c: /* FCMGE (zero) */
genfn = gen_helper_advsimd_cge_f16;
break;
default:
g_assert_not_reached();
}
} else {
switch (opcode) {
case 0x2e: /* FCMLT (zero) */
swap = true;
- /* fall through */
+ fallthrough;
case 0x2c: /* FCMGT (zero) */
genfn = gen_helper_neon_cgt_f32;
break;
case 0x2d: /* FCMEQ (zero) */
genfn = gen_helper_neon_ceq_f32;
break;
case 0x6d: /* FCMLE (zero) */
swap = true;
- /* fall through */
+ fallthrough;
case 0x6c: /* FCMGE (zero) */
genfn = gen_helper_neon_cge_f32;
break;
default:
g_assert_not_reached();
}
}
if (is_scalar) {
maxpasses = 1;
} else {
int vector_size = 8 << is_q;
maxpasses = vector_size >> size;
}
for (pass = 0; pass < maxpasses; pass++) {
read_vec_element_i32(s, tcg_op, rn, pass, size);
if (swap) {
genfn(tcg_res, tcg_zero, tcg_op, fpst);
} else {
genfn(tcg_res, tcg_op, tcg_zero, fpst);
}
if (is_scalar) {
write_fp_sreg(s, rd, tcg_res);
} else {
write_vec_element_i32(s, tcg_res, rd, pass, size);
}
}
if (!is_scalar) {
clear_vec_high(s, is_q, rd);
}
}
}
@@ -9859,194 +9859,194 @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
/* AdvSIMD scalar two reg misc
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
* +-----+---+-----------+------+-----------+--------+-----+------+------+
* | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
* +-----+---+-----------+------+-----------+--------+-----+------+------+
*/
static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
{
int rd = extract32(insn, 0, 5);
int rn = extract32(insn, 5, 5);
int opcode = extract32(insn, 12, 5);
int size = extract32(insn, 22, 2);
bool u = extract32(insn, 29, 1);
bool is_fcvt = false;
int rmode;
TCGv_i32 tcg_rmode;
TCGv_ptr tcg_fpstatus;
switch (opcode) {
case 0x3: /* USQADD / SUQADD*/
if (!fp_access_check(s)) {
return;
}
handle_2misc_satacc(s, true, u, false, size, rn, rd);
return;
case 0x7: /* SQABS / SQNEG */
break;
case 0xa: /* CMLT */
if (u) {
unallocated_encoding(s);
return;
}
- /* fall through */
+ fallthrough;
case 0x8: /* CMGT, CMGE */
case 0x9: /* CMEQ, CMLE */
case 0xb: /* ABS, NEG */
if (size != 3) {
unallocated_encoding(s);
return;
}
break;
case 0x12: /* SQXTUN */
if (!u) {
unallocated_encoding(s);
return;
}
- /* fall through */
+ fallthrough;
case 0x14: /* SQXTN, UQXTN */
if (size == 3) {
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
handle_2misc_narrow(s, true, opcode, u, false, size, rn, rd);
return;
case 0xc ... 0xf:
case 0x16 ... 0x1d:
case 0x1f:
/* Floating point: U, size[1] and opcode indicate operation;
* size[0] indicates single or double precision.
*/
opcode |= (extract32(size, 1, 1) << 5) | (u << 6);
size = extract32(size, 0, 1) ? 3 : 2;
switch (opcode) {
case 0x2c: /* FCMGT (zero) */
case 0x2d: /* FCMEQ (zero) */
case 0x2e: /* FCMLT (zero) */
case 0x6c: /* FCMGE (zero) */
case 0x6d: /* FCMLE (zero) */
handle_2misc_fcmp_zero(s, opcode, true, u, true, size, rn, rd);
return;
case 0x1d: /* SCVTF */
case 0x5d: /* UCVTF */
{
bool is_signed = (opcode == 0x1d);
if (!fp_access_check(s)) {
return;
}
handle_simd_intfp_conv(s, rd, rn, 1, is_signed, 0, size);
return;
}
case 0x3d: /* FRECPE */
case 0x3f: /* FRECPX */
case 0x7d: /* FRSQRTE */
if (!fp_access_check(s)) {
return;
}
handle_2misc_reciprocal(s, opcode, true, u, true, size, rn, rd);
return;
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
case 0x3a: /* FCVTPS */
case 0x3b: /* FCVTZS */
case 0x5a: /* FCVTNU */
case 0x5b: /* FCVTMU */
case 0x7a: /* FCVTPU */
case 0x7b: /* FCVTZU */
is_fcvt = true;
rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
break;
case 0x1c: /* FCVTAS */
case 0x5c: /* FCVTAU */
/* TIEAWAY doesn't fit in the usual rounding mode encoding */
is_fcvt = true;
rmode = FPROUNDING_TIEAWAY;
break;
case 0x56: /* FCVTXN, FCVTXN2 */
if (size == 2) {
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
handle_2misc_narrow(s, true, opcode, u, false, size - 1, rn, rd);
return;
default:
unallocated_encoding(s);
return;
}
break;
default:
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
if (is_fcvt) {
tcg_fpstatus = fpstatus_ptr(FPST_FPCR);
tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
} else {
tcg_fpstatus = NULL;
tcg_rmode = NULL;
}
if (size == 3) {
TCGv_i64 tcg_rn = read_fp_dreg(s, rn);
TCGv_i64 tcg_rd = tcg_temp_new_i64();
handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rmode, tcg_fpstatus);
write_fp_dreg(s, rd, tcg_rd);
} else {
TCGv_i32 tcg_rn = tcg_temp_new_i32();
TCGv_i32 tcg_rd = tcg_temp_new_i32();
read_vec_element_i32(s, tcg_rn, rn, 0, size);
switch (opcode) {
case 0x7: /* SQABS, SQNEG */
{
NeonGenOneOpEnvFn *genfn;
static NeonGenOneOpEnvFn * const fns[3][2] = {
{ gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 },
{ gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 },
{ gen_helper_neon_qabs_s32, gen_helper_neon_qneg_s32 },
};
genfn = fns[size][u];
genfn(tcg_rd, tcg_env, tcg_rn);
break;
}
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
case 0x1c: /* FCVTAS */
case 0x3a: /* FCVTPS */
case 0x3b: /* FCVTZS */
gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_constant_i32(0),
tcg_fpstatus);
break;
case 0x5a: /* FCVTNU */
case 0x5b: /* FCVTMU */
case 0x5c: /* FCVTAU */
case 0x7a: /* FCVTPU */
case 0x7b: /* FCVTZU */
gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_constant_i32(0),
tcg_fpstatus);
break;
default:
g_assert_not_reached();
}
write_fp_sreg(s, rd, tcg_rd);
}
if (is_fcvt) {
gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
/* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
@@ -10230,78 +10230,78 @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
/* AdvSIMD shift by immediate
* 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
* +---+---+---+-------------+------+------+--------+---+------+------+
* | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
* +---+---+---+-------------+------+------+--------+---+------+------+
*/
static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
{
int rd = extract32(insn, 0, 5);
int rn = extract32(insn, 5, 5);
int opcode = extract32(insn, 11, 5);
int immb = extract32(insn, 16, 3);
int immh = extract32(insn, 19, 4);
bool is_u = extract32(insn, 29, 1);
bool is_q = extract32(insn, 30, 1);
/* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
assert(immh != 0);
switch (opcode) {
case 0x08: /* SRI */
if (!is_u) {
unallocated_encoding(s);
return;
}
- /* fall through */
+ fallthrough;
case 0x00: /* SSHR / USHR */
case 0x02: /* SSRA / USRA (accumulate) */
case 0x04: /* SRSHR / URSHR (rounding) */
case 0x06: /* SRSRA / URSRA (accum + rounding) */
handle_vec_simd_shri(s, is_q, is_u, immh, immb, opcode, rn, rd);
break;
case 0x0a: /* SHL / SLI */
handle_vec_simd_shli(s, is_q, is_u, immh, immb, opcode, rn, rd);
break;
case 0x10: /* SHRN */
case 0x11: /* RSHRN / SQRSHRUN */
if (is_u) {
handle_vec_simd_sqshrn(s, false, is_q, false, true, immh, immb,
opcode, rn, rd);
} else {
handle_vec_simd_shrn(s, is_q, immh, immb, opcode, rn, rd);
}
break;
case 0x12: /* SQSHRN / UQSHRN */
case 0x13: /* SQRSHRN / UQRSHRN */
handle_vec_simd_sqshrn(s, false, is_q, is_u, is_u, immh, immb,
opcode, rn, rd);
break;
case 0x14: /* SSHLL / USHLL */
handle_vec_simd_wshli(s, is_q, is_u, immh, immb, opcode, rn, rd);
break;
case 0x1c: /* SCVTF / UCVTF */
handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb,
opcode, rn, rd);
break;
case 0xc: /* SQSHLU */
if (!is_u) {
unallocated_encoding(s);
return;
}
handle_simd_qshl(s, false, is_q, false, true, immh, immb, rn, rd);
break;
case 0xe: /* SQSHL, UQSHL */
handle_simd_qshl(s, false, is_q, is_u, is_u, immh, immb, rn, rd);
break;
case 0x1f: /* FCVTZS/ FCVTZU */
handle_simd_shift_fpint_conv(s, false, is_q, is_u, immh, immb, rn, rd);
return;
default:
unallocated_encoding(s);
return;
}
}
/* Generate code to do a "long" addition or subtraction, ie one done in
* TCGv_i64 on vector lanes twice the width specified by size.
*/
@@ -10598,118 +10598,118 @@ static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size,
/* AdvSIMD three different
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
* | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
*/
static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
{
/* Instructions in this group fall into three basic classes
* (in each case with the operation working on each element in
* the input vectors):
* (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
* 128 bit input)
* (2) wide 64 x 128 -> 128
* (3) narrowing 128 x 128 -> 64
* Here we do initial decode, catch unallocated cases and
* dispatch to separate functions for each class.
*/
int is_q = extract32(insn, 30, 1);
int is_u = extract32(insn, 29, 1);
int size = extract32(insn, 22, 2);
int opcode = extract32(insn, 12, 4);
int rm = extract32(insn, 16, 5);
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
switch (opcode) {
case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
/* 64 x 128 -> 128 */
if (size == 3) {
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
handle_3rd_wide(s, is_q, is_u, size, opcode, rd, rn, rm);
break;
case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
/* 128 x 128 -> 64 */
if (size == 3) {
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
handle_3rd_narrowing(s, is_q, is_u, size, opcode, rd, rn, rm);
break;
case 14: /* PMULL, PMULL2 */
if (is_u) {
unallocated_encoding(s);
return;
}
switch (size) {
case 0: /* PMULL.P8 */
if (!fp_access_check(s)) {
return;
}
/* The Q field specifies lo/hi half input for this insn. */
gen_gvec_op3_ool(s, true, rd, rn, rm, is_q,
gen_helper_neon_pmull_h);
break;
case 3: /* PMULL.P64 */
if (!dc_isar_feature(aa64_pmull, s)) {
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
/* The Q field specifies lo/hi half input for this insn. */
gen_gvec_op3_ool(s, true, rd, rn, rm, is_q,
gen_helper_gvec_pmull_q);
break;
default:
unallocated_encoding(s);
break;
}
return;
case 9: /* SQDMLAL, SQDMLAL2 */
case 11: /* SQDMLSL, SQDMLSL2 */
case 13: /* SQDMULL, SQDMULL2 */
if (is_u || size == 0) {
unallocated_encoding(s);
return;
}
- /* fall through */
+ fallthrough;
case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
/* 64 x 64 -> 128 */
if (size == 3) {
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
handle_3rd_widening(s, is_q, is_u, size, opcode, rd, rn, rm);
break;
default:
/* opcode 15 not allocated */
unallocated_encoding(s);
break;
}
}
/* Logic op (opcode == 3) subgroup of C3.6.16. */
@@ -10993,260 +10993,260 @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
/* Integer op subgroup of C3.6.16. */
static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
{
int is_q = extract32(insn, 30, 1);
int u = extract32(insn, 29, 1);
int size = extract32(insn, 22, 2);
int opcode = extract32(insn, 11, 5);
int rm = extract32(insn, 16, 5);
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
int pass;
TCGCond cond;
switch (opcode) {
case 0x13: /* MUL, PMUL */
if (u && size != 0) {
unallocated_encoding(s);
return;
}
- /* fall through */
+ fallthrough;
case 0x0: /* SHADD, UHADD */
case 0x2: /* SRHADD, URHADD */
case 0x4: /* SHSUB, UHSUB */
case 0xc: /* SMAX, UMAX */
case 0xd: /* SMIN, UMIN */
case 0xe: /* SABD, UABD */
case 0xf: /* SABA, UABA */
case 0x12: /* MLA, MLS */
if (size == 3) {
unallocated_encoding(s);
return;
}
break;
case 0x16: /* SQDMULH, SQRDMULH */
if (size == 0 || size == 3) {
unallocated_encoding(s);
return;
}
break;
default:
if (size == 3 && !is_q) {
unallocated_encoding(s);
return;
}
break;
}
if (!fp_access_check(s)) {
return;
}
switch (opcode) {
case 0x01: /* SQADD, UQADD */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uqadd_qc, size);
} else {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqadd_qc, size);
}
return;
case 0x05: /* SQSUB, UQSUB */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uqsub_qc, size);
} else {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqsub_qc, size);
}
return;
case 0x08: /* SSHL, USHL */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_ushl, size);
} else {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sshl, size);
}
return;
case 0x0c: /* SMAX, UMAX */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size);
} else {
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smax, size);
}
return;
case 0x0d: /* SMIN, UMIN */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umin, size);
} else {
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smin, size);
}
return;
case 0xe: /* SABD, UABD */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uabd, size);
} else {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sabd, size);
}
return;
case 0xf: /* SABA, UABA */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uaba, size);
} else {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_saba, size);
}
return;
case 0x10: /* ADD, SUB */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_sub, size);
} else {
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_add, size);
}
return;
case 0x13: /* MUL, PMUL */
if (!u) { /* MUL */
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_mul, size);
} else { /* PMUL */
gen_gvec_op3_ool(s, is_q, rd, rn, rm, 0, gen_helper_gvec_pmul_b);
}
return;
case 0x12: /* MLA, MLS */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mls, size);
} else {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mla, size);
}
return;
case 0x16: /* SQDMULH, SQRDMULH */
{
static gen_helper_gvec_3_ptr * const fns[2][2] = {
{ gen_helper_neon_sqdmulh_h, gen_helper_neon_sqrdmulh_h },
{ gen_helper_neon_sqdmulh_s, gen_helper_neon_sqrdmulh_s },
};
gen_gvec_op3_qc(s, is_q, rd, rn, rm, fns[size - 1][u]);
}
return;
case 0x11:
if (!u) { /* CMTST */
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_cmtst, size);
return;
}
/* else CMEQ */
cond = TCG_COND_EQ;
goto do_gvec_cmp;
case 0x06: /* CMGT, CMHI */
cond = u ? TCG_COND_GTU : TCG_COND_GT;
goto do_gvec_cmp;
case 0x07: /* CMGE, CMHS */
cond = u ? TCG_COND_GEU : TCG_COND_GE;
do_gvec_cmp:
tcg_gen_gvec_cmp(cond, size, vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm),
is_q ? 16 : 8, vec_full_reg_size(s));
return;
}
if (size == 3) {
assert(is_q);
for (pass = 0; pass < 2; pass++) {
TCGv_i64 tcg_op1 = tcg_temp_new_i64();
TCGv_i64 tcg_op2 = tcg_temp_new_i64();
TCGv_i64 tcg_res = tcg_temp_new_i64();
read_vec_element(s, tcg_op1, rn, pass, MO_64);
read_vec_element(s, tcg_op2, rm, pass, MO_64);
handle_3same_64(s, opcode, u, tcg_res, tcg_op1, tcg_op2);
write_vec_element(s, tcg_res, rd, pass, MO_64);
}
} else {
for (pass = 0; pass < (is_q ? 4 : 2); pass++) {
TCGv_i32 tcg_op1 = tcg_temp_new_i32();
TCGv_i32 tcg_op2 = tcg_temp_new_i32();
TCGv_i32 tcg_res = tcg_temp_new_i32();
NeonGenTwoOpFn *genfn = NULL;
NeonGenTwoOpEnvFn *genenvfn = NULL;
read_vec_element_i32(s, tcg_op1, rn, pass, MO_32);
read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);
switch (opcode) {
case 0x0: /* SHADD, UHADD */
{
static NeonGenTwoOpFn * const fns[3][2] = {
{ gen_helper_neon_hadd_s8, gen_helper_neon_hadd_u8 },
{ gen_helper_neon_hadd_s16, gen_helper_neon_hadd_u16 },
{ gen_helper_neon_hadd_s32, gen_helper_neon_hadd_u32 },
};
genfn = fns[size][u];
break;
}
case 0x2: /* SRHADD, URHADD */
{
static NeonGenTwoOpFn * const fns[3][2] = {
{ gen_helper_neon_rhadd_s8, gen_helper_neon_rhadd_u8 },
{ gen_helper_neon_rhadd_s16, gen_helper_neon_rhadd_u16 },
{ gen_helper_neon_rhadd_s32, gen_helper_neon_rhadd_u32 },
};
genfn = fns[size][u];
break;
}
case 0x4: /* SHSUB, UHSUB */
{
static NeonGenTwoOpFn * const fns[3][2] = {
{ gen_helper_neon_hsub_s8, gen_helper_neon_hsub_u8 },
{ gen_helper_neon_hsub_s16, gen_helper_neon_hsub_u16 },
{ gen_helper_neon_hsub_s32, gen_helper_neon_hsub_u32 },
};
genfn = fns[size][u];
break;
}
case 0x9: /* SQSHL, UQSHL */
{
static NeonGenTwoOpEnvFn * const fns[3][2] = {
{ gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 },
{ gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 },
{ gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 },
};
genenvfn = fns[size][u];
break;
}
case 0xa: /* SRSHL, URSHL */
{
static NeonGenTwoOpFn * const fns[3][2] = {
{ gen_helper_neon_rshl_s8, gen_helper_neon_rshl_u8 },
{ gen_helper_neon_rshl_s16, gen_helper_neon_rshl_u16 },
{ gen_helper_neon_rshl_s32, gen_helper_neon_rshl_u32 },
};
genfn = fns[size][u];
break;
}
case 0xb: /* SQRSHL, UQRSHL */
{
static NeonGenTwoOpEnvFn * const fns[3][2] = {
{ gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 },
{ gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 },
{ gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 },
};
genenvfn = fns[size][u];
break;
}
default:
g_assert_not_reached();
}
if (genenvfn) {
genenvfn(tcg_res, tcg_env, tcg_op1, tcg_op2);
} else {
genfn(tcg_res, tcg_op1, tcg_op2);
}
write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
}
}
clear_vec_high(s, is_q, rd);
}
/* AdvSIMD three same
* 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
* +---+---+---+-----------+------+---+------+--------+---+------+------+
* | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
* +---+---+---+-----------+------+---+------+--------+---+------+------+
*/
@@ -11894,489 +11894,489 @@ static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)
/* AdvSIMD two reg misc
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
* | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
*/
static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
{
int size = extract32(insn, 22, 2);
int opcode = extract32(insn, 12, 5);
bool u = extract32(insn, 29, 1);
bool is_q = extract32(insn, 30, 1);
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
bool need_fpstatus = false;
int rmode = -1;
TCGv_i32 tcg_rmode;
TCGv_ptr tcg_fpstatus;
switch (opcode) {
case 0x0: /* REV64, REV32 */
case 0x1: /* REV16 */
handle_rev(s, opcode, u, is_q, size, rn, rd);
return;
case 0x5: /* CNT, NOT, RBIT */
if (u && size == 0) {
/* NOT */
break;
} else if (u && size == 1) {
/* RBIT */
break;
} else if (!u && size == 0) {
/* CNT */
break;
}
unallocated_encoding(s);
return;
case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
if (size == 3) {
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd);
return;
case 0x4: /* CLS, CLZ */
if (size == 3) {
unallocated_encoding(s);
return;
}
break;
case 0x2: /* SADDLP, UADDLP */
case 0x6: /* SADALP, UADALP */
if (size == 3) {
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
handle_2misc_pairwise(s, opcode, u, is_q, size, rn, rd);
return;
case 0x13: /* SHLL, SHLL2 */
if (u == 0 || size == 3) {
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
handle_shll(s, is_q, size, rn, rd);
return;
case 0xa: /* CMLT */
if (u == 1) {
unallocated_encoding(s);
return;
}
- /* fall through */
+ fallthrough;
case 0x8: /* CMGT, CMGE */
case 0x9: /* CMEQ, CMLE */
case 0xb: /* ABS, NEG */
if (size == 3 && !is_q) {
unallocated_encoding(s);
return;
}
break;
case 0x3: /* SUQADD, USQADD */
if (size == 3 && !is_q) {
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
handle_2misc_satacc(s, false, u, is_q, size, rn, rd);
return;
case 0x7: /* SQABS, SQNEG */
if (size == 3 && !is_q) {
unallocated_encoding(s);
return;
}
break;
case 0xc ... 0xf:
case 0x16 ... 0x1f:
{
/* Floating point: U, size[1] and opcode indicate operation;
* size[0] indicates single or double precision.
*/
int is_double = extract32(size, 0, 1);
opcode |= (extract32(size, 1, 1) << 5) | (u << 6);
size = is_double ? 3 : 2;
switch (opcode) {
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
if (size == 3 && !is_q) {
unallocated_encoding(s);
return;
}
break;
case 0x1d: /* SCVTF */
case 0x5d: /* UCVTF */
{
bool is_signed = (opcode == 0x1d) ? true : false;
int elements = is_double ? 2 : is_q ? 4 : 2;
if (is_double && !is_q) {
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
handle_simd_intfp_conv(s, rd, rn, elements, is_signed, 0, size);
return;
}
case 0x2c: /* FCMGT (zero) */
case 0x2d: /* FCMEQ (zero) */
case 0x2e: /* FCMLT (zero) */
case 0x6c: /* FCMGE (zero) */
case 0x6d: /* FCMLE (zero) */
if (size == 3 && !is_q) {
unallocated_encoding(s);
return;
}
handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd);
return;
case 0x7f: /* FSQRT */
if (size == 3 && !is_q) {
unallocated_encoding(s);
return;
}
break;
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
case 0x3a: /* FCVTPS */
case 0x3b: /* FCVTZS */
case 0x5a: /* FCVTNU */
case 0x5b: /* FCVTMU */
case 0x7a: /* FCVTPU */
case 0x7b: /* FCVTZU */
need_fpstatus = true;
rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
if (size == 3 && !is_q) {
unallocated_encoding(s);
return;
}
break;
case 0x5c: /* FCVTAU */
case 0x1c: /* FCVTAS */
need_fpstatus = true;
rmode = FPROUNDING_TIEAWAY;
if (size == 3 && !is_q) {
unallocated_encoding(s);
return;
}
break;
case 0x3c: /* URECPE */
if (size == 3) {
unallocated_encoding(s);
return;
}
- /* fall through */
+ fallthrough;
case 0x3d: /* FRECPE */
case 0x7d: /* FRSQRTE */
if (size == 3 && !is_q) {
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
handle_2misc_reciprocal(s, opcode, false, u, is_q, size, rn, rd);
return;
case 0x56: /* FCVTXN, FCVTXN2 */
if (size == 2) {
unallocated_encoding(s);
return;
}
- /* fall through */
+ fallthrough;
case 0x16: /* FCVTN, FCVTN2 */
/* handle_2misc_narrow does a 2*size -> size operation, but these
* instructions encode the source size rather than dest size.
*/
if (!fp_access_check(s)) {
return;
}
handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd);
return;
case 0x36: /* BFCVTN, BFCVTN2 */
if (!dc_isar_feature(aa64_bf16, s) || size != 2) {
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd);
return;
case 0x17: /* FCVTL, FCVTL2 */
if (!fp_access_check(s)) {
return;
}
handle_2misc_widening(s, opcode, is_q, size, rn, rd);
return;
case 0x18: /* FRINTN */
case 0x19: /* FRINTM */
case 0x38: /* FRINTP */
case 0x39: /* FRINTZ */
rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
- /* fall through */
+ fallthrough;
case 0x59: /* FRINTX */
case 0x79: /* FRINTI */
need_fpstatus = true;
if (size == 3 && !is_q) {
unallocated_encoding(s);
return;
}
break;
case 0x58: /* FRINTA */
rmode = FPROUNDING_TIEAWAY;
need_fpstatus = true;
if (size == 3 && !is_q) {
unallocated_encoding(s);
return;
}
break;
case 0x7c: /* URSQRTE */
if (size == 3) {
unallocated_encoding(s);
return;
}
break;
case 0x1e: /* FRINT32Z */
case 0x1f: /* FRINT64Z */
rmode = FPROUNDING_ZERO;
- /* fall through */
+ fallthrough;
case 0x5e: /* FRINT32X */
case 0x5f: /* FRINT64X */
need_fpstatus = true;
if ((size == 3 && !is_q) || !dc_isar_feature(aa64_frint, s)) {
unallocated_encoding(s);
return;
}
break;
default:
unallocated_encoding(s);
return;
}
break;
}
default:
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
if (need_fpstatus || rmode >= 0) {
tcg_fpstatus = fpstatus_ptr(FPST_FPCR);
} else {
tcg_fpstatus = NULL;
}
if (rmode >= 0) {
tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
} else {
tcg_rmode = NULL;
}
switch (opcode) {
case 0x5:
if (u && size == 0) { /* NOT */
gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_not, 0);
return;
}
break;
case 0x8: /* CMGT, CMGE */
if (u) {
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cge0, size);
} else {
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cgt0, size);
}
return;
case 0x9: /* CMEQ, CMLE */
if (u) {
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cle0, size);
} else {
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_ceq0, size);
}
return;
case 0xa: /* CMLT */
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_clt0, size);
return;
case 0xb:
if (u) { /* ABS, NEG */
gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size);
} else {
gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_abs, size);
}
return;
}
if (size == 3) {
/* All 64-bit element operations can be shared with scalar 2misc */
int pass;
/* Coverity claims (size == 3 && !is_q) has been eliminated
* from all paths leading to here.
*/
tcg_debug_assert(is_q);
for (pass = 0; pass < 2; pass++) {
TCGv_i64 tcg_op = tcg_temp_new_i64();
TCGv_i64 tcg_res = tcg_temp_new_i64();
read_vec_element(s, tcg_op, rn, pass, MO_64);
handle_2misc_64(s, opcode, u, tcg_res, tcg_op,
tcg_rmode, tcg_fpstatus);
write_vec_element(s, tcg_res, rd, pass, MO_64);
}
} else {
int pass;
for (pass = 0; pass < (is_q ? 4 : 2); pass++) {
TCGv_i32 tcg_op = tcg_temp_new_i32();
TCGv_i32 tcg_res = tcg_temp_new_i32();
read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
if (size == 2) {
/* Special cases for 32 bit elements */
switch (opcode) {
case 0x4: /* CLS */
if (u) {
tcg_gen_clzi_i32(tcg_res, tcg_op, 32);
} else {
tcg_gen_clrsb_i32(tcg_res, tcg_op);
}
break;
case 0x7: /* SQABS, SQNEG */
if (u) {
gen_helper_neon_qneg_s32(tcg_res, tcg_env, tcg_op);
} else {
gen_helper_neon_qabs_s32(tcg_res, tcg_env, tcg_op);
}
break;
case 0x2f: /* FABS */
gen_helper_vfp_abss(tcg_res, tcg_op);
break;
case 0x6f: /* FNEG */
gen_helper_vfp_negs(tcg_res, tcg_op);
break;
case 0x7f: /* FSQRT */
gen_helper_vfp_sqrts(tcg_res, tcg_op, tcg_env);
break;
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
case 0x1c: /* FCVTAS */
case 0x3a: /* FCVTPS */
case 0x3b: /* FCVTZS */
gen_helper_vfp_tosls(tcg_res, tcg_op,
tcg_constant_i32(0), tcg_fpstatus);
break;
case 0x5a: /* FCVTNU */
case 0x5b: /* FCVTMU */
case 0x5c: /* FCVTAU */
case 0x7a: /* FCVTPU */
case 0x7b: /* FCVTZU */
gen_helper_vfp_touls(tcg_res, tcg_op,
tcg_constant_i32(0), tcg_fpstatus);
break;
case 0x18: /* FRINTN */
case 0x19: /* FRINTM */
case 0x38: /* FRINTP */
case 0x39: /* FRINTZ */
case 0x58: /* FRINTA */
case 0x79: /* FRINTI */
gen_helper_rints(tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x59: /* FRINTX */
gen_helper_rints_exact(tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x7c: /* URSQRTE */
gen_helper_rsqrte_u32(tcg_res, tcg_op);
break;
case 0x1e: /* FRINT32Z */
case 0x5e: /* FRINT32X */
gen_helper_frint32_s(tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x1f: /* FRINT64Z */
case 0x5f: /* FRINT64X */
gen_helper_frint64_s(tcg_res, tcg_op, tcg_fpstatus);
break;
default:
g_assert_not_reached();
}
} else {
/* Use helpers for 8 and 16 bit elements */
switch (opcode) {
case 0x5: /* CNT, RBIT */
/* For these two insns size is part of the opcode specifier
* (handled earlier); they always operate on byte elements.
*/
if (u) {
gen_helper_neon_rbit_u8(tcg_res, tcg_op);
} else {
gen_helper_neon_cnt_u8(tcg_res, tcg_op);
}
break;
case 0x7: /* SQABS, SQNEG */
{
NeonGenOneOpEnvFn *genfn;
static NeonGenOneOpEnvFn * const fns[2][2] = {
{ gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 },
{ gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 },
};
genfn = fns[size][u];
genfn(tcg_res, tcg_env, tcg_op);
break;
}
case 0x4: /* CLS, CLZ */
if (u) {
if (size == 0) {
gen_helper_neon_clz_u8(tcg_res, tcg_op);
} else {
gen_helper_neon_clz_u16(tcg_res, tcg_op);
}
} else {
if (size == 0) {
gen_helper_neon_cls_s8(tcg_res, tcg_op);
} else {
gen_helper_neon_cls_s16(tcg_res, tcg_op);
}
}
break;
default:
g_assert_not_reached();
}
}
write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
}
}
clear_vec_high(s, is_q, rd);
if (tcg_rmode) {
gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
/* AdvSIMD [scalar] two register miscellaneous (FP16)
*
* 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
* +---+---+---+---+---------+---+-------------+--------+-----+------+------+
* | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
* +---+---+---+---+---------+---+-------------+--------+-----+------+------+
* mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
* val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
*
* This actually covers two groups where scalar access is governed by
* bit 28. A bunch of the instructions (float to integral) only exist
* in the vector form and are un-allocated for the scalar decode. Also
* in the scalar decode Q is always 1.
*/
@@ -12637,716 +12637,716 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
/* AdvSIMD scalar x indexed element
* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
* | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
* AdvSIMD vector x indexed element
* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
* +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
* | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
* +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
*/
static void disas_simd_indexed(DisasContext *s, uint32_t insn)
{
/* This encoding has two kinds of instruction:
* normal, where we perform elt x idxelt => elt for each
* element in the vector
* long, where we perform elt x idxelt and generate a result of
* double the width of the input element
* The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
*/
bool is_scalar = extract32(insn, 28, 1);
bool is_q = extract32(insn, 30, 1);
bool u = extract32(insn, 29, 1);
int size = extract32(insn, 22, 2);
int l = extract32(insn, 21, 1);
int m = extract32(insn, 20, 1);
/* Note that the Rm field here is only 4 bits, not 5 as it usually is */
int rm = extract32(insn, 16, 4);
int opcode = extract32(insn, 12, 4);
int h = extract32(insn, 11, 1);
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
bool is_long = false;
int is_fp = 0;
bool is_fp16 = false;
int index;
TCGv_ptr fpst;
switch (16 * u + opcode) {
case 0x08: /* MUL */
case 0x10: /* MLA */
case 0x14: /* MLS */
if (is_scalar) {
unallocated_encoding(s);
return;
}
break;
case 0x02: /* SMLAL, SMLAL2 */
case 0x12: /* UMLAL, UMLAL2 */
case 0x06: /* SMLSL, SMLSL2 */
case 0x16: /* UMLSL, UMLSL2 */
case 0x0a: /* SMULL, SMULL2 */
case 0x1a: /* UMULL, UMULL2 */
if (is_scalar) {
unallocated_encoding(s);
return;
}
is_long = true;
break;
case 0x03: /* SQDMLAL, SQDMLAL2 */
case 0x07: /* SQDMLSL, SQDMLSL2 */
case 0x0b: /* SQDMULL, SQDMULL2 */
is_long = true;
break;
case 0x0c: /* SQDMULH */
case 0x0d: /* SQRDMULH */
break;
case 0x01: /* FMLA */
case 0x05: /* FMLS */
case 0x09: /* FMUL */
case 0x19: /* FMULX */
is_fp = 1;
break;
case 0x1d: /* SQRDMLAH */
case 0x1f: /* SQRDMLSH */
if (!dc_isar_feature(aa64_rdm, s)) {
unallocated_encoding(s);
return;
}
break;
case 0x0e: /* SDOT */
case 0x1e: /* UDOT */
if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_dp, s)) {
unallocated_encoding(s);
return;
}
break;
case 0x0f:
switch (size) {
case 0: /* SUDOT */
case 2: /* USDOT */
if (is_scalar || !dc_isar_feature(aa64_i8mm, s)) {
unallocated_encoding(s);
return;
}
size = MO_32;
break;
case 1: /* BFDOT */
if (is_scalar || !dc_isar_feature(aa64_bf16, s)) {
unallocated_encoding(s);
return;
}
size = MO_32;
break;
case 3: /* BFMLAL{B,T} */
if (is_scalar || !dc_isar_feature(aa64_bf16, s)) {
unallocated_encoding(s);
return;
}
/* can't set is_fp without other incorrect size checks */
size = MO_16;
break;
default:
unallocated_encoding(s);
return;
}
break;
case 0x11: /* FCMLA #0 */
case 0x13: /* FCMLA #90 */
case 0x15: /* FCMLA #180 */
case 0x17: /* FCMLA #270 */
if (is_scalar || !dc_isar_feature(aa64_fcma, s)) {
unallocated_encoding(s);
return;
}
is_fp = 2;
break;
case 0x00: /* FMLAL */
case 0x04: /* FMLSL */
case 0x18: /* FMLAL2 */
case 0x1c: /* FMLSL2 */
if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_fhm, s)) {
unallocated_encoding(s);
return;
}
size = MO_16;
/* is_fp, but we pass tcg_env not fp_status. */
break;
default:
unallocated_encoding(s);
return;
}
switch (is_fp) {
case 1: /* normal fp */
/* convert insn encoded size to MemOp size */
switch (size) {
case 0: /* half-precision */
size = MO_16;
is_fp16 = true;
break;
case MO_32: /* single precision */
case MO_64: /* double precision */
break;
default:
unallocated_encoding(s);
return;
}
break;
case 2: /* complex fp */
/* Each indexable element is a complex pair. */
size += 1;
switch (size) {
case MO_32:
if (h && !is_q) {
unallocated_encoding(s);
return;
}
is_fp16 = true;
break;
case MO_64:
break;
default:
unallocated_encoding(s);
return;
}
break;
default: /* integer */
switch (size) {
case MO_8:
case MO_64:
unallocated_encoding(s);
return;
}
break;
}
if (is_fp16 && !dc_isar_feature(aa64_fp16, s)) {
unallocated_encoding(s);
return;
}
/* Given MemOp size, adjust register and indexing. */
switch (size) {
case MO_16:
index = h << 2 | l << 1 | m;
break;
case MO_32:
index = h << 1 | l;
rm |= m << 4;
break;
case MO_64:
if (l || !is_q) {
unallocated_encoding(s);
return;
}
index = h;
rm |= m << 4;
break;
default:
g_assert_not_reached();
}
if (!fp_access_check(s)) {
return;
}
if (is_fp) {
fpst = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR);
} else {
fpst = NULL;
}
switch (16 * u + opcode) {
case 0x0e: /* SDOT */
case 0x1e: /* UDOT */
gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, index,
u ? gen_helper_gvec_udot_idx_b
: gen_helper_gvec_sdot_idx_b);
return;
case 0x0f:
switch (extract32(insn, 22, 2)) {
case 0: /* SUDOT */
gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, index,
gen_helper_gvec_sudot_idx_b);
return;
case 1: /* BFDOT */
gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, index,
gen_helper_gvec_bfdot_idx);
return;
case 2: /* USDOT */
gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, index,
gen_helper_gvec_usdot_idx_b);
return;
case 3: /* BFMLAL{B,T} */
gen_gvec_op4_fpst(s, 1, rd, rn, rm, rd, 0, (index << 1) | is_q,
gen_helper_gvec_bfmlal_idx);
return;
}
g_assert_not_reached();
case 0x11: /* FCMLA #0 */
case 0x13: /* FCMLA #90 */
case 0x15: /* FCMLA #180 */
case 0x17: /* FCMLA #270 */
{
int rot = extract32(insn, 13, 2);
int data = (index << 2) | rot;
tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm),
vec_full_reg_offset(s, rd), fpst,
is_q ? 16 : 8, vec_full_reg_size(s), data,
size == MO_64
? gen_helper_gvec_fcmlas_idx
: gen_helper_gvec_fcmlah_idx);
}
return;
case 0x00: /* FMLAL */
case 0x04: /* FMLSL */
case 0x18: /* FMLAL2 */
case 0x1c: /* FMLSL2 */
{
int is_s = extract32(opcode, 2, 1);
int is_2 = u;
int data = (index << 2) | (is_2 << 1) | is_s;
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm), tcg_env,
is_q ? 16 : 8, vec_full_reg_size(s),
data, gen_helper_gvec_fmlal_idx_a64);
}
return;
case 0x08: /* MUL */
if (!is_long && !is_scalar) {
static gen_helper_gvec_3 * const fns[3] = {
gen_helper_gvec_mul_idx_h,
gen_helper_gvec_mul_idx_s,
gen_helper_gvec_mul_idx_d,
};
tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm),
is_q ? 16 : 8, vec_full_reg_size(s),
index, fns[size - 1]);
return;
}
break;
case 0x10: /* MLA */
if (!is_long && !is_scalar) {
static gen_helper_gvec_4 * const fns[3] = {
gen_helper_gvec_mla_idx_h,
gen_helper_gvec_mla_idx_s,
gen_helper_gvec_mla_idx_d,
};
tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm),
vec_full_reg_offset(s, rd),
is_q ? 16 : 8, vec_full_reg_size(s),
index, fns[size - 1]);
return;
}
break;
case 0x14: /* MLS */
if (!is_long && !is_scalar) {
static gen_helper_gvec_4 * const fns[3] = {
gen_helper_gvec_mls_idx_h,
gen_helper_gvec_mls_idx_s,
gen_helper_gvec_mls_idx_d,
};
tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm),
vec_full_reg_offset(s, rd),
is_q ? 16 : 8, vec_full_reg_size(s),
index, fns[size - 1]);
return;
}
break;
}
if (size == 3) {
TCGv_i64 tcg_idx = tcg_temp_new_i64();
int pass;
assert(is_fp && is_q && !is_long);
read_vec_element(s, tcg_idx, rm, index, MO_64);
for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
TCGv_i64 tcg_op = tcg_temp_new_i64();
TCGv_i64 tcg_res = tcg_temp_new_i64();
read_vec_element(s, tcg_op, rn, pass, MO_64);
switch (16 * u + opcode) {
case 0x05: /* FMLS */
/* As usual for ARM, separate negation for fused multiply-add */
gen_helper_vfp_negd(tcg_op, tcg_op);
- /* fall through */
+ fallthrough;
case 0x01: /* FMLA */
read_vec_element(s, tcg_res, rd, pass, MO_64);
gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst);
break;
case 0x09: /* FMUL */
gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst);
break;
case 0x19: /* FMULX */
gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst);
break;
default:
g_assert_not_reached();
}
write_vec_element(s, tcg_res, rd, pass, MO_64);
}
clear_vec_high(s, !is_scalar, rd);
} else if (!is_long) {
/* 32 bit floating point, or 16 or 32 bit integer.
* For the 16 bit scalar case we use the usual Neon helpers and
* rely on the fact that 0 op 0 == 0 with no side effects.
*/
TCGv_i32 tcg_idx = tcg_temp_new_i32();
int pass, maxpasses;
if (is_scalar) {
maxpasses = 1;
} else {
maxpasses = is_q ? 4 : 2;
}
read_vec_element_i32(s, tcg_idx, rm, index, size);
if (size == 1 && !is_scalar) {
/* The simplest way to handle the 16x16 indexed ops is to duplicate
* the index into both halves of the 32 bit tcg_idx and then use
* the usual Neon helpers.
*/
tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16);
}
for (pass = 0; pass < maxpasses; pass++) {
TCGv_i32 tcg_op = tcg_temp_new_i32();
TCGv_i32 tcg_res = tcg_temp_new_i32();
read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32);
switch (16 * u + opcode) {
case 0x08: /* MUL */
case 0x10: /* MLA */
case 0x14: /* MLS */
{
static NeonGenTwoOpFn * const fns[2][2] = {
{ gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
{ tcg_gen_add_i32, tcg_gen_sub_i32 },
};
NeonGenTwoOpFn *genfn;
bool is_sub = opcode == 0x4;
if (size == 1) {
gen_helper_neon_mul_u16(tcg_res, tcg_op, tcg_idx);
} else {
tcg_gen_mul_i32(tcg_res, tcg_op, tcg_idx);
}
if (opcode == 0x8) {
break;
}
read_vec_element_i32(s, tcg_op, rd, pass, MO_32);
genfn = fns[size - 1][is_sub];
genfn(tcg_res, tcg_op, tcg_res);
break;
}
case 0x05: /* FMLS */
case 0x01: /* FMLA */
read_vec_element_i32(s, tcg_res, rd, pass,
is_scalar ? size : MO_32);
switch (size) {
case 1:
if (opcode == 0x5) {
/* As usual for ARM, separate negation for fused
* multiply-add */
tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000);
}
if (is_scalar) {
gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx,
tcg_res, fpst);
} else {
gen_helper_advsimd_muladd2h(tcg_res, tcg_op, tcg_idx,
tcg_res, fpst);
}
break;
case 2:
if (opcode == 0x5) {
/* As usual for ARM, separate negation for
* fused multiply-add */
tcg_gen_xori_i32(tcg_op, tcg_op, 0x80000000);
}
gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx,
tcg_res, fpst);
break;
default:
g_assert_not_reached();
}
break;
case 0x09: /* FMUL */
switch (size) {
case 1:
if (is_scalar) {
gen_helper_advsimd_mulh(tcg_res, tcg_op,
tcg_idx, fpst);
} else {
gen_helper_advsimd_mul2h(tcg_res, tcg_op,
tcg_idx, fpst);
}
break;
case 2:
gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
break;
default:
g_assert_not_reached();
}
break;
case 0x19: /* FMULX */
switch (size) {
case 1:
if (is_scalar) {
gen_helper_advsimd_mulxh(tcg_res, tcg_op,
tcg_idx, fpst);
} else {
gen_helper_advsimd_mulx2h(tcg_res, tcg_op,
tcg_idx, fpst);
}
break;
case 2:
gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
break;
default:
g_assert_not_reached();
}
break;
case 0x0c: /* SQDMULH */
if (size == 1) {
gen_helper_neon_qdmulh_s16(tcg_res, tcg_env,
tcg_op, tcg_idx);
} else {
gen_helper_neon_qdmulh_s32(tcg_res, tcg_env,
tcg_op, tcg_idx);
}
break;
case 0x0d: /* SQRDMULH */
if (size == 1) {
gen_helper_neon_qrdmulh_s16(tcg_res, tcg_env,
tcg_op, tcg_idx);
} else {
gen_helper_neon_qrdmulh_s32(tcg_res, tcg_env,
tcg_op, tcg_idx);
}
break;
case 0x1d: /* SQRDMLAH */
read_vec_element_i32(s, tcg_res, rd, pass,
is_scalar ? size : MO_32);
if (size == 1) {
gen_helper_neon_qrdmlah_s16(tcg_res, tcg_env,
tcg_op, tcg_idx, tcg_res);
} else {
gen_helper_neon_qrdmlah_s32(tcg_res, tcg_env,
tcg_op, tcg_idx, tcg_res);
}
break;
case 0x1f: /* SQRDMLSH */
read_vec_element_i32(s, tcg_res, rd, pass,
is_scalar ? size : MO_32);
if (size == 1) {
gen_helper_neon_qrdmlsh_s16(tcg_res, tcg_env,
tcg_op, tcg_idx, tcg_res);
} else {
gen_helper_neon_qrdmlsh_s32(tcg_res, tcg_env,
tcg_op, tcg_idx, tcg_res);
}
break;
default:
g_assert_not_reached();
}
if (is_scalar) {
write_fp_sreg(s, rd, tcg_res);
} else {
write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
}
}
clear_vec_high(s, is_q, rd);
} else {
/* long ops: 16x16->32 or 32x32->64 */
TCGv_i64 tcg_res[2];
int pass;
bool satop = extract32(opcode, 0, 1);
MemOp memop = MO_32;
if (satop || !u) {
memop |= MO_SIGN;
}
if (size == 2) {
TCGv_i64 tcg_idx = tcg_temp_new_i64();
read_vec_element(s, tcg_idx, rm, index, memop);
for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
TCGv_i64 tcg_op = tcg_temp_new_i64();
TCGv_i64 tcg_passres;
int passelt;
if (is_scalar) {
passelt = 0;
} else {
passelt = pass + (is_q * 2);
}
read_vec_element(s, tcg_op, rn, passelt, memop);
tcg_res[pass] = tcg_temp_new_i64();
if (opcode == 0xa || opcode == 0xb) {
/* Non-accumulating ops */
tcg_passres = tcg_res[pass];
} else {
tcg_passres = tcg_temp_new_i64();
}
tcg_gen_mul_i64(tcg_passres, tcg_op, tcg_idx);
if (satop) {
/* saturating, doubling */
gen_helper_neon_addl_saturate_s64(tcg_passres, tcg_env,
tcg_passres, tcg_passres);
}
if (opcode == 0xa || opcode == 0xb) {
continue;
}
/* Accumulating op: handle accumulate step */
read_vec_element(s, tcg_res[pass], rd, pass, MO_64);
switch (opcode) {
case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
break;
case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
break;
case 0x7: /* SQDMLSL, SQDMLSL2 */
tcg_gen_neg_i64(tcg_passres, tcg_passres);
- /* fall through */
+ fallthrough;
case 0x3: /* SQDMLAL, SQDMLAL2 */
gen_helper_neon_addl_saturate_s64(tcg_res[pass], tcg_env,
tcg_res[pass],
tcg_passres);
break;
default:
g_assert_not_reached();
}
}
clear_vec_high(s, !is_scalar, rd);
} else {
TCGv_i32 tcg_idx = tcg_temp_new_i32();
assert(size == 1);
read_vec_element_i32(s, tcg_idx, rm, index, size);
if (!is_scalar) {
/* The simplest way to handle the 16x16 indexed ops is to
* duplicate the index into both halves of the 32 bit tcg_idx
* and then use the usual Neon helpers.
*/
tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16);
}
for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
TCGv_i32 tcg_op = tcg_temp_new_i32();
TCGv_i64 tcg_passres;
if (is_scalar) {
read_vec_element_i32(s, tcg_op, rn, pass, size);
} else {
read_vec_element_i32(s, tcg_op, rn,
pass + (is_q * 2), MO_32);
}
tcg_res[pass] = tcg_temp_new_i64();
if (opcode == 0xa || opcode == 0xb) {
/* Non-accumulating ops */
tcg_passres = tcg_res[pass];
} else {
tcg_passres = tcg_temp_new_i64();
}
if (memop & MO_SIGN) {
gen_helper_neon_mull_s16(tcg_passres, tcg_op, tcg_idx);
} else {
gen_helper_neon_mull_u16(tcg_passres, tcg_op, tcg_idx);
}
if (satop) {
gen_helper_neon_addl_saturate_s32(tcg_passres, tcg_env,
tcg_passres, tcg_passres);
}
if (opcode == 0xa || opcode == 0xb) {
continue;
}
/* Accumulating op: handle accumulate step */
read_vec_element(s, tcg_res[pass], rd, pass, MO_64);
switch (opcode) {
case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
gen_helper_neon_addl_u32(tcg_res[pass], tcg_res[pass],
tcg_passres);
break;
case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
gen_helper_neon_subl_u32(tcg_res[pass], tcg_res[pass],
tcg_passres);
break;
case 0x7: /* SQDMLSL, SQDMLSL2 */
gen_helper_neon_negl_u32(tcg_passres, tcg_passres);
- /* fall through */
+ fallthrough;
case 0x3: /* SQDMLAL, SQDMLAL2 */
gen_helper_neon_addl_saturate_s32(tcg_res[pass], tcg_env,
tcg_res[pass],
tcg_passres);
break;
default:
g_assert_not_reached();
}
}
if (is_scalar) {
tcg_gen_ext32u_i64(tcg_res[0], tcg_res[0]);
}
}
if (is_scalar) {
tcg_res[1] = tcg_constant_i64(0);
}
for (pass = 0; pass < 2; pass++) {
write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
}
}
}
/* Crypto AES
* 31 24 23 22 21 17 16 12 11 10 9 5 4 0
* +-----------------+------+-----------+--------+-----+------+------+
* | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
* +-----------------+------+-----------+--------+-----+------+------+
*/
@@ -14202,67 +14202,67 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
if (unlikely(dc->ss_active)) {
/* Note that this means single stepping WFI doesn't halt the CPU.
* For conditional branch insns this is harmless unreachable code as
* gen_goto_tb() has already handled emitting the debug exception
* (and thus a tb-jump is not possible when singlestepping).
*/
switch (dc->base.is_jmp) {
default:
gen_a64_update_pc(dc, 4);
- /* fall through */
+ fallthrough;
case DISAS_EXIT:
case DISAS_JUMP:
gen_step_complete_exception(dc);
break;
case DISAS_NORETURN:
break;
}
} else {
switch (dc->base.is_jmp) {
case DISAS_NEXT:
case DISAS_TOO_MANY:
gen_goto_tb(dc, 1, 4);
break;
default:
case DISAS_UPDATE_EXIT:
gen_a64_update_pc(dc, 4);
- /* fall through */
+ fallthrough;
case DISAS_EXIT:
tcg_gen_exit_tb(NULL, 0);
break;
case DISAS_UPDATE_NOCHAIN:
gen_a64_update_pc(dc, 4);
- /* fall through */
+ fallthrough;
case DISAS_JUMP:
tcg_gen_lookup_and_goto_ptr();
break;
case DISAS_NORETURN:
case DISAS_SWI:
break;
case DISAS_WFE:
gen_a64_update_pc(dc, 4);
gen_helper_wfe(tcg_env);
break;
case DISAS_YIELD:
gen_a64_update_pc(dc, 4);
gen_helper_yield(tcg_env);
break;
case DISAS_WFI:
/*
* This is a special case because we don't want to just halt
* the CPU if trying to debug across a WFI.
*/
gen_a64_update_pc(dc, 4);
gen_helper_wfi(tcg_env, tcg_constant_i32(4));
/*
* The helper doesn't necessarily throw an exception, but we
* must go back to the main loop to check for interrupts anyway.
*/
tcg_gen_exit_tb(NULL, 0);
break;
}
}
}
diff --git a/target/arm/tcg/translate-m-nocp.c b/target/arm/tcg/translate-m-nocp.c
index f564d06ccf..42d6f516ba 100644
--- a/target/arm/tcg/translate-m-nocp.c
+++ b/target/arm/tcg/translate-m-nocp.c
@@ -305,122 +305,122 @@ static void gen_branch_fpInactive(DisasContext *s, TCGCond cond,
static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
fp_sysreg_loadfn *loadfn,
void *opaque)
{
/* Do a write to an M-profile floating point system register */
TCGv_i32 tmp;
TCGLabel *lab_end = NULL;
switch (fp_sysreg_checks(s, regno)) {
case FPSysRegCheckFailed:
return false;
case FPSysRegCheckDone:
return true;
case FPSysRegCheckContinue:
break;
}
switch (regno) {
case ARM_VFP_FPSCR:
tmp = loadfn(s, opaque, true);
gen_helper_vfp_set_fpscr(tcg_env, tmp);
gen_lookup_tb(s);
break;
case ARM_VFP_FPSCR_NZCVQC:
{
TCGv_i32 fpscr;
tmp = loadfn(s, opaque, true);
if (dc_isar_feature(aa32_mve, s)) {
/* QC is only present for MVE; otherwise RES0 */
TCGv_i32 qc = tcg_temp_new_i32();
tcg_gen_andi_i32(qc, tmp, FPCR_QC);
/*
* The 4 vfp.qc[] fields need only be "zero" vs "non-zero";
* here writing the same value into all elements is simplest.
*/
tcg_gen_gvec_dup_i32(MO_32, offsetof(CPUARMState, vfp.qc),
16, 16, qc);
}
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK);
tcg_gen_or_i32(fpscr, fpscr, tmp);
store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]);
break;
}
case ARM_VFP_FPCXT_NS:
{
TCGLabel *lab_active = gen_new_label();
lab_end = gen_new_label();
gen_branch_fpInactive(s, TCG_COND_EQ, lab_active);
/*
* fpInactive case: write is a NOP, so only do side effects
* like register writeback before we branch to end
*/
loadfn(s, opaque, false);
tcg_gen_br(lab_end);
gen_set_label(lab_active);
/*
* !fpInactive: if FPU disabled, take NOCP exception;
* otherwise PreserveFPState(), and then FPCXT_NS writes
* behave the same as FPCXT_S writes.
*/
if (!vfp_access_check_m(s, true)) {
/*
* This was only a conditional exception, so override
* gen_exception_insn_el()'s default to DISAS_NORETURN
*/
s->base.is_jmp = DISAS_NEXT;
break;
}
+ fallthrough;
}
- /* fall through */
case ARM_VFP_FPCXT_S:
{
TCGv_i32 sfpa, control;
/*
* Set FPSCR and CONTROL.SFPA from value; the new FPSCR takes
* bits [27:0] from value and zeroes bits [31:28].
*/
tmp = loadfn(s, opaque, true);
sfpa = tcg_temp_new_i32();
tcg_gen_shri_i32(sfpa, tmp, 31);
control = load_cpu_field(v7m.control[M_REG_S]);
tcg_gen_deposit_i32(control, control, sfpa,
R_V7M_CONTROL_SFPA_SHIFT, 1);
store_cpu_field(control, v7m.control[M_REG_S]);
tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
gen_helper_vfp_set_fpscr(tcg_env, tmp);
s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
break;
}
case ARM_VFP_VPR:
/* Behaves as NOP if not privileged */
if (IS_USER(s)) {
loadfn(s, opaque, false);
break;
}
tmp = loadfn(s, opaque, true);
store_cpu_field(tmp, v7m.vpr);
s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
break;
case ARM_VFP_P0:
{
TCGv_i32 vpr;
tmp = loadfn(s, opaque, true);
vpr = load_cpu_field(v7m.vpr);
tcg_gen_deposit_i32(vpr, vpr, tmp,
R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH);
store_cpu_field(vpr, v7m.vpr);
s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
break;
}
default:
g_assert_not_reached();
}
if (lab_end) {
gen_set_label(lab_end);
}
return true;
}
diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c
index b9af03b7c3..57d3c41596 100644
--- a/target/arm/tcg/translate-vfp.c
+++ b/target/arm/tcg/translate-vfp.c
@@ -743,140 +743,140 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
{
TCGv_i32 tmp;
bool ignore_vfp_enabled = false;
if (arm_dc_feature(s, ARM_FEATURE_M)) {
/* M profile version was already handled in m-nocp.decode */
return false;
}
if (!dc_isar_feature(aa32_fpsp_v2, s)) {
return false;
}
switch (a->reg) {
case ARM_VFP_FPSID:
/*
* VFPv2 allows access to FPSID from userspace; VFPv3 restricts
* all ID registers to privileged access only.
*/
if (IS_USER(s) && dc_isar_feature(aa32_fpsp_v3, s)) {
return false;
}
ignore_vfp_enabled = true;
break;
case ARM_VFP_MVFR0:
case ARM_VFP_MVFR1:
if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_MVFR)) {
return false;
}
ignore_vfp_enabled = true;
break;
case ARM_VFP_MVFR2:
if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_V8)) {
return false;
}
ignore_vfp_enabled = true;
break;
case ARM_VFP_FPSCR:
break;
case ARM_VFP_FPEXC:
if (IS_USER(s)) {
return false;
}
ignore_vfp_enabled = true;
break;
case ARM_VFP_FPINST:
case ARM_VFP_FPINST2:
/* Not present in VFPv3 */
if (IS_USER(s) || dc_isar_feature(aa32_fpsp_v3, s)) {
return false;
}
break;
default:
return false;
}
/*
* Call vfp_access_check_a() directly, because we need to tell
* it to ignore FPEXC.EN for some register accesses.
*/
if (!vfp_access_check_a(s, ignore_vfp_enabled)) {
return true;
}
if (a->l) {
/* VMRS, move VFP special register to gp register */
switch (a->reg) {
case ARM_VFP_MVFR0:
case ARM_VFP_MVFR1:
case ARM_VFP_MVFR2:
case ARM_VFP_FPSID:
if (s->current_el == 1) {
gen_set_condexec(s);
gen_update_pc(s, 0);
gen_helper_check_hcr_el2_trap(tcg_env,
tcg_constant_i32(a->rt),
tcg_constant_i32(a->reg));
}
- /* fall through */
+ fallthrough;
case ARM_VFP_FPEXC:
case ARM_VFP_FPINST:
case ARM_VFP_FPINST2:
tmp = load_cpu_field(vfp.xregs[a->reg]);
break;
case ARM_VFP_FPSCR:
if (a->rt == 15) {
tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
} else {
tmp = tcg_temp_new_i32();
gen_helper_vfp_get_fpscr(tmp, tcg_env);
}
break;
default:
g_assert_not_reached();
}
if (a->rt == 15) {
/* Set the 4 flag bits in the CPSR. */
gen_set_nzcv(tmp);
} else {
store_reg(s, a->rt, tmp);
}
} else {
/* VMSR, move gp register to VFP special register */
switch (a->reg) {
case ARM_VFP_FPSID:
case ARM_VFP_MVFR0:
case ARM_VFP_MVFR1:
case ARM_VFP_MVFR2:
/* Writes are ignored. */
break;
case ARM_VFP_FPSCR:
tmp = load_reg(s, a->rt);
gen_helper_vfp_set_fpscr(tcg_env, tmp);
gen_lookup_tb(s);
break;
case ARM_VFP_FPEXC:
/*
* TODO: VFP subarchitecture support.
* For now, keep the EN bit only
*/
tmp = load_reg(s, a->rt);
tcg_gen_andi_i32(tmp, tmp, 1 << 30);
store_cpu_field(tmp, vfp.xregs[a->reg]);
gen_lookup_tb(s);
break;
case ARM_VFP_FPINST:
case ARM_VFP_FPINST2:
tmp = load_reg(s, a->rt);
store_cpu_field(tmp, vfp.xregs[a->reg]);
break;
default:
g_assert_not_reached();
}
}
return true;
}
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index 48927fbb8c..595ef02f0d 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -1486,975 +1486,975 @@ static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv_i32 dest)
/* Disassemble an iwMMXt instruction. Returns nonzero if an error occurred
(ie. an undefined instruction). */
static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
{
int rd, wrd;
int rdhi, rdlo, rd0, rd1, i;
TCGv_i32 addr;
TCGv_i32 tmp, tmp2, tmp3;
if ((insn & 0x0e000e00) == 0x0c000000) {
if ((insn & 0x0fe00ff0) == 0x0c400000) {
wrd = insn & 0xf;
rdlo = (insn >> 12) & 0xf;
rdhi = (insn >> 16) & 0xf;
if (insn & ARM_CP_RW_BIT) { /* TMRRC */
iwmmxt_load_reg(cpu_V0, wrd);
tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0);
tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0);
} else { /* TMCRR */
tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
iwmmxt_store_reg(cpu_V0, wrd);
gen_op_iwmmxt_set_mup();
}
return 0;
}
wrd = (insn >> 12) & 0xf;
addr = tcg_temp_new_i32();
if (gen_iwmmxt_address(s, insn, addr)) {
return 1;
}
if (insn & ARM_CP_RW_BIT) {
if ((insn >> 28) == 0xf) { /* WLDRW wCx */
tmp = tcg_temp_new_i32();
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
iwmmxt_store_creg(wrd, tmp);
} else {
i = 1;
if (insn & (1 << 8)) {
if (insn & (1 << 22)) { /* WLDRD */
gen_aa32_ld64(s, cpu_M0, addr, get_mem_index(s));
i = 0;
} else { /* WLDRW wRd */
tmp = tcg_temp_new_i32();
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
}
} else {
tmp = tcg_temp_new_i32();
if (insn & (1 << 22)) { /* WLDRH */
gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
} else { /* WLDRB */
gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
}
}
if (i) {
tcg_gen_extu_i32_i64(cpu_M0, tmp);
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
}
} else {
if ((insn >> 28) == 0xf) { /* WSTRW wCx */
tmp = iwmmxt_load_creg(wrd);
gen_aa32_st32(s, tmp, addr, get_mem_index(s));
} else {
gen_op_iwmmxt_movq_M0_wRn(wrd);
tmp = tcg_temp_new_i32();
if (insn & (1 << 8)) {
if (insn & (1 << 22)) { /* WSTRD */
gen_aa32_st64(s, cpu_M0, addr, get_mem_index(s));
} else { /* WSTRW wRd */
tcg_gen_extrl_i64_i32(tmp, cpu_M0);
gen_aa32_st32(s, tmp, addr, get_mem_index(s));
}
} else {
if (insn & (1 << 22)) { /* WSTRH */
tcg_gen_extrl_i64_i32(tmp, cpu_M0);
gen_aa32_st16(s, tmp, addr, get_mem_index(s));
} else { /* WSTRB */
tcg_gen_extrl_i64_i32(tmp, cpu_M0);
gen_aa32_st8(s, tmp, addr, get_mem_index(s));
}
}
}
}
return 0;
}
if ((insn & 0x0f000000) != 0x0e000000)
return 1;
switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
case 0x000: /* WOR */
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 0) & 0xf;
rd1 = (insn >> 16) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
gen_op_iwmmxt_orq_M0_wRn(rd1);
gen_op_iwmmxt_setpsr_nz();
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
break;
case 0x011: /* TMCR */
if (insn & 0xf)
return 1;
rd = (insn >> 12) & 0xf;
wrd = (insn >> 16) & 0xf;
switch (wrd) {
case ARM_IWMMXT_wCID:
case ARM_IWMMXT_wCASF:
break;
case ARM_IWMMXT_wCon:
gen_op_iwmmxt_set_cup();
- /* Fall through. */
+ fallthrough;
case ARM_IWMMXT_wCSSF:
tmp = iwmmxt_load_creg(wrd);
tmp2 = load_reg(s, rd);
tcg_gen_andc_i32(tmp, tmp, tmp2);
iwmmxt_store_creg(wrd, tmp);
break;
case ARM_IWMMXT_wCGR0:
case ARM_IWMMXT_wCGR1:
case ARM_IWMMXT_wCGR2:
case ARM_IWMMXT_wCGR3:
gen_op_iwmmxt_set_cup();
tmp = load_reg(s, rd);
iwmmxt_store_creg(wrd, tmp);
break;
default:
return 1;
}
break;
case 0x100: /* WXOR */
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 0) & 0xf;
rd1 = (insn >> 16) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
gen_op_iwmmxt_xorq_M0_wRn(rd1);
gen_op_iwmmxt_setpsr_nz();
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
break;
case 0x111: /* TMRC */
if (insn & 0xf)
return 1;
rd = (insn >> 12) & 0xf;
wrd = (insn >> 16) & 0xf;
tmp = iwmmxt_load_creg(wrd);
store_reg(s, rd, tmp);
break;
case 0x300: /* WANDN */
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 0) & 0xf;
rd1 = (insn >> 16) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
tcg_gen_neg_i64(cpu_M0, cpu_M0);
gen_op_iwmmxt_andq_M0_wRn(rd1);
gen_op_iwmmxt_setpsr_nz();
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
break;
case 0x200: /* WAND */
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 0) & 0xf;
rd1 = (insn >> 16) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
gen_op_iwmmxt_andq_M0_wRn(rd1);
gen_op_iwmmxt_setpsr_nz();
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
break;
case 0x810: case 0xa10: /* WMADD */
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 0) & 0xf;
rd1 = (insn >> 16) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
if (insn & (1 << 21))
gen_op_iwmmxt_maddsq_M0_wRn(rd1);
else
gen_op_iwmmxt_madduq_M0_wRn(rd1);
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
break;
case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
rd1 = (insn >> 0) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
switch ((insn >> 22) & 3) {
case 0:
gen_op_iwmmxt_unpacklb_M0_wRn(rd1);
break;
case 1:
gen_op_iwmmxt_unpacklw_M0_wRn(rd1);
break;
case 2:
gen_op_iwmmxt_unpackll_M0_wRn(rd1);
break;
case 3:
return 1;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
break;
case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
rd1 = (insn >> 0) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
switch ((insn >> 22) & 3) {
case 0:
gen_op_iwmmxt_unpackhb_M0_wRn(rd1);
break;
case 1:
gen_op_iwmmxt_unpackhw_M0_wRn(rd1);
break;
case 2:
gen_op_iwmmxt_unpackhl_M0_wRn(rd1);
break;
case 3:
return 1;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
break;
case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
rd1 = (insn >> 0) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
if (insn & (1 << 22))
gen_op_iwmmxt_sadw_M0_wRn(rd1);
else
gen_op_iwmmxt_sadb_M0_wRn(rd1);
if (!(insn & (1 << 20)))
gen_op_iwmmxt_addl_M0_wRn(wrd);
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
break;
case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
rd1 = (insn >> 0) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
if (insn & (1 << 21)) {
if (insn & (1 << 20))
gen_op_iwmmxt_mulshw_M0_wRn(rd1);
else
gen_op_iwmmxt_mulslw_M0_wRn(rd1);
} else {
if (insn & (1 << 20))
gen_op_iwmmxt_muluhw_M0_wRn(rd1);
else
gen_op_iwmmxt_mululw_M0_wRn(rd1);
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
break;
case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
rd1 = (insn >> 0) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
if (insn & (1 << 21))
gen_op_iwmmxt_macsw_M0_wRn(rd1);
else
gen_op_iwmmxt_macuw_M0_wRn(rd1);
if (!(insn & (1 << 20))) {
iwmmxt_load_reg(cpu_V1, wrd);
tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
break;
case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
rd1 = (insn >> 0) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
switch ((insn >> 22) & 3) {
case 0:
gen_op_iwmmxt_cmpeqb_M0_wRn(rd1);
break;
case 1:
gen_op_iwmmxt_cmpeqw_M0_wRn(rd1);
break;
case 2:
gen_op_iwmmxt_cmpeql_M0_wRn(rd1);
break;
case 3:
return 1;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
break;
case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
rd1 = (insn >> 0) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
if (insn & (1 << 22)) {
if (insn & (1 << 20))
gen_op_iwmmxt_avgw1_M0_wRn(rd1);
else
gen_op_iwmmxt_avgw0_M0_wRn(rd1);
} else {
if (insn & (1 << 20))
gen_op_iwmmxt_avgb1_M0_wRn(rd1);
else
gen_op_iwmmxt_avgb0_M0_wRn(rd1);
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
break;
case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
rd1 = (insn >> 0) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
tcg_gen_andi_i32(tmp, tmp, 7);
iwmmxt_load_reg(cpu_V1, rd1);
gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
break;
case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
if (((insn >> 6) & 3) == 3)
return 1;
rd = (insn >> 12) & 0xf;
wrd = (insn >> 16) & 0xf;
tmp = load_reg(s, rd);
gen_op_iwmmxt_movq_M0_wRn(wrd);
switch ((insn >> 6) & 3) {
case 0:
tmp2 = tcg_constant_i32(0xff);
tmp3 = tcg_constant_i32((insn & 7) << 3);
break;
case 1:
tmp2 = tcg_constant_i32(0xffff);
tmp3 = tcg_constant_i32((insn & 3) << 4);
break;
case 2:
tmp2 = tcg_constant_i32(0xffffffff);
tmp3 = tcg_constant_i32((insn & 1) << 5);
break;
default:
g_assert_not_reached();
}
gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
break;
case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
rd = (insn >> 12) & 0xf;
wrd = (insn >> 16) & 0xf;
if (rd == 15 || ((insn >> 22) & 3) == 3)
return 1;
gen_op_iwmmxt_movq_M0_wRn(wrd);
tmp = tcg_temp_new_i32();
switch ((insn >> 22) & 3) {
case 0:
tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3);
tcg_gen_extrl_i64_i32(tmp, cpu_M0);
if (insn & 8) {
tcg_gen_ext8s_i32(tmp, tmp);
} else {
tcg_gen_andi_i32(tmp, tmp, 0xff);
}
break;
case 1:
tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4);
tcg_gen_extrl_i64_i32(tmp, cpu_M0);
if (insn & 8) {
tcg_gen_ext16s_i32(tmp, tmp);
} else {
tcg_gen_andi_i32(tmp, tmp, 0xffff);
}
break;
case 2:
tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5);
tcg_gen_extrl_i64_i32(tmp, cpu_M0);
break;
}
store_reg(s, rd, tmp);
break;
case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3)
return 1;
tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
switch ((insn >> 22) & 3) {
case 0:
tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0);
break;
case 1:
tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4);
break;
case 2:
tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12);
break;
}
tcg_gen_shli_i32(tmp, tmp, 28);
gen_set_nzcv(tmp);
break;
case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
if (((insn >> 6) & 3) == 3)
return 1;
rd = (insn >> 12) & 0xf;
wrd = (insn >> 16) & 0xf;
tmp = load_reg(s, rd);
switch ((insn >> 6) & 3) {
case 0:
gen_helper_iwmmxt_bcstb(cpu_M0, tmp);
break;
case 1:
gen_helper_iwmmxt_bcstw(cpu_M0, tmp);
break;
case 2:
gen_helper_iwmmxt_bcstl(cpu_M0, tmp);
break;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
break;
case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
return 1;
tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
tmp2 = tcg_temp_new_i32();
tcg_gen_mov_i32(tmp2, tmp);
switch ((insn >> 22) & 3) {
case 0:
for (i = 0; i < 7; i ++) {
tcg_gen_shli_i32(tmp2, tmp2, 4);
tcg_gen_and_i32(tmp, tmp, tmp2);
}
break;
case 1:
for (i = 0; i < 3; i ++) {
tcg_gen_shli_i32(tmp2, tmp2, 8);
tcg_gen_and_i32(tmp, tmp, tmp2);
}
break;
case 2:
tcg_gen_shli_i32(tmp2, tmp2, 16);
tcg_gen_and_i32(tmp, tmp, tmp2);
break;
}
gen_set_nzcv(tmp);
break;
case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
switch ((insn >> 22) & 3) {
case 0:
gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
break;
case 1:
gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
break;
case 2:
gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
break;
case 3:
return 1;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
break;
case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
return 1;
tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
tmp2 = tcg_temp_new_i32();
tcg_gen_mov_i32(tmp2, tmp);
switch ((insn >> 22) & 3) {
case 0:
for (i = 0; i < 7; i ++) {
tcg_gen_shli_i32(tmp2, tmp2, 4);
tcg_gen_or_i32(tmp, tmp, tmp2);
}
break;
case 1:
for (i = 0; i < 3; i ++) {
tcg_gen_shli_i32(tmp2, tmp2, 8);
tcg_gen_or_i32(tmp, tmp, tmp2);
}
break;
case 2:
tcg_gen_shli_i32(tmp2, tmp2, 16);
tcg_gen_or_i32(tmp, tmp, tmp2);
break;
}
gen_set_nzcv(tmp);
break;
case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
rd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3)
return 1;
gen_op_iwmmxt_movq_M0_wRn(rd0);
tmp = tcg_temp_new_i32();
switch ((insn >> 22) & 3) {
case 0:
gen_helper_iwmmxt_msbb(tmp, cpu_M0);
break;
case 1:
gen_helper_iwmmxt_msbw(tmp, cpu_M0);
break;
case 2:
gen_helper_iwmmxt_msbl(tmp, cpu_M0);
break;
}
store_reg(s, rd, tmp);
break;
case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
case 0x906: case 0xb06: case 0xd06: case 0xf06:
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
rd1 = (insn >> 0) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
switch ((insn >> 22) & 3) {
case 0:
if (insn & (1 << 21))
gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1);
else
gen_op_iwmmxt_cmpgtub_M0_wRn(rd1);
break;
case 1:
if (insn & (1 << 21))
gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1);
else
gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1);
break;
case 2:
if (insn & (1 << 21))
gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1);
else
gen_op_iwmmxt_cmpgtul_M0_wRn(rd1);
break;
case 3:
return 1;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
break;
case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
switch ((insn >> 22) & 3) {
case 0:
if (insn & (1 << 21))
gen_op_iwmmxt_unpacklsb_M0();
else
gen_op_iwmmxt_unpacklub_M0();
break;
case 1:
if (insn & (1 << 21))
gen_op_iwmmxt_unpacklsw_M0();
else
gen_op_iwmmxt_unpackluw_M0();
break;
case 2:
if (insn & (1 << 21))
gen_op_iwmmxt_unpacklsl_M0();
else
gen_op_iwmmxt_unpacklul_M0();
break;
case 3:
return 1;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
break;
case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
switch ((insn >> 22) & 3) {
case 0:
if (insn & (1 << 21))
gen_op_iwmmxt_unpackhsb_M0();
else
gen_op_iwmmxt_unpackhub_M0();
break;
case 1:
if (insn & (1 << 21))
gen_op_iwmmxt_unpackhsw_M0();
else
gen_op_iwmmxt_unpackhuw_M0();
break;
case 2:
if (insn & (1 << 21))
gen_op_iwmmxt_unpackhsl_M0();
else
gen_op_iwmmxt_unpackhul_M0();
break;
case 3:
return 1;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
break;
case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
case 0x214: case 0x614: case 0xa14: case 0xe14:
if (((insn >> 22) & 3) == 0)
return 1;
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
tmp = tcg_temp_new_i32();
if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
return 1;
}
switch ((insn >> 22) & 3) {
case 1:
gen_helper_iwmmxt_srlw(cpu_M0, tcg_env, cpu_M0, tmp);
break;
case 2:
gen_helper_iwmmxt_srll(cpu_M0, tcg_env, cpu_M0, tmp);
break;
case 3:
gen_helper_iwmmxt_srlq(cpu_M0, tcg_env, cpu_M0, tmp);
break;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
break;
case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
case 0x014: case 0x414: case 0x814: case 0xc14:
if (((insn >> 22) & 3) == 0)
return 1;
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
tmp = tcg_temp_new_i32();
if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
return 1;
}
switch ((insn >> 22) & 3) {
case 1:
gen_helper_iwmmxt_sraw(cpu_M0, tcg_env, cpu_M0, tmp);
break;
case 2:
gen_helper_iwmmxt_sral(cpu_M0, tcg_env, cpu_M0, tmp);
break;
case 3:
gen_helper_iwmmxt_sraq(cpu_M0, tcg_env, cpu_M0, tmp);
break;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
break;
case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
case 0x114: case 0x514: case 0x914: case 0xd14:
if (((insn >> 22) & 3) == 0)
return 1;
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
tmp = tcg_temp_new_i32();
if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
return 1;
}
switch ((insn >> 22) & 3) {
case 1:
gen_helper_iwmmxt_sllw(cpu_M0, tcg_env, cpu_M0, tmp);
break;
case 2:
gen_helper_iwmmxt_slll(cpu_M0, tcg_env, cpu_M0, tmp);
break;
case 3:
gen_helper_iwmmxt_sllq(cpu_M0, tcg_env, cpu_M0, tmp);
break;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
break;
case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
case 0x314: case 0x714: case 0xb14: case 0xf14:
if (((insn >> 22) & 3) == 0)
return 1;
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
tmp = tcg_temp_new_i32();
switch ((insn >> 22) & 3) {
case 1:
if (gen_iwmmxt_shift(insn, 0xf, tmp)) {
return 1;
}
gen_helper_iwmmxt_rorw(cpu_M0, tcg_env, cpu_M0, tmp);
break;
case 2:
if (gen_iwmmxt_shift(insn, 0x1f, tmp)) {
return 1;
}
gen_helper_iwmmxt_rorl(cpu_M0, tcg_env, cpu_M0, tmp);
break;
case 3:
if (gen_iwmmxt_shift(insn, 0x3f, tmp)) {
return 1;
}
gen_helper_iwmmxt_rorq(cpu_M0, tcg_env, cpu_M0, tmp);
break;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
break;
case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
case 0x916: case 0xb16: case 0xd16: case 0xf16:
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
rd1 = (insn >> 0) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
switch ((insn >> 22) & 3) {
case 0:
if (insn & (1 << 21))
gen_op_iwmmxt_minsb_M0_wRn(rd1);
else
gen_op_iwmmxt_minub_M0_wRn(rd1);
break;
case 1:
if (insn & (1 << 21))
gen_op_iwmmxt_minsw_M0_wRn(rd1);
else
gen_op_iwmmxt_minuw_M0_wRn(rd1);
break;
case 2:
if (insn & (1 << 21))
gen_op_iwmmxt_minsl_M0_wRn(rd1);
else
gen_op_iwmmxt_minul_M0_wRn(rd1);
break;
case 3:
return 1;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
break;
case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
case 0x816: case 0xa16: case 0xc16: case 0xe16:
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
rd1 = (insn >> 0) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
switch ((insn >> 22) & 3) {
case 0:
if (insn & (1 << 21))
gen_op_iwmmxt_maxsb_M0_wRn(rd1);
else
gen_op_iwmmxt_maxub_M0_wRn(rd1);
break;
case 1:
if (insn & (1 << 21))
gen_op_iwmmxt_maxsw_M0_wRn(rd1);
else
gen_op_iwmmxt_maxuw_M0_wRn(rd1);
break;
case 2:
if (insn & (1 << 21))
gen_op_iwmmxt_maxsl_M0_wRn(rd1);
else
gen_op_iwmmxt_maxul_M0_wRn(rd1);
break;
case 3:
return 1;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
break;
case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
case 0x402: case 0x502: case 0x602: case 0x702:
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
rd1 = (insn >> 0) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
iwmmxt_load_reg(cpu_V1, rd1);
gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1,
tcg_constant_i32((insn >> 20) & 3));
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
break;
case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
case 0x41a: case 0x51a: case 0x61a: case 0x71a:
case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
rd1 = (insn >> 0) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
switch ((insn >> 20) & 0xf) {
case 0x0:
gen_op_iwmmxt_subnb_M0_wRn(rd1);
break;
case 0x1:
gen_op_iwmmxt_subub_M0_wRn(rd1);
break;
case 0x3:
gen_op_iwmmxt_subsb_M0_wRn(rd1);
break;
case 0x4:
gen_op_iwmmxt_subnw_M0_wRn(rd1);
break;
case 0x5:
gen_op_iwmmxt_subuw_M0_wRn(rd1);
break;
case 0x7:
gen_op_iwmmxt_subsw_M0_wRn(rd1);
break;
case 0x8:
gen_op_iwmmxt_subnl_M0_wRn(rd1);
break;
case 0x9:
gen_op_iwmmxt_subul_M0_wRn(rd1);
break;
case 0xb:
gen_op_iwmmxt_subsl_M0_wRn(rd1);
break;
default:
return 1;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
break;
case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
case 0x41e: case 0x51e: case 0x61e: case 0x71e:
case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
tmp = tcg_constant_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
gen_helper_iwmmxt_shufh(cpu_M0, tcg_env, cpu_M0, tmp);
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
break;
case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
case 0x418: case 0x518: case 0x618: case 0x718:
case 0x818: case 0x918: case 0xa18: case 0xb18:
case 0xc18: case 0xd18: case 0xe18: case 0xf18:
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
rd1 = (insn >> 0) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
switch ((insn >> 20) & 0xf) {
case 0x0:
gen_op_iwmmxt_addnb_M0_wRn(rd1);
break;
case 0x1:
gen_op_iwmmxt_addub_M0_wRn(rd1);
break;
case 0x3:
gen_op_iwmmxt_addsb_M0_wRn(rd1);
break;
case 0x4:
gen_op_iwmmxt_addnw_M0_wRn(rd1);
break;
case 0x5:
gen_op_iwmmxt_adduw_M0_wRn(rd1);
break;
case 0x7:
gen_op_iwmmxt_addsw_M0_wRn(rd1);
break;
case 0x8:
gen_op_iwmmxt_addnl_M0_wRn(rd1);
break;
case 0x9:
gen_op_iwmmxt_addul_M0_wRn(rd1);
break;
case 0xb:
gen_op_iwmmxt_addsl_M0_wRn(rd1);
break;
default:
return 1;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
break;
case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
case 0x408: case 0x508: case 0x608: case 0x708:
case 0x808: case 0x908: case 0xa08: case 0xb08:
case 0xc08: case 0xd08: case 0xe08: case 0xf08:
if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0)
return 1;
wrd = (insn >> 12) & 0xf;
rd0 = (insn >> 16) & 0xf;
rd1 = (insn >> 0) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
switch ((insn >> 22) & 3) {
case 1:
if (insn & (1 << 21))
gen_op_iwmmxt_packsw_M0_wRn(rd1);
else
gen_op_iwmmxt_packuw_M0_wRn(rd1);
break;
case 2:
if (insn & (1 << 21))
gen_op_iwmmxt_packsl_M0_wRn(rd1);
else
gen_op_iwmmxt_packul_M0_wRn(rd1);
break;
case 3:
if (insn & (1 << 21))
gen_op_iwmmxt_packsq_M0_wRn(rd1);
else
gen_op_iwmmxt_packuq_M0_wRn(rd1);
break;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
break;
case 0x201: case 0x203: case 0x205: case 0x207:
case 0x209: case 0x20b: case 0x20d: case 0x20f:
case 0x211: case 0x213: case 0x215: case 0x217:
case 0x219: case 0x21b: case 0x21d: case 0x21f:
wrd = (insn >> 5) & 0xf;
rd0 = (insn >> 12) & 0xf;
rd1 = (insn >> 0) & 0xf;
if (rd0 == 0xf || rd1 == 0xf)
return 1;
gen_op_iwmmxt_movq_M0_wRn(wrd);
tmp = load_reg(s, rd0);
tmp2 = load_reg(s, rd1);
switch ((insn >> 16) & 0xf) {
case 0x0: /* TMIA */
gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
break;
case 0x8: /* TMIAPH */
gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
break;
case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
if (insn & (1 << 16))
tcg_gen_shri_i32(tmp, tmp, 16);
if (insn & (1 << 17))
tcg_gen_shri_i32(tmp2, tmp2, 16);
gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
break;
default:
return 1;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
break;
default:
return 1;
}
return 0;
}
/* Disassemble an XScale DSP instruction. Returns nonzero if an error occurred
(ie. an undefined instruction). */
@@ -9544,111 +9544,111 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
/* At this stage dc->condjmp will only be set when the skipped
instruction was a conditional branch or trap, and the PC has
already been written. */
gen_set_condexec(dc);
if (dc->base.is_jmp == DISAS_BX_EXCRET) {
/* Exception return branches need some special case code at the
* end of the TB, which is complex enough that it has to
* handle the single-step vs not and the condition-failed
* insn codepath itself.
*/
gen_bx_excret_final_code(dc);
} else if (unlikely(dc->ss_active)) {
/* Unconditional and "condition passed" instruction codepath. */
switch (dc->base.is_jmp) {
case DISAS_SWI:
gen_ss_advance(dc);
gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));
break;
case DISAS_HVC:
gen_ss_advance(dc);
gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2);
break;
case DISAS_SMC:
gen_ss_advance(dc);
gen_exception_el(EXCP_SMC, syn_aa32_smc(), 3);
break;
case DISAS_NEXT:
case DISAS_TOO_MANY:
case DISAS_UPDATE_EXIT:
case DISAS_UPDATE_NOCHAIN:
gen_update_pc(dc, curr_insn_len(dc));
- /* fall through */
+ fallthrough;
default:
/* FIXME: Single stepping a WFI insn will not halt the CPU. */
gen_singlestep_exception(dc);
break;
case DISAS_NORETURN:
break;
}
} else {
/* While branches must always occur at the end of an IT block,
there are a few other things that can cause us to terminate
the TB in the middle of an IT block:
- Exception generating instructions (bkpt, swi, undefined).
- Page boundaries.
- Hardware watchpoints.
Hardware breakpoints have already been handled and skip this code.
*/
switch (dc->base.is_jmp) {
case DISAS_NEXT:
case DISAS_TOO_MANY:
gen_goto_tb(dc, 1, curr_insn_len(dc));
break;
case DISAS_UPDATE_NOCHAIN:
gen_update_pc(dc, curr_insn_len(dc));
- /* fall through */
+ fallthrough;
case DISAS_JUMP:
gen_goto_ptr();
break;
case DISAS_UPDATE_EXIT:
gen_update_pc(dc, curr_insn_len(dc));
- /* fall through */
+ fallthrough;
default:
/* indicate that the hash table must be used to find the next TB */
tcg_gen_exit_tb(NULL, 0);
break;
case DISAS_NORETURN:
/* nothing more to generate */
break;
case DISAS_WFI:
gen_helper_wfi(tcg_env, tcg_constant_i32(curr_insn_len(dc)));
/*
* The helper doesn't necessarily throw an exception, but we
* must go back to the main loop to check for interrupts anyway.
*/
tcg_gen_exit_tb(NULL, 0);
break;
case DISAS_WFE:
gen_helper_wfe(tcg_env);
break;
case DISAS_YIELD:
gen_helper_yield(tcg_env);
break;
case DISAS_SWI:
gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));
break;
case DISAS_HVC:
gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2);
break;
case DISAS_SMC:
gen_exception_el(EXCP_SMC, syn_aa32_smc(), 3);
break;
}
}
if (dc->condjmp) {
/* "Condition failed" instruction codepath for the branch/trap insn */
set_disas_label(dc, dc->condlabel);
gen_set_condexec(dc);
if (unlikely(dc->ss_active)) {
gen_update_pc(dc, curr_insn_len(dc));
gen_singlestep_exception(dc);
} else {
gen_goto_tb(dc, 1, curr_insn_len(dc));
}
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 24/78] target/alpha: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (22 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 23/78] target/arm: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 25/78] target/i386: " Emmanouil Pitsidianakis
` (54 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Richard Henderson
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
target/alpha/helper.c | 6 +++---
target/alpha/translate.c | 4 +++-
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/alpha/helper.c b/target/alpha/helper.c
index 970c869771..1afdc1beec 100644
--- a/target/alpha/helper.c
+++ b/target/alpha/helper.c
@@ -436,45 +436,45 @@ void alpha_cpu_do_interrupt(CPUState *cs)
bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
AlphaCPU *cpu = ALPHA_CPU(cs);
CPUAlphaState *env = &cpu->env;
int idx = -1;
/* We never take interrupts while in PALmode. */
if (env->flags & ENV_FLAG_PAL_MODE) {
return false;
}
/* Fall through the switch, collecting the highest priority
interrupt that isn't masked by the processor status IPL. */
/* ??? This hard-codes the OSF/1 interrupt levels. */
switch ((env->flags >> ENV_FLAG_PS_SHIFT) & PS_INT_MASK) {
case 0 ... 3:
if (interrupt_request & CPU_INTERRUPT_HARD) {
idx = EXCP_DEV_INTERRUPT;
}
- /* FALLTHRU */
+ fallthrough;
case 4:
if (interrupt_request & CPU_INTERRUPT_TIMER) {
idx = EXCP_CLK_INTERRUPT;
}
- /* FALLTHRU */
+ fallthrough;
case 5:
if (interrupt_request & CPU_INTERRUPT_SMP) {
idx = EXCP_SMP_INTERRUPT;
}
- /* FALLTHRU */
+ fallthrough;
case 6:
if (interrupt_request & CPU_INTERRUPT_MCHK) {
idx = EXCP_MCHK;
}
}
if (idx >= 0) {
cs->exception_index = idx;
env->error_code = 0;
alpha_cpu_do_interrupt(cs);
return true;
}
return false;
}
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 32333081d8..19e1d2ed86 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -1377,1493 +1377,1493 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno)
static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
{
int32_t disp21, disp16, disp12 __attribute__((unused));
uint16_t fn11;
uint8_t opc, ra, rb, rc, fpfn, fn7, lit;
bool islit, real_islit;
TCGv va, vb, vc, tmp, tmp2;
TCGv_i32 t32;
DisasJumpType ret;
/* Decode all instruction fields */
opc = extract32(insn, 26, 6);
ra = extract32(insn, 21, 5);
rb = extract32(insn, 16, 5);
rc = extract32(insn, 0, 5);
real_islit = islit = extract32(insn, 12, 1);
lit = extract32(insn, 13, 8);
disp21 = sextract32(insn, 0, 21);
disp16 = sextract32(insn, 0, 16);
disp12 = sextract32(insn, 0, 12);
fn11 = extract32(insn, 5, 11);
fpfn = extract32(insn, 5, 6);
fn7 = extract32(insn, 5, 7);
if (rb == 31 && !islit) {
islit = true;
lit = 0;
}
ret = DISAS_NEXT;
switch (opc) {
case 0x00:
/* CALL_PAL */
ret = gen_call_pal(ctx, insn & 0x03ffffff);
break;
case 0x01:
/* OPC01 */
goto invalid_opc;
case 0x02:
/* OPC02 */
goto invalid_opc;
case 0x03:
/* OPC03 */
goto invalid_opc;
case 0x04:
/* OPC04 */
goto invalid_opc;
case 0x05:
/* OPC05 */
goto invalid_opc;
case 0x06:
/* OPC06 */
goto invalid_opc;
case 0x07:
/* OPC07 */
goto invalid_opc;
case 0x09:
/* LDAH */
disp16 = (uint32_t)disp16 << 16;
- /* fall through */
+ fallthrough;
case 0x08:
/* LDA */
va = dest_gpr(ctx, ra);
/* It's worth special-casing immediate loads. */
if (rb == 31) {
tcg_gen_movi_i64(va, disp16);
} else {
tcg_gen_addi_i64(va, load_gpr(ctx, rb), disp16);
}
break;
case 0x0A:
/* LDBU */
REQUIRE_AMASK(BWX);
gen_load_int(ctx, ra, rb, disp16, MO_UB, 0, 0);
break;
case 0x0B:
/* LDQ_U */
gen_load_int(ctx, ra, rb, disp16, MO_LEUQ, 1, 0);
break;
case 0x0C:
/* LDWU */
REQUIRE_AMASK(BWX);
gen_load_int(ctx, ra, rb, disp16, MO_LEUW, 0, 0);
break;
case 0x0D:
/* STW */
REQUIRE_AMASK(BWX);
gen_store_int(ctx, ra, rb, disp16, MO_LEUW, 0);
break;
case 0x0E:
/* STB */
REQUIRE_AMASK(BWX);
gen_store_int(ctx, ra, rb, disp16, MO_UB, 0);
break;
case 0x0F:
/* STQ_U */
gen_store_int(ctx, ra, rb, disp16, MO_LEUQ, 1);
break;
case 0x10:
vc = dest_gpr(ctx, rc);
vb = load_gpr_lit(ctx, rb, lit, islit);
if (ra == 31) {
if (fn7 == 0x00) {
/* Special case ADDL as SEXTL. */
tcg_gen_ext32s_i64(vc, vb);
break;
}
if (fn7 == 0x29) {
/* Special case SUBQ as NEGQ. */
tcg_gen_neg_i64(vc, vb);
break;
}
}
va = load_gpr(ctx, ra);
switch (fn7) {
case 0x00:
/* ADDL */
tcg_gen_add_i64(vc, va, vb);
tcg_gen_ext32s_i64(vc, vc);
break;
case 0x02:
/* S4ADDL */
tmp = tcg_temp_new();
tcg_gen_shli_i64(tmp, va, 2);
tcg_gen_add_i64(tmp, tmp, vb);
tcg_gen_ext32s_i64(vc, tmp);
break;
case 0x09:
/* SUBL */
tcg_gen_sub_i64(vc, va, vb);
tcg_gen_ext32s_i64(vc, vc);
break;
case 0x0B:
/* S4SUBL */
tmp = tcg_temp_new();
tcg_gen_shli_i64(tmp, va, 2);
tcg_gen_sub_i64(tmp, tmp, vb);
tcg_gen_ext32s_i64(vc, tmp);
break;
case 0x0F:
/* CMPBGE */
if (ra == 31) {
/* Special case 0 >= X as X == 0. */
gen_helper_cmpbe0(vc, vb);
} else {
gen_helper_cmpbge(vc, va, vb);
}
break;
case 0x12:
/* S8ADDL */
tmp = tcg_temp_new();
tcg_gen_shli_i64(tmp, va, 3);
tcg_gen_add_i64(tmp, tmp, vb);
tcg_gen_ext32s_i64(vc, tmp);
break;
case 0x1B:
/* S8SUBL */
tmp = tcg_temp_new();
tcg_gen_shli_i64(tmp, va, 3);
tcg_gen_sub_i64(tmp, tmp, vb);
tcg_gen_ext32s_i64(vc, tmp);
break;
case 0x1D:
/* CMPULT */
tcg_gen_setcond_i64(TCG_COND_LTU, vc, va, vb);
break;
case 0x20:
/* ADDQ */
tcg_gen_add_i64(vc, va, vb);
break;
case 0x22:
/* S4ADDQ */
tmp = tcg_temp_new();
tcg_gen_shli_i64(tmp, va, 2);
tcg_gen_add_i64(vc, tmp, vb);
break;
case 0x29:
/* SUBQ */
tcg_gen_sub_i64(vc, va, vb);
break;
case 0x2B:
/* S4SUBQ */
tmp = tcg_temp_new();
tcg_gen_shli_i64(tmp, va, 2);
tcg_gen_sub_i64(vc, tmp, vb);
break;
case 0x2D:
/* CMPEQ */
tcg_gen_setcond_i64(TCG_COND_EQ, vc, va, vb);
break;
case 0x32:
/* S8ADDQ */
tmp = tcg_temp_new();
tcg_gen_shli_i64(tmp, va, 3);
tcg_gen_add_i64(vc, tmp, vb);
break;
case 0x3B:
/* S8SUBQ */
tmp = tcg_temp_new();
tcg_gen_shli_i64(tmp, va, 3);
tcg_gen_sub_i64(vc, tmp, vb);
break;
case 0x3D:
/* CMPULE */
tcg_gen_setcond_i64(TCG_COND_LEU, vc, va, vb);
break;
case 0x40:
/* ADDL/V */
tmp = tcg_temp_new();
tcg_gen_ext32s_i64(tmp, va);
tcg_gen_ext32s_i64(vc, vb);
tcg_gen_add_i64(tmp, tmp, vc);
tcg_gen_ext32s_i64(vc, tmp);
gen_helper_check_overflow(tcg_env, vc, tmp);
break;
case 0x49:
/* SUBL/V */
tmp = tcg_temp_new();
tcg_gen_ext32s_i64(tmp, va);
tcg_gen_ext32s_i64(vc, vb);
tcg_gen_sub_i64(tmp, tmp, vc);
tcg_gen_ext32s_i64(vc, tmp);
gen_helper_check_overflow(tcg_env, vc, tmp);
break;
case 0x4D:
/* CMPLT */
tcg_gen_setcond_i64(TCG_COND_LT, vc, va, vb);
break;
case 0x60:
/* ADDQ/V */
tmp = tcg_temp_new();
tmp2 = tcg_temp_new();
tcg_gen_eqv_i64(tmp, va, vb);
tcg_gen_mov_i64(tmp2, va);
tcg_gen_add_i64(vc, va, vb);
tcg_gen_xor_i64(tmp2, tmp2, vc);
tcg_gen_and_i64(tmp, tmp, tmp2);
tcg_gen_shri_i64(tmp, tmp, 63);
tcg_gen_movi_i64(tmp2, 0);
gen_helper_check_overflow(tcg_env, tmp, tmp2);
break;
case 0x69:
/* SUBQ/V */
tmp = tcg_temp_new();
tmp2 = tcg_temp_new();
tcg_gen_xor_i64(tmp, va, vb);
tcg_gen_mov_i64(tmp2, va);
tcg_gen_sub_i64(vc, va, vb);
tcg_gen_xor_i64(tmp2, tmp2, vc);
tcg_gen_and_i64(tmp, tmp, tmp2);
tcg_gen_shri_i64(tmp, tmp, 63);
tcg_gen_movi_i64(tmp2, 0);
gen_helper_check_overflow(tcg_env, tmp, tmp2);
break;
case 0x6D:
/* CMPLE */
tcg_gen_setcond_i64(TCG_COND_LE, vc, va, vb);
break;
default:
goto invalid_opc;
}
break;
case 0x11:
if (fn7 == 0x20) {
if (rc == 31) {
/* Special case BIS as NOP. */
break;
}
if (ra == 31) {
/* Special case BIS as MOV. */
vc = dest_gpr(ctx, rc);
if (islit) {
tcg_gen_movi_i64(vc, lit);
} else {
tcg_gen_mov_i64(vc, load_gpr(ctx, rb));
}
break;
}
}
vc = dest_gpr(ctx, rc);
vb = load_gpr_lit(ctx, rb, lit, islit);
if (fn7 == 0x28 && ra == 31) {
/* Special case ORNOT as NOT. */
tcg_gen_not_i64(vc, vb);
break;
}
va = load_gpr(ctx, ra);
switch (fn7) {
case 0x00:
/* AND */
tcg_gen_and_i64(vc, va, vb);
break;
case 0x08:
/* BIC */
tcg_gen_andc_i64(vc, va, vb);
break;
case 0x14:
/* CMOVLBS */
tmp = tcg_temp_new();
tcg_gen_andi_i64(tmp, va, 1);
tcg_gen_movcond_i64(TCG_COND_NE, vc, tmp, load_zero(ctx),
vb, load_gpr(ctx, rc));
break;
case 0x16:
/* CMOVLBC */
tmp = tcg_temp_new();
tcg_gen_andi_i64(tmp, va, 1);
tcg_gen_movcond_i64(TCG_COND_EQ, vc, tmp, load_zero(ctx),
vb, load_gpr(ctx, rc));
break;
case 0x20:
/* BIS */
tcg_gen_or_i64(vc, va, vb);
break;
case 0x24:
/* CMOVEQ */
tcg_gen_movcond_i64(TCG_COND_EQ, vc, va, load_zero(ctx),
vb, load_gpr(ctx, rc));
break;
case 0x26:
/* CMOVNE */
tcg_gen_movcond_i64(TCG_COND_NE, vc, va, load_zero(ctx),
vb, load_gpr(ctx, rc));
break;
case 0x28:
/* ORNOT */
tcg_gen_orc_i64(vc, va, vb);
break;
case 0x40:
/* XOR */
tcg_gen_xor_i64(vc, va, vb);
break;
case 0x44:
/* CMOVLT */
tcg_gen_movcond_i64(TCG_COND_LT, vc, va, load_zero(ctx),
vb, load_gpr(ctx, rc));
break;
case 0x46:
/* CMOVGE */
tcg_gen_movcond_i64(TCG_COND_GE, vc, va, load_zero(ctx),
vb, load_gpr(ctx, rc));
break;
case 0x48:
/* EQV */
tcg_gen_eqv_i64(vc, va, vb);
break;
case 0x61:
/* AMASK */
REQUIRE_REG_31(ra);
tcg_gen_andi_i64(vc, vb, ~ctx->amask);
break;
case 0x64:
/* CMOVLE */
tcg_gen_movcond_i64(TCG_COND_LE, vc, va, load_zero(ctx),
vb, load_gpr(ctx, rc));
break;
case 0x66:
/* CMOVGT */
tcg_gen_movcond_i64(TCG_COND_GT, vc, va, load_zero(ctx),
vb, load_gpr(ctx, rc));
break;
case 0x6C:
/* IMPLVER */
REQUIRE_REG_31(ra);
tcg_gen_movi_i64(vc, ctx->implver);
break;
default:
goto invalid_opc;
}
break;
case 0x12:
vc = dest_gpr(ctx, rc);
va = load_gpr(ctx, ra);
switch (fn7) {
case 0x02:
/* MSKBL */
gen_msk_l(ctx, vc, va, rb, islit, lit, 0x01);
break;
case 0x06:
/* EXTBL */
gen_ext_l(ctx, vc, va, rb, islit, lit, 0x01);
break;
case 0x0B:
/* INSBL */
gen_ins_l(ctx, vc, va, rb, islit, lit, 0x01);
break;
case 0x12:
/* MSKWL */
gen_msk_l(ctx, vc, va, rb, islit, lit, 0x03);
break;
case 0x16:
/* EXTWL */
gen_ext_l(ctx, vc, va, rb, islit, lit, 0x03);
break;
case 0x1B:
/* INSWL */
gen_ins_l(ctx, vc, va, rb, islit, lit, 0x03);
break;
case 0x22:
/* MSKLL */
gen_msk_l(ctx, vc, va, rb, islit, lit, 0x0f);
break;
case 0x26:
/* EXTLL */
gen_ext_l(ctx, vc, va, rb, islit, lit, 0x0f);
break;
case 0x2B:
/* INSLL */
gen_ins_l(ctx, vc, va, rb, islit, lit, 0x0f);
break;
case 0x30:
/* ZAP */
if (islit) {
gen_zapnoti(vc, va, ~lit);
} else {
gen_helper_zap(vc, va, load_gpr(ctx, rb));
}
break;
case 0x31:
/* ZAPNOT */
if (islit) {
gen_zapnoti(vc, va, lit);
} else {
gen_helper_zapnot(vc, va, load_gpr(ctx, rb));
}
break;
case 0x32:
/* MSKQL */
gen_msk_l(ctx, vc, va, rb, islit, lit, 0xff);
break;
case 0x34:
/* SRL */
if (islit) {
tcg_gen_shri_i64(vc, va, lit & 0x3f);
} else {
tmp = tcg_temp_new();
vb = load_gpr(ctx, rb);
tcg_gen_andi_i64(tmp, vb, 0x3f);
tcg_gen_shr_i64(vc, va, tmp);
}
break;
case 0x36:
/* EXTQL */
gen_ext_l(ctx, vc, va, rb, islit, lit, 0xff);
break;
case 0x39:
/* SLL */
if (islit) {
tcg_gen_shli_i64(vc, va, lit & 0x3f);
} else {
tmp = tcg_temp_new();
vb = load_gpr(ctx, rb);
tcg_gen_andi_i64(tmp, vb, 0x3f);
tcg_gen_shl_i64(vc, va, tmp);
}
break;
case 0x3B:
/* INSQL */
gen_ins_l(ctx, vc, va, rb, islit, lit, 0xff);
break;
case 0x3C:
/* SRA */
if (islit) {
tcg_gen_sari_i64(vc, va, lit & 0x3f);
} else {
tmp = tcg_temp_new();
vb = load_gpr(ctx, rb);
tcg_gen_andi_i64(tmp, vb, 0x3f);
tcg_gen_sar_i64(vc, va, tmp);
}
break;
case 0x52:
/* MSKWH */
gen_msk_h(ctx, vc, va, rb, islit, lit, 0x03);
break;
case 0x57:
/* INSWH */
gen_ins_h(ctx, vc, va, rb, islit, lit, 0x03);
break;
case 0x5A:
/* EXTWH */
gen_ext_h(ctx, vc, va, rb, islit, lit, 0x03);
break;
case 0x62:
/* MSKLH */
gen_msk_h(ctx, vc, va, rb, islit, lit, 0x0f);
break;
case 0x67:
/* INSLH */
gen_ins_h(ctx, vc, va, rb, islit, lit, 0x0f);
break;
case 0x6A:
/* EXTLH */
gen_ext_h(ctx, vc, va, rb, islit, lit, 0x0f);
break;
case 0x72:
/* MSKQH */
gen_msk_h(ctx, vc, va, rb, islit, lit, 0xff);
break;
case 0x77:
/* INSQH */
gen_ins_h(ctx, vc, va, rb, islit, lit, 0xff);
break;
case 0x7A:
/* EXTQH */
gen_ext_h(ctx, vc, va, rb, islit, lit, 0xff);
break;
default:
goto invalid_opc;
}
break;
case 0x13:
vc = dest_gpr(ctx, rc);
vb = load_gpr_lit(ctx, rb, lit, islit);
va = load_gpr(ctx, ra);
switch (fn7) {
case 0x00:
/* MULL */
tcg_gen_mul_i64(vc, va, vb);
tcg_gen_ext32s_i64(vc, vc);
break;
case 0x20:
/* MULQ */
tcg_gen_mul_i64(vc, va, vb);
break;
case 0x30:
/* UMULH */
tmp = tcg_temp_new();
tcg_gen_mulu2_i64(tmp, vc, va, vb);
break;
case 0x40:
/* MULL/V */
tmp = tcg_temp_new();
tcg_gen_ext32s_i64(tmp, va);
tcg_gen_ext32s_i64(vc, vb);
tcg_gen_mul_i64(tmp, tmp, vc);
tcg_gen_ext32s_i64(vc, tmp);
gen_helper_check_overflow(tcg_env, vc, tmp);
break;
case 0x60:
/* MULQ/V */
tmp = tcg_temp_new();
tmp2 = tcg_temp_new();
tcg_gen_muls2_i64(vc, tmp, va, vb);
tcg_gen_sari_i64(tmp2, vc, 63);
gen_helper_check_overflow(tcg_env, tmp, tmp2);
break;
default:
goto invalid_opc;
}
break;
case 0x14:
REQUIRE_AMASK(FIX);
vc = dest_fpr(ctx, rc);
switch (fpfn) { /* fn11 & 0x3F */
case 0x04:
/* ITOFS */
REQUIRE_REG_31(rb);
REQUIRE_FEN;
t32 = tcg_temp_new_i32();
va = load_gpr(ctx, ra);
tcg_gen_extrl_i64_i32(t32, va);
gen_helper_memory_to_s(vc, t32);
break;
case 0x0A:
/* SQRTF */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
vb = load_fpr(ctx, rb);
gen_helper_sqrtf(vc, tcg_env, vb);
break;
case 0x0B:
/* SQRTS */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_sqrts(ctx, rb, rc, fn11);
break;
case 0x14:
/* ITOFF */
REQUIRE_REG_31(rb);
REQUIRE_FEN;
t32 = tcg_temp_new_i32();
va = load_gpr(ctx, ra);
tcg_gen_extrl_i64_i32(t32, va);
gen_helper_memory_to_f(vc, t32);
break;
case 0x24:
/* ITOFT */
REQUIRE_REG_31(rb);
REQUIRE_FEN;
va = load_gpr(ctx, ra);
tcg_gen_mov_i64(vc, va);
break;
case 0x2A:
/* SQRTG */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
vb = load_fpr(ctx, rb);
gen_helper_sqrtg(vc, tcg_env, vb);
break;
case 0x02B:
/* SQRTT */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_sqrtt(ctx, rb, rc, fn11);
break;
default:
goto invalid_opc;
}
break;
case 0x15:
/* VAX floating point */
/* XXX: rounding mode and trap are ignored (!) */
vc = dest_fpr(ctx, rc);
vb = load_fpr(ctx, rb);
va = load_fpr(ctx, ra);
switch (fpfn) { /* fn11 & 0x3F */
case 0x00:
/* ADDF */
REQUIRE_FEN;
gen_helper_addf(vc, tcg_env, va, vb);
break;
case 0x01:
/* SUBF */
REQUIRE_FEN;
gen_helper_subf(vc, tcg_env, va, vb);
break;
case 0x02:
/* MULF */
REQUIRE_FEN;
gen_helper_mulf(vc, tcg_env, va, vb);
break;
case 0x03:
/* DIVF */
REQUIRE_FEN;
gen_helper_divf(vc, tcg_env, va, vb);
break;
case 0x1E:
/* CVTDG -- TODO */
REQUIRE_REG_31(ra);
goto invalid_opc;
case 0x20:
/* ADDG */
REQUIRE_FEN;
gen_helper_addg(vc, tcg_env, va, vb);
break;
case 0x21:
/* SUBG */
REQUIRE_FEN;
gen_helper_subg(vc, tcg_env, va, vb);
break;
case 0x22:
/* MULG */
REQUIRE_FEN;
gen_helper_mulg(vc, tcg_env, va, vb);
break;
case 0x23:
/* DIVG */
REQUIRE_FEN;
gen_helper_divg(vc, tcg_env, va, vb);
break;
case 0x25:
/* CMPGEQ */
REQUIRE_FEN;
gen_helper_cmpgeq(vc, tcg_env, va, vb);
break;
case 0x26:
/* CMPGLT */
REQUIRE_FEN;
gen_helper_cmpglt(vc, tcg_env, va, vb);
break;
case 0x27:
/* CMPGLE */
REQUIRE_FEN;
gen_helper_cmpgle(vc, tcg_env, va, vb);
break;
case 0x2C:
/* CVTGF */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_helper_cvtgf(vc, tcg_env, vb);
break;
case 0x2D:
/* CVTGD -- TODO */
REQUIRE_REG_31(ra);
goto invalid_opc;
case 0x2F:
/* CVTGQ */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_helper_cvtgq(vc, tcg_env, vb);
break;
case 0x3C:
/* CVTQF */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_helper_cvtqf(vc, tcg_env, vb);
break;
case 0x3E:
/* CVTQG */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_helper_cvtqg(vc, tcg_env, vb);
break;
default:
goto invalid_opc;
}
break;
case 0x16:
/* IEEE floating-point */
switch (fpfn) { /* fn11 & 0x3F */
case 0x00:
/* ADDS */
REQUIRE_FEN;
gen_adds(ctx, ra, rb, rc, fn11);
break;
case 0x01:
/* SUBS */
REQUIRE_FEN;
gen_subs(ctx, ra, rb, rc, fn11);
break;
case 0x02:
/* MULS */
REQUIRE_FEN;
gen_muls(ctx, ra, rb, rc, fn11);
break;
case 0x03:
/* DIVS */
REQUIRE_FEN;
gen_divs(ctx, ra, rb, rc, fn11);
break;
case 0x20:
/* ADDT */
REQUIRE_FEN;
gen_addt(ctx, ra, rb, rc, fn11);
break;
case 0x21:
/* SUBT */
REQUIRE_FEN;
gen_subt(ctx, ra, rb, rc, fn11);
break;
case 0x22:
/* MULT */
REQUIRE_FEN;
gen_mult(ctx, ra, rb, rc, fn11);
break;
case 0x23:
/* DIVT */
REQUIRE_FEN;
gen_divt(ctx, ra, rb, rc, fn11);
break;
case 0x24:
/* CMPTUN */
REQUIRE_FEN;
gen_cmptun(ctx, ra, rb, rc, fn11);
break;
case 0x25:
/* CMPTEQ */
REQUIRE_FEN;
gen_cmpteq(ctx, ra, rb, rc, fn11);
break;
case 0x26:
/* CMPTLT */
REQUIRE_FEN;
gen_cmptlt(ctx, ra, rb, rc, fn11);
break;
case 0x27:
/* CMPTLE */
REQUIRE_FEN;
gen_cmptle(ctx, ra, rb, rc, fn11);
break;
case 0x2C:
REQUIRE_REG_31(ra);
REQUIRE_FEN;
if (fn11 == 0x2AC || fn11 == 0x6AC) {
/* CVTST */
gen_cvtst(ctx, rb, rc, fn11);
} else {
/* CVTTS */
gen_cvtts(ctx, rb, rc, fn11);
}
break;
case 0x2F:
/* CVTTQ */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_cvttq(ctx, rb, rc, fn11);
break;
case 0x3C:
/* CVTQS */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_cvtqs(ctx, rb, rc, fn11);
break;
case 0x3E:
/* CVTQT */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_cvtqt(ctx, rb, rc, fn11);
break;
default:
goto invalid_opc;
}
break;
case 0x17:
switch (fn11) {
case 0x010:
/* CVTLQ */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
vc = dest_fpr(ctx, rc);
vb = load_fpr(ctx, rb);
gen_cvtlq(vc, vb);
break;
case 0x020:
/* CPYS */
REQUIRE_FEN;
if (rc == 31) {
/* Special case CPYS as FNOP. */
} else {
vc = dest_fpr(ctx, rc);
va = load_fpr(ctx, ra);
if (ra == rb) {
/* Special case CPYS as FMOV. */
tcg_gen_mov_i64(vc, va);
} else {
vb = load_fpr(ctx, rb);
gen_cpy_mask(vc, va, vb, 0, 0x8000000000000000ULL);
}
}
break;
case 0x021:
/* CPYSN */
REQUIRE_FEN;
vc = dest_fpr(ctx, rc);
vb = load_fpr(ctx, rb);
va = load_fpr(ctx, ra);
gen_cpy_mask(vc, va, vb, 1, 0x8000000000000000ULL);
break;
case 0x022:
/* CPYSE */
REQUIRE_FEN;
vc = dest_fpr(ctx, rc);
vb = load_fpr(ctx, rb);
va = load_fpr(ctx, ra);
gen_cpy_mask(vc, va, vb, 0, 0xFFF0000000000000ULL);
break;
case 0x024:
/* MT_FPCR */
REQUIRE_FEN;
va = load_fpr(ctx, ra);
gen_helper_store_fpcr(tcg_env, va);
if (ctx->tb_rm == QUAL_RM_D) {
/* Re-do the copy of the rounding mode to fp_status
the next time we use dynamic rounding. */
ctx->tb_rm = -1;
}
break;
case 0x025:
/* MF_FPCR */
REQUIRE_FEN;
va = dest_fpr(ctx, ra);
gen_helper_load_fpcr(va, tcg_env);
break;
case 0x02A:
/* FCMOVEQ */
REQUIRE_FEN;
gen_fcmov(ctx, TCG_COND_EQ, ra, rb, rc);
break;
case 0x02B:
/* FCMOVNE */
REQUIRE_FEN;
gen_fcmov(ctx, TCG_COND_NE, ra, rb, rc);
break;
case 0x02C:
/* FCMOVLT */
REQUIRE_FEN;
gen_fcmov(ctx, TCG_COND_LT, ra, rb, rc);
break;
case 0x02D:
/* FCMOVGE */
REQUIRE_FEN;
gen_fcmov(ctx, TCG_COND_GE, ra, rb, rc);
break;
case 0x02E:
/* FCMOVLE */
REQUIRE_FEN;
gen_fcmov(ctx, TCG_COND_LE, ra, rb, rc);
break;
case 0x02F:
/* FCMOVGT */
REQUIRE_FEN;
gen_fcmov(ctx, TCG_COND_GT, ra, rb, rc);
break;
case 0x030: /* CVTQL */
case 0x130: /* CVTQL/V */
case 0x530: /* CVTQL/SV */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
vc = dest_fpr(ctx, rc);
vb = load_fpr(ctx, rb);
gen_helper_cvtql(vc, tcg_env, vb);
gen_fp_exc_raise(rc, fn11);
break;
default:
goto invalid_opc;
}
break;
case 0x18:
switch ((uint16_t)disp16) {
case 0x0000:
/* TRAPB */
/* No-op. */
break;
case 0x0400:
/* EXCB */
/* No-op. */
break;
case 0x4000:
/* MB */
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
break;
case 0x4400:
/* WMB */
tcg_gen_mb(TCG_MO_ST_ST | TCG_BAR_SC);
break;
case 0x8000:
/* FETCH */
/* No-op */
break;
case 0xA000:
/* FETCH_M */
/* No-op */
break;
case 0xC000:
/* RPCC */
va = dest_gpr(ctx, ra);
if (translator_io_start(&ctx->base)) {
ret = DISAS_PC_STALE;
}
gen_helper_load_pcc(va, tcg_env);
break;
case 0xE000:
/* RC */
gen_rx(ctx, ra, 0);
break;
case 0xE800:
/* ECB */
break;
case 0xF000:
/* RS */
gen_rx(ctx, ra, 1);
break;
case 0xF800:
/* WH64 */
/* No-op */
break;
case 0xFC00:
/* WH64EN */
/* No-op */
break;
default:
goto invalid_opc;
}
break;
case 0x19:
/* HW_MFPR (PALcode) */
#ifndef CONFIG_USER_ONLY
REQUIRE_TB_FLAG(ENV_FLAG_PAL_MODE);
va = dest_gpr(ctx, ra);
ret = gen_mfpr(ctx, va, insn & 0xffff);
break;
#else
goto invalid_opc;
#endif
case 0x1A:
/* JMP, JSR, RET, JSR_COROUTINE. These only differ by the branch
prediction stack action, which of course we don't implement. */
vb = load_gpr(ctx, rb);
tcg_gen_andi_i64(cpu_pc, vb, ~3);
if (ra != 31) {
tcg_gen_movi_i64(ctx->ir[ra], ctx->base.pc_next);
}
ret = DISAS_PC_UPDATED;
break;
case 0x1B:
/* HW_LD (PALcode) */
#ifndef CONFIG_USER_ONLY
REQUIRE_TB_FLAG(ENV_FLAG_PAL_MODE);
{
TCGv addr = tcg_temp_new();
vb = load_gpr(ctx, rb);
va = dest_gpr(ctx, ra);
tcg_gen_addi_i64(addr, vb, disp12);
switch ((insn >> 12) & 0xF) {
case 0x0:
/* Longword physical access (hw_ldl/p) */
tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL | MO_ALIGN);
break;
case 0x1:
/* Quadword physical access (hw_ldq/p) */
tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEUQ | MO_ALIGN);
break;
case 0x2:
/* Longword physical access with lock (hw_ldl_l/p) */
tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL | MO_ALIGN);
tcg_gen_mov_i64(cpu_lock_addr, addr);
tcg_gen_mov_i64(cpu_lock_value, va);
break;
case 0x3:
/* Quadword physical access with lock (hw_ldq_l/p) */
tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEUQ | MO_ALIGN);
tcg_gen_mov_i64(cpu_lock_addr, addr);
tcg_gen_mov_i64(cpu_lock_value, va);
break;
case 0x4:
/* Longword virtual PTE fetch (hw_ldl/v) */
goto invalid_opc;
case 0x5:
/* Quadword virtual PTE fetch (hw_ldq/v) */
goto invalid_opc;
break;
case 0x6:
/* Invalid */
goto invalid_opc;
case 0x7:
/* Invaliid */
goto invalid_opc;
case 0x8:
/* Longword virtual access (hw_ldl) */
goto invalid_opc;
case 0x9:
/* Quadword virtual access (hw_ldq) */
goto invalid_opc;
case 0xA:
/* Longword virtual access with protection check (hw_ldl/w) */
tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX,
MO_LESL | MO_ALIGN);
break;
case 0xB:
/* Quadword virtual access with protection check (hw_ldq/w) */
tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX,
MO_LEUQ | MO_ALIGN);
break;
case 0xC:
/* Longword virtual access with alt access mode (hw_ldl/a)*/
goto invalid_opc;
case 0xD:
/* Quadword virtual access with alt access mode (hw_ldq/a) */
goto invalid_opc;
case 0xE:
/* Longword virtual access with alternate access mode and
protection checks (hw_ldl/wa) */
tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX,
MO_LESL | MO_ALIGN);
break;
case 0xF:
/* Quadword virtual access with alternate access mode and
protection checks (hw_ldq/wa) */
tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX,
MO_LEUQ | MO_ALIGN);
break;
}
break;
}
#else
goto invalid_opc;
#endif
case 0x1C:
vc = dest_gpr(ctx, rc);
if (fn7 == 0x70) {
/* FTOIT */
REQUIRE_AMASK(FIX);
REQUIRE_REG_31(rb);
va = load_fpr(ctx, ra);
tcg_gen_mov_i64(vc, va);
break;
} else if (fn7 == 0x78) {
/* FTOIS */
REQUIRE_AMASK(FIX);
REQUIRE_REG_31(rb);
t32 = tcg_temp_new_i32();
va = load_fpr(ctx, ra);
gen_helper_s_to_memory(t32, va);
tcg_gen_ext_i32_i64(vc, t32);
break;
}
vb = load_gpr_lit(ctx, rb, lit, islit);
switch (fn7) {
case 0x00:
/* SEXTB */
REQUIRE_AMASK(BWX);
REQUIRE_REG_31(ra);
tcg_gen_ext8s_i64(vc, vb);
break;
case 0x01:
/* SEXTW */
REQUIRE_AMASK(BWX);
REQUIRE_REG_31(ra);
tcg_gen_ext16s_i64(vc, vb);
break;
case 0x30:
/* CTPOP */
REQUIRE_AMASK(CIX);
REQUIRE_REG_31(ra);
REQUIRE_NO_LIT;
tcg_gen_ctpop_i64(vc, vb);
break;
case 0x31:
/* PERR */
REQUIRE_AMASK(MVI);
REQUIRE_NO_LIT;
va = load_gpr(ctx, ra);
gen_helper_perr(vc, va, vb);
break;
case 0x32:
/* CTLZ */
REQUIRE_AMASK(CIX);
REQUIRE_REG_31(ra);
REQUIRE_NO_LIT;
tcg_gen_clzi_i64(vc, vb, 64);
break;
case 0x33:
/* CTTZ */
REQUIRE_AMASK(CIX);
REQUIRE_REG_31(ra);
REQUIRE_NO_LIT;
tcg_gen_ctzi_i64(vc, vb, 64);
break;
case 0x34:
/* UNPKBW */
REQUIRE_AMASK(MVI);
REQUIRE_REG_31(ra);
REQUIRE_NO_LIT;
gen_helper_unpkbw(vc, vb);
break;
case 0x35:
/* UNPKBL */
REQUIRE_AMASK(MVI);
REQUIRE_REG_31(ra);
REQUIRE_NO_LIT;
gen_helper_unpkbl(vc, vb);
break;
case 0x36:
/* PKWB */
REQUIRE_AMASK(MVI);
REQUIRE_REG_31(ra);
REQUIRE_NO_LIT;
gen_helper_pkwb(vc, vb);
break;
case 0x37:
/* PKLB */
REQUIRE_AMASK(MVI);
REQUIRE_REG_31(ra);
REQUIRE_NO_LIT;
gen_helper_pklb(vc, vb);
break;
case 0x38:
/* MINSB8 */
REQUIRE_AMASK(MVI);
va = load_gpr(ctx, ra);
gen_helper_minsb8(vc, va, vb);
break;
case 0x39:
/* MINSW4 */
REQUIRE_AMASK(MVI);
va = load_gpr(ctx, ra);
gen_helper_minsw4(vc, va, vb);
break;
case 0x3A:
/* MINUB8 */
REQUIRE_AMASK(MVI);
va = load_gpr(ctx, ra);
gen_helper_minub8(vc, va, vb);
break;
case 0x3B:
/* MINUW4 */
REQUIRE_AMASK(MVI);
va = load_gpr(ctx, ra);
gen_helper_minuw4(vc, va, vb);
break;
case 0x3C:
/* MAXUB8 */
REQUIRE_AMASK(MVI);
va = load_gpr(ctx, ra);
gen_helper_maxub8(vc, va, vb);
break;
case 0x3D:
/* MAXUW4 */
REQUIRE_AMASK(MVI);
va = load_gpr(ctx, ra);
gen_helper_maxuw4(vc, va, vb);
break;
case 0x3E:
/* MAXSB8 */
REQUIRE_AMASK(MVI);
va = load_gpr(ctx, ra);
gen_helper_maxsb8(vc, va, vb);
break;
case 0x3F:
/* MAXSW4 */
REQUIRE_AMASK(MVI);
va = load_gpr(ctx, ra);
gen_helper_maxsw4(vc, va, vb);
break;
default:
goto invalid_opc;
}
break;
case 0x1D:
/* HW_MTPR (PALcode) */
#ifndef CONFIG_USER_ONLY
REQUIRE_TB_FLAG(ENV_FLAG_PAL_MODE);
vb = load_gpr(ctx, rb);
ret = gen_mtpr(ctx, vb, insn & 0xffff);
break;
#else
goto invalid_opc;
#endif
case 0x1E:
/* HW_RET (PALcode) */
#ifndef CONFIG_USER_ONLY
REQUIRE_TB_FLAG(ENV_FLAG_PAL_MODE);
if (rb == 31) {
/* Pre-EV6 CPUs interpreted this as HW_REI, loading the return
address from EXC_ADDR. This turns out to be useful for our
emulation PALcode, so continue to accept it. */
vb = dest_sink(ctx);
tcg_gen_ld_i64(vb, tcg_env, offsetof(CPUAlphaState, exc_addr));
} else {
vb = load_gpr(ctx, rb);
}
tcg_gen_movi_i64(cpu_lock_addr, -1);
st_flag_byte(load_zero(ctx), ENV_FLAG_RX_SHIFT);
tmp = tcg_temp_new();
tcg_gen_andi_i64(tmp, vb, 1);
st_flag_byte(tmp, ENV_FLAG_PAL_SHIFT);
tcg_gen_andi_i64(cpu_pc, vb, ~3);
/* Allow interrupts to be recognized right away. */
ret = DISAS_PC_UPDATED_NOCHAIN;
break;
#else
goto invalid_opc;
#endif
case 0x1F:
/* HW_ST (PALcode) */
#ifndef CONFIG_USER_ONLY
REQUIRE_TB_FLAG(ENV_FLAG_PAL_MODE);
{
switch ((insn >> 12) & 0xF) {
case 0x0:
/* Longword physical access */
va = load_gpr(ctx, ra);
vb = load_gpr(ctx, rb);
tmp = tcg_temp_new();
tcg_gen_addi_i64(tmp, vb, disp12);
tcg_gen_qemu_st_i64(va, tmp, MMU_PHYS_IDX, MO_LESL | MO_ALIGN);
break;
case 0x1:
/* Quadword physical access */
va = load_gpr(ctx, ra);
vb = load_gpr(ctx, rb);
tmp = tcg_temp_new();
tcg_gen_addi_i64(tmp, vb, disp12);
tcg_gen_qemu_st_i64(va, tmp, MMU_PHYS_IDX, MO_LEUQ | MO_ALIGN);
break;
case 0x2:
/* Longword physical access with lock */
ret = gen_store_conditional(ctx, ra, rb, disp12,
MMU_PHYS_IDX, MO_LESL | MO_ALIGN);
break;
case 0x3:
/* Quadword physical access with lock */
ret = gen_store_conditional(ctx, ra, rb, disp12,
MMU_PHYS_IDX, MO_LEUQ | MO_ALIGN);
break;
case 0x4:
/* Longword virtual access */
goto invalid_opc;
case 0x5:
/* Quadword virtual access */
goto invalid_opc;
case 0x6:
/* Invalid */
goto invalid_opc;
case 0x7:
/* Invalid */
goto invalid_opc;
case 0x8:
/* Invalid */
goto invalid_opc;
case 0x9:
/* Invalid */
goto invalid_opc;
case 0xA:
/* Invalid */
goto invalid_opc;
case 0xB:
/* Invalid */
goto invalid_opc;
case 0xC:
/* Longword virtual access with alternate access mode */
goto invalid_opc;
case 0xD:
/* Quadword virtual access with alternate access mode */
goto invalid_opc;
case 0xE:
/* Invalid */
goto invalid_opc;
case 0xF:
/* Invalid */
goto invalid_opc;
}
break;
}
#else
goto invalid_opc;
#endif
case 0x20:
/* LDF */
REQUIRE_FEN;
gen_load_fp(ctx, ra, rb, disp16, gen_ldf);
break;
case 0x21:
/* LDG */
REQUIRE_FEN;
gen_load_fp(ctx, ra, rb, disp16, gen_ldg);
break;
case 0x22:
/* LDS */
REQUIRE_FEN;
gen_load_fp(ctx, ra, rb, disp16, gen_lds);
break;
case 0x23:
/* LDT */
REQUIRE_FEN;
gen_load_fp(ctx, ra, rb, disp16, gen_ldt);
break;
case 0x24:
/* STF */
REQUIRE_FEN;
gen_store_fp(ctx, ra, rb, disp16, gen_stf);
break;
case 0x25:
/* STG */
REQUIRE_FEN;
gen_store_fp(ctx, ra, rb, disp16, gen_stg);
break;
case 0x26:
/* STS */
REQUIRE_FEN;
gen_store_fp(ctx, ra, rb, disp16, gen_sts);
break;
case 0x27:
/* STT */
REQUIRE_FEN;
gen_store_fp(ctx, ra, rb, disp16, gen_stt);
break;
case 0x28:
/* LDL */
gen_load_int(ctx, ra, rb, disp16, MO_LESL, 0, 0);
break;
case 0x29:
/* LDQ */
gen_load_int(ctx, ra, rb, disp16, MO_LEUQ, 0, 0);
break;
case 0x2A:
/* LDL_L */
gen_load_int(ctx, ra, rb, disp16, MO_LESL | MO_ALIGN, 0, 1);
break;
case 0x2B:
/* LDQ_L */
gen_load_int(ctx, ra, rb, disp16, MO_LEUQ | MO_ALIGN, 0, 1);
break;
case 0x2C:
/* STL */
gen_store_int(ctx, ra, rb, disp16, MO_LEUL, 0);
break;
case 0x2D:
/* STQ */
gen_store_int(ctx, ra, rb, disp16, MO_LEUQ, 0);
break;
case 0x2E:
/* STL_C */
ret = gen_store_conditional(ctx, ra, rb, disp16,
ctx->mem_idx, MO_LESL | MO_ALIGN);
break;
case 0x2F:
/* STQ_C */
ret = gen_store_conditional(ctx, ra, rb, disp16,
ctx->mem_idx, MO_LEUQ | MO_ALIGN);
break;
case 0x30:
/* BR */
ret = gen_bdirect(ctx, ra, disp21);
break;
case 0x31: /* FBEQ */
REQUIRE_FEN;
ret = gen_fbcond(ctx, TCG_COND_EQ, ra, disp21);
break;
case 0x32: /* FBLT */
REQUIRE_FEN;
ret = gen_fbcond(ctx, TCG_COND_LT, ra, disp21);
break;
case 0x33: /* FBLE */
REQUIRE_FEN;
ret = gen_fbcond(ctx, TCG_COND_LE, ra, disp21);
break;
case 0x34:
/* BSR */
ret = gen_bdirect(ctx, ra, disp21);
break;
case 0x35: /* FBNE */
REQUIRE_FEN;
ret = gen_fbcond(ctx, TCG_COND_NE, ra, disp21);
break;
case 0x36: /* FBGE */
REQUIRE_FEN;
ret = gen_fbcond(ctx, TCG_COND_GE, ra, disp21);
break;
case 0x37: /* FBGT */
REQUIRE_FEN;
ret = gen_fbcond(ctx, TCG_COND_GT, ra, disp21);
break;
case 0x38:
/* BLBC */
ret = gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 1);
break;
case 0x39:
/* BEQ */
ret = gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 0);
break;
case 0x3A:
/* BLT */
ret = gen_bcond(ctx, TCG_COND_LT, ra, disp21, 0);
break;
case 0x3B:
/* BLE */
ret = gen_bcond(ctx, TCG_COND_LE, ra, disp21, 0);
break;
case 0x3C:
/* BLBS */
ret = gen_bcond(ctx, TCG_COND_NE, ra, disp21, 1);
break;
case 0x3D:
/* BNE */
ret = gen_bcond(ctx, TCG_COND_NE, ra, disp21, 0);
break;
case 0x3E:
/* BGE */
ret = gen_bcond(ctx, TCG_COND_GE, ra, disp21, 0);
break;
case 0x3F:
/* BGT */
ret = gen_bcond(ctx, TCG_COND_GT, ra, disp21, 0);
break;
invalid_opc:
ret = gen_invalid(ctx);
break;
raise_fen:
ret = gen_excp(ctx, EXCP_FEN, 0);
break;
}
return ret;
}
@@ -2929,27 +2929,29 @@ static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
static void alpha_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
switch (ctx->base.is_jmp) {
case DISAS_NORETURN:
break;
case DISAS_TOO_MANY:
if (use_goto_tb(ctx, ctx->base.pc_next)) {
tcg_gen_goto_tb(0);
tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next);
tcg_gen_exit_tb(ctx->base.tb, 0);
}
/* FALLTHRU */
+ fallthrough;
case DISAS_PC_STALE:
tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next);
/* FALLTHRU */
+ fallthrough;
case DISAS_PC_UPDATED:
tcg_gen_lookup_and_goto_ptr();
break;
case DISAS_PC_UPDATED_NOCHAIN:
tcg_gen_exit_tb(NULL, 0);
break;
default:
g_assert_not_reached();
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 25/78] target/i386: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (23 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 24/78] target/alpha: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 26/78] target/s390x: " Emmanouil Pitsidianakis
` (53 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Cameron Esfahani, Roman Bolshakov,
Paolo Bonzini, Marcelo Tosatti, Richard Henderson,
Eduardo Habkost, open list:X86 KVM CPUs
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
target/i386/cpu.c | 2 +-
target/i386/hvf/x86_decode.c | 1 +
target/i386/kvm/kvm.c | 4 ++--
target/i386/tcg/decode-new.c.inc | 6 +++---
target/i386/tcg/emit.c.inc | 2 +-
target/i386/tcg/translate.c | 8 +++-----
6 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index cec5d2b7b6..f73784edca 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6009,670 +6009,670 @@ uint32_t cpu_x86_virtual_addr_width(CPUX86State *env)
void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx)
{
X86CPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
uint32_t die_offset;
uint32_t limit;
uint32_t signature[3];
X86CPUTopoInfo topo_info;
topo_info.dies_per_pkg = env->nr_dies;
topo_info.cores_per_die = cs->nr_cores;
topo_info.threads_per_core = cs->nr_threads;
/* Calculate & apply limits for different index ranges */
if (index >= 0xC0000000) {
limit = env->cpuid_xlevel2;
} else if (index >= 0x80000000) {
limit = env->cpuid_xlevel;
} else if (index >= 0x40000000) {
limit = 0x40000001;
} else {
limit = env->cpuid_level;
}
if (index > limit) {
/* Intel documentation states that invalid EAX input will
* return the same information as EAX=cpuid_level
* (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
*/
index = env->cpuid_level;
}
switch(index) {
case 0:
*eax = env->cpuid_level;
*ebx = env->cpuid_vendor1;
*edx = env->cpuid_vendor2;
*ecx = env->cpuid_vendor3;
break;
case 1:
*eax = env->cpuid_version;
*ebx = (cpu->apic_id << 24) |
8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
*ecx = env->features[FEAT_1_ECX];
if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
*ecx |= CPUID_EXT_OSXSAVE;
}
*edx = env->features[FEAT_1_EDX];
if (cs->nr_cores * cs->nr_threads > 1) {
*ebx |= (cs->nr_cores * cs->nr_threads) << 16;
*edx |= CPUID_HT;
}
if (!cpu->enable_pmu) {
*ecx &= ~CPUID_EXT_PDCM;
}
break;
case 2:
/* cache info: needed for Pentium Pro compatibility */
if (cpu->cache_info_passthrough) {
x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx);
break;
} else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) {
*eax = *ebx = *ecx = *edx = 0;
break;
}
*eax = 1; /* Number of CPUID[EAX=2] calls required */
*ebx = 0;
if (!cpu->enable_l3_cache) {
*ecx = 0;
} else {
*ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
}
*edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
(cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
(cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
break;
case 4:
/* cache info: needed for Core compatibility */
if (cpu->cache_info_passthrough) {
x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx);
/*
* QEMU has its own number of cores/logical cpus,
* set 24..14, 31..26 bit to configured values
*/
if (*eax & 31) {
int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14);
int vcpus_per_socket = env->nr_dies * cs->nr_cores *
cs->nr_threads;
if (cs->nr_cores > 1) {
*eax &= ~0xFC000000;
*eax |= (pow2ceil(cs->nr_cores) - 1) << 26;
}
if (host_vcpus_per_cache > vcpus_per_socket) {
*eax &= ~0x3FFC000;
*eax |= (pow2ceil(vcpus_per_socket) - 1) << 14;
}
}
} else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) {
*eax = *ebx = *ecx = *edx = 0;
} else {
*eax = 0;
switch (count) {
case 0: /* L1 dcache info */
encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
1, cs->nr_cores,
eax, ebx, ecx, edx);
break;
case 1: /* L1 icache info */
encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
1, cs->nr_cores,
eax, ebx, ecx, edx);
break;
case 2: /* L2 cache info */
encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
cs->nr_threads, cs->nr_cores,
eax, ebx, ecx, edx);
break;
case 3: /* L3 cache info */
die_offset = apicid_die_offset(&topo_info);
if (cpu->enable_l3_cache) {
encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
(1 << die_offset), cs->nr_cores,
eax, ebx, ecx, edx);
break;
}
- /* fall through */
+ fallthrough;
default: /* end of info */
*eax = *ebx = *ecx = *edx = 0;
break;
}
}
break;
case 5:
/* MONITOR/MWAIT Leaf */
*eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
*ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
*ecx = cpu->mwait.ecx; /* flags */
*edx = cpu->mwait.edx; /* mwait substates */
break;
case 6:
/* Thermal and Power Leaf */
*eax = env->features[FEAT_6_EAX];
*ebx = 0;
*ecx = 0;
*edx = 0;
break;
case 7:
/* Structured Extended Feature Flags Enumeration Leaf */
if (count == 0) {
uint32_t eax_0_unused, ebx_0, ecx_0, edx_0_unused;
/* Maximum ECX value for sub-leaves */
*eax = env->cpuid_level_func7;
*ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
*ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
*ecx |= CPUID_7_0_ECX_OSPKE;
}
*edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
/*
* SGX cannot be emulated in software. If hardware does not
* support enabling SGX and/or SGX flexible launch control,
* then we need to update the VM's CPUID values accordingly.
*/
x86_cpu_get_supported_cpuid(0x7, 0,
&eax_0_unused, &ebx_0,
&ecx_0, &edx_0_unused);
if ((*ebx & CPUID_7_0_EBX_SGX) && !(ebx_0 & CPUID_7_0_EBX_SGX)) {
*ebx &= ~CPUID_7_0_EBX_SGX;
}
if ((*ecx & CPUID_7_0_ECX_SGX_LC)
&& (!(*ebx & CPUID_7_0_EBX_SGX) || !(ecx_0 & CPUID_7_0_ECX_SGX_LC))) {
*ecx &= ~CPUID_7_0_ECX_SGX_LC;
}
} else if (count == 1) {
*eax = env->features[FEAT_7_1_EAX];
*edx = env->features[FEAT_7_1_EDX];
*ebx = 0;
*ecx = 0;
} else if (count == 2) {
*edx = env->features[FEAT_7_2_EDX];
*eax = 0;
*ebx = 0;
*ecx = 0;
} else {
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
}
break;
case 9:
/* Direct Cache Access Information Leaf */
*eax = 0; /* Bits 0-31 in DCA_CAP MSR */
*ebx = 0;
*ecx = 0;
*edx = 0;
break;
case 0xA:
/* Architectural Performance Monitoring Leaf */
if (cpu->enable_pmu) {
x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx);
} else {
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
}
break;
case 0xB:
/* Extended Topology Enumeration Leaf */
if (!cpu->enable_cpuid_0xb) {
*eax = *ebx = *ecx = *edx = 0;
break;
}
*ecx = count & 0xff;
*edx = cpu->apic_id;
switch (count) {
case 0:
*eax = apicid_core_offset(&topo_info);
*ebx = cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
break;
case 1:
*eax = apicid_pkg_offset(&topo_info);
*ebx = cs->nr_cores * cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
default:
*eax = 0;
*ebx = 0;
*ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
}
assert(!(*eax & ~0x1f));
*ebx &= 0xffff; /* The count doesn't need to be reliable. */
break;
case 0x1C:
if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx);
*edx = 0;
}
break;
case 0x1F:
/* V2 Extended Topology Enumeration Leaf */
if (env->nr_dies < 2) {
*eax = *ebx = *ecx = *edx = 0;
break;
}
*ecx = count & 0xff;
*edx = cpu->apic_id;
switch (count) {
case 0:
*eax = apicid_core_offset(&topo_info);
*ebx = cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
break;
case 1:
*eax = apicid_die_offset(&topo_info);
*ebx = cs->nr_cores * cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
case 2:
*eax = apicid_pkg_offset(&topo_info);
*ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
break;
default:
*eax = 0;
*ebx = 0;
*ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
}
assert(!(*eax & ~0x1f));
*ebx &= 0xffff; /* The count doesn't need to be reliable. */
break;
case 0xD: {
/* Processor Extended State */
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
break;
}
if (count == 0) {
*ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false);
*eax = env->features[FEAT_XSAVE_XCR0_LO];
*edx = env->features[FEAT_XSAVE_XCR0_HI];
/*
* The initial value of xcr0 and ebx == 0, On host without kvm
* commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
* even through guest update xcr0, this will crash some legacy guest
* (e.g., CentOS 6), So set ebx == ecx to workaround it.
*/
*ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false);
} else if (count == 1) {
uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) |
x86_cpu_xsave_xss_components(cpu);
*eax = env->features[FEAT_XSAVE];
*ebx = xsave_area_size(xstate, true);
*ecx = env->features[FEAT_XSAVE_XSS_LO];
*edx = env->features[FEAT_XSAVE_XSS_HI];
if (kvm_enabled() && cpu->enable_pmu &&
(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) &&
(*eax & CPUID_XSAVE_XSAVES)) {
*ecx |= XSTATE_ARCH_LBR_MASK;
} else {
*ecx &= ~XSTATE_ARCH_LBR_MASK;
}
} else if (count == 0xf && cpu->enable_pmu
&& (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx);
} else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
const ExtSaveArea *esa = &x86_ext_save_areas[count];
if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) {
*eax = esa->size;
*ebx = esa->offset;
*ecx = esa->ecx &
(ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK);
} else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) {
*eax = esa->size;
*ebx = 0;
*ecx = 1;
}
}
break;
}
case 0x12:
#ifndef CONFIG_USER_ONLY
if (!kvm_enabled() ||
!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) {
*eax = *ebx = *ecx = *edx = 0;
break;
}
/*
* SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve
* the EPC properties, e.g. confidentiality and integrity, from the
* host's first EPC section, i.e. assume there is one EPC section or
* that all EPC sections have the same security properties.
*/
if (count > 1) {
uint64_t epc_addr, epc_size;
if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) {
*eax = *ebx = *ecx = *edx = 0;
break;
}
host_cpuid(index, 2, eax, ebx, ecx, edx);
*eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1;
*ebx = (uint32_t)(epc_addr >> 32);
*ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf);
*edx = (uint32_t)(epc_size >> 32);
break;
}
/*
* SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware
* and KVM, i.e. QEMU cannot emulate features to override what KVM
* supports. Features can be further restricted by userspace, but not
* made more permissive.
*/
x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx);
if (count == 0) {
*eax &= env->features[FEAT_SGX_12_0_EAX];
*ebx &= env->features[FEAT_SGX_12_0_EBX];
} else {
*eax &= env->features[FEAT_SGX_12_1_EAX];
*ebx &= 0; /* ebx reserve */
*ecx &= env->features[FEAT_XSAVE_XCR0_LO];
*edx &= env->features[FEAT_XSAVE_XCR0_HI];
/* FP and SSE are always allowed regardless of XSAVE/XCR0. */
*ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK;
/* Access to PROVISIONKEY requires additional credentials. */
if ((*eax & (1U << 4)) &&
!kvm_enable_sgx_provisioning(cs->kvm_state)) {
*eax &= ~(1U << 4);
}
}
#endif
break;
case 0x14: {
/* Intel Processor Trace Enumeration */
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
!kvm_enabled()) {
break;
}
if (count == 0) {
*eax = INTEL_PT_MAX_SUBLEAF;
*ebx = INTEL_PT_MINIMAL_EBX;
*ecx = INTEL_PT_MINIMAL_ECX;
if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) {
*ecx |= CPUID_14_0_ECX_LIP;
}
} else if (count == 1) {
*eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
*ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
}
break;
}
case 0x1D: {
/* AMX TILE, for now hardcoded for Sapphire Rapids*/
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) {
break;
}
if (count == 0) {
/* Highest numbered palette subleaf */
*eax = INTEL_AMX_TILE_MAX_SUBLEAF;
} else if (count == 1) {
*eax = INTEL_AMX_TOTAL_TILE_BYTES |
(INTEL_AMX_BYTES_PER_TILE << 16);
*ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16);
*ecx = INTEL_AMX_TILE_MAX_ROWS;
}
break;
}
case 0x1E: {
/* AMX TMUL, for now hardcoded for Sapphire Rapids */
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) {
break;
}
if (count == 0) {
/* Highest numbered palette subleaf */
*ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8);
}
break;
}
case 0x40000000:
/*
* CPUID code in kvm_arch_init_vcpu() ignores stuff
* set here, but we restrict to TCG none the less.
*/
if (tcg_enabled() && cpu->expose_tcg) {
memcpy(signature, "TCGTCGTCGTCG", 12);
*eax = 0x40000001;
*ebx = signature[0];
*ecx = signature[1];
*edx = signature[2];
} else {
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
}
break;
case 0x40000001:
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
break;
case 0x80000000:
*eax = env->cpuid_xlevel;
*ebx = env->cpuid_vendor1;
*edx = env->cpuid_vendor2;
*ecx = env->cpuid_vendor3;
break;
case 0x80000001:
*eax = env->cpuid_version;
*ebx = 0;
*ecx = env->features[FEAT_8000_0001_ECX];
*edx = env->features[FEAT_8000_0001_EDX];
/* The Linux kernel checks for the CMPLegacy bit and
* discards multiple thread information if it is set.
* So don't set it here for Intel to make Linux guests happy.
*/
if (cs->nr_cores * cs->nr_threads > 1) {
if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
*ecx |= 1 << 1; /* CmpLegacy bit */
}
}
if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 &&
!(env->hflags & HF_LMA_MASK)) {
*edx &= ~CPUID_EXT2_SYSCALL;
}
break;
case 0x80000002:
case 0x80000003:
case 0x80000004:
*eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
*ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
*ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
*edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
break;
case 0x80000005:
/* cache info (L1 cache) */
if (cpu->cache_info_passthrough) {
x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx);
break;
}
*eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) |
(L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
*ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) |
(L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
*ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
*edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
break;
case 0x80000006:
/* cache info (L2 cache) */
if (cpu->cache_info_passthrough) {
x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx);
break;
}
*eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) |
(L2_DTLB_2M_ENTRIES << 16) |
(AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) |
(L2_ITLB_2M_ENTRIES);
*ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) |
(L2_DTLB_4K_ENTRIES << 16) |
(AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) |
(L2_ITLB_4K_ENTRIES);
encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
cpu->enable_l3_cache ?
env->cache_info_amd.l3_cache : NULL,
ecx, edx);
break;
case 0x80000007:
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = env->features[FEAT_8000_0007_EDX];
break;
case 0x80000008:
/* virtual & phys address size in low 2 bytes. */
*eax = cpu->phys_bits;
if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
/* 64 bit processor */
*eax |= (cpu_x86_virtual_addr_width(env) << 8);
}
*ebx = env->features[FEAT_8000_0008_EBX];
if (cs->nr_cores * cs->nr_threads > 1) {
/*
* Bits 15:12 is "The number of bits in the initial
* Core::X86::Apic::ApicId[ApicId] value that indicate
* thread ID within a package".
* Bits 7:0 is "The number of threads in the package is NC+1"
*/
*ecx = (apicid_pkg_offset(&topo_info) << 12) |
((cs->nr_cores * cs->nr_threads) - 1);
} else {
*ecx = 0;
}
*edx = 0;
break;
case 0x8000000A:
if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
*eax = 0x00000001; /* SVM Revision */
*ebx = 0x00000010; /* nr of ASIDs */
*ecx = 0;
*edx = env->features[FEAT_SVM]; /* optional features */
} else {
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
}
break;
case 0x8000001D:
*eax = 0;
if (cpu->cache_info_passthrough) {
x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx);
break;
}
switch (count) {
case 0: /* L1 dcache info */
encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
&topo_info, eax, ebx, ecx, edx);
break;
case 1: /* L1 icache info */
encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
&topo_info, eax, ebx, ecx, edx);
break;
case 2: /* L2 cache info */
encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
&topo_info, eax, ebx, ecx, edx);
break;
case 3: /* L3 cache info */
encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
&topo_info, eax, ebx, ecx, edx);
break;
default: /* end of info */
*eax = *ebx = *ecx = *edx = 0;
break;
}
break;
case 0x8000001E:
if (cpu->core_id <= 255) {
encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx);
} else {
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
}
break;
case 0xC0000000:
*eax = env->cpuid_xlevel2;
*ebx = 0;
*ecx = 0;
*edx = 0;
break;
case 0xC0000001:
/* Support for VIA CPU's CPUID instruction */
*eax = env->cpuid_version;
*ebx = 0;
*ecx = 0;
*edx = env->features[FEAT_C000_0001_EDX];
break;
case 0xC0000002:
case 0xC0000003:
case 0xC0000004:
/* Reserved for the future, and now filled with zero */
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
break;
case 0x8000001F:
*eax = *ebx = *ecx = *edx = 0;
if (sev_enabled()) {
*eax = 0x2;
*eax |= sev_es_enabled() ? 0x8 : 0;
*ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */
*ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */
}
break;
case 0x80000021:
*eax = env->features[FEAT_8000_0021_EAX];
*ebx = *ecx = *edx = 0;
break;
default:
/* reserved values: zero */
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
break;
}
}
diff --git a/target/i386/hvf/x86_decode.c b/target/i386/hvf/x86_decode.c
index 3728d7705e..7c2e3dab8d 100644
--- a/target/i386/hvf/x86_decode.c
+++ b/target/i386/hvf/x86_decode.c
@@ -1847,48 +1847,49 @@ void calc_modrm_operand(CPUX86State *env, struct x86_decode *decode,
static void decode_prefix(CPUX86State *env, struct x86_decode *decode)
{
while (1) {
/*
* REX prefix must come after legacy prefixes.
* REX before legacy is ignored.
* Clear rex to simulate this.
*/
uint8_t byte = decode_byte(env, decode);
switch (byte) {
case PREFIX_LOCK:
decode->lock = byte;
decode->rex.rex = 0;
break;
case PREFIX_REPN:
case PREFIX_REP:
decode->rep = byte;
decode->rex.rex = 0;
break;
case PREFIX_CS_SEG_OVERRIDE:
case PREFIX_SS_SEG_OVERRIDE:
case PREFIX_DS_SEG_OVERRIDE:
case PREFIX_ES_SEG_OVERRIDE:
case PREFIX_FS_SEG_OVERRIDE:
case PREFIX_GS_SEG_OVERRIDE:
decode->segment_override = byte;
decode->rex.rex = 0;
break;
case PREFIX_OP_SIZE_OVERRIDE:
decode->op_size_override = byte;
decode->rex.rex = 0;
break;
case PREFIX_ADDR_SIZE_OVERRIDE:
decode->addr_size_override = byte;
decode->rex.rex = 0;
break;
case PREFIX_REX ... (PREFIX_REX + 0xf):
if (x86_is_long_mode(env_cpu(env))) {
decode->rex.rex = byte;
break;
}
/* fall through when not in long mode */
+ fallthrough;
default:
decode->len--;
return;
}
}
}
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index f6c7f7e268..d283d56aa9 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -497,77 +497,77 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
{
struct {
struct kvm_msrs info;
struct kvm_msr_entry entries[1];
} msr_data = {};
uint64_t value;
uint32_t ret, can_be_one, must_be_one;
if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
return 0;
}
/* Check if requested MSR is supported feature MSR */
int i;
for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
if (kvm_feature_msrs->indices[i] == index) {
break;
}
if (i == kvm_feature_msrs->nmsrs) {
return 0; /* if the feature MSR is not supported, simply return 0 */
}
msr_data.info.nmsrs = 1;
msr_data.entries[0].index = index;
ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
if (ret != 1) {
error_report("KVM get MSR (index=0x%x) feature failed, %s",
index, strerror(-ret));
exit(1);
}
value = msr_data.entries[0].data;
switch (index) {
case MSR_IA32_VMX_PROCBASED_CTLS2:
if (!has_msr_vmx_procbased_ctls2) {
/* KVM forgot to add these bits for some time, do this ourselves. */
if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) &
CPUID_XSAVE_XSAVES) {
value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32;
}
if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) &
CPUID_EXT_RDRAND) {
value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32;
}
if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
CPUID_7_0_EBX_INVPCID) {
value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32;
}
if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
CPUID_7_0_EBX_RDSEED) {
value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32;
}
if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) &
CPUID_EXT2_RDTSCP) {
value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32;
}
}
- /* fall through */
+ fallthrough;
case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
case MSR_IA32_VMX_TRUE_EXIT_CTLS:
/*
* Return true for bits that can be one, but do not have to be one.
* The SDM tells us which bits could have a "must be one" setting,
* so we can do the opposite transformation in make_vmx_msr_value.
*/
must_be_one = (uint32_t)value;
can_be_one = (uint32_t)(value >> 32);
return can_be_one & ~must_be_one;
default:
return value;
}
}
@@ -1752,524 +1752,524 @@ static void kvm_init_nested_state(CPUX86State *env)
int kvm_arch_init_vcpu(CPUState *cs)
{
struct {
struct kvm_cpuid2 cpuid;
struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
} cpuid_data;
/*
* The kernel defines these structs with padding fields so there
* should be no extra padding in our cpuid_data struct.
*/
QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
sizeof(struct kvm_cpuid2) +
sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
uint32_t limit, i, j, cpuid_i;
uint32_t unused;
struct kvm_cpuid_entry2 *c;
uint32_t signature[3];
int kvm_base = KVM_CPUID_SIGNATURE;
int max_nested_state_len;
int r;
Error *local_err = NULL;
memset(&cpuid_data, 0, sizeof(cpuid_data));
cpuid_i = 0;
has_xsave2 = kvm_check_extension(cs->kvm_state, KVM_CAP_XSAVE2);
r = kvm_arch_set_tsc_khz(cs);
if (r < 0) {
return r;
}
/* vcpu's TSC frequency is either specified by user, or following
* the value used by KVM if the former is not present. In the
* latter case, we query it from KVM and record in env->tsc_khz,
* so that vcpu's TSC frequency can be migrated later via this field.
*/
if (!env->tsc_khz) {
r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
-ENOTSUP;
if (r > 0) {
env->tsc_khz = r;
}
}
env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY;
/*
* kvm_hyperv_expand_features() is called here for the second time in case
* KVM_CAP_SYS_HYPERV_CPUID is not supported. While we can't possibly handle
* 'query-cpu-model-expansion' in this case as we don't have a KVM vCPU to
* check which Hyper-V enlightenments are supported and which are not, we
* can still proceed and check/expand Hyper-V enlightenments here so legacy
* behavior is preserved.
*/
if (!kvm_hyperv_expand_features(cpu, &local_err)) {
error_report_err(local_err);
return -ENOSYS;
}
if (hyperv_enabled(cpu)) {
r = hyperv_init_vcpu(cpu);
if (r) {
return r;
}
cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries);
kvm_base = KVM_CPUID_SIGNATURE_NEXT;
has_msr_hv_hypercall = true;
}
if (cs->kvm_state->xen_version) {
#ifdef CONFIG_XEN_EMU
struct kvm_cpuid_entry2 *xen_max_leaf;
memcpy(signature, "XenVMMXenVMM", 12);
xen_max_leaf = c = &cpuid_data.entries[cpuid_i++];
c->function = kvm_base + XEN_CPUID_SIGNATURE;
c->eax = kvm_base + XEN_CPUID_TIME;
c->ebx = signature[0];
c->ecx = signature[1];
c->edx = signature[2];
c = &cpuid_data.entries[cpuid_i++];
c->function = kvm_base + XEN_CPUID_VENDOR;
c->eax = cs->kvm_state->xen_version;
c->ebx = 0;
c->ecx = 0;
c->edx = 0;
c = &cpuid_data.entries[cpuid_i++];
c->function = kvm_base + XEN_CPUID_HVM_MSR;
/* Number of hypercall-transfer pages */
c->eax = 1;
/* Hypercall MSR base address */
if (hyperv_enabled(cpu)) {
c->ebx = XEN_HYPERCALL_MSR_HYPERV;
kvm_xen_init(cs->kvm_state, c->ebx);
} else {
c->ebx = XEN_HYPERCALL_MSR;
}
c->ecx = 0;
c->edx = 0;
c = &cpuid_data.entries[cpuid_i++];
c->function = kvm_base + XEN_CPUID_TIME;
c->eax = ((!!tsc_is_stable_and_known(env) << 1) |
(!!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP) << 2));
/* default=0 (emulate if necessary) */
c->ebx = 0;
/* guest tsc frequency */
c->ecx = env->user_tsc_khz;
/* guest tsc incarnation (migration count) */
c->edx = 0;
c = &cpuid_data.entries[cpuid_i++];
c->function = kvm_base + XEN_CPUID_HVM;
xen_max_leaf->eax = kvm_base + XEN_CPUID_HVM;
if (cs->kvm_state->xen_version >= XEN_VERSION(4, 5)) {
c->function = kvm_base + XEN_CPUID_HVM;
if (cpu->xen_vapic) {
c->eax |= XEN_HVM_CPUID_APIC_ACCESS_VIRT;
c->eax |= XEN_HVM_CPUID_X2APIC_VIRT;
}
c->eax |= XEN_HVM_CPUID_IOMMU_MAPPINGS;
if (cs->kvm_state->xen_version >= XEN_VERSION(4, 6)) {
c->eax |= XEN_HVM_CPUID_VCPU_ID_PRESENT;
c->ebx = cs->cpu_index;
}
}
r = kvm_xen_init_vcpu(cs);
if (r) {
return r;
}
kvm_base += 0x100;
#else /* CONFIG_XEN_EMU */
/* This should never happen as kvm_arch_init() would have died first. */
fprintf(stderr, "Cannot enable Xen CPUID without Xen support\n");
abort();
#endif
} else if (cpu->expose_kvm) {
memcpy(signature, "KVMKVMKVM\0\0\0", 12);
c = &cpuid_data.entries[cpuid_i++];
c->function = KVM_CPUID_SIGNATURE | kvm_base;
c->eax = KVM_CPUID_FEATURES | kvm_base;
c->ebx = signature[0];
c->ecx = signature[1];
c->edx = signature[2];
c = &cpuid_data.entries[cpuid_i++];
c->function = KVM_CPUID_FEATURES | kvm_base;
c->eax = env->features[FEAT_KVM];
c->edx = env->features[FEAT_KVM_HINTS];
}
cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
if (cpu->kvm_pv_enforce_cpuid) {
r = kvm_vcpu_enable_cap(cs, KVM_CAP_ENFORCE_PV_FEATURE_CPUID, 0, 1);
if (r < 0) {
fprintf(stderr,
"failed to enable KVM_CAP_ENFORCE_PV_FEATURE_CPUID: %s",
strerror(-r));
abort();
}
}
for (i = 0; i <= limit; i++) {
if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
fprintf(stderr, "unsupported level value: 0x%x\n", limit);
abort();
}
c = &cpuid_data.entries[cpuid_i++];
switch (i) {
case 2: {
/* Keep reading function 2 till all the input is received */
int times;
c->function = i;
c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
KVM_CPUID_FLAG_STATE_READ_NEXT;
cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
times = c->eax & 0xff;
for (j = 1; j < times; ++j) {
if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
fprintf(stderr, "cpuid_data is full, no space for "
"cpuid(eax:2):eax & 0xf = 0x%x\n", times);
abort();
}
c = &cpuid_data.entries[cpuid_i++];
c->function = i;
c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
}
break;
}
case 0x1f:
if (env->nr_dies < 2) {
break;
}
- /* fallthrough */
+ fallthrough;
case 4:
case 0xb:
case 0xd:
for (j = 0; ; j++) {
if (i == 0xd && j == 64) {
break;
}
if (i == 0x1f && j == 64) {
break;
}
c->function = i;
c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
c->index = j;
cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
if (i == 4 && c->eax == 0) {
break;
}
if (i == 0xb && !(c->ecx & 0xff00)) {
break;
}
if (i == 0x1f && !(c->ecx & 0xff00)) {
break;
}
if (i == 0xd && c->eax == 0) {
continue;
}
if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
fprintf(stderr, "cpuid_data is full, no space for "
"cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
abort();
}
c = &cpuid_data.entries[cpuid_i++];
}
break;
case 0x7:
case 0x12:
for (j = 0; ; j++) {
c->function = i;
c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
c->index = j;
cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
if (j > 1 && (c->eax & 0xf) != 1) {
break;
}
if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
fprintf(stderr, "cpuid_data is full, no space for "
"cpuid(eax:0x12,ecx:0x%x)\n", j);
abort();
}
c = &cpuid_data.entries[cpuid_i++];
}
break;
case 0x14:
case 0x1d:
case 0x1e: {
uint32_t times;
c->function = i;
c->index = 0;
c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
times = c->eax;
for (j = 1; j <= times; ++j) {
if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
fprintf(stderr, "cpuid_data is full, no space for "
"cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
abort();
}
c = &cpuid_data.entries[cpuid_i++];
c->function = i;
c->index = j;
c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
}
break;
}
default:
c->function = i;
c->flags = 0;
cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
/*
* KVM already returns all zeroes if a CPUID entry is missing,
* so we can omit it and avoid hitting KVM's 80-entry limit.
*/
cpuid_i--;
}
break;
}
}
if (limit >= 0x0a) {
uint32_t eax, edx;
cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
has_architectural_pmu_version = eax & 0xff;
if (has_architectural_pmu_version > 0) {
num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
/* Shouldn't be more than 32, since that's the number of bits
* available in EBX to tell us _which_ counters are available.
* Play it safe.
*/
if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
}
if (has_architectural_pmu_version > 1) {
num_architectural_pmu_fixed_counters = edx & 0x1f;
if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
}
}
}
}
cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
for (i = 0x80000000; i <= limit; i++) {
if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
abort();
}
c = &cpuid_data.entries[cpuid_i++];
switch (i) {
case 0x8000001d:
/* Query for all AMD cache information leaves */
for (j = 0; ; j++) {
c->function = i;
c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
c->index = j;
cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
if (c->eax == 0) {
break;
}
if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
fprintf(stderr, "cpuid_data is full, no space for "
"cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
abort();
}
c = &cpuid_data.entries[cpuid_i++];
}
break;
default:
c->function = i;
c->flags = 0;
cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
/*
* KVM already returns all zeroes if a CPUID entry is missing,
* so we can omit it and avoid hitting KVM's 80-entry limit.
*/
cpuid_i--;
}
break;
}
}
/* Call Centaur's CPUID instructions they are supported. */
if (env->cpuid_xlevel2 > 0) {
cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
for (i = 0xC0000000; i <= limit; i++) {
if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
abort();
}
c = &cpuid_data.entries[cpuid_i++];
c->function = i;
c->flags = 0;
cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
}
}
cpuid_data.cpuid.nent = cpuid_i;
if (((env->cpuid_version >> 8)&0xF) >= 6
&& (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
(CPUID_MCE | CPUID_MCA)
&& kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
uint64_t mcg_cap, unsupported_caps;
int banks;
int ret;
ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
if (ret < 0) {
fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
return ret;
}
if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
(int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
return -ENOTSUP;
}
unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
if (unsupported_caps) {
if (unsupported_caps & MCG_LMCE_P) {
error_report("kvm: LMCE not supported");
return -ENOTSUP;
}
warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
unsupported_caps);
}
env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
if (ret < 0) {
fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
return ret;
}
}
cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env);
c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
if (c) {
has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
!!(c->ecx & CPUID_EXT_SMX);
}
c = cpuid_find_entry(&cpuid_data.cpuid, 7, 0);
if (c && (c->ebx & CPUID_7_0_EBX_SGX)) {
has_msr_feature_control = true;
}
if (env->mcg_cap & MCG_LMCE_P) {
has_msr_mcg_ext_ctl = has_msr_feature_control = true;
}
if (!env->user_tsc_khz) {
if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
invtsc_mig_blocker == NULL) {
error_setg(&invtsc_mig_blocker,
"State blocked by non-migratable CPU device"
" (invtsc flag)");
r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
if (r < 0) {
error_report_err(local_err);
return r;
}
}
}
if (cpu->vmware_cpuid_freq
/* Guests depend on 0x40000000 to detect this feature, so only expose
* it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
&& cpu->expose_kvm
&& kvm_base == KVM_CPUID_SIGNATURE
/* TSC clock must be stable and known for this feature. */
&& tsc_is_stable_and_known(env)) {
c = &cpuid_data.entries[cpuid_i++];
c->function = KVM_CPUID_SIGNATURE | 0x10;
c->eax = env->tsc_khz;
c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */
c->ecx = c->edx = 0;
c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
}
cpuid_data.cpuid.nent = cpuid_i;
cpuid_data.cpuid.padding = 0;
r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
if (r) {
goto fail;
}
kvm_init_xsave(env);
max_nested_state_len = kvm_max_nested_state_length();
if (max_nested_state_len > 0) {
assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
if (cpu_has_vmx(env) || cpu_has_svm(env)) {
env->nested_state = g_malloc0(max_nested_state_len);
env->nested_state->size = max_nested_state_len;
kvm_init_nested_state(env);
}
}
cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
has_msr_tsc_aux = false;
}
kvm_init_msrs(cpu);
return 0;
fail:
migrate_del_blocker(invtsc_mig_blocker);
return r;
}
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index 7d76f15275..0e663e9124 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -1050,84 +1050,84 @@ static int decode_modrm(DisasContext *s, CPUX86State *env, X86DecodedInsn *decod
static bool decode_op_size(DisasContext *s, X86OpEntry *e, X86OpSize size, MemOp *ot)
{
switch (size) {
case X86_SIZE_b: /* byte */
*ot = MO_8;
return true;
case X86_SIZE_d: /* 32-bit */
case X86_SIZE_ss: /* SSE/AVX scalar single precision */
*ot = MO_32;
return true;
case X86_SIZE_p: /* Far pointer, return offset size */
case X86_SIZE_s: /* Descriptor, return offset size */
case X86_SIZE_v: /* 16/32/64-bit, based on operand size */
*ot = s->dflag;
return true;
case X86_SIZE_pi: /* MMX */
case X86_SIZE_q: /* 64-bit */
case X86_SIZE_sd: /* SSE/AVX scalar double precision */
*ot = MO_64;
return true;
case X86_SIZE_w: /* 16-bit */
*ot = MO_16;
return true;
case X86_SIZE_y: /* 32/64-bit, based on operand size */
*ot = s->dflag == MO_16 ? MO_32 : s->dflag;
return true;
case X86_SIZE_z: /* 16-bit for 16-bit operand size, else 32-bit */
*ot = s->dflag == MO_16 ? MO_16 : MO_32;
return true;
case X86_SIZE_dq: /* SSE/AVX 128-bit */
if (e->special == X86_SPECIAL_MMX &&
!(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
*ot = MO_64;
return true;
}
if (s->vex_l && e->s0 != X86_SIZE_qq && e->s1 != X86_SIZE_qq) {
return false;
}
*ot = MO_128;
return true;
case X86_SIZE_qq: /* AVX 256-bit */
if (!s->vex_l) {
return false;
}
*ot = MO_256;
return true;
case X86_SIZE_x: /* 128/256-bit, based on operand size */
if (e->special == X86_SPECIAL_MMX &&
!(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
*ot = MO_64;
return true;
}
- /* fall through */
+ fallthrough;
case X86_SIZE_ps: /* SSE/AVX packed single precision */
case X86_SIZE_pd: /* SSE/AVX packed double precision */
*ot = s->vex_l ? MO_256 : MO_128;
return true;
case X86_SIZE_xh: /* SSE/AVX packed half register */
*ot = s->vex_l ? MO_128 : MO_64;
return true;
case X86_SIZE_d64: /* Default to 64-bit in 64-bit mode */
*ot = CODE64(s) && s->dflag == MO_32 ? MO_64 : s->dflag;
return true;
case X86_SIZE_f64: /* Ignore size override prefix in 64-bit mode */
*ot = CODE64(s) ? MO_64 : s->dflag;
return true;
default:
*ot = -1;
return true;
}
}
@@ -1135,183 +1135,183 @@ static bool decode_op_size(DisasContext *s, X86OpEntry *e, X86OpSize size, MemOp
static bool decode_op(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
X86DecodedOp *op, X86OpType type, int b)
{
int modrm;
switch (type) {
case X86_TYPE_None: /* Implicit or absent */
case X86_TYPE_A: /* Implicit */
case X86_TYPE_F: /* EFLAGS/RFLAGS */
break;
case X86_TYPE_B: /* VEX.vvvv selects a GPR */
op->unit = X86_OP_INT;
op->n = s->vex_v;
break;
case X86_TYPE_C: /* REG in the modrm byte selects a control register */
op->unit = X86_OP_CR;
goto get_reg;
case X86_TYPE_D: /* REG in the modrm byte selects a debug register */
op->unit = X86_OP_DR;
goto get_reg;
case X86_TYPE_G: /* REG in the modrm byte selects a GPR */
op->unit = X86_OP_INT;
goto get_reg;
case X86_TYPE_S: /* reg selects a segment register */
op->unit = X86_OP_SEG;
goto get_reg;
case X86_TYPE_P:
op->unit = X86_OP_MMX;
goto get_reg;
case X86_TYPE_V: /* reg in the modrm byte selects an XMM/YMM register */
if (decode->e.special == X86_SPECIAL_MMX &&
!(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
op->unit = X86_OP_MMX;
} else {
op->unit = X86_OP_SSE;
}
get_reg:
op->n = ((get_modrm(s, env) >> 3) & 7) | REX_R(s);
break;
case X86_TYPE_E: /* ALU modrm operand */
op->unit = X86_OP_INT;
goto get_modrm;
case X86_TYPE_Q: /* MMX modrm operand */
op->unit = X86_OP_MMX;
goto get_modrm;
case X86_TYPE_W: /* XMM/YMM modrm operand */
if (decode->e.special == X86_SPECIAL_MMX &&
!(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
op->unit = X86_OP_MMX;
} else {
op->unit = X86_OP_SSE;
}
goto get_modrm;
case X86_TYPE_N: /* R/M in the modrm byte selects an MMX register */
op->unit = X86_OP_MMX;
goto get_modrm_reg;
case X86_TYPE_U: /* R/M in the modrm byte selects an XMM/YMM register */
if (decode->e.special == X86_SPECIAL_MMX &&
!(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
op->unit = X86_OP_MMX;
} else {
op->unit = X86_OP_SSE;
}
goto get_modrm_reg;
case X86_TYPE_R: /* R/M in the modrm byte selects a register */
op->unit = X86_OP_INT;
get_modrm_reg:
modrm = get_modrm(s, env);
if ((modrm >> 6) != 3) {
return false;
}
goto get_modrm;
case X86_TYPE_WM: /* modrm byte selects an XMM/YMM memory operand */
op->unit = X86_OP_SSE;
- /* fall through */
+ fallthrough;
case X86_TYPE_M: /* modrm byte selects a memory operand */
modrm = get_modrm(s, env);
if ((modrm >> 6) == 3) {
return false;
}
get_modrm:
decode_modrm(s, env, decode, op, type);
break;
case X86_TYPE_O: /* Absolute address encoded in the instruction */
op->unit = X86_OP_INT;
op->has_ea = true;
op->n = -1;
decode->mem = (AddressParts) {
.def_seg = R_DS,
.base = -1,
.index = -1,
.disp = insn_get_addr(env, s, s->aflag)
};
break;
case X86_TYPE_H: /* For AVX, VEX.vvvv selects an XMM/YMM register */
if ((s->prefix & PREFIX_VEX)) {
op->unit = X86_OP_SSE;
op->n = s->vex_v;
break;
}
if (op == &decode->op[0]) {
/* shifts place the destination in VEX.vvvv, use modrm */
return decode_op(s, env, decode, op, decode->e.op1, b);
} else {
return decode_op(s, env, decode, op, decode->e.op0, b);
}
case X86_TYPE_I: /* Immediate */
op->unit = X86_OP_IMM;
decode->immediate = insn_get_signed(env, s, op->ot);
break;
case X86_TYPE_J: /* Relative offset for a jump */
op->unit = X86_OP_IMM;
decode->immediate = insn_get_signed(env, s, op->ot);
decode->immediate += s->pc - s->cs_base;
if (s->dflag == MO_16) {
decode->immediate &= 0xffff;
} else if (!CODE64(s)) {
decode->immediate &= 0xffffffffu;
}
break;
case X86_TYPE_L: /* The upper 4 bits of the immediate select a 128-bit register */
op->n = insn_get(env, s, op->ot) >> 4;
break;
case X86_TYPE_X: /* string source */
op->n = -1;
decode->mem = (AddressParts) {
.def_seg = R_DS,
.base = R_ESI,
.index = -1,
};
break;
case X86_TYPE_Y: /* string destination */
op->n = -1;
decode->mem = (AddressParts) {
.def_seg = R_ES,
.base = R_EDI,
.index = -1,
};
break;
case X86_TYPE_2op:
*op = decode->op[0];
break;
case X86_TYPE_LoBits:
op->n = (b & 7) | REX_B(s);
op->unit = X86_OP_INT;
break;
case X86_TYPE_0 ... X86_TYPE_7:
op->n = type - X86_TYPE_0;
op->unit = X86_OP_INT;
break;
case X86_TYPE_ES ... X86_TYPE_GS:
op->n = type - X86_TYPE_ES;
op->unit = X86_OP_SEG;
break;
}
return true;
}
@@ -1463,120 +1463,120 @@ static bool has_cpuid_feature(DisasContext *s, X86CPUIDFeature cpuid)
static bool validate_vex(DisasContext *s, X86DecodedInsn *decode)
{
X86OpEntry *e = &decode->e;
switch (e->vex_special) {
case X86_VEX_REPScalar:
/*
* Instructions which differ between 00/66 and F2/F3 in the
* exception classification and the size of the memory operand.
*/
assert(e->vex_class == 1 || e->vex_class == 2 || e->vex_class == 4);
if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
e->vex_class = e->vex_class < 4 ? 3 : 5;
if (s->vex_l) {
goto illegal;
}
assert(decode->e.s2 == X86_SIZE_x);
if (decode->op[2].has_ea) {
decode->op[2].ot = s->prefix & PREFIX_REPZ ? MO_32 : MO_64;
}
}
break;
case X86_VEX_SSEUnaligned:
/* handled in sse_needs_alignment. */
break;
case X86_VEX_AVX2_256:
if ((s->prefix & PREFIX_VEX) && s->vex_l && !has_cpuid_feature(s, X86_FEAT_AVX2)) {
goto illegal;
}
}
/* TODO: instructions that require VEX.W=0 (Table 2-16) */
switch (e->vex_class) {
case 0:
if (s->prefix & PREFIX_VEX) {
goto illegal;
}
return true;
case 1:
case 2:
case 3:
case 4:
case 5:
case 7:
if (s->prefix & PREFIX_VEX) {
if (!(s->flags & HF_AVX_EN_MASK)) {
goto illegal;
}
} else if (e->special != X86_SPECIAL_MMX ||
(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))) {
if (!(s->flags & HF_OSFXSR_MASK)) {
goto illegal;
}
}
break;
case 12:
/* Must have a VSIB byte and no address prefix. */
assert(s->has_modrm);
if ((s->modrm & 7) != 4 || s->aflag == MO_16) {
goto illegal;
}
/* Check no overlap between registers. */
if (!decode->op[0].has_ea &&
(decode->op[0].n == decode->mem.index || decode->op[0].n == decode->op[1].n)) {
goto illegal;
}
assert(!decode->op[1].has_ea);
if (decode->op[1].n == decode->mem.index) {
goto illegal;
}
if (!decode->op[2].has_ea &&
(decode->op[2].n == decode->mem.index || decode->op[2].n == decode->op[1].n)) {
goto illegal;
}
- /* fall through */
+ fallthrough;
case 6:
case 11:
if (!(s->prefix & PREFIX_VEX)) {
goto illegal;
}
if (!(s->flags & HF_AVX_EN_MASK)) {
goto illegal;
}
break;
case 8:
/* Non-VEX case handled in decode_0F77. */
assert(s->prefix & PREFIX_VEX);
if (!(s->flags & HF_AVX_EN_MASK)) {
goto illegal;
}
break;
case 13:
if (!(s->prefix & PREFIX_VEX)) {
goto illegal;
}
if (s->vex_l) {
goto illegal;
}
/* All integer instructions use VEX.vvvv, so exit. */
return true;
}
if (s->vex_v != 0 &&
e->op0 != X86_TYPE_H && e->op0 != X86_TYPE_B &&
e->op1 != X86_TYPE_H && e->op1 != X86_TYPE_B &&
e->op2 != X86_TYPE_H && e->op2 != X86_TYPE_B) {
goto illegal;
}
if (s->flags & HF_TS_MASK) {
goto nm_exception;
}
if (s->flags & HF_EM_MASK) {
goto illegal;
}
return true;
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index 88793ba988..0e0a2efbf9 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -202,18 +202,18 @@ static void gen_load_sse(DisasContext *s, TCGv temp, MemOp ot, int dest_ofs, boo
static bool sse_needs_alignment(DisasContext *s, X86DecodedInsn *decode, MemOp ot)
{
switch (decode->e.vex_class) {
case 2:
case 4:
if ((s->prefix & PREFIX_VEX) ||
decode->e.vex_special == X86_VEX_SSEUnaligned) {
/* MOST legacy SSE instructions require aligned memory operands, but not all. */
return false;
}
- /* fall through */
+ fallthrough;
case 1:
return ot >= MO_128;
default:
return false;
}
}
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index e42e3dd653..77a8fcc5e1 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -1001,26 +1001,26 @@ static CCPrepare gen_prepare_eflags_p(DisasContext *s, TCGv reg)
/* compute eflags.S to reg */
static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg)
{
switch (s->cc_op) {
case CC_OP_DYNAMIC:
gen_compute_eflags(s);
- /* FALLTHRU */
+ fallthrough;
case CC_OP_EFLAGS:
case CC_OP_ADCX:
case CC_OP_ADOX:
case CC_OP_ADCOX:
return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
.mask = CC_S };
case CC_OP_CLR:
case CC_OP_POPCNT:
return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 };
default:
{
MemOp size = (s->cc_op - CC_OP_ADDB) & 3;
TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, true);
return (CCPrepare) { .cond = TCG_COND_LT, .reg = t0, .mask = -1 };
}
}
}
/* compute eflags.O to reg */
@@ -1044,29 +1044,29 @@ static CCPrepare gen_prepare_eflags_o(DisasContext *s, TCGv reg)
/* compute eflags.Z to reg */
static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
{
switch (s->cc_op) {
case CC_OP_DYNAMIC:
gen_compute_eflags(s);
- /* FALLTHRU */
+ fallthrough;
case CC_OP_EFLAGS:
case CC_OP_ADCX:
case CC_OP_ADOX:
case CC_OP_ADCOX:
return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
.mask = CC_Z };
case CC_OP_CLR:
return (CCPrepare) { .cond = TCG_COND_ALWAYS, .mask = -1 };
case CC_OP_POPCNT:
return (CCPrepare) { .cond = TCG_COND_EQ, .reg = cpu_cc_src,
.mask = -1 };
default:
{
MemOp size = (s->cc_op - CC_OP_ADDB) & 3;
TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, false);
return (CCPrepare) { .cond = TCG_COND_EQ, .reg = t0, .mask = -1 };
}
}
}
/* perform a conditional store into register 'reg' according to jump opcode
value 'b'. In the fast case, T0 is guaranteed not to be used. */
@@ -3079,3751 +3079,3750 @@ static void gen_cmpxchg16b(DisasContext *s, CPUX86State *env, int modrm)
/* convert one instruction. s->base.is_jmp is set if the translation must
be stopped. Return the next pc value */
static bool disas_insn(DisasContext *s, CPUState *cpu)
{
CPUX86State *env = cpu_env(cpu);
int b, prefixes;
int shift;
MemOp ot, aflag, dflag;
int modrm, reg, rm, mod, op, opreg, val;
bool orig_cc_op_dirty = s->cc_op_dirty;
CCOp orig_cc_op = s->cc_op;
target_ulong orig_pc_save = s->pc_save;
s->pc = s->base.pc_next;
s->override = -1;
#ifdef TARGET_X86_64
s->rex_r = 0;
s->rex_x = 0;
s->rex_b = 0;
#endif
s->rip_offset = 0; /* for relative ip address */
s->vex_l = 0;
s->vex_v = 0;
s->vex_w = false;
switch (sigsetjmp(s->jmpbuf, 0)) {
case 0:
break;
case 1:
gen_exception_gpf(s);
return true;
case 2:
/* Restore state that may affect the next instruction. */
s->pc = s->base.pc_next;
/*
* TODO: These save/restore can be removed after the table-based
* decoder is complete; we will be decoding the insn completely
* before any code generation that might affect these variables.
*/
s->cc_op_dirty = orig_cc_op_dirty;
s->cc_op = orig_cc_op;
s->pc_save = orig_pc_save;
/* END TODO */
s->base.num_insns--;
tcg_remove_ops_after(s->prev_insn_end);
s->base.is_jmp = DISAS_TOO_MANY;
return false;
default:
g_assert_not_reached();
}
prefixes = 0;
next_byte:
s->prefix = prefixes;
b = x86_ldub_code(env, s);
/* Collect prefixes. */
switch (b) {
default:
break;
case 0x0f:
b = x86_ldub_code(env, s) + 0x100;
break;
case 0xf3:
prefixes |= PREFIX_REPZ;
prefixes &= ~PREFIX_REPNZ;
goto next_byte;
case 0xf2:
prefixes |= PREFIX_REPNZ;
prefixes &= ~PREFIX_REPZ;
goto next_byte;
case 0xf0:
prefixes |= PREFIX_LOCK;
goto next_byte;
case 0x2e:
s->override = R_CS;
goto next_byte;
case 0x36:
s->override = R_SS;
goto next_byte;
case 0x3e:
s->override = R_DS;
goto next_byte;
case 0x26:
s->override = R_ES;
goto next_byte;
case 0x64:
s->override = R_FS;
goto next_byte;
case 0x65:
s->override = R_GS;
goto next_byte;
case 0x66:
prefixes |= PREFIX_DATA;
goto next_byte;
case 0x67:
prefixes |= PREFIX_ADR;
goto next_byte;
#ifdef TARGET_X86_64
case 0x40 ... 0x4f:
if (CODE64(s)) {
/* REX prefix */
prefixes |= PREFIX_REX;
s->vex_w = (b >> 3) & 1;
s->rex_r = (b & 0x4) << 1;
s->rex_x = (b & 0x2) << 2;
s->rex_b = (b & 0x1) << 3;
goto next_byte;
}
break;
#endif
case 0xc5: /* 2-byte VEX */
case 0xc4: /* 3-byte VEX */
if (CODE32(s) && !VM86(s)) {
int vex2 = x86_ldub_code(env, s);
s->pc--; /* rewind the advance_pc() x86_ldub_code() did */
if (!CODE64(s) && (vex2 & 0xc0) != 0xc0) {
/* 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b,
otherwise the instruction is LES or LDS. */
break;
}
disas_insn_new(s, cpu, b);
return s->pc;
}
break;
}
/* Post-process prefixes. */
if (CODE64(s)) {
/* In 64-bit mode, the default data size is 32-bit. Select 64-bit
data with rex_w, and 16-bit data with 0x66; rex_w takes precedence
over 0x66 if both are present. */
dflag = (REX_W(s) ? MO_64 : prefixes & PREFIX_DATA ? MO_16 : MO_32);
/* In 64-bit mode, 0x67 selects 32-bit addressing. */
aflag = (prefixes & PREFIX_ADR ? MO_32 : MO_64);
} else {
/* In 16/32-bit mode, 0x66 selects the opposite data size. */
if (CODE32(s) ^ ((prefixes & PREFIX_DATA) != 0)) {
dflag = MO_32;
} else {
dflag = MO_16;
}
/* In 16/32-bit mode, 0x67 selects the opposite addressing. */
if (CODE32(s) ^ ((prefixes & PREFIX_ADR) != 0)) {
aflag = MO_32;
} else {
aflag = MO_16;
}
}
s->prefix = prefixes;
s->aflag = aflag;
s->dflag = dflag;
/* now check op code */
switch (b) {
/**************************/
/* arith & logic */
case 0x00 ... 0x05:
case 0x08 ... 0x0d:
case 0x10 ... 0x15:
case 0x18 ... 0x1d:
case 0x20 ... 0x25:
case 0x28 ... 0x2d:
case 0x30 ... 0x35:
case 0x38 ... 0x3d:
{
int f;
op = (b >> 3) & 7;
f = (b >> 1) & 3;
ot = mo_b_d(b, dflag);
switch(f) {
case 0: /* OP Ev, Gv */
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
opreg = OR_TMP0;
} else if (op == OP_XORL && rm == reg) {
xor_zero:
/* xor reg, reg optimisation */
set_cc_op(s, CC_OP_CLR);
tcg_gen_movi_tl(s->T0, 0);
gen_op_mov_reg_v(s, ot, reg, s->T0);
break;
} else {
opreg = rm;
}
gen_op_mov_v_reg(s, ot, s->T1, reg);
gen_op(s, op, ot, opreg);
break;
case 1: /* OP Gv, Ev */
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
reg = ((modrm >> 3) & 7) | REX_R(s);
rm = (modrm & 7) | REX_B(s);
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, s->T1, s->A0);
} else if (op == OP_XORL && rm == reg) {
goto xor_zero;
} else {
gen_op_mov_v_reg(s, ot, s->T1, rm);
}
gen_op(s, op, ot, reg);
break;
case 2: /* OP A, Iv */
val = insn_get(env, s, ot);
tcg_gen_movi_tl(s->T1, val);
gen_op(s, op, ot, OR_EAX);
break;
}
}
break;
case 0x82:
if (CODE64(s))
goto illegal_op;
- /* fall through */
fallthrough;
case 0x80: /* GRP1 */
case 0x81:
case 0x83:
{
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
op = (modrm >> 3) & 7;
if (mod != 3) {
if (b == 0x83)
s->rip_offset = 1;
else
s->rip_offset = insn_const_size(ot);
gen_lea_modrm(env, s, modrm);
opreg = OR_TMP0;
} else {
opreg = rm;
}
switch(b) {
default:
case 0x80:
case 0x81:
case 0x82:
val = insn_get(env, s, ot);
break;
case 0x83:
val = (int8_t)insn_get(env, s, MO_8);
break;
}
tcg_gen_movi_tl(s->T1, val);
gen_op(s, op, ot, opreg);
}
break;
/**************************/
/* inc, dec, and other misc arith */
case 0x40 ... 0x47: /* inc Gv */
ot = dflag;
gen_inc(s, ot, OR_EAX + (b & 7), 1);
break;
case 0x48 ... 0x4f: /* dec Gv */
ot = dflag;
gen_inc(s, ot, OR_EAX + (b & 7), -1);
break;
case 0xf6: /* GRP3 */
case 0xf7:
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
op = (modrm >> 3) & 7;
if (mod != 3) {
if (op == 0) {
s->rip_offset = insn_const_size(ot);
}
gen_lea_modrm(env, s, modrm);
/* For those below that handle locked memory, don't load here. */
if (!(s->prefix & PREFIX_LOCK)
|| op != 2) {
gen_op_ld_v(s, ot, s->T0, s->A0);
}
} else {
gen_op_mov_v_reg(s, ot, s->T0, rm);
}
switch(op) {
case 0: /* test */
val = insn_get(env, s, ot);
tcg_gen_movi_tl(s->T1, val);
gen_op_testl_T0_T1_cc(s);
set_cc_op(s, CC_OP_LOGICB + ot);
break;
case 2: /* not */
if (s->prefix & PREFIX_LOCK) {
if (mod == 3) {
goto illegal_op;
}
tcg_gen_movi_tl(s->T0, ~0);
tcg_gen_atomic_xor_fetch_tl(s->T0, s->A0, s->T0,
s->mem_index, ot | MO_LE);
} else {
tcg_gen_not_tl(s->T0, s->T0);
if (mod != 3) {
gen_op_st_v(s, ot, s->T0, s->A0);
} else {
gen_op_mov_reg_v(s, ot, rm, s->T0);
}
}
break;
case 3: /* neg */
if (s->prefix & PREFIX_LOCK) {
TCGLabel *label1;
TCGv a0, t0, t1, t2;
if (mod == 3) {
goto illegal_op;
}
a0 = s->A0;
t0 = s->T0;
label1 = gen_new_label();
gen_set_label(label1);
t1 = tcg_temp_new();
t2 = tcg_temp_new();
tcg_gen_mov_tl(t2, t0);
tcg_gen_neg_tl(t1, t0);
tcg_gen_atomic_cmpxchg_tl(t0, a0, t0, t1,
s->mem_index, ot | MO_LE);
tcg_gen_brcond_tl(TCG_COND_NE, t0, t2, label1);
tcg_gen_neg_tl(s->T0, t0);
} else {
tcg_gen_neg_tl(s->T0, s->T0);
if (mod != 3) {
gen_op_st_v(s, ot, s->T0, s->A0);
} else {
gen_op_mov_reg_v(s, ot, rm, s->T0);
}
}
gen_op_update_neg_cc(s);
set_cc_op(s, CC_OP_SUBB + ot);
break;
case 4: /* mul */
switch(ot) {
case MO_8:
gen_op_mov_v_reg(s, MO_8, s->T1, R_EAX);
tcg_gen_ext8u_tl(s->T0, s->T0);
tcg_gen_ext8u_tl(s->T1, s->T1);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(s->T0, s->T0, s->T1);
gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);
tcg_gen_mov_tl(cpu_cc_dst, s->T0);
tcg_gen_andi_tl(cpu_cc_src, s->T0, 0xff00);
set_cc_op(s, CC_OP_MULB);
break;
case MO_16:
gen_op_mov_v_reg(s, MO_16, s->T1, R_EAX);
tcg_gen_ext16u_tl(s->T0, s->T0);
tcg_gen_ext16u_tl(s->T1, s->T1);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(s->T0, s->T0, s->T1);
gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);
tcg_gen_mov_tl(cpu_cc_dst, s->T0);
tcg_gen_shri_tl(s->T0, s->T0, 16);
gen_op_mov_reg_v(s, MO_16, R_EDX, s->T0);
tcg_gen_mov_tl(cpu_cc_src, s->T0);
set_cc_op(s, CC_OP_MULW);
break;
default:
case MO_32:
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
tcg_gen_trunc_tl_i32(s->tmp3_i32, cpu_regs[R_EAX]);
tcg_gen_mulu2_i32(s->tmp2_i32, s->tmp3_i32,
s->tmp2_i32, s->tmp3_i32);
tcg_gen_extu_i32_tl(cpu_regs[R_EAX], s->tmp2_i32);
tcg_gen_extu_i32_tl(cpu_regs[R_EDX], s->tmp3_i32);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
tcg_gen_mov_tl(cpu_cc_src, cpu_regs[R_EDX]);
set_cc_op(s, CC_OP_MULL);
break;
#ifdef TARGET_X86_64
case MO_64:
tcg_gen_mulu2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX],
s->T0, cpu_regs[R_EAX]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
tcg_gen_mov_tl(cpu_cc_src, cpu_regs[R_EDX]);
set_cc_op(s, CC_OP_MULQ);
break;
#endif
}
break;
case 5: /* imul */
switch(ot) {
case MO_8:
gen_op_mov_v_reg(s, MO_8, s->T1, R_EAX);
tcg_gen_ext8s_tl(s->T0, s->T0);
tcg_gen_ext8s_tl(s->T1, s->T1);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(s->T0, s->T0, s->T1);
gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);
tcg_gen_mov_tl(cpu_cc_dst, s->T0);
tcg_gen_ext8s_tl(s->tmp0, s->T0);
tcg_gen_sub_tl(cpu_cc_src, s->T0, s->tmp0);
set_cc_op(s, CC_OP_MULB);
break;
case MO_16:
gen_op_mov_v_reg(s, MO_16, s->T1, R_EAX);
tcg_gen_ext16s_tl(s->T0, s->T0);
tcg_gen_ext16s_tl(s->T1, s->T1);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(s->T0, s->T0, s->T1);
gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);
tcg_gen_mov_tl(cpu_cc_dst, s->T0);
tcg_gen_ext16s_tl(s->tmp0, s->T0);
tcg_gen_sub_tl(cpu_cc_src, s->T0, s->tmp0);
tcg_gen_shri_tl(s->T0, s->T0, 16);
gen_op_mov_reg_v(s, MO_16, R_EDX, s->T0);
set_cc_op(s, CC_OP_MULW);
break;
default:
case MO_32:
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
tcg_gen_trunc_tl_i32(s->tmp3_i32, cpu_regs[R_EAX]);
tcg_gen_muls2_i32(s->tmp2_i32, s->tmp3_i32,
s->tmp2_i32, s->tmp3_i32);
tcg_gen_extu_i32_tl(cpu_regs[R_EAX], s->tmp2_i32);
tcg_gen_extu_i32_tl(cpu_regs[R_EDX], s->tmp3_i32);
tcg_gen_sari_i32(s->tmp2_i32, s->tmp2_i32, 31);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
tcg_gen_sub_i32(s->tmp2_i32, s->tmp2_i32, s->tmp3_i32);
tcg_gen_extu_i32_tl(cpu_cc_src, s->tmp2_i32);
set_cc_op(s, CC_OP_MULL);
break;
#ifdef TARGET_X86_64
case MO_64:
tcg_gen_muls2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX],
s->T0, cpu_regs[R_EAX]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
tcg_gen_sari_tl(cpu_cc_src, cpu_regs[R_EAX], 63);
tcg_gen_sub_tl(cpu_cc_src, cpu_cc_src, cpu_regs[R_EDX]);
set_cc_op(s, CC_OP_MULQ);
break;
#endif
}
break;
case 6: /* div */
switch(ot) {
case MO_8:
gen_helper_divb_AL(tcg_env, s->T0);
break;
case MO_16:
gen_helper_divw_AX(tcg_env, s->T0);
break;
default:
case MO_32:
gen_helper_divl_EAX(tcg_env, s->T0);
break;
#ifdef TARGET_X86_64
case MO_64:
gen_helper_divq_EAX(tcg_env, s->T0);
break;
#endif
}
break;
case 7: /* idiv */
switch(ot) {
case MO_8:
gen_helper_idivb_AL(tcg_env, s->T0);
break;
case MO_16:
gen_helper_idivw_AX(tcg_env, s->T0);
break;
default:
case MO_32:
gen_helper_idivl_EAX(tcg_env, s->T0);
break;
#ifdef TARGET_X86_64
case MO_64:
gen_helper_idivq_EAX(tcg_env, s->T0);
break;
#endif
}
break;
default:
goto unknown_op;
}
break;
case 0xfe: /* GRP4 */
case 0xff: /* GRP5 */
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
op = (modrm >> 3) & 7;
if (op >= 2 && b == 0xfe) {
goto unknown_op;
}
if (CODE64(s)) {
if (op == 2 || op == 4) {
/* operand size for jumps is 64 bit */
ot = MO_64;
} else if (op == 3 || op == 5) {
ot = dflag != MO_16 ? MO_32 + REX_W(s) : MO_16;
} else if (op == 6) {
/* default push size is 64 bit */
ot = mo_pushpop(s, dflag);
}
}
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
if (op >= 2 && op != 3 && op != 5)
gen_op_ld_v(s, ot, s->T0, s->A0);
} else {
gen_op_mov_v_reg(s, ot, s->T0, rm);
}
switch(op) {
case 0: /* inc Ev */
if (mod != 3)
opreg = OR_TMP0;
else
opreg = rm;
gen_inc(s, ot, opreg, 1);
break;
case 1: /* dec Ev */
if (mod != 3)
opreg = OR_TMP0;
else
opreg = rm;
gen_inc(s, ot, opreg, -1);
break;
case 2: /* call Ev */
/* XXX: optimize if memory (no 'and' is necessary) */
if (dflag == MO_16) {
tcg_gen_ext16u_tl(s->T0, s->T0);
}
gen_push_v(s, eip_next_tl(s));
gen_op_jmp_v(s, s->T0);
gen_bnd_jmp(s);
s->base.is_jmp = DISAS_JUMP;
break;
case 3: /* lcall Ev */
if (mod == 3) {
goto illegal_op;
}
gen_op_ld_v(s, ot, s->T1, s->A0);
gen_add_A0_im(s, 1 << ot);
gen_op_ld_v(s, MO_16, s->T0, s->A0);
do_lcall:
if (PE(s) && !VM86(s)) {
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
gen_helper_lcall_protected(tcg_env, s->tmp2_i32, s->T1,
tcg_constant_i32(dflag - 1),
eip_next_tl(s));
} else {
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);
gen_helper_lcall_real(tcg_env, s->tmp2_i32, s->tmp3_i32,
tcg_constant_i32(dflag - 1),
eip_next_i32(s));
}
s->base.is_jmp = DISAS_JUMP;
break;
case 4: /* jmp Ev */
if (dflag == MO_16) {
tcg_gen_ext16u_tl(s->T0, s->T0);
}
gen_op_jmp_v(s, s->T0);
gen_bnd_jmp(s);
s->base.is_jmp = DISAS_JUMP;
break;
case 5: /* ljmp Ev */
if (mod == 3) {
goto illegal_op;
}
gen_op_ld_v(s, ot, s->T1, s->A0);
gen_add_A0_im(s, 1 << ot);
gen_op_ld_v(s, MO_16, s->T0, s->A0);
do_ljmp:
if (PE(s) && !VM86(s)) {
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
gen_helper_ljmp_protected(tcg_env, s->tmp2_i32, s->T1,
eip_next_tl(s));
} else {
gen_op_movl_seg_T0_vm(s, R_CS);
gen_op_jmp_v(s, s->T1);
}
s->base.is_jmp = DISAS_JUMP;
break;
case 6: /* push Ev */
gen_push_v(s, s->T0);
break;
default:
goto unknown_op;
}
break;
case 0x84: /* test Ev, Gv */
case 0x85:
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_op_mov_v_reg(s, ot, s->T1, reg);
gen_op_testl_T0_T1_cc(s);
set_cc_op(s, CC_OP_LOGICB + ot);
break;
case 0xa8: /* test eAX, Iv */
case 0xa9:
ot = mo_b_d(b, dflag);
val = insn_get(env, s, ot);
gen_op_mov_v_reg(s, ot, s->T0, OR_EAX);
tcg_gen_movi_tl(s->T1, val);
gen_op_testl_T0_T1_cc(s);
set_cc_op(s, CC_OP_LOGICB + ot);
break;
case 0x98: /* CWDE/CBW */
switch (dflag) {
#ifdef TARGET_X86_64
case MO_64:
gen_op_mov_v_reg(s, MO_32, s->T0, R_EAX);
tcg_gen_ext32s_tl(s->T0, s->T0);
gen_op_mov_reg_v(s, MO_64, R_EAX, s->T0);
break;
#endif
case MO_32:
gen_op_mov_v_reg(s, MO_16, s->T0, R_EAX);
tcg_gen_ext16s_tl(s->T0, s->T0);
gen_op_mov_reg_v(s, MO_32, R_EAX, s->T0);
break;
case MO_16:
gen_op_mov_v_reg(s, MO_8, s->T0, R_EAX);
tcg_gen_ext8s_tl(s->T0, s->T0);
gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);
break;
default:
g_assert_not_reached();
}
break;
case 0x99: /* CDQ/CWD */
switch (dflag) {
#ifdef TARGET_X86_64
case MO_64:
gen_op_mov_v_reg(s, MO_64, s->T0, R_EAX);
tcg_gen_sari_tl(s->T0, s->T0, 63);
gen_op_mov_reg_v(s, MO_64, R_EDX, s->T0);
break;
#endif
case MO_32:
gen_op_mov_v_reg(s, MO_32, s->T0, R_EAX);
tcg_gen_ext32s_tl(s->T0, s->T0);
tcg_gen_sari_tl(s->T0, s->T0, 31);
gen_op_mov_reg_v(s, MO_32, R_EDX, s->T0);
break;
case MO_16:
gen_op_mov_v_reg(s, MO_16, s->T0, R_EAX);
tcg_gen_ext16s_tl(s->T0, s->T0);
tcg_gen_sari_tl(s->T0, s->T0, 15);
gen_op_mov_reg_v(s, MO_16, R_EDX, s->T0);
break;
default:
g_assert_not_reached();
}
break;
case 0x1af: /* imul Gv, Ev */
case 0x69: /* imul Gv, Ev, I */
case 0x6b:
ot = dflag;
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
if (b == 0x69)
s->rip_offset = insn_const_size(ot);
else if (b == 0x6b)
s->rip_offset = 1;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
if (b == 0x69) {
val = insn_get(env, s, ot);
tcg_gen_movi_tl(s->T1, val);
} else if (b == 0x6b) {
val = (int8_t)insn_get(env, s, MO_8);
tcg_gen_movi_tl(s->T1, val);
} else {
gen_op_mov_v_reg(s, ot, s->T1, reg);
}
switch (ot) {
#ifdef TARGET_X86_64
case MO_64:
tcg_gen_muls2_i64(cpu_regs[reg], s->T1, s->T0, s->T1);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[reg]);
tcg_gen_sari_tl(cpu_cc_src, cpu_cc_dst, 63);
tcg_gen_sub_tl(cpu_cc_src, cpu_cc_src, s->T1);
break;
#endif
case MO_32:
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);
tcg_gen_muls2_i32(s->tmp2_i32, s->tmp3_i32,
s->tmp2_i32, s->tmp3_i32);
tcg_gen_extu_i32_tl(cpu_regs[reg], s->tmp2_i32);
tcg_gen_sari_i32(s->tmp2_i32, s->tmp2_i32, 31);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[reg]);
tcg_gen_sub_i32(s->tmp2_i32, s->tmp2_i32, s->tmp3_i32);
tcg_gen_extu_i32_tl(cpu_cc_src, s->tmp2_i32);
break;
default:
tcg_gen_ext16s_tl(s->T0, s->T0);
tcg_gen_ext16s_tl(s->T1, s->T1);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(s->T0, s->T0, s->T1);
tcg_gen_mov_tl(cpu_cc_dst, s->T0);
tcg_gen_ext16s_tl(s->tmp0, s->T0);
tcg_gen_sub_tl(cpu_cc_src, s->T0, s->tmp0);
gen_op_mov_reg_v(s, ot, reg, s->T0);
break;
}
set_cc_op(s, CC_OP_MULB + ot);
break;
case 0x1c0:
case 0x1c1: /* xadd Ev, Gv */
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
mod = (modrm >> 6) & 3;
gen_op_mov_v_reg(s, ot, s->T0, reg);
if (mod == 3) {
rm = (modrm & 7) | REX_B(s);
gen_op_mov_v_reg(s, ot, s->T1, rm);
tcg_gen_add_tl(s->T0, s->T0, s->T1);
gen_op_mov_reg_v(s, ot, reg, s->T1);
gen_op_mov_reg_v(s, ot, rm, s->T0);
} else {
gen_lea_modrm(env, s, modrm);
if (s->prefix & PREFIX_LOCK) {
tcg_gen_atomic_fetch_add_tl(s->T1, s->A0, s->T0,
s->mem_index, ot | MO_LE);
tcg_gen_add_tl(s->T0, s->T0, s->T1);
} else {
gen_op_ld_v(s, ot, s->T1, s->A0);
tcg_gen_add_tl(s->T0, s->T0, s->T1);
gen_op_st_v(s, ot, s->T0, s->A0);
}
gen_op_mov_reg_v(s, ot, reg, s->T1);
}
gen_op_update2_cc(s);
set_cc_op(s, CC_OP_ADDB + ot);
break;
case 0x1b0:
case 0x1b1: /* cmpxchg Ev, Gv */
{
TCGv oldv, newv, cmpv, dest;
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
mod = (modrm >> 6) & 3;
oldv = tcg_temp_new();
newv = tcg_temp_new();
cmpv = tcg_temp_new();
gen_op_mov_v_reg(s, ot, newv, reg);
tcg_gen_mov_tl(cmpv, cpu_regs[R_EAX]);
gen_extu(ot, cmpv);
if (s->prefix & PREFIX_LOCK) {
if (mod == 3) {
goto illegal_op;
}
gen_lea_modrm(env, s, modrm);
tcg_gen_atomic_cmpxchg_tl(oldv, s->A0, cmpv, newv,
s->mem_index, ot | MO_LE);
} else {
if (mod == 3) {
rm = (modrm & 7) | REX_B(s);
gen_op_mov_v_reg(s, ot, oldv, rm);
gen_extu(ot, oldv);
/*
* Unlike the memory case, where "the destination operand receives
* a write cycle without regard to the result of the comparison",
* rm must not be touched altogether if the write fails, including
* not zero-extending it on 64-bit processors. So, precompute
* the result of a successful writeback and perform the movcond
* directly on cpu_regs. Also need to write accumulator first, in
* case rm is part of RAX too.
*/
dest = gen_op_deposit_reg_v(s, ot, rm, newv, newv);
tcg_gen_movcond_tl(TCG_COND_EQ, dest, oldv, cmpv, newv, dest);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, oldv, s->A0);
/*
* Perform an unconditional store cycle like physical cpu;
* must be before changing accumulator to ensure
* idempotency if the store faults and the instruction
* is restarted
*/
tcg_gen_movcond_tl(TCG_COND_EQ, newv, oldv, cmpv, newv, oldv);
gen_op_st_v(s, ot, newv, s->A0);
}
}
/*
* Write EAX only if the cmpxchg fails; reuse newv as the destination,
* since it's dead here.
*/
dest = gen_op_deposit_reg_v(s, ot, R_EAX, newv, oldv);
tcg_gen_movcond_tl(TCG_COND_EQ, dest, oldv, cmpv, dest, newv);
tcg_gen_mov_tl(cpu_cc_src, oldv);
tcg_gen_mov_tl(s->cc_srcT, cmpv);
tcg_gen_sub_tl(cpu_cc_dst, cmpv, oldv);
set_cc_op(s, CC_OP_SUBB + ot);
}
break;
case 0x1c7: /* cmpxchg8b */
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
switch ((modrm >> 3) & 7) {
case 1: /* CMPXCHG8, CMPXCHG16 */
if (mod == 3) {
goto illegal_op;
}
#ifdef TARGET_X86_64
if (dflag == MO_64) {
if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) {
goto illegal_op;
}
gen_cmpxchg16b(s, env, modrm);
break;
}
#endif
if (!(s->cpuid_features & CPUID_CX8)) {
goto illegal_op;
}
gen_cmpxchg8b(s, env, modrm);
break;
case 7: /* RDSEED, RDPID with f3 prefix */
if (mod != 3 ||
(s->prefix & (PREFIX_LOCK | PREFIX_REPNZ))) {
goto illegal_op;
}
if (s->prefix & PREFIX_REPZ) {
if (!(s->cpuid_ext_features & CPUID_7_0_ECX_RDPID)) {
goto illegal_op;
}
gen_helper_rdpid(s->T0, tcg_env);
rm = (modrm & 7) | REX_B(s);
gen_op_mov_reg_v(s, dflag, rm, s->T0);
break;
} else {
if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_RDSEED)) {
goto illegal_op;
}
goto do_rdrand;
}
case 6: /* RDRAND */
if (mod != 3 ||
(s->prefix & (PREFIX_LOCK | PREFIX_REPZ | PREFIX_REPNZ)) ||
!(s->cpuid_ext_features & CPUID_EXT_RDRAND)) {
goto illegal_op;
}
do_rdrand:
translator_io_start(&s->base);
gen_helper_rdrand(s->T0, tcg_env);
rm = (modrm & 7) | REX_B(s);
gen_op_mov_reg_v(s, dflag, rm, s->T0);
set_cc_op(s, CC_OP_EFLAGS);
break;
default:
goto illegal_op;
}
break;
/**************************/
/* push/pop */
case 0x50 ... 0x57: /* push */
gen_op_mov_v_reg(s, MO_32, s->T0, (b & 7) | REX_B(s));
gen_push_v(s, s->T0);
break;
case 0x58 ... 0x5f: /* pop */
ot = gen_pop_T0(s);
/* NOTE: order is important for pop %sp */
gen_pop_update(s, ot);
gen_op_mov_reg_v(s, ot, (b & 7) | REX_B(s), s->T0);
break;
case 0x60: /* pusha */
if (CODE64(s))
goto illegal_op;
gen_pusha(s);
break;
case 0x61: /* popa */
if (CODE64(s))
goto illegal_op;
gen_popa(s);
break;
case 0x68: /* push Iv */
case 0x6a:
ot = mo_pushpop(s, dflag);
if (b == 0x68)
val = insn_get(env, s, ot);
else
val = (int8_t)insn_get(env, s, MO_8);
tcg_gen_movi_tl(s->T0, val);
gen_push_v(s, s->T0);
break;
case 0x8f: /* pop Ev */
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
ot = gen_pop_T0(s);
if (mod == 3) {
/* NOTE: order is important for pop %sp */
gen_pop_update(s, ot);
rm = (modrm & 7) | REX_B(s);
gen_op_mov_reg_v(s, ot, rm, s->T0);
} else {
/* NOTE: order is important too for MMU exceptions */
s->popl_esp_hack = 1 << ot;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
s->popl_esp_hack = 0;
gen_pop_update(s, ot);
}
break;
case 0xc8: /* enter */
{
int level;
val = x86_lduw_code(env, s);
level = x86_ldub_code(env, s);
gen_enter(s, val, level);
}
break;
case 0xc9: /* leave */
gen_leave(s);
break;
case 0x06: /* push es */
case 0x0e: /* push cs */
case 0x16: /* push ss */
case 0x1e: /* push ds */
if (CODE64(s))
goto illegal_op;
gen_op_movl_T0_seg(s, b >> 3);
gen_push_v(s, s->T0);
break;
case 0x1a0: /* push fs */
case 0x1a8: /* push gs */
gen_op_movl_T0_seg(s, (b >> 3) & 7);
gen_push_v(s, s->T0);
break;
case 0x07: /* pop es */
case 0x17: /* pop ss */
case 0x1f: /* pop ds */
if (CODE64(s))
goto illegal_op;
reg = b >> 3;
ot = gen_pop_T0(s);
gen_movl_seg_T0(s, reg);
gen_pop_update(s, ot);
break;
case 0x1a1: /* pop fs */
case 0x1a9: /* pop gs */
ot = gen_pop_T0(s);
gen_movl_seg_T0(s, (b >> 3) & 7);
gen_pop_update(s, ot);
break;
/**************************/
/* mov */
case 0x88:
case 0x89: /* mov Gv, Ev */
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
/* generate a generic store */
gen_ldst_modrm(env, s, modrm, ot, reg, 1);
break;
case 0xc6:
case 0xc7: /* mov Ev, Iv */
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
if (mod != 3) {
s->rip_offset = insn_const_size(ot);
gen_lea_modrm(env, s, modrm);
}
val = insn_get(env, s, ot);
tcg_gen_movi_tl(s->T0, val);
if (mod != 3) {
gen_op_st_v(s, ot, s->T0, s->A0);
} else {
gen_op_mov_reg_v(s, ot, (modrm & 7) | REX_B(s), s->T0);
}
break;
case 0x8a:
case 0x8b: /* mov Ev, Gv */
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_op_mov_reg_v(s, ot, reg, s->T0);
break;
case 0x8e: /* mov seg, Gv */
modrm = x86_ldub_code(env, s);
reg = (modrm >> 3) & 7;
if (reg >= 6 || reg == R_CS)
goto illegal_op;
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
gen_movl_seg_T0(s, reg);
break;
case 0x8c: /* mov Gv, seg */
modrm = x86_ldub_code(env, s);
reg = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
if (reg >= 6)
goto illegal_op;
gen_op_movl_T0_seg(s, reg);
ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
case 0x1b6: /* movzbS Gv, Eb */
case 0x1b7: /* movzwS Gv, Eb */
case 0x1be: /* movsbS Gv, Eb */
case 0x1bf: /* movswS Gv, Eb */
{
MemOp d_ot;
MemOp s_ot;
/* d_ot is the size of destination */
d_ot = dflag;
/* ot is the size of source */
ot = (b & 1) + MO_8;
/* s_ot is the sign+size of source */
s_ot = b & 8 ? MO_SIGN | ot : ot;
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
if (mod == 3) {
if (s_ot == MO_SB && byte_reg_is_xH(s, rm)) {
tcg_gen_sextract_tl(s->T0, cpu_regs[rm - 4], 8, 8);
} else {
gen_op_mov_v_reg(s, ot, s->T0, rm);
switch (s_ot) {
case MO_UB:
tcg_gen_ext8u_tl(s->T0, s->T0);
break;
case MO_SB:
tcg_gen_ext8s_tl(s->T0, s->T0);
break;
case MO_UW:
tcg_gen_ext16u_tl(s->T0, s->T0);
break;
default:
case MO_SW:
tcg_gen_ext16s_tl(s->T0, s->T0);
break;
}
}
gen_op_mov_reg_v(s, d_ot, reg, s->T0);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, s_ot, s->T0, s->A0);
gen_op_mov_reg_v(s, d_ot, reg, s->T0);
}
}
break;
case 0x8d: /* lea */
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
if (mod == 3)
goto illegal_op;
reg = ((modrm >> 3) & 7) | REX_R(s);
{
AddressParts a = gen_lea_modrm_0(env, s, modrm);
TCGv ea = gen_lea_modrm_1(s, a, false);
gen_lea_v_seg(s, s->aflag, ea, -1, -1);
gen_op_mov_reg_v(s, dflag, reg, s->A0);
}
break;
case 0xa0: /* mov EAX, Ov */
case 0xa1:
case 0xa2: /* mov Ov, EAX */
case 0xa3:
{
target_ulong offset_addr;
ot = mo_b_d(b, dflag);
offset_addr = insn_get_addr(env, s, s->aflag);
tcg_gen_movi_tl(s->A0, offset_addr);
gen_add_A0_ds_seg(s);
if ((b & 2) == 0) {
gen_op_ld_v(s, ot, s->T0, s->A0);
gen_op_mov_reg_v(s, ot, R_EAX, s->T0);
} else {
gen_op_mov_v_reg(s, ot, s->T0, R_EAX);
gen_op_st_v(s, ot, s->T0, s->A0);
}
}
break;
case 0xd7: /* xlat */
tcg_gen_mov_tl(s->A0, cpu_regs[R_EBX]);
tcg_gen_ext8u_tl(s->T0, cpu_regs[R_EAX]);
tcg_gen_add_tl(s->A0, s->A0, s->T0);
gen_extu(s->aflag, s->A0);
gen_add_A0_ds_seg(s);
gen_op_ld_v(s, MO_8, s->T0, s->A0);
gen_op_mov_reg_v(s, MO_8, R_EAX, s->T0);
break;
case 0xb0 ... 0xb7: /* mov R, Ib */
val = insn_get(env, s, MO_8);
tcg_gen_movi_tl(s->T0, val);
gen_op_mov_reg_v(s, MO_8, (b & 7) | REX_B(s), s->T0);
break;
case 0xb8 ... 0xbf: /* mov R, Iv */
#ifdef TARGET_X86_64
if (dflag == MO_64) {
uint64_t tmp;
/* 64 bit case */
tmp = x86_ldq_code(env, s);
reg = (b & 7) | REX_B(s);
tcg_gen_movi_tl(s->T0, tmp);
gen_op_mov_reg_v(s, MO_64, reg, s->T0);
} else
#endif
{
ot = dflag;
val = insn_get(env, s, ot);
reg = (b & 7) | REX_B(s);
tcg_gen_movi_tl(s->T0, val);
gen_op_mov_reg_v(s, ot, reg, s->T0);
}
break;
case 0x91 ... 0x97: /* xchg R, EAX */
do_xchg_reg_eax:
ot = dflag;
reg = (b & 7) | REX_B(s);
rm = R_EAX;
goto do_xchg_reg;
case 0x86:
case 0x87: /* xchg Ev, Gv */
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
mod = (modrm >> 6) & 3;
if (mod == 3) {
rm = (modrm & 7) | REX_B(s);
do_xchg_reg:
gen_op_mov_v_reg(s, ot, s->T0, reg);
gen_op_mov_v_reg(s, ot, s->T1, rm);
gen_op_mov_reg_v(s, ot, rm, s->T0);
gen_op_mov_reg_v(s, ot, reg, s->T1);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_mov_v_reg(s, ot, s->T0, reg);
/* for xchg, lock is implicit */
tcg_gen_atomic_xchg_tl(s->T1, s->A0, s->T0,
s->mem_index, ot | MO_LE);
gen_op_mov_reg_v(s, ot, reg, s->T1);
}
break;
case 0xc4: /* les Gv */
/* In CODE64 this is VEX3; see above. */
op = R_ES;
goto do_lxx;
case 0xc5: /* lds Gv */
/* In CODE64 this is VEX2; see above. */
op = R_DS;
goto do_lxx;
case 0x1b2: /* lss Gv */
op = R_SS;
goto do_lxx;
case 0x1b4: /* lfs Gv */
op = R_FS;
goto do_lxx;
case 0x1b5: /* lgs Gv */
op = R_GS;
do_lxx:
ot = dflag != MO_16 ? MO_32 : MO_16;
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
mod = (modrm >> 6) & 3;
if (mod == 3)
goto illegal_op;
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, s->T1, s->A0);
gen_add_A0_im(s, 1 << ot);
/* load the segment first to handle exceptions properly */
gen_op_ld_v(s, MO_16, s->T0, s->A0);
gen_movl_seg_T0(s, op);
/* then put the data */
gen_op_mov_reg_v(s, ot, reg, s->T1);
break;
/************************/
/* shifts */
case 0xc0:
case 0xc1:
/* shift Ev,Ib */
shift = 2;
grp2:
{
ot = mo_b_d(b, dflag);
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
op = (modrm >> 3) & 7;
if (mod != 3) {
if (shift == 2) {
s->rip_offset = 1;
}
gen_lea_modrm(env, s, modrm);
opreg = OR_TMP0;
} else {
opreg = (modrm & 7) | REX_B(s);
}
/* simpler op */
if (shift == 0) {
gen_shift(s, op, ot, opreg, OR_ECX);
} else {
if (shift == 2) {
shift = x86_ldub_code(env, s);
}
gen_shifti(s, op, ot, opreg, shift);
}
}
break;
case 0xd0:
case 0xd1:
/* shift Ev,1 */
shift = 1;
goto grp2;
case 0xd2:
case 0xd3:
/* shift Ev,cl */
shift = 0;
goto grp2;
case 0x1a4: /* shld imm */
op = 0;
shift = 1;
goto do_shiftd;
case 0x1a5: /* shld cl */
op = 0;
shift = 0;
goto do_shiftd;
case 0x1ac: /* shrd imm */
op = 1;
shift = 1;
goto do_shiftd;
case 0x1ad: /* shrd cl */
op = 1;
shift = 0;
do_shiftd:
ot = dflag;
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
reg = ((modrm >> 3) & 7) | REX_R(s);
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
opreg = OR_TMP0;
} else {
opreg = rm;
}
gen_op_mov_v_reg(s, ot, s->T1, reg);
if (shift) {
TCGv imm = tcg_constant_tl(x86_ldub_code(env, s));
gen_shiftd_rm_T1(s, ot, opreg, op, imm);
} else {
gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]);
}
break;
/************************/
/* floats */
case 0xd8 ... 0xdf:
{
bool update_fip = true;
if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
/* if CR0.EM or CR0.TS are set, generate an FPU exception */
/* XXX: what to do if illegal op ? */
gen_exception(s, EXCP07_PREX);
break;
}
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
rm = modrm & 7;
op = ((b & 7) << 3) | ((modrm >> 3) & 7);
if (mod != 3) {
/* memory op */
AddressParts a = gen_lea_modrm_0(env, s, modrm);
TCGv ea = gen_lea_modrm_1(s, a, false);
TCGv last_addr = tcg_temp_new();
bool update_fdp = true;
tcg_gen_mov_tl(last_addr, ea);
gen_lea_v_seg(s, s->aflag, ea, a.def_seg, s->override);
switch (op) {
case 0x00 ... 0x07: /* fxxxs */
case 0x10 ... 0x17: /* fixxxl */
case 0x20 ... 0x27: /* fxxxl */
case 0x30 ... 0x37: /* fixxx */
{
int op1;
op1 = op & 7;
switch (op >> 4) {
case 0:
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
gen_helper_flds_FT0(tcg_env, s->tmp2_i32);
break;
case 1:
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
gen_helper_fildl_FT0(tcg_env, s->tmp2_i32);
break;
case 2:
tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0,
s->mem_index, MO_LEUQ);
gen_helper_fldl_FT0(tcg_env, s->tmp1_i64);
break;
case 3:
default:
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LESW);
gen_helper_fildl_FT0(tcg_env, s->tmp2_i32);
break;
}
gen_helper_fp_arith_ST0_FT0(op1);
if (op1 == 3) {
/* fcomp needs pop */
gen_helper_fpop(tcg_env);
}
}
break;
case 0x08: /* flds */
case 0x0a: /* fsts */
case 0x0b: /* fstps */
case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
switch (op & 7) {
case 0:
switch (op >> 4) {
case 0:
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
gen_helper_flds_ST0(tcg_env, s->tmp2_i32);
break;
case 1:
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
gen_helper_fildl_ST0(tcg_env, s->tmp2_i32);
break;
case 2:
tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0,
s->mem_index, MO_LEUQ);
gen_helper_fldl_ST0(tcg_env, s->tmp1_i64);
break;
case 3:
default:
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LESW);
gen_helper_fildl_ST0(tcg_env, s->tmp2_i32);
break;
}
break;
case 1:
/* XXX: the corresponding CPUID bit must be tested ! */
switch (op >> 4) {
case 1:
gen_helper_fisttl_ST0(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
break;
case 2:
gen_helper_fisttll_ST0(s->tmp1_i64, tcg_env);
tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0,
s->mem_index, MO_LEUQ);
break;
case 3:
default:
gen_helper_fistt_ST0(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUW);
break;
}
gen_helper_fpop(tcg_env);
break;
default:
switch (op >> 4) {
case 0:
gen_helper_fsts_ST0(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
break;
case 1:
gen_helper_fistl_ST0(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
break;
case 2:
gen_helper_fstl_ST0(s->tmp1_i64, tcg_env);
tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0,
s->mem_index, MO_LEUQ);
break;
case 3:
default:
gen_helper_fist_ST0(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUW);
break;
}
if ((op & 7) == 3) {
gen_helper_fpop(tcg_env);
}
break;
}
break;
case 0x0c: /* fldenv mem */
gen_helper_fldenv(tcg_env, s->A0,
tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x0d: /* fldcw mem */
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUW);
gen_helper_fldcw(tcg_env, s->tmp2_i32);
update_fip = update_fdp = false;
break;
case 0x0e: /* fnstenv mem */
gen_helper_fstenv(tcg_env, s->A0,
tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x0f: /* fnstcw mem */
gen_helper_fnstcw(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUW);
update_fip = update_fdp = false;
break;
case 0x1d: /* fldt mem */
gen_helper_fldt_ST0(tcg_env, s->A0);
break;
case 0x1f: /* fstpt mem */
gen_helper_fstt_ST0(tcg_env, s->A0);
gen_helper_fpop(tcg_env);
break;
case 0x2c: /* frstor mem */
gen_helper_frstor(tcg_env, s->A0,
tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x2e: /* fnsave mem */
gen_helper_fsave(tcg_env, s->A0,
tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x2f: /* fnstsw mem */
gen_helper_fnstsw(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUW);
update_fip = update_fdp = false;
break;
case 0x3c: /* fbld */
gen_helper_fbld_ST0(tcg_env, s->A0);
break;
case 0x3e: /* fbstp */
gen_helper_fbst_ST0(tcg_env, s->A0);
gen_helper_fpop(tcg_env);
break;
case 0x3d: /* fildll */
tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0,
s->mem_index, MO_LEUQ);
gen_helper_fildll_ST0(tcg_env, s->tmp1_i64);
break;
case 0x3f: /* fistpll */
gen_helper_fistll_ST0(s->tmp1_i64, tcg_env);
tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0,
s->mem_index, MO_LEUQ);
gen_helper_fpop(tcg_env);
break;
default:
goto unknown_op;
}
if (update_fdp) {
int last_seg = s->override >= 0 ? s->override : a.def_seg;
tcg_gen_ld_i32(s->tmp2_i32, tcg_env,
offsetof(CPUX86State,
segs[last_seg].selector));
tcg_gen_st16_i32(s->tmp2_i32, tcg_env,
offsetof(CPUX86State, fpds));
tcg_gen_st_tl(last_addr, tcg_env,
offsetof(CPUX86State, fpdp));
}
} else {
/* register float ops */
opreg = rm;
switch (op) {
case 0x08: /* fld sti */
gen_helper_fpush(tcg_env);
gen_helper_fmov_ST0_STN(tcg_env,
tcg_constant_i32((opreg + 1) & 7));
break;
case 0x09: /* fxchg sti */
case 0x29: /* fxchg4 sti, undocumented op */
case 0x39: /* fxchg7 sti, undocumented op */
gen_helper_fxchg_ST0_STN(tcg_env, tcg_constant_i32(opreg));
break;
case 0x0a: /* grp d9/2 */
switch (rm) {
case 0: /* fnop */
/*
* check exceptions (FreeBSD FPU probe)
* needs to be treated as I/O because of ferr_irq
*/
translator_io_start(&s->base);
gen_helper_fwait(tcg_env);
update_fip = false;
break;
default:
goto unknown_op;
}
break;
case 0x0c: /* grp d9/4 */
switch (rm) {
case 0: /* fchs */
gen_helper_fchs_ST0(tcg_env);
break;
case 1: /* fabs */
gen_helper_fabs_ST0(tcg_env);
break;
case 4: /* ftst */
gen_helper_fldz_FT0(tcg_env);
gen_helper_fcom_ST0_FT0(tcg_env);
break;
case 5: /* fxam */
gen_helper_fxam_ST0(tcg_env);
break;
default:
goto unknown_op;
}
break;
case 0x0d: /* grp d9/5 */
{
switch (rm) {
case 0:
gen_helper_fpush(tcg_env);
gen_helper_fld1_ST0(tcg_env);
break;
case 1:
gen_helper_fpush(tcg_env);
gen_helper_fldl2t_ST0(tcg_env);
break;
case 2:
gen_helper_fpush(tcg_env);
gen_helper_fldl2e_ST0(tcg_env);
break;
case 3:
gen_helper_fpush(tcg_env);
gen_helper_fldpi_ST0(tcg_env);
break;
case 4:
gen_helper_fpush(tcg_env);
gen_helper_fldlg2_ST0(tcg_env);
break;
case 5:
gen_helper_fpush(tcg_env);
gen_helper_fldln2_ST0(tcg_env);
break;
case 6:
gen_helper_fpush(tcg_env);
gen_helper_fldz_ST0(tcg_env);
break;
default:
goto unknown_op;
}
}
break;
case 0x0e: /* grp d9/6 */
switch (rm) {
case 0: /* f2xm1 */
gen_helper_f2xm1(tcg_env);
break;
case 1: /* fyl2x */
gen_helper_fyl2x(tcg_env);
break;
case 2: /* fptan */
gen_helper_fptan(tcg_env);
break;
case 3: /* fpatan */
gen_helper_fpatan(tcg_env);
break;
case 4: /* fxtract */
gen_helper_fxtract(tcg_env);
break;
case 5: /* fprem1 */
gen_helper_fprem1(tcg_env);
break;
case 6: /* fdecstp */
gen_helper_fdecstp(tcg_env);
break;
default:
case 7: /* fincstp */
gen_helper_fincstp(tcg_env);
break;
}
break;
case 0x0f: /* grp d9/7 */
switch (rm) {
case 0: /* fprem */
gen_helper_fprem(tcg_env);
break;
case 1: /* fyl2xp1 */
gen_helper_fyl2xp1(tcg_env);
break;
case 2: /* fsqrt */
gen_helper_fsqrt(tcg_env);
break;
case 3: /* fsincos */
gen_helper_fsincos(tcg_env);
break;
case 5: /* fscale */
gen_helper_fscale(tcg_env);
break;
case 4: /* frndint */
gen_helper_frndint(tcg_env);
break;
case 6: /* fsin */
gen_helper_fsin(tcg_env);
break;
default:
case 7: /* fcos */
gen_helper_fcos(tcg_env);
break;
}
break;
case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
{
int op1;
op1 = op & 7;
if (op >= 0x20) {
gen_helper_fp_arith_STN_ST0(op1, opreg);
if (op >= 0x30) {
gen_helper_fpop(tcg_env);
}
} else {
gen_helper_fmov_FT0_STN(tcg_env,
tcg_constant_i32(opreg));
gen_helper_fp_arith_ST0_FT0(op1);
}
}
break;
case 0x02: /* fcom */
case 0x22: /* fcom2, undocumented op */
gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
gen_helper_fcom_ST0_FT0(tcg_env);
break;
case 0x03: /* fcomp */
case 0x23: /* fcomp3, undocumented op */
case 0x32: /* fcomp5, undocumented op */
gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
gen_helper_fcom_ST0_FT0(tcg_env);
gen_helper_fpop(tcg_env);
break;
case 0x15: /* da/5 */
switch (rm) {
case 1: /* fucompp */
gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(1));
gen_helper_fucom_ST0_FT0(tcg_env);
gen_helper_fpop(tcg_env);
gen_helper_fpop(tcg_env);
break;
default:
goto unknown_op;
}
break;
case 0x1c:
switch (rm) {
case 0: /* feni (287 only, just do nop here) */
break;
case 1: /* fdisi (287 only, just do nop here) */
break;
case 2: /* fclex */
gen_helper_fclex(tcg_env);
update_fip = false;
break;
case 3: /* fninit */
gen_helper_fninit(tcg_env);
update_fip = false;
break;
case 4: /* fsetpm (287 only, just do nop here) */
break;
default:
goto unknown_op;
}
break;
case 0x1d: /* fucomi */
if (!(s->cpuid_features & CPUID_CMOV)) {
goto illegal_op;
}
gen_update_cc_op(s);
gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
gen_helper_fucomi_ST0_FT0(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x1e: /* fcomi */
if (!(s->cpuid_features & CPUID_CMOV)) {
goto illegal_op;
}
gen_update_cc_op(s);
gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
gen_helper_fcomi_ST0_FT0(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x28: /* ffree sti */
gen_helper_ffree_STN(tcg_env, tcg_constant_i32(opreg));
break;
case 0x2a: /* fst sti */
gen_helper_fmov_STN_ST0(tcg_env, tcg_constant_i32(opreg));
break;
case 0x2b: /* fstp sti */
case 0x0b: /* fstp1 sti, undocumented op */
case 0x3a: /* fstp8 sti, undocumented op */
case 0x3b: /* fstp9 sti, undocumented op */
gen_helper_fmov_STN_ST0(tcg_env, tcg_constant_i32(opreg));
gen_helper_fpop(tcg_env);
break;
case 0x2c: /* fucom st(i) */
gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
gen_helper_fucom_ST0_FT0(tcg_env);
break;
case 0x2d: /* fucomp st(i) */
gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
gen_helper_fucom_ST0_FT0(tcg_env);
gen_helper_fpop(tcg_env);
break;
case 0x33: /* de/3 */
switch (rm) {
case 1: /* fcompp */
gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(1));
gen_helper_fcom_ST0_FT0(tcg_env);
gen_helper_fpop(tcg_env);
gen_helper_fpop(tcg_env);
break;
default:
goto unknown_op;
}
break;
case 0x38: /* ffreep sti, undocumented op */
gen_helper_ffree_STN(tcg_env, tcg_constant_i32(opreg));
gen_helper_fpop(tcg_env);
break;
case 0x3c: /* df/4 */
switch (rm) {
case 0:
gen_helper_fnstsw(s->tmp2_i32, tcg_env);
tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32);
gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);
break;
default:
goto unknown_op;
}
break;
case 0x3d: /* fucomip */
if (!(s->cpuid_features & CPUID_CMOV)) {
goto illegal_op;
}
gen_update_cc_op(s);
gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
gen_helper_fucomi_ST0_FT0(tcg_env);
gen_helper_fpop(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x3e: /* fcomip */
if (!(s->cpuid_features & CPUID_CMOV)) {
goto illegal_op;
}
gen_update_cc_op(s);
gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
gen_helper_fcomi_ST0_FT0(tcg_env);
gen_helper_fpop(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x10 ... 0x13: /* fcmovxx */
case 0x18 ... 0x1b:
{
int op1;
TCGLabel *l1;
static const uint8_t fcmov_cc[8] = {
(JCC_B << 1),
(JCC_Z << 1),
(JCC_BE << 1),
(JCC_P << 1),
};
if (!(s->cpuid_features & CPUID_CMOV)) {
goto illegal_op;
}
op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
l1 = gen_new_label();
gen_jcc1_noeob(s, op1, l1);
gen_helper_fmov_ST0_STN(tcg_env,
tcg_constant_i32(opreg));
gen_set_label(l1);
}
break;
default:
goto unknown_op;
}
}
if (update_fip) {
tcg_gen_ld_i32(s->tmp2_i32, tcg_env,
offsetof(CPUX86State, segs[R_CS].selector));
tcg_gen_st16_i32(s->tmp2_i32, tcg_env,
offsetof(CPUX86State, fpcs));
tcg_gen_st_tl(eip_cur_tl(s),
tcg_env, offsetof(CPUX86State, fpip));
}
}
break;
/************************/
/* string ops */
case 0xa4: /* movsS */
case 0xa5:
ot = mo_b_d(b, dflag);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_movs(s, ot);
} else {
gen_movs(s, ot);
}
break;
case 0xaa: /* stosS */
case 0xab:
ot = mo_b_d(b, dflag);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_stos(s, ot);
} else {
gen_stos(s, ot);
}
break;
case 0xac: /* lodsS */
case 0xad:
ot = mo_b_d(b, dflag);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_lods(s, ot);
} else {
gen_lods(s, ot);
}
break;
case 0xae: /* scasS */
case 0xaf:
ot = mo_b_d(b, dflag);
if (prefixes & PREFIX_REPNZ) {
gen_repz_scas(s, ot, 1);
} else if (prefixes & PREFIX_REPZ) {
gen_repz_scas(s, ot, 0);
} else {
gen_scas(s, ot);
}
break;
case 0xa6: /* cmpsS */
case 0xa7:
ot = mo_b_d(b, dflag);
if (prefixes & PREFIX_REPNZ) {
gen_repz_cmps(s, ot, 1);
} else if (prefixes & PREFIX_REPZ) {
gen_repz_cmps(s, ot, 0);
} else {
gen_cmps(s, ot);
}
break;
case 0x6c: /* insS */
case 0x6d:
ot = mo_b_d32(b, dflag);
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_EDX]);
tcg_gen_ext16u_i32(s->tmp2_i32, s->tmp2_i32);
if (!gen_check_io(s, ot, s->tmp2_i32,
SVM_IOIO_TYPE_MASK | SVM_IOIO_STR_MASK)) {
break;
}
translator_io_start(&s->base);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_ins(s, ot);
} else {
gen_ins(s, ot);
}
break;
case 0x6e: /* outsS */
case 0x6f:
ot = mo_b_d32(b, dflag);
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_EDX]);
tcg_gen_ext16u_i32(s->tmp2_i32, s->tmp2_i32);
if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_STR_MASK)) {
break;
}
translator_io_start(&s->base);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_outs(s, ot);
} else {
gen_outs(s, ot);
}
break;
/************************/
/* port I/O */
case 0xe4:
case 0xe5:
ot = mo_b_d32(b, dflag);
val = x86_ldub_code(env, s);
tcg_gen_movi_i32(s->tmp2_i32, val);
if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_TYPE_MASK)) {
break;
}
translator_io_start(&s->base);
gen_helper_in_func(ot, s->T1, s->tmp2_i32);
gen_op_mov_reg_v(s, ot, R_EAX, s->T1);
gen_bpt_io(s, s->tmp2_i32, ot);
break;
case 0xe6:
case 0xe7:
ot = mo_b_d32(b, dflag);
val = x86_ldub_code(env, s);
tcg_gen_movi_i32(s->tmp2_i32, val);
if (!gen_check_io(s, ot, s->tmp2_i32, 0)) {
break;
}
translator_io_start(&s->base);
gen_op_mov_v_reg(s, ot, s->T1, R_EAX);
tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);
gen_helper_out_func(ot, s->tmp2_i32, s->tmp3_i32);
gen_bpt_io(s, s->tmp2_i32, ot);
break;
case 0xec:
case 0xed:
ot = mo_b_d32(b, dflag);
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_EDX]);
tcg_gen_ext16u_i32(s->tmp2_i32, s->tmp2_i32);
if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_TYPE_MASK)) {
break;
}
translator_io_start(&s->base);
gen_helper_in_func(ot, s->T1, s->tmp2_i32);
gen_op_mov_reg_v(s, ot, R_EAX, s->T1);
gen_bpt_io(s, s->tmp2_i32, ot);
break;
case 0xee:
case 0xef:
ot = mo_b_d32(b, dflag);
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_EDX]);
tcg_gen_ext16u_i32(s->tmp2_i32, s->tmp2_i32);
if (!gen_check_io(s, ot, s->tmp2_i32, 0)) {
break;
}
translator_io_start(&s->base);
gen_op_mov_v_reg(s, ot, s->T1, R_EAX);
tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);
gen_helper_out_func(ot, s->tmp2_i32, s->tmp3_i32);
gen_bpt_io(s, s->tmp2_i32, ot);
break;
/************************/
/* control */
case 0xc2: /* ret im */
val = x86_ldsw_code(env, s);
ot = gen_pop_T0(s);
gen_stack_update(s, val + (1 << ot));
/* Note that gen_pop_T0 uses a zero-extending load. */
gen_op_jmp_v(s, s->T0);
gen_bnd_jmp(s);
s->base.is_jmp = DISAS_JUMP;
break;
case 0xc3: /* ret */
ot = gen_pop_T0(s);
gen_pop_update(s, ot);
/* Note that gen_pop_T0 uses a zero-extending load. */
gen_op_jmp_v(s, s->T0);
gen_bnd_jmp(s);
s->base.is_jmp = DISAS_JUMP;
break;
case 0xca: /* lret im */
val = x86_ldsw_code(env, s);
do_lret:
if (PE(s) && !VM86(s)) {
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_lret_protected(tcg_env, tcg_constant_i32(dflag - 1),
tcg_constant_i32(val));
} else {
gen_stack_A0(s);
/* pop offset */
gen_op_ld_v(s, dflag, s->T0, s->A0);
/* NOTE: keeping EIP updated is not a problem in case of
exception */
gen_op_jmp_v(s, s->T0);
/* pop selector */
gen_add_A0_im(s, 1 << dflag);
gen_op_ld_v(s, dflag, s->T0, s->A0);
gen_op_movl_seg_T0_vm(s, R_CS);
/* add stack offset */
gen_stack_update(s, val + (2 << dflag));
}
s->base.is_jmp = DISAS_EOB_ONLY;
break;
case 0xcb: /* lret */
val = 0;
goto do_lret;
case 0xcf: /* iret */
gen_svm_check_intercept(s, SVM_EXIT_IRET);
if (!PE(s) || VM86(s)) {
/* real mode or vm86 mode */
if (!check_vm86_iopl(s)) {
break;
}
gen_helper_iret_real(tcg_env, tcg_constant_i32(dflag - 1));
} else {
gen_helper_iret_protected(tcg_env, tcg_constant_i32(dflag - 1),
eip_next_i32(s));
}
set_cc_op(s, CC_OP_EFLAGS);
s->base.is_jmp = DISAS_EOB_ONLY;
break;
case 0xe8: /* call im */
{
int diff = (dflag != MO_16
? (int32_t)insn_get(env, s, MO_32)
: (int16_t)insn_get(env, s, MO_16));
gen_push_v(s, eip_next_tl(s));
gen_bnd_jmp(s);
gen_jmp_rel(s, dflag, diff, 0);
}
break;
case 0x9a: /* lcall im */
{
unsigned int selector, offset;
if (CODE64(s))
goto illegal_op;
ot = dflag;
offset = insn_get(env, s, ot);
selector = insn_get(env, s, MO_16);
tcg_gen_movi_tl(s->T0, selector);
tcg_gen_movi_tl(s->T1, offset);
}
goto do_lcall;
case 0xe9: /* jmp im */
{
int diff = (dflag != MO_16
? (int32_t)insn_get(env, s, MO_32)
: (int16_t)insn_get(env, s, MO_16));
gen_bnd_jmp(s);
gen_jmp_rel(s, dflag, diff, 0);
}
break;
case 0xea: /* ljmp im */
{
unsigned int selector, offset;
if (CODE64(s))
goto illegal_op;
ot = dflag;
offset = insn_get(env, s, ot);
selector = insn_get(env, s, MO_16);
tcg_gen_movi_tl(s->T0, selector);
tcg_gen_movi_tl(s->T1, offset);
}
goto do_ljmp;
case 0xeb: /* jmp Jb */
{
int diff = (int8_t)insn_get(env, s, MO_8);
gen_jmp_rel(s, dflag, diff, 0);
}
break;
case 0x70 ... 0x7f: /* jcc Jb */
{
int diff = (int8_t)insn_get(env, s, MO_8);
gen_bnd_jmp(s);
gen_jcc(s, b, diff);
}
break;
case 0x180 ... 0x18f: /* jcc Jv */
{
int diff = (dflag != MO_16
? (int32_t)insn_get(env, s, MO_32)
: (int16_t)insn_get(env, s, MO_16));
gen_bnd_jmp(s);
gen_jcc(s, b, diff);
}
break;
case 0x190 ... 0x19f: /* setcc Gv */
modrm = x86_ldub_code(env, s);
gen_setcc1(s, b, s->T0);
gen_ldst_modrm(env, s, modrm, MO_8, OR_TMP0, 1);
break;
case 0x140 ... 0x14f: /* cmov Gv, Ev */
if (!(s->cpuid_features & CPUID_CMOV)) {
goto illegal_op;
}
ot = dflag;
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
gen_cmovcc1(env, s, ot, b, modrm, reg);
break;
/************************/
/* flags */
case 0x9c: /* pushf */
gen_svm_check_intercept(s, SVM_EXIT_PUSHF);
if (check_vm86_iopl(s)) {
gen_update_cc_op(s);
gen_helper_read_eflags(s->T0, tcg_env);
gen_push_v(s, s->T0);
}
break;
case 0x9d: /* popf */
gen_svm_check_intercept(s, SVM_EXIT_POPF);
if (check_vm86_iopl(s)) {
int mask = TF_MASK | AC_MASK | ID_MASK | NT_MASK;
if (CPL(s) == 0) {
mask |= IF_MASK | IOPL_MASK;
} else if (CPL(s) <= IOPL(s)) {
mask |= IF_MASK;
}
if (dflag == MO_16) {
mask &= 0xffff;
}
ot = gen_pop_T0(s);
gen_helper_write_eflags(tcg_env, s->T0, tcg_constant_i32(mask));
gen_pop_update(s, ot);
set_cc_op(s, CC_OP_EFLAGS);
/* abort translation because TF/AC flag may change */
s->base.is_jmp = DISAS_EOB_NEXT;
}
break;
case 0x9e: /* sahf */
if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
goto illegal_op;
tcg_gen_shri_tl(s->T0, cpu_regs[R_EAX], 8);
gen_compute_eflags(s);
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
tcg_gen_andi_tl(s->T0, s->T0, CC_S | CC_Z | CC_A | CC_P | CC_C);
tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, s->T0);
break;
case 0x9f: /* lahf */
if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
goto illegal_op;
gen_compute_eflags(s);
/* Note: gen_compute_eflags() only gives the condition codes */
tcg_gen_ori_tl(s->T0, cpu_cc_src, 0x02);
tcg_gen_deposit_tl(cpu_regs[R_EAX], cpu_regs[R_EAX], s->T0, 8, 8);
break;
case 0xf5: /* cmc */
gen_compute_eflags(s);
tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);
break;
case 0xf8: /* clc */
gen_compute_eflags(s);
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C);
break;
case 0xf9: /* stc */
gen_compute_eflags(s);
tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C);
break;
case 0xfc: /* cld */
tcg_gen_movi_i32(s->tmp2_i32, 1);
tcg_gen_st_i32(s->tmp2_i32, tcg_env, offsetof(CPUX86State, df));
break;
case 0xfd: /* std */
tcg_gen_movi_i32(s->tmp2_i32, -1);
tcg_gen_st_i32(s->tmp2_i32, tcg_env, offsetof(CPUX86State, df));
break;
/************************/
/* bit operations */
case 0x1ba: /* bt/bts/btr/btc Gv, im */
ot = dflag;
modrm = x86_ldub_code(env, s);
op = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
if (mod != 3) {
s->rip_offset = 1;
gen_lea_modrm(env, s, modrm);
if (!(s->prefix & PREFIX_LOCK)) {
gen_op_ld_v(s, ot, s->T0, s->A0);
}
} else {
gen_op_mov_v_reg(s, ot, s->T0, rm);
}
/* load shift */
val = x86_ldub_code(env, s);
tcg_gen_movi_tl(s->T1, val);
if (op < 4)
goto unknown_op;
op -= 4;
goto bt_op;
case 0x1a3: /* bt Gv, Ev */
op = 0;
goto do_btx;
case 0x1ab: /* bts */
op = 1;
goto do_btx;
case 0x1b3: /* btr */
op = 2;
goto do_btx;
case 0x1bb: /* btc */
op = 3;
do_btx:
ot = dflag;
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
gen_op_mov_v_reg(s, MO_32, s->T1, reg);
if (mod != 3) {
AddressParts a = gen_lea_modrm_0(env, s, modrm);
/* specific case: we need to add a displacement */
gen_exts(ot, s->T1);
tcg_gen_sari_tl(s->tmp0, s->T1, 3 + ot);
tcg_gen_shli_tl(s->tmp0, s->tmp0, ot);
tcg_gen_add_tl(s->A0, gen_lea_modrm_1(s, a, false), s->tmp0);
gen_lea_v_seg(s, s->aflag, s->A0, a.def_seg, s->override);
if (!(s->prefix & PREFIX_LOCK)) {
gen_op_ld_v(s, ot, s->T0, s->A0);
}
} else {
gen_op_mov_v_reg(s, ot, s->T0, rm);
}
bt_op:
tcg_gen_andi_tl(s->T1, s->T1, (1 << (3 + ot)) - 1);
tcg_gen_movi_tl(s->tmp0, 1);
tcg_gen_shl_tl(s->tmp0, s->tmp0, s->T1);
if (s->prefix & PREFIX_LOCK) {
switch (op) {
case 0: /* bt */
/* Needs no atomic ops; we suppressed the normal
memory load for LOCK above so do it now. */
gen_op_ld_v(s, ot, s->T0, s->A0);
break;
case 1: /* bts */
tcg_gen_atomic_fetch_or_tl(s->T0, s->A0, s->tmp0,
s->mem_index, ot | MO_LE);
break;
case 2: /* btr */
tcg_gen_not_tl(s->tmp0, s->tmp0);
tcg_gen_atomic_fetch_and_tl(s->T0, s->A0, s->tmp0,
s->mem_index, ot | MO_LE);
break;
default:
case 3: /* btc */
tcg_gen_atomic_fetch_xor_tl(s->T0, s->A0, s->tmp0,
s->mem_index, ot | MO_LE);
break;
}
tcg_gen_shr_tl(s->tmp4, s->T0, s->T1);
} else {
tcg_gen_shr_tl(s->tmp4, s->T0, s->T1);
switch (op) {
case 0: /* bt */
/* Data already loaded; nothing to do. */
break;
case 1: /* bts */
tcg_gen_or_tl(s->T0, s->T0, s->tmp0);
break;
case 2: /* btr */
tcg_gen_andc_tl(s->T0, s->T0, s->tmp0);
break;
default:
case 3: /* btc */
tcg_gen_xor_tl(s->T0, s->T0, s->tmp0);
break;
}
if (op != 0) {
if (mod != 3) {
gen_op_st_v(s, ot, s->T0, s->A0);
} else {
gen_op_mov_reg_v(s, ot, rm, s->T0);
}
}
}
/* Delay all CC updates until after the store above. Note that
C is the result of the test, Z is unchanged, and the others
are all undefined. */
switch (s->cc_op) {
case CC_OP_MULB ... CC_OP_MULQ:
case CC_OP_ADDB ... CC_OP_ADDQ:
case CC_OP_ADCB ... CC_OP_ADCQ:
case CC_OP_SUBB ... CC_OP_SUBQ:
case CC_OP_SBBB ... CC_OP_SBBQ:
case CC_OP_LOGICB ... CC_OP_LOGICQ:
case CC_OP_INCB ... CC_OP_INCQ:
case CC_OP_DECB ... CC_OP_DECQ:
case CC_OP_SHLB ... CC_OP_SHLQ:
case CC_OP_SARB ... CC_OP_SARQ:
case CC_OP_BMILGB ... CC_OP_BMILGQ:
/* Z was going to be computed from the non-zero status of CC_DST.
We can get that same Z value (and the new C value) by leaving
CC_DST alone, setting CC_SRC, and using a CC_OP_SAR of the
same width. */
tcg_gen_mov_tl(cpu_cc_src, s->tmp4);
set_cc_op(s, ((s->cc_op - CC_OP_MULB) & 3) + CC_OP_SARB);
break;
default:
/* Otherwise, generate EFLAGS and replace the C bit. */
gen_compute_eflags(s);
tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, s->tmp4,
ctz32(CC_C), 1);
break;
}
break;
case 0x1bc: /* bsf / tzcnt */
case 0x1bd: /* bsr / lzcnt */
ot = dflag;
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_extu(ot, s->T0);
/* Note that lzcnt and tzcnt are in different extensions. */
if ((prefixes & PREFIX_REPZ)
&& (b & 1
? s->cpuid_ext3_features & CPUID_EXT3_ABM
: s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1)) {
int size = 8 << ot;
/* For lzcnt/tzcnt, C bit is defined related to the input. */
tcg_gen_mov_tl(cpu_cc_src, s->T0);
if (b & 1) {
/* For lzcnt, reduce the target_ulong result by the
number of zeros that we expect to find at the top. */
tcg_gen_clzi_tl(s->T0, s->T0, TARGET_LONG_BITS);
tcg_gen_subi_tl(s->T0, s->T0, TARGET_LONG_BITS - size);
} else {
/* For tzcnt, a zero input must return the operand size. */
tcg_gen_ctzi_tl(s->T0, s->T0, size);
}
/* For lzcnt/tzcnt, Z bit is defined related to the result. */
gen_op_update1_cc(s);
set_cc_op(s, CC_OP_BMILGB + ot);
} else {
/* For bsr/bsf, only the Z bit is defined and it is related
to the input and not the result. */
tcg_gen_mov_tl(cpu_cc_dst, s->T0);
set_cc_op(s, CC_OP_LOGICB + ot);
/* ??? The manual says that the output is undefined when the
input is zero, but real hardware leaves it unchanged, and
real programs appear to depend on that. Accomplish this
by passing the output as the value to return upon zero. */
if (b & 1) {
/* For bsr, return the bit index of the first 1 bit,
not the count of leading zeros. */
tcg_gen_xori_tl(s->T1, cpu_regs[reg], TARGET_LONG_BITS - 1);
tcg_gen_clz_tl(s->T0, s->T0, s->T1);
tcg_gen_xori_tl(s->T0, s->T0, TARGET_LONG_BITS - 1);
} else {
tcg_gen_ctz_tl(s->T0, s->T0, cpu_regs[reg]);
}
}
gen_op_mov_reg_v(s, ot, reg, s->T0);
break;
/************************/
/* bcd */
case 0x27: /* daa */
if (CODE64(s))
goto illegal_op;
gen_update_cc_op(s);
gen_helper_daa(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x2f: /* das */
if (CODE64(s))
goto illegal_op;
gen_update_cc_op(s);
gen_helper_das(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x37: /* aaa */
if (CODE64(s))
goto illegal_op;
gen_update_cc_op(s);
gen_helper_aaa(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x3f: /* aas */
if (CODE64(s))
goto illegal_op;
gen_update_cc_op(s);
gen_helper_aas(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0xd4: /* aam */
if (CODE64(s))
goto illegal_op;
val = x86_ldub_code(env, s);
if (val == 0) {
gen_exception(s, EXCP00_DIVZ);
} else {
gen_helper_aam(tcg_env, tcg_constant_i32(val));
set_cc_op(s, CC_OP_LOGICB);
}
break;
case 0xd5: /* aad */
if (CODE64(s))
goto illegal_op;
val = x86_ldub_code(env, s);
gen_helper_aad(tcg_env, tcg_constant_i32(val));
set_cc_op(s, CC_OP_LOGICB);
break;
/************************/
/* misc */
case 0x90: /* nop */
/* XXX: correct lock test for all insn */
if (prefixes & PREFIX_LOCK) {
goto illegal_op;
}
/* If REX_B is set, then this is xchg eax, r8d, not a nop. */
if (REX_B(s)) {
goto do_xchg_reg_eax;
}
if (prefixes & PREFIX_REPZ) {
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_pause(tcg_env, cur_insn_len_i32(s));
s->base.is_jmp = DISAS_NORETURN;
}
break;
case 0x9b: /* fwait */
if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
(HF_MP_MASK | HF_TS_MASK)) {
gen_exception(s, EXCP07_PREX);
} else {
/* needs to be treated as I/O because of ferr_irq */
translator_io_start(&s->base);
gen_helper_fwait(tcg_env);
}
break;
case 0xcc: /* int3 */
gen_interrupt(s, EXCP03_INT3);
break;
case 0xcd: /* int N */
val = x86_ldub_code(env, s);
if (check_vm86_iopl(s)) {
gen_interrupt(s, val);
}
break;
case 0xce: /* into */
if (CODE64(s))
goto illegal_op;
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_into(tcg_env, cur_insn_len_i32(s));
break;
#ifdef WANT_ICEBP
case 0xf1: /* icebp (undocumented, exits to external debugger) */
gen_svm_check_intercept(s, SVM_EXIT_ICEBP);
gen_debug(s);
break;
#endif
case 0xfa: /* cli */
if (check_iopl(s)) {
gen_reset_eflags(s, IF_MASK);
}
break;
case 0xfb: /* sti */
if (check_iopl(s)) {
gen_set_eflags(s, IF_MASK);
/* interruptions are enabled only the first insn after sti */
gen_update_eip_next(s);
gen_eob_inhibit_irq(s, true);
}
break;
case 0x62: /* bound */
if (CODE64(s))
goto illegal_op;
ot = dflag;
modrm = x86_ldub_code(env, s);
reg = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
if (mod == 3)
goto illegal_op;
gen_op_mov_v_reg(s, ot, s->T0, reg);
gen_lea_modrm(env, s, modrm);
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
if (ot == MO_16) {
gen_helper_boundw(tcg_env, s->A0, s->tmp2_i32);
} else {
gen_helper_boundl(tcg_env, s->A0, s->tmp2_i32);
}
break;
case 0x1c8 ... 0x1cf: /* bswap reg */
reg = (b & 7) | REX_B(s);
#ifdef TARGET_X86_64
if (dflag == MO_64) {
tcg_gen_bswap64_i64(cpu_regs[reg], cpu_regs[reg]);
break;
}
#endif
tcg_gen_bswap32_tl(cpu_regs[reg], cpu_regs[reg], TCG_BSWAP_OZ);
break;
case 0xd6: /* salc */
if (CODE64(s))
goto illegal_op;
gen_compute_eflags_c(s, s->T0);
tcg_gen_neg_tl(s->T0, s->T0);
gen_op_mov_reg_v(s, MO_8, R_EAX, s->T0);
break;
case 0xe0: /* loopnz */
case 0xe1: /* loopz */
case 0xe2: /* loop */
case 0xe3: /* jecxz */
{
TCGLabel *l1, *l2;
int diff = (int8_t)insn_get(env, s, MO_8);
l1 = gen_new_label();
l2 = gen_new_label();
gen_update_cc_op(s);
b &= 3;
switch(b) {
case 0: /* loopnz */
case 1: /* loopz */
gen_op_add_reg_im(s, s->aflag, R_ECX, -1);
gen_op_jz_ecx(s, l2);
gen_jcc1(s, (JCC_Z << 1) | (b ^ 1), l1);
break;
case 2: /* loop */
gen_op_add_reg_im(s, s->aflag, R_ECX, -1);
gen_op_jnz_ecx(s, l1);
break;
default:
case 3: /* jcxz */
gen_op_jz_ecx(s, l1);
break;
}
gen_set_label(l2);
gen_jmp_rel_csize(s, 0, 1);
gen_set_label(l1);
gen_jmp_rel(s, dflag, diff, 0);
}
break;
case 0x130: /* wrmsr */
case 0x132: /* rdmsr */
if (check_cpl0(s)) {
gen_update_cc_op(s);
gen_update_eip_cur(s);
if (b & 2) {
gen_helper_rdmsr(tcg_env);
} else {
gen_helper_wrmsr(tcg_env);
s->base.is_jmp = DISAS_EOB_NEXT;
}
}
break;
case 0x131: /* rdtsc */
gen_update_cc_op(s);
gen_update_eip_cur(s);
translator_io_start(&s->base);
gen_helper_rdtsc(tcg_env);
break;
case 0x133: /* rdpmc */
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_rdpmc(tcg_env);
s->base.is_jmp = DISAS_NORETURN;
break;
case 0x134: /* sysenter */
/* For AMD SYSENTER is not valid in long mode */
if (LMA(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) {
goto illegal_op;
}
if (!PE(s)) {
gen_exception_gpf(s);
} else {
gen_helper_sysenter(tcg_env);
s->base.is_jmp = DISAS_EOB_ONLY;
}
break;
case 0x135: /* sysexit */
/* For AMD SYSEXIT is not valid in long mode */
if (LMA(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) {
goto illegal_op;
}
if (!PE(s) || CPL(s) != 0) {
gen_exception_gpf(s);
} else {
gen_helper_sysexit(tcg_env, tcg_constant_i32(dflag - 1));
s->base.is_jmp = DISAS_EOB_ONLY;
}
break;
case 0x105: /* syscall */
/* For Intel SYSCALL is only valid in long mode */
if (!LMA(s) && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1) {
goto illegal_op;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_syscall(tcg_env, cur_insn_len_i32(s));
/* TF handling for the syscall insn is different. The TF bit is checked
after the syscall insn completes. This allows #DB to not be
generated after one has entered CPL0 if TF is set in FMASK. */
gen_eob_worker(s, false, true);
break;
case 0x107: /* sysret */
/* For Intel SYSRET is only valid in long mode */
if (!LMA(s) && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1) {
goto illegal_op;
}
if (!PE(s) || CPL(s) != 0) {
gen_exception_gpf(s);
} else {
gen_helper_sysret(tcg_env, tcg_constant_i32(dflag - 1));
/* condition codes are modified only in long mode */
if (LMA(s)) {
set_cc_op(s, CC_OP_EFLAGS);
}
/* TF handling for the sysret insn is different. The TF bit is
checked after the sysret insn completes. This allows #DB to be
generated "as if" the syscall insn in userspace has just
completed. */
gen_eob_worker(s, false, true);
}
break;
case 0x1a2: /* cpuid */
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_cpuid(tcg_env);
break;
case 0xf4: /* hlt */
if (check_cpl0(s)) {
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_hlt(tcg_env, cur_insn_len_i32(s));
s->base.is_jmp = DISAS_NORETURN;
}
break;
case 0x100:
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
op = (modrm >> 3) & 7;
switch(op) {
case 0: /* sldt */
if (!PE(s) || VM86(s))
goto illegal_op;
if (s->flags & HF_UMIP_MASK && !check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_LDTR_READ);
tcg_gen_ld32u_tl(s->T0, tcg_env,
offsetof(CPUX86State, ldt.selector));
ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
case 2: /* lldt */
if (!PE(s) || VM86(s))
goto illegal_op;
if (check_cpl0(s)) {
gen_svm_check_intercept(s, SVM_EXIT_LDTR_WRITE);
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
gen_helper_lldt(tcg_env, s->tmp2_i32);
}
break;
case 1: /* str */
if (!PE(s) || VM86(s))
goto illegal_op;
if (s->flags & HF_UMIP_MASK && !check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_TR_READ);
tcg_gen_ld32u_tl(s->T0, tcg_env,
offsetof(CPUX86State, tr.selector));
ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
case 3: /* ltr */
if (!PE(s) || VM86(s))
goto illegal_op;
if (check_cpl0(s)) {
gen_svm_check_intercept(s, SVM_EXIT_TR_WRITE);
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
gen_helper_ltr(tcg_env, s->tmp2_i32);
}
break;
case 4: /* verr */
case 5: /* verw */
if (!PE(s) || VM86(s))
goto illegal_op;
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
gen_update_cc_op(s);
if (op == 4) {
gen_helper_verr(tcg_env, s->T0);
} else {
gen_helper_verw(tcg_env, s->T0);
}
set_cc_op(s, CC_OP_EFLAGS);
break;
default:
goto unknown_op;
}
break;
case 0x101:
modrm = x86_ldub_code(env, s);
switch (modrm) {
CASE_MODRM_MEM_OP(0): /* sgdt */
if (s->flags & HF_UMIP_MASK && !check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_GDTR_READ);
gen_lea_modrm(env, s, modrm);
tcg_gen_ld32u_tl(s->T0,
tcg_env, offsetof(CPUX86State, gdt.limit));
gen_op_st_v(s, MO_16, s->T0, s->A0);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(s->T0, tcg_env, offsetof(CPUX86State, gdt.base));
if (dflag == MO_16) {
tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);
}
gen_op_st_v(s, CODE64(s) + MO_32, s->T0, s->A0);
break;
case 0xc8: /* monitor */
if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || CPL(s) != 0) {
goto illegal_op;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
tcg_gen_mov_tl(s->A0, cpu_regs[R_EAX]);
gen_extu(s->aflag, s->A0);
gen_add_A0_ds_seg(s);
gen_helper_monitor(tcg_env, s->A0);
break;
case 0xc9: /* mwait */
if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || CPL(s) != 0) {
goto illegal_op;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_mwait(tcg_env, cur_insn_len_i32(s));
s->base.is_jmp = DISAS_NORETURN;
break;
case 0xca: /* clac */
if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP)
|| CPL(s) != 0) {
goto illegal_op;
}
gen_reset_eflags(s, AC_MASK);
s->base.is_jmp = DISAS_EOB_NEXT;
break;
case 0xcb: /* stac */
if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP)
|| CPL(s) != 0) {
goto illegal_op;
}
gen_set_eflags(s, AC_MASK);
s->base.is_jmp = DISAS_EOB_NEXT;
break;
CASE_MODRM_MEM_OP(1): /* sidt */
if (s->flags & HF_UMIP_MASK && !check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_IDTR_READ);
gen_lea_modrm(env, s, modrm);
tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, idt.limit));
gen_op_st_v(s, MO_16, s->T0, s->A0);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(s->T0, tcg_env, offsetof(CPUX86State, idt.base));
if (dflag == MO_16) {
tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);
}
gen_op_st_v(s, CODE64(s) + MO_32, s->T0, s->A0);
break;
case 0xd0: /* xgetbv */
if ((s->cpuid_ext_features & CPUID_EXT_XSAVE) == 0
|| (s->prefix & (PREFIX_LOCK | PREFIX_DATA
| PREFIX_REPZ | PREFIX_REPNZ))) {
goto illegal_op;
}
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]);
gen_helper_xgetbv(s->tmp1_i64, tcg_env, s->tmp2_i32);
tcg_gen_extr_i64_tl(cpu_regs[R_EAX], cpu_regs[R_EDX], s->tmp1_i64);
break;
case 0xd1: /* xsetbv */
if ((s->cpuid_ext_features & CPUID_EXT_XSAVE) == 0
|| (s->prefix & (PREFIX_LOCK | PREFIX_DATA
| PREFIX_REPZ | PREFIX_REPNZ))) {
goto illegal_op;
}
if (!check_cpl0(s)) {
break;
}
tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX],
cpu_regs[R_EDX]);
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]);
gen_helper_xsetbv(tcg_env, s->tmp2_i32, s->tmp1_i64);
/* End TB because translation flags may change. */
s->base.is_jmp = DISAS_EOB_NEXT;
break;
case 0xd8: /* VMRUN */
if (!SVME(s) || !PE(s)) {
goto illegal_op;
}
if (!check_cpl0(s)) {
break;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_vmrun(tcg_env, tcg_constant_i32(s->aflag - 1),
cur_insn_len_i32(s));
tcg_gen_exit_tb(NULL, 0);
s->base.is_jmp = DISAS_NORETURN;
break;
case 0xd9: /* VMMCALL */
if (!SVME(s)) {
goto illegal_op;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_vmmcall(tcg_env);
break;
case 0xda: /* VMLOAD */
if (!SVME(s) || !PE(s)) {
goto illegal_op;
}
if (!check_cpl0(s)) {
break;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_vmload(tcg_env, tcg_constant_i32(s->aflag - 1));
break;
case 0xdb: /* VMSAVE */
if (!SVME(s) || !PE(s)) {
goto illegal_op;
}
if (!check_cpl0(s)) {
break;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_vmsave(tcg_env, tcg_constant_i32(s->aflag - 1));
break;
case 0xdc: /* STGI */
if ((!SVME(s) && !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT))
|| !PE(s)) {
goto illegal_op;
}
if (!check_cpl0(s)) {
break;
}
gen_update_cc_op(s);
gen_helper_stgi(tcg_env);
s->base.is_jmp = DISAS_EOB_NEXT;
break;
case 0xdd: /* CLGI */
if (!SVME(s) || !PE(s)) {
goto illegal_op;
}
if (!check_cpl0(s)) {
break;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_clgi(tcg_env);
break;
case 0xde: /* SKINIT */
if ((!SVME(s) && !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT))
|| !PE(s)) {
goto illegal_op;
}
gen_svm_check_intercept(s, SVM_EXIT_SKINIT);
/* If not intercepted, not implemented -- raise #UD. */
goto illegal_op;
case 0xdf: /* INVLPGA */
if (!SVME(s) || !PE(s)) {
goto illegal_op;
}
if (!check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_INVLPGA);
if (s->aflag == MO_64) {
tcg_gen_mov_tl(s->A0, cpu_regs[R_EAX]);
} else {
tcg_gen_ext32u_tl(s->A0, cpu_regs[R_EAX]);
}
gen_helper_flush_page(tcg_env, s->A0);
s->base.is_jmp = DISAS_EOB_NEXT;
break;
CASE_MODRM_MEM_OP(2): /* lgdt */
if (!check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_GDTR_WRITE);
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, MO_16, s->T1, s->A0);
gen_add_A0_im(s, 2);
gen_op_ld_v(s, CODE64(s) + MO_32, s->T0, s->A0);
if (dflag == MO_16) {
tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);
}
tcg_gen_st_tl(s->T0, tcg_env, offsetof(CPUX86State, gdt.base));
tcg_gen_st32_tl(s->T1, tcg_env, offsetof(CPUX86State, gdt.limit));
break;
CASE_MODRM_MEM_OP(3): /* lidt */
if (!check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_IDTR_WRITE);
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, MO_16, s->T1, s->A0);
gen_add_A0_im(s, 2);
gen_op_ld_v(s, CODE64(s) + MO_32, s->T0, s->A0);
if (dflag == MO_16) {
tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);
}
tcg_gen_st_tl(s->T0, tcg_env, offsetof(CPUX86State, idt.base));
tcg_gen_st32_tl(s->T1, tcg_env, offsetof(CPUX86State, idt.limit));
break;
CASE_MODRM_OP(4): /* smsw */
if (s->flags & HF_UMIP_MASK && !check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_READ_CR0);
tcg_gen_ld_tl(s->T0, tcg_env, offsetof(CPUX86State, cr[0]));
/*
* In 32-bit mode, the higher 16 bits of the destination
* register are undefined. In practice CR0[31:0] is stored
* just like in 64-bit mode.
*/
mod = (modrm >> 6) & 3;
ot = (mod != 3 ? MO_16 : s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
case 0xee: /* rdpkru */
if (prefixes & PREFIX_LOCK) {
goto illegal_op;
}
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]);
gen_helper_rdpkru(s->tmp1_i64, tcg_env, s->tmp2_i32);
tcg_gen_extr_i64_tl(cpu_regs[R_EAX], cpu_regs[R_EDX], s->tmp1_i64);
break;
case 0xef: /* wrpkru */
if (prefixes & PREFIX_LOCK) {
goto illegal_op;
}
tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX],
cpu_regs[R_EDX]);
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]);
gen_helper_wrpkru(tcg_env, s->tmp2_i32, s->tmp1_i64);
break;
CASE_MODRM_OP(6): /* lmsw */
if (!check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0);
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
/*
* Only the 4 lower bits of CR0 are modified.
* PE cannot be set to zero if already set to one.
*/
tcg_gen_ld_tl(s->T1, tcg_env, offsetof(CPUX86State, cr[0]));
tcg_gen_andi_tl(s->T0, s->T0, 0xf);
tcg_gen_andi_tl(s->T1, s->T1, ~0xe);
tcg_gen_or_tl(s->T0, s->T0, s->T1);
gen_helper_write_crN(tcg_env, tcg_constant_i32(0), s->T0);
s->base.is_jmp = DISAS_EOB_NEXT;
break;
CASE_MODRM_MEM_OP(7): /* invlpg */
if (!check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_INVLPG);
gen_lea_modrm(env, s, modrm);
gen_helper_flush_page(tcg_env, s->A0);
s->base.is_jmp = DISAS_EOB_NEXT;
break;
case 0xf8: /* swapgs */
#ifdef TARGET_X86_64
if (CODE64(s)) {
if (check_cpl0(s)) {
tcg_gen_mov_tl(s->T0, cpu_seg_base[R_GS]);
tcg_gen_ld_tl(cpu_seg_base[R_GS], tcg_env,
offsetof(CPUX86State, kernelgsbase));
tcg_gen_st_tl(s->T0, tcg_env,
offsetof(CPUX86State, kernelgsbase));
}
break;
}
#endif
goto illegal_op;
case 0xf9: /* rdtscp */
if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP)) {
goto illegal_op;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
translator_io_start(&s->base);
gen_helper_rdtsc(tcg_env);
gen_helper_rdpid(s->T0, tcg_env);
gen_op_mov_reg_v(s, dflag, R_ECX, s->T0);
break;
default:
goto unknown_op;
}
break;
case 0x108: /* invd */
case 0x109: /* wbinvd; wbnoinvd with REPZ prefix */
if (check_cpl0(s)) {
gen_svm_check_intercept(s, (b & 1) ? SVM_EXIT_WBINVD : SVM_EXIT_INVD);
/* nothing to do */
}
break;
case 0x63: /* arpl or movslS (x86_64) */
#ifdef TARGET_X86_64
if (CODE64(s)) {
int d_ot;
/* d_ot is the size of destination */
d_ot = dflag;
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
if (mod == 3) {
gen_op_mov_v_reg(s, MO_32, s->T0, rm);
/* sign extend */
if (d_ot == MO_64) {
tcg_gen_ext32s_tl(s->T0, s->T0);
}
gen_op_mov_reg_v(s, d_ot, reg, s->T0);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, MO_32 | MO_SIGN, s->T0, s->A0);
gen_op_mov_reg_v(s, d_ot, reg, s->T0);
}
} else
#endif
{
TCGLabel *label1;
TCGv t0, t1, t2;
if (!PE(s) || VM86(s))
goto illegal_op;
t0 = tcg_temp_new();
t1 = tcg_temp_new();
t2 = tcg_temp_new();
ot = MO_16;
modrm = x86_ldub_code(env, s);
reg = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
rm = modrm & 7;
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, t0, s->A0);
} else {
gen_op_mov_v_reg(s, ot, t0, rm);
}
gen_op_mov_v_reg(s, ot, t1, reg);
tcg_gen_andi_tl(s->tmp0, t0, 3);
tcg_gen_andi_tl(t1, t1, 3);
tcg_gen_movi_tl(t2, 0);
label1 = gen_new_label();
tcg_gen_brcond_tl(TCG_COND_GE, s->tmp0, t1, label1);
tcg_gen_andi_tl(t0, t0, ~3);
tcg_gen_or_tl(t0, t0, t1);
tcg_gen_movi_tl(t2, CC_Z);
gen_set_label(label1);
if (mod != 3) {
gen_op_st_v(s, ot, t0, s->A0);
} else {
gen_op_mov_reg_v(s, ot, rm, t0);
}
gen_compute_eflags(s);
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2);
}
break;
case 0x102: /* lar */
case 0x103: /* lsl */
{
TCGLabel *label1;
TCGv t0;
if (!PE(s) || VM86(s))
goto illegal_op;
ot = dflag != MO_16 ? MO_32 : MO_16;
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
t0 = tcg_temp_new();
gen_update_cc_op(s);
if (b == 0x102) {
gen_helper_lar(t0, tcg_env, s->T0);
} else {
gen_helper_lsl(t0, tcg_env, s->T0);
}
tcg_gen_andi_tl(s->tmp0, cpu_cc_src, CC_Z);
label1 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, s->tmp0, 0, label1);
gen_op_mov_reg_v(s, ot, reg, t0);
gen_set_label(label1);
set_cc_op(s, CC_OP_EFLAGS);
}
break;
case 0x118:
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
op = (modrm >> 3) & 7;
switch(op) {
case 0: /* prefetchnta */
case 1: /* prefetchnt0 */
case 2: /* prefetchnt0 */
case 3: /* prefetchnt0 */
if (mod == 3)
goto illegal_op;
gen_nop_modrm(env, s, modrm);
/* nothing more to do */
break;
default: /* nop (multi byte) */
gen_nop_modrm(env, s, modrm);
break;
}
break;
case 0x11a:
modrm = x86_ldub_code(env, s);
if (s->flags & HF_MPX_EN_MASK) {
mod = (modrm >> 6) & 3;
reg = ((modrm >> 3) & 7) | REX_R(s);
if (prefixes & PREFIX_REPZ) {
/* bndcl */
if (reg >= 4
|| (prefixes & PREFIX_LOCK)
|| s->aflag == MO_16) {
goto illegal_op;
}
gen_bndck(env, s, modrm, TCG_COND_LTU, cpu_bndl[reg]);
} else if (prefixes & PREFIX_REPNZ) {
/* bndcu */
if (reg >= 4
|| (prefixes & PREFIX_LOCK)
|| s->aflag == MO_16) {
goto illegal_op;
}
TCGv_i64 notu = tcg_temp_new_i64();
tcg_gen_not_i64(notu, cpu_bndu[reg]);
gen_bndck(env, s, modrm, TCG_COND_GTU, notu);
} else if (prefixes & PREFIX_DATA) {
/* bndmov -- from reg/mem */
if (reg >= 4 || s->aflag == MO_16) {
goto illegal_op;
}
if (mod == 3) {
int reg2 = (modrm & 7) | REX_B(s);
if (reg2 >= 4 || (prefixes & PREFIX_LOCK)) {
goto illegal_op;
}
if (s->flags & HF_MPX_IU_MASK) {
tcg_gen_mov_i64(cpu_bndl[reg], cpu_bndl[reg2]);
tcg_gen_mov_i64(cpu_bndu[reg], cpu_bndu[reg2]);
}
} else {
gen_lea_modrm(env, s, modrm);
if (CODE64(s)) {
tcg_gen_qemu_ld_i64(cpu_bndl[reg], s->A0,
s->mem_index, MO_LEUQ);
tcg_gen_addi_tl(s->A0, s->A0, 8);
tcg_gen_qemu_ld_i64(cpu_bndu[reg], s->A0,
s->mem_index, MO_LEUQ);
} else {
tcg_gen_qemu_ld_i64(cpu_bndl[reg], s->A0,
s->mem_index, MO_LEUL);
tcg_gen_addi_tl(s->A0, s->A0, 4);
tcg_gen_qemu_ld_i64(cpu_bndu[reg], s->A0,
s->mem_index, MO_LEUL);
}
/* bnd registers are now in-use */
gen_set_hflag(s, HF_MPX_IU_MASK);
}
} else if (mod != 3) {
/* bndldx */
AddressParts a = gen_lea_modrm_0(env, s, modrm);
if (reg >= 4
|| (prefixes & PREFIX_LOCK)
|| s->aflag == MO_16
|| a.base < -1) {
goto illegal_op;
}
if (a.base >= 0) {
tcg_gen_addi_tl(s->A0, cpu_regs[a.base], a.disp);
} else {
tcg_gen_movi_tl(s->A0, 0);
}
gen_lea_v_seg(s, s->aflag, s->A0, a.def_seg, s->override);
if (a.index >= 0) {
tcg_gen_mov_tl(s->T0, cpu_regs[a.index]);
} else {
tcg_gen_movi_tl(s->T0, 0);
}
if (CODE64(s)) {
gen_helper_bndldx64(cpu_bndl[reg], tcg_env, s->A0, s->T0);
tcg_gen_ld_i64(cpu_bndu[reg], tcg_env,
offsetof(CPUX86State, mmx_t0.MMX_Q(0)));
} else {
gen_helper_bndldx32(cpu_bndu[reg], tcg_env, s->A0, s->T0);
tcg_gen_ext32u_i64(cpu_bndl[reg], cpu_bndu[reg]);
tcg_gen_shri_i64(cpu_bndu[reg], cpu_bndu[reg], 32);
}
gen_set_hflag(s, HF_MPX_IU_MASK);
}
}
gen_nop_modrm(env, s, modrm);
break;
case 0x11b:
modrm = x86_ldub_code(env, s);
if (s->flags & HF_MPX_EN_MASK) {
mod = (modrm >> 6) & 3;
reg = ((modrm >> 3) & 7) | REX_R(s);
if (mod != 3 && (prefixes & PREFIX_REPZ)) {
/* bndmk */
if (reg >= 4
|| (prefixes & PREFIX_LOCK)
|| s->aflag == MO_16) {
goto illegal_op;
}
AddressParts a = gen_lea_modrm_0(env, s, modrm);
if (a.base >= 0) {
tcg_gen_extu_tl_i64(cpu_bndl[reg], cpu_regs[a.base]);
if (!CODE64(s)) {
tcg_gen_ext32u_i64(cpu_bndl[reg], cpu_bndl[reg]);
}
} else if (a.base == -1) {
/* no base register has lower bound of 0 */
tcg_gen_movi_i64(cpu_bndl[reg], 0);
} else {
/* rip-relative generates #ud */
goto illegal_op;
}
tcg_gen_not_tl(s->A0, gen_lea_modrm_1(s, a, false));
if (!CODE64(s)) {
tcg_gen_ext32u_tl(s->A0, s->A0);
}
tcg_gen_extu_tl_i64(cpu_bndu[reg], s->A0);
/* bnd registers are now in-use */
gen_set_hflag(s, HF_MPX_IU_MASK);
break;
} else if (prefixes & PREFIX_REPNZ) {
/* bndcn */
if (reg >= 4
|| (prefixes & PREFIX_LOCK)
|| s->aflag == MO_16) {
goto illegal_op;
}
gen_bndck(env, s, modrm, TCG_COND_GTU, cpu_bndu[reg]);
} else if (prefixes & PREFIX_DATA) {
/* bndmov -- to reg/mem */
if (reg >= 4 || s->aflag == MO_16) {
goto illegal_op;
}
if (mod == 3) {
int reg2 = (modrm & 7) | REX_B(s);
if (reg2 >= 4 || (prefixes & PREFIX_LOCK)) {
goto illegal_op;
}
if (s->flags & HF_MPX_IU_MASK) {
tcg_gen_mov_i64(cpu_bndl[reg2], cpu_bndl[reg]);
tcg_gen_mov_i64(cpu_bndu[reg2], cpu_bndu[reg]);
}
} else {
gen_lea_modrm(env, s, modrm);
if (CODE64(s)) {
tcg_gen_qemu_st_i64(cpu_bndl[reg], s->A0,
s->mem_index, MO_LEUQ);
tcg_gen_addi_tl(s->A0, s->A0, 8);
tcg_gen_qemu_st_i64(cpu_bndu[reg], s->A0,
s->mem_index, MO_LEUQ);
} else {
tcg_gen_qemu_st_i64(cpu_bndl[reg], s->A0,
s->mem_index, MO_LEUL);
tcg_gen_addi_tl(s->A0, s->A0, 4);
tcg_gen_qemu_st_i64(cpu_bndu[reg], s->A0,
s->mem_index, MO_LEUL);
}
}
} else if (mod != 3) {
/* bndstx */
AddressParts a = gen_lea_modrm_0(env, s, modrm);
if (reg >= 4
|| (prefixes & PREFIX_LOCK)
|| s->aflag == MO_16
|| a.base < -1) {
goto illegal_op;
}
if (a.base >= 0) {
tcg_gen_addi_tl(s->A0, cpu_regs[a.base], a.disp);
} else {
tcg_gen_movi_tl(s->A0, 0);
}
gen_lea_v_seg(s, s->aflag, s->A0, a.def_seg, s->override);
if (a.index >= 0) {
tcg_gen_mov_tl(s->T0, cpu_regs[a.index]);
} else {
tcg_gen_movi_tl(s->T0, 0);
}
if (CODE64(s)) {
gen_helper_bndstx64(tcg_env, s->A0, s->T0,
cpu_bndl[reg], cpu_bndu[reg]);
} else {
gen_helper_bndstx32(tcg_env, s->A0, s->T0,
cpu_bndl[reg], cpu_bndu[reg]);
}
}
}
gen_nop_modrm(env, s, modrm);
break;
case 0x119: case 0x11c ... 0x11f: /* nop (multi byte) */
modrm = x86_ldub_code(env, s);
gen_nop_modrm(env, s, modrm);
break;
case 0x120: /* mov reg, crN */
case 0x122: /* mov crN, reg */
if (!check_cpl0(s)) {
break;
}
modrm = x86_ldub_code(env, s);
/*
* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
* AMD documentation (24594.pdf) and testing of Intel 386 and 486
* processors all show that the mod bits are assumed to be 1's,
* regardless of actual values.
*/
rm = (modrm & 7) | REX_B(s);
reg = ((modrm >> 3) & 7) | REX_R(s);
switch (reg) {
case 0:
if ((prefixes & PREFIX_LOCK) &&
(s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) {
reg = 8;
}
break;
case 2:
case 3:
case 4:
case 8:
break;
default:
goto unknown_op;
}
ot = (CODE64(s) ? MO_64 : MO_32);
translator_io_start(&s->base);
if (b & 2) {
gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0 + reg);
gen_op_mov_v_reg(s, ot, s->T0, rm);
gen_helper_write_crN(tcg_env, tcg_constant_i32(reg), s->T0);
s->base.is_jmp = DISAS_EOB_NEXT;
} else {
gen_svm_check_intercept(s, SVM_EXIT_READ_CR0 + reg);
gen_helper_read_crN(s->T0, tcg_env, tcg_constant_i32(reg));
gen_op_mov_reg_v(s, ot, rm, s->T0);
}
break;
case 0x121: /* mov reg, drN */
case 0x123: /* mov drN, reg */
if (check_cpl0(s)) {
modrm = x86_ldub_code(env, s);
/* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
* AMD documentation (24594.pdf) and testing of
* intel 386 and 486 processors all show that the mod bits
* are assumed to be 1's, regardless of actual values.
*/
rm = (modrm & 7) | REX_B(s);
reg = ((modrm >> 3) & 7) | REX_R(s);
if (CODE64(s))
ot = MO_64;
else
ot = MO_32;
if (reg >= 8) {
goto illegal_op;
}
if (b & 2) {
gen_svm_check_intercept(s, SVM_EXIT_WRITE_DR0 + reg);
gen_op_mov_v_reg(s, ot, s->T0, rm);
tcg_gen_movi_i32(s->tmp2_i32, reg);
gen_helper_set_dr(tcg_env, s->tmp2_i32, s->T0);
s->base.is_jmp = DISAS_EOB_NEXT;
} else {
gen_svm_check_intercept(s, SVM_EXIT_READ_DR0 + reg);
tcg_gen_movi_i32(s->tmp2_i32, reg);
gen_helper_get_dr(s->T0, tcg_env, s->tmp2_i32);
gen_op_mov_reg_v(s, ot, rm, s->T0);
}
}
break;
case 0x106: /* clts */
if (check_cpl0(s)) {
gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0);
gen_helper_clts(tcg_env);
/* abort block because static cpu state changed */
s->base.is_jmp = DISAS_EOB_NEXT;
}
break;
/* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
case 0x1c3: /* MOVNTI reg, mem */
if (!(s->cpuid_features & CPUID_SSE2))
goto illegal_op;
ot = mo_64_32(dflag);
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
if (mod == 3)
goto illegal_op;
reg = ((modrm >> 3) & 7) | REX_R(s);
/* generate a generic store */
gen_ldst_modrm(env, s, modrm, ot, reg, 1);
break;
case 0x1ae:
modrm = x86_ldub_code(env, s);
switch (modrm) {
CASE_MODRM_MEM_OP(0): /* fxsave */
if (!(s->cpuid_features & CPUID_FXSR)
|| (prefixes & PREFIX_LOCK)) {
goto illegal_op;
}
if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
gen_exception(s, EXCP07_PREX);
break;
}
gen_lea_modrm(env, s, modrm);
gen_helper_fxsave(tcg_env, s->A0);
break;
CASE_MODRM_MEM_OP(1): /* fxrstor */
if (!(s->cpuid_features & CPUID_FXSR)
|| (prefixes & PREFIX_LOCK)) {
goto illegal_op;
}
if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
gen_exception(s, EXCP07_PREX);
break;
}
gen_lea_modrm(env, s, modrm);
gen_helper_fxrstor(tcg_env, s->A0);
break;
CASE_MODRM_MEM_OP(2): /* ldmxcsr */
if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK)) {
goto illegal_op;
}
if (s->flags & HF_TS_MASK) {
gen_exception(s, EXCP07_PREX);
break;
}
gen_lea_modrm(env, s, modrm);
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL);
gen_helper_ldmxcsr(tcg_env, s->tmp2_i32);
break;
CASE_MODRM_MEM_OP(3): /* stmxcsr */
if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK)) {
goto illegal_op;
}
if (s->flags & HF_TS_MASK) {
gen_exception(s, EXCP07_PREX);
break;
}
gen_helper_update_mxcsr(tcg_env);
gen_lea_modrm(env, s, modrm);
tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, mxcsr));
gen_op_st_v(s, MO_32, s->T0, s->A0);
break;
CASE_MODRM_MEM_OP(4): /* xsave */
if ((s->cpuid_ext_features & CPUID_EXT_XSAVE) == 0
|| (prefixes & (PREFIX_LOCK | PREFIX_DATA
| PREFIX_REPZ | PREFIX_REPNZ))) {
goto illegal_op;
}
gen_lea_modrm(env, s, modrm);
tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX],
cpu_regs[R_EDX]);
gen_helper_xsave(tcg_env, s->A0, s->tmp1_i64);
break;
CASE_MODRM_MEM_OP(5): /* xrstor */
if ((s->cpuid_ext_features & CPUID_EXT_XSAVE) == 0
|| (prefixes & (PREFIX_LOCK | PREFIX_DATA
| PREFIX_REPZ | PREFIX_REPNZ))) {
goto illegal_op;
}
gen_lea_modrm(env, s, modrm);
tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX],
cpu_regs[R_EDX]);
gen_helper_xrstor(tcg_env, s->A0, s->tmp1_i64);
/* XRSTOR is how MPX is enabled, which changes how
we translate. Thus we need to end the TB. */
s->base.is_jmp = DISAS_EOB_NEXT;
break;
CASE_MODRM_MEM_OP(6): /* xsaveopt / clwb */
if (prefixes & PREFIX_LOCK) {
goto illegal_op;
}
if (prefixes & PREFIX_DATA) {
/* clwb */
if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_CLWB)) {
goto illegal_op;
}
gen_nop_modrm(env, s, modrm);
} else {
/* xsaveopt */
if ((s->cpuid_ext_features & CPUID_EXT_XSAVE) == 0
|| (s->cpuid_xsave_features & CPUID_XSAVE_XSAVEOPT) == 0
|| (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))) {
goto illegal_op;
}
gen_lea_modrm(env, s, modrm);
tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX],
cpu_regs[R_EDX]);
gen_helper_xsaveopt(tcg_env, s->A0, s->tmp1_i64);
}
break;
CASE_MODRM_MEM_OP(7): /* clflush / clflushopt */
if (prefixes & PREFIX_LOCK) {
goto illegal_op;
}
if (prefixes & PREFIX_DATA) {
/* clflushopt */
if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_CLFLUSHOPT)) {
goto illegal_op;
}
} else {
/* clflush */
if ((s->prefix & (PREFIX_REPZ | PREFIX_REPNZ))
|| !(s->cpuid_features & CPUID_CLFLUSH)) {
goto illegal_op;
}
}
gen_nop_modrm(env, s, modrm);
break;
case 0xc0 ... 0xc7: /* rdfsbase (f3 0f ae /0) */
case 0xc8 ... 0xcf: /* rdgsbase (f3 0f ae /1) */
case 0xd0 ... 0xd7: /* wrfsbase (f3 0f ae /2) */
case 0xd8 ... 0xdf: /* wrgsbase (f3 0f ae /3) */
if (CODE64(s)
&& (prefixes & PREFIX_REPZ)
&& !(prefixes & PREFIX_LOCK)
&& (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_FSGSBASE)) {
TCGv base, treg, src, dst;
/* Preserve hflags bits by testing CR4 at runtime. */
tcg_gen_movi_i32(s->tmp2_i32, CR4_FSGSBASE_MASK);
gen_helper_cr4_testbit(tcg_env, s->tmp2_i32);
base = cpu_seg_base[modrm & 8 ? R_GS : R_FS];
treg = cpu_regs[(modrm & 7) | REX_B(s)];
if (modrm & 0x10) {
/* wr*base */
dst = base, src = treg;
} else {
/* rd*base */
dst = treg, src = base;
}
if (s->dflag == MO_32) {
tcg_gen_ext32u_tl(dst, src);
} else {
tcg_gen_mov_tl(dst, src);
}
break;
}
goto unknown_op;
case 0xf8: /* sfence / pcommit */
if (prefixes & PREFIX_DATA) {
/* pcommit */
if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_PCOMMIT)
|| (prefixes & PREFIX_LOCK)) {
goto illegal_op;
}
break;
}
- /* fallthru */
+ fallthrough;
case 0xf9 ... 0xff: /* sfence */
if (!(s->cpuid_features & CPUID_SSE)
|| (prefixes & PREFIX_LOCK)) {
goto illegal_op;
}
tcg_gen_mb(TCG_MO_ST_ST | TCG_BAR_SC);
break;
case 0xe8 ... 0xef: /* lfence */
if (!(s->cpuid_features & CPUID_SSE)
|| (prefixes & PREFIX_LOCK)) {
goto illegal_op;
}
tcg_gen_mb(TCG_MO_LD_LD | TCG_BAR_SC);
break;
case 0xf0 ... 0xf7: /* mfence */
if (!(s->cpuid_features & CPUID_SSE2)
|| (prefixes & PREFIX_LOCK)) {
goto illegal_op;
}
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
break;
default:
goto unknown_op;
}
break;
case 0x10d: /* 3DNow! prefetch(w) */
modrm = x86_ldub_code(env, s);
mod = (modrm >> 6) & 3;
if (mod == 3)
goto illegal_op;
gen_nop_modrm(env, s, modrm);
break;
case 0x1aa: /* rsm */
gen_svm_check_intercept(s, SVM_EXIT_RSM);
if (!(s->flags & HF_SMM_MASK))
goto illegal_op;
#ifdef CONFIG_USER_ONLY
/* we should not be in SMM mode */
g_assert_not_reached();
#else
gen_update_cc_op(s);
gen_update_eip_next(s);
gen_helper_rsm(tcg_env);
#endif /* CONFIG_USER_ONLY */
s->base.is_jmp = DISAS_EOB_ONLY;
break;
case 0x1b8: /* SSE4.2 popcnt */
if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) !=
PREFIX_REPZ)
goto illegal_op;
if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT))
goto illegal_op;
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
if (s->prefix & PREFIX_DATA) {
ot = MO_16;
} else {
ot = mo_64_32(dflag);
}
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_extu(ot, s->T0);
tcg_gen_mov_tl(cpu_cc_src, s->T0);
tcg_gen_ctpop_tl(s->T0, s->T0);
gen_op_mov_reg_v(s, ot, reg, s->T0);
set_cc_op(s, CC_OP_POPCNT);
break;
case 0x10e ... 0x117:
case 0x128 ... 0x12f:
case 0x138 ... 0x13a:
case 0x150 ... 0x179:
case 0x17c ... 0x17f:
case 0x1c2:
case 0x1c4 ... 0x1c6:
case 0x1d0 ... 0x1fe:
disas_insn_new(s, cpu, b);
break;
default:
goto unknown_op;
}
return true;
illegal_op:
gen_illegal_opcode(s);
return true;
unknown_op:
gen_unknown_opcode(env, s);
return true;
}
@@ -7036,31 +7035,30 @@ static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
static void i386_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
switch (dc->base.is_jmp) {
case DISAS_NORETURN:
break;
case DISAS_TOO_MANY:
gen_update_cc_op(dc);
gen_jmp_rel_csize(dc, 0, 0);
break;
case DISAS_EOB_NEXT:
gen_update_cc_op(dc);
gen_update_eip_cur(dc);
- /* fall through */
fallthrough;
case DISAS_EOB_ONLY:
gen_eob(dc);
break;
case DISAS_EOB_INHIBIT_IRQ:
gen_update_cc_op(dc);
gen_update_eip_cur(dc);
gen_eob_inhibit_irq(dc, true);
break;
case DISAS_JUMP:
gen_jr(dc);
break;
default:
g_assert_not_reached();
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 26/78] target/s390x: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (24 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 25/78] target/i386: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 27/78] target/riscv: " Emmanouil Pitsidianakis
` (52 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Richard Henderson, David Hildenbrand,
Ilya Leoshkevich, Thomas Huth, Halil Pasic, Christian Borntraeger,
open list:S390 TCG CPUs
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
target/s390x/cpu.c | 4 ++--
target/s390x/kvm/kvm.c | 2 +-
target/s390x/mmu_helper.c | 6 +++---
target/s390x/tcg/translate.c | 18 +++++++++++-------
target/s390x/tcg/translate_vx.c.inc | 2 +-
5 files changed, 18 insertions(+), 14 deletions(-)
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 4f7599d72c..01df983991 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -150,69 +150,69 @@ static void s390_query_cpu_fast(CPUState *cpu, CpuInfoFast *value)
/* S390CPUClass::reset() */
static void s390_cpu_reset(CPUState *s, cpu_reset_type type)
{
S390CPU *cpu = S390_CPU(s);
S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
CPUS390XState *env = &cpu->env;
DeviceState *dev = DEVICE(s);
scc->parent_reset(dev);
cpu->env.sigp_order = 0;
s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);
switch (type) {
case S390_CPU_RESET_CLEAR:
memset(env, 0, offsetof(CPUS390XState, start_initial_reset_fields));
- /* fall through */
+ fallthrough;
case S390_CPU_RESET_INITIAL:
/* initial reset does not clear everything! */
memset(&env->start_initial_reset_fields, 0,
offsetof(CPUS390XState, start_normal_reset_fields) -
offsetof(CPUS390XState, start_initial_reset_fields));
/* architectured initial value for Breaking-Event-Address register */
env->gbea = 1;
/* architectured initial values for CR 0 and 14 */
env->cregs[0] = CR0_RESET;
env->cregs[14] = CR14_RESET;
#if defined(CONFIG_USER_ONLY)
/* user mode should always be allowed to use the full FPU */
env->cregs[0] |= CR0_AFP;
if (s390_has_feat(S390_FEAT_VECTOR)) {
env->cregs[0] |= CR0_VECTOR;
}
#endif
/* tininess for underflow is detected before rounding */
set_float_detect_tininess(float_tininess_before_rounding,
&env->fpu_status);
- /* fall through */
+ fallthrough;
case S390_CPU_RESET_NORMAL:
env->psw.mask &= ~PSW_MASK_RI;
memset(&env->start_normal_reset_fields, 0,
offsetof(CPUS390XState, end_reset_fields) -
offsetof(CPUS390XState, start_normal_reset_fields));
env->pfault_token = -1UL;
env->bpbc = false;
break;
default:
g_assert_not_reached();
}
/* Reset state inside the kernel that we cannot access yet from QEMU. */
if (kvm_enabled()) {
switch (type) {
case S390_CPU_RESET_CLEAR:
kvm_s390_reset_vcpu_clear(cpu);
break;
case S390_CPU_RESET_INITIAL:
kvm_s390_reset_vcpu_initial(cpu);
break;
case S390_CPU_RESET_NORMAL:
kvm_s390_reset_vcpu_normal(cpu);
break;
}
}
}
diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c
index bc5c56a305..11b2c05df6 100644
--- a/target/s390x/kvm/kvm.c
+++ b/target/s390x/kvm/kvm.c
@@ -1080,48 +1080,48 @@ int kvm_arch_process_async_events(CPUState *cs)
static int s390_kvm_irq_to_interrupt(struct kvm_s390_irq *irq,
struct kvm_s390_interrupt *interrupt)
{
int r = 0;
interrupt->type = irq->type;
switch (irq->type) {
case KVM_S390_INT_VIRTIO:
interrupt->parm = irq->u.ext.ext_params;
- /* fall through */
+ fallthrough;
case KVM_S390_INT_PFAULT_INIT:
case KVM_S390_INT_PFAULT_DONE:
interrupt->parm64 = irq->u.ext.ext_params2;
break;
case KVM_S390_PROGRAM_INT:
interrupt->parm = irq->u.pgm.code;
break;
case KVM_S390_SIGP_SET_PREFIX:
interrupt->parm = irq->u.prefix.address;
break;
case KVM_S390_INT_SERVICE:
interrupt->parm = irq->u.ext.ext_params;
break;
case KVM_S390_MCHK:
interrupt->parm = irq->u.mchk.cr14;
interrupt->parm64 = irq->u.mchk.mcic;
break;
case KVM_S390_INT_EXTERNAL_CALL:
interrupt->parm = irq->u.extcall.code;
break;
case KVM_S390_INT_EMERGENCY:
interrupt->parm = irq->u.emerg.code;
break;
case KVM_S390_SIGP_STOP:
case KVM_S390_RESTART:
break; /* These types have no parameters */
case KVM_S390_INT_IO_MIN...KVM_S390_INT_IO_MAX:
interrupt->parm = irq->u.io.subchannel_id << 16;
interrupt->parm |= irq->u.io.subchannel_nr;
interrupt->parm64 = (uint64_t)irq->u.io.io_int_parm << 32;
interrupt->parm64 |= irq->u.io.io_int_word;
break;
default:
r = -EINVAL;
break;
}
return r;
}
diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
index fbb2f1b4d4..5833917552 100644
--- a/target/s390x/mmu_helper.c
+++ b/target/s390x/mmu_helper.c
@@ -126,173 +126,173 @@ static inline bool read_table_entry(CPUS390XState *env, hwaddr gaddr,
static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
uint64_t asc, uint64_t asce, target_ulong *raddr,
int *flags)
{
const bool edat1 = (env->cregs[0] & CR0_EDAT) &&
s390_has_feat(S390_FEAT_EDAT);
const bool edat2 = edat1 && s390_has_feat(S390_FEAT_EDAT_2);
const bool iep = (env->cregs[0] & CR0_IEP) &&
s390_has_feat(S390_FEAT_INSTRUCTION_EXEC_PROT);
const int asce_tl = asce & ASCE_TABLE_LENGTH;
const int asce_p = asce & ASCE_PRIVATE_SPACE;
hwaddr gaddr = asce & ASCE_ORIGIN;
uint64_t entry;
if (asce & ASCE_REAL_SPACE) {
/* direct mapping */
*raddr = vaddr;
return 0;
}
switch (asce & ASCE_TYPE_MASK) {
case ASCE_TYPE_REGION1:
if (VADDR_REGION1_TL(vaddr) > asce_tl) {
return PGM_REG_FIRST_TRANS;
}
gaddr += VADDR_REGION1_TX(vaddr) * 8;
break;
case ASCE_TYPE_REGION2:
if (VADDR_REGION1_TX(vaddr)) {
return PGM_ASCE_TYPE;
}
if (VADDR_REGION2_TL(vaddr) > asce_tl) {
return PGM_REG_SEC_TRANS;
}
gaddr += VADDR_REGION2_TX(vaddr) * 8;
break;
case ASCE_TYPE_REGION3:
if (VADDR_REGION1_TX(vaddr) || VADDR_REGION2_TX(vaddr)) {
return PGM_ASCE_TYPE;
}
if (VADDR_REGION3_TL(vaddr) > asce_tl) {
return PGM_REG_THIRD_TRANS;
}
gaddr += VADDR_REGION3_TX(vaddr) * 8;
break;
case ASCE_TYPE_SEGMENT:
if (VADDR_REGION1_TX(vaddr) || VADDR_REGION2_TX(vaddr) ||
VADDR_REGION3_TX(vaddr)) {
return PGM_ASCE_TYPE;
}
if (VADDR_SEGMENT_TL(vaddr) > asce_tl) {
return PGM_SEGMENT_TRANS;
}
gaddr += VADDR_SEGMENT_TX(vaddr) * 8;
break;
}
switch (asce & ASCE_TYPE_MASK) {
case ASCE_TYPE_REGION1:
if (!read_table_entry(env, gaddr, &entry)) {
return PGM_ADDRESSING;
}
if (entry & REGION_ENTRY_I) {
return PGM_REG_FIRST_TRANS;
}
if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION1) {
return PGM_TRANS_SPEC;
}
if (VADDR_REGION2_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
VADDR_REGION2_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
return PGM_REG_SEC_TRANS;
}
if (edat1 && (entry & REGION_ENTRY_P)) {
*flags &= ~PAGE_WRITE;
}
gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION2_TX(vaddr) * 8;
- /* fall through */
+ fallthrough;
case ASCE_TYPE_REGION2:
if (!read_table_entry(env, gaddr, &entry)) {
return PGM_ADDRESSING;
}
if (entry & REGION_ENTRY_I) {
return PGM_REG_SEC_TRANS;
}
if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION2) {
return PGM_TRANS_SPEC;
}
if (VADDR_REGION3_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
VADDR_REGION3_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
return PGM_REG_THIRD_TRANS;
}
if (edat1 && (entry & REGION_ENTRY_P)) {
*flags &= ~PAGE_WRITE;
}
gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION3_TX(vaddr) * 8;
- /* fall through */
+ fallthrough;
case ASCE_TYPE_REGION3:
if (!read_table_entry(env, gaddr, &entry)) {
return PGM_ADDRESSING;
}
if (entry & REGION_ENTRY_I) {
return PGM_REG_THIRD_TRANS;
}
if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION3) {
return PGM_TRANS_SPEC;
}
if (edat2 && (entry & REGION3_ENTRY_CR) && asce_p) {
return PGM_TRANS_SPEC;
}
if (edat1 && (entry & REGION_ENTRY_P)) {
*flags &= ~PAGE_WRITE;
}
if (edat2 && (entry & REGION3_ENTRY_FC)) {
if (iep && (entry & REGION3_ENTRY_IEP)) {
*flags &= ~PAGE_EXEC;
}
*raddr = (entry & REGION3_ENTRY_RFAA) |
(vaddr & ~REGION3_ENTRY_RFAA);
return 0;
}
if (VADDR_SEGMENT_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
VADDR_SEGMENT_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
return PGM_SEGMENT_TRANS;
}
gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_SEGMENT_TX(vaddr) * 8;
- /* fall through */
+ fallthrough;
case ASCE_TYPE_SEGMENT:
if (!read_table_entry(env, gaddr, &entry)) {
return PGM_ADDRESSING;
}
if (entry & SEGMENT_ENTRY_I) {
return PGM_SEGMENT_TRANS;
}
if ((entry & SEGMENT_ENTRY_TT) != SEGMENT_ENTRY_TT_SEGMENT) {
return PGM_TRANS_SPEC;
}
if ((entry & SEGMENT_ENTRY_CS) && asce_p) {
return PGM_TRANS_SPEC;
}
if (entry & SEGMENT_ENTRY_P) {
*flags &= ~PAGE_WRITE;
}
if (edat1 && (entry & SEGMENT_ENTRY_FC)) {
if (iep && (entry & SEGMENT_ENTRY_IEP)) {
*flags &= ~PAGE_EXEC;
}
*raddr = (entry & SEGMENT_ENTRY_SFAA) |
(vaddr & ~SEGMENT_ENTRY_SFAA);
return 0;
}
gaddr = (entry & SEGMENT_ENTRY_ORIGIN) + VADDR_PAGE_TX(vaddr) * 8;
break;
}
if (!read_table_entry(env, gaddr, &entry)) {
return PGM_ADDRESSING;
}
if (entry & PAGE_ENTRY_I) {
return PGM_PAGE_TRANS;
}
if (entry & PAGE_ENTRY_0) {
return PGM_TRANS_SPEC;
}
if (entry & PAGE_ENTRY_P) {
*flags &= ~PAGE_WRITE;
}
if (iep && (entry & PAGE_ENTRY_IEP)) {
*flags &= ~PAGE_EXEC;
}
*raddr = entry & TARGET_PAGE_MASK;
return 0;
}
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 4bae1509f5..986d6433d2 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -569,90 +569,91 @@ static void set_cc_static(DisasContext *s)
/* calculates cc into cc_op */
static void gen_op_calc_cc(DisasContext *s)
{
TCGv_i32 local_cc_op = NULL;
TCGv_i64 dummy = NULL;
switch (s->cc_op) {
default:
dummy = tcg_constant_i64(0);
/* FALLTHRU */
+ fallthrough;
case CC_OP_ADD_64:
case CC_OP_SUB_64:
case CC_OP_ADD_32:
case CC_OP_SUB_32:
local_cc_op = tcg_constant_i32(s->cc_op);
break;
case CC_OP_CONST0:
case CC_OP_CONST1:
case CC_OP_CONST2:
case CC_OP_CONST3:
case CC_OP_STATIC:
case CC_OP_DYNAMIC:
break;
}
switch (s->cc_op) {
case CC_OP_CONST0:
case CC_OP_CONST1:
case CC_OP_CONST2:
case CC_OP_CONST3:
/* s->cc_op is the cc value */
tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
break;
case CC_OP_STATIC:
/* env->cc_op already is the cc value */
break;
case CC_OP_NZ:
tcg_gen_setcondi_i64(TCG_COND_NE, cc_dst, cc_dst, 0);
tcg_gen_extrl_i64_i32(cc_op, cc_dst);
break;
case CC_OP_ABS_64:
case CC_OP_NABS_64:
case CC_OP_ABS_32:
case CC_OP_NABS_32:
case CC_OP_LTGT0_32:
case CC_OP_LTGT0_64:
case CC_OP_COMP_32:
case CC_OP_COMP_64:
case CC_OP_NZ_F32:
case CC_OP_NZ_F64:
case CC_OP_FLOGR:
case CC_OP_LCBB:
case CC_OP_MULS_32:
/* 1 argument */
gen_helper_calc_cc(cc_op, tcg_env, local_cc_op, dummy, cc_dst, dummy);
break;
case CC_OP_ADDU:
case CC_OP_ICM:
case CC_OP_LTGT_32:
case CC_OP_LTGT_64:
case CC_OP_LTUGTU_32:
case CC_OP_LTUGTU_64:
case CC_OP_TM_32:
case CC_OP_TM_64:
case CC_OP_SLA:
case CC_OP_SUBU:
case CC_OP_NZ_F128:
case CC_OP_VC:
case CC_OP_MULS_64:
/* 2 arguments */
gen_helper_calc_cc(cc_op, tcg_env, local_cc_op, cc_src, cc_dst, dummy);
break;
case CC_OP_ADD_64:
case CC_OP_SUB_64:
case CC_OP_ADD_32:
case CC_OP_SUB_32:
/* 3 arguments */
gen_helper_calc_cc(cc_op, tcg_env, local_cc_op, cc_src, cc_dst, cc_vr);
break;
case CC_OP_DYNAMIC:
/* unknown operation - assume 3 arguments and cc_op in env */
gen_helper_calc_cc(cc_op, tcg_env, cc_op, cc_src, cc_dst, cc_vr);
break;
default:
g_assert_not_reached();
}
/* We now have cc in cc_op as constant */
set_cc_static(s);
}
@@ -708,263 +709,264 @@ static const TCGCond nz_cond[16] = {
/* Interpret MASK in terms of S->CC_OP, and fill in C with all the
details required to generate a TCG comparison. */
static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
{
TCGCond cond;
enum cc_op old_cc_op = s->cc_op;
if (mask == 15 || mask == 0) {
c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER);
c->u.s32.a = cc_op;
c->u.s32.b = cc_op;
c->is_64 = false;
return;
}
/* Find the TCG condition for the mask + cc op. */
switch (old_cc_op) {
case CC_OP_LTGT0_32:
case CC_OP_LTGT0_64:
case CC_OP_LTGT_32:
case CC_OP_LTGT_64:
cond = ltgt_cond[mask];
if (cond == TCG_COND_NEVER) {
goto do_dynamic;
}
account_inline_branch(s, old_cc_op);
break;
case CC_OP_LTUGTU_32:
case CC_OP_LTUGTU_64:
cond = tcg_unsigned_cond(ltgt_cond[mask]);
if (cond == TCG_COND_NEVER) {
goto do_dynamic;
}
account_inline_branch(s, old_cc_op);
break;
case CC_OP_NZ:
cond = nz_cond[mask];
if (cond == TCG_COND_NEVER) {
goto do_dynamic;
}
account_inline_branch(s, old_cc_op);
break;
case CC_OP_TM_32:
case CC_OP_TM_64:
switch (mask) {
case 8:
cond = TCG_COND_EQ;
break;
case 4 | 2 | 1:
cond = TCG_COND_NE;
break;
default:
goto do_dynamic;
}
account_inline_branch(s, old_cc_op);
break;
case CC_OP_ICM:
switch (mask) {
case 8:
cond = TCG_COND_EQ;
break;
case 4 | 2 | 1:
case 4 | 2:
cond = TCG_COND_NE;
break;
default:
goto do_dynamic;
}
account_inline_branch(s, old_cc_op);
break;
case CC_OP_FLOGR:
switch (mask & 0xa) {
case 8: /* src == 0 -> no one bit found */
cond = TCG_COND_EQ;
break;
case 2: /* src != 0 -> one bit found */
cond = TCG_COND_NE;
break;
default:
goto do_dynamic;
}
account_inline_branch(s, old_cc_op);
break;
case CC_OP_ADDU:
case CC_OP_SUBU:
switch (mask) {
case 8 | 2: /* result == 0 */
cond = TCG_COND_EQ;
break;
case 4 | 1: /* result != 0 */
cond = TCG_COND_NE;
break;
case 8 | 4: /* !carry (borrow) */
cond = old_cc_op == CC_OP_ADDU ? TCG_COND_EQ : TCG_COND_NE;
break;
case 2 | 1: /* carry (!borrow) */
cond = old_cc_op == CC_OP_ADDU ? TCG_COND_NE : TCG_COND_EQ;
break;
default:
goto do_dynamic;
}
account_inline_branch(s, old_cc_op);
break;
default:
do_dynamic:
/* Calculate cc value. */
gen_op_calc_cc(s);
/* FALLTHRU */
+ fallthrough;
case CC_OP_STATIC:
/* Jump based on CC. We'll load up the real cond below;
the assignment here merely avoids a compiler warning. */
account_noninline_branch(s, old_cc_op);
old_cc_op = CC_OP_STATIC;
cond = TCG_COND_NEVER;
break;
}
/* Load up the arguments of the comparison. */
c->is_64 = true;
switch (old_cc_op) {
case CC_OP_LTGT0_32:
c->is_64 = false;
c->u.s32.a = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(c->u.s32.a, cc_dst);
c->u.s32.b = tcg_constant_i32(0);
break;
case CC_OP_LTGT_32:
case CC_OP_LTUGTU_32:
c->is_64 = false;
c->u.s32.a = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(c->u.s32.a, cc_src);
c->u.s32.b = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(c->u.s32.b, cc_dst);
break;
case CC_OP_LTGT0_64:
case CC_OP_NZ:
case CC_OP_FLOGR:
c->u.s64.a = cc_dst;
c->u.s64.b = tcg_constant_i64(0);
break;
case CC_OP_LTGT_64:
case CC_OP_LTUGTU_64:
c->u.s64.a = cc_src;
c->u.s64.b = cc_dst;
break;
case CC_OP_TM_32:
case CC_OP_TM_64:
case CC_OP_ICM:
c->u.s64.a = tcg_temp_new_i64();
c->u.s64.b = tcg_constant_i64(0);
tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
break;
case CC_OP_ADDU:
case CC_OP_SUBU:
c->is_64 = true;
c->u.s64.b = tcg_constant_i64(0);
switch (mask) {
case 8 | 2:
case 4 | 1: /* result */
c->u.s64.a = cc_dst;
break;
case 8 | 4:
case 2 | 1: /* carry */
c->u.s64.a = cc_src;
break;
default:
g_assert_not_reached();
}
break;
case CC_OP_STATIC:
c->is_64 = false;
c->u.s32.a = cc_op;
switch (mask) {
case 0x8 | 0x4 | 0x2: /* cc != 3 */
cond = TCG_COND_NE;
c->u.s32.b = tcg_constant_i32(3);
break;
case 0x8 | 0x4 | 0x1: /* cc != 2 */
cond = TCG_COND_NE;
c->u.s32.b = tcg_constant_i32(2);
break;
case 0x8 | 0x2 | 0x1: /* cc != 1 */
cond = TCG_COND_NE;
c->u.s32.b = tcg_constant_i32(1);
break;
case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
cond = TCG_COND_EQ;
c->u.s32.a = tcg_temp_new_i32();
c->u.s32.b = tcg_constant_i32(0);
tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
break;
case 0x8 | 0x4: /* cc < 2 */
cond = TCG_COND_LTU;
c->u.s32.b = tcg_constant_i32(2);
break;
case 0x8: /* cc == 0 */
cond = TCG_COND_EQ;
c->u.s32.b = tcg_constant_i32(0);
break;
case 0x4 | 0x2 | 0x1: /* cc != 0 */
cond = TCG_COND_NE;
c->u.s32.b = tcg_constant_i32(0);
break;
case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
cond = TCG_COND_NE;
c->u.s32.a = tcg_temp_new_i32();
c->u.s32.b = tcg_constant_i32(0);
tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
break;
case 0x4: /* cc == 1 */
cond = TCG_COND_EQ;
c->u.s32.b = tcg_constant_i32(1);
break;
case 0x2 | 0x1: /* cc > 1 */
cond = TCG_COND_GTU;
c->u.s32.b = tcg_constant_i32(1);
break;
case 0x2: /* cc == 2 */
cond = TCG_COND_EQ;
c->u.s32.b = tcg_constant_i32(2);
break;
case 0x1: /* cc == 3 */
cond = TCG_COND_EQ;
c->u.s32.b = tcg_constant_i32(3);
break;
default:
/* CC is masked by something else: (8 >> cc) & mask. */
cond = TCG_COND_NE;
c->u.s32.a = tcg_temp_new_i32();
c->u.s32.b = tcg_constant_i32(0);
tcg_gen_shr_i32(c->u.s32.a, tcg_constant_i32(8), cc_op);
tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
break;
}
break;
default:
abort();
}
c->cond = cond;
}
/* ====================================================================== */
/* Define the insn format enumeration. */
#define F0(N) FMT_##N,
#define F1(N, X1) F0(N)
#define F2(N, X1, X2) F0(N)
#define F3(N, X1, X2, X3) F0(N)
#define F4(N, X1, X2, X3, X4) F0(N)
#define F5(N, X1, X2, X3, X4, X5) F0(N)
#define F6(N, X1, X2, X3, X4, X5, X6) F0(N)
@@ -1314,20 +1316,20 @@ static DisasJumpType op_addu64(DisasContext *s, DisasOps *o)
/* Compute carry into cc_src. */
static void compute_carry(DisasContext *s)
{
switch (s->cc_op) {
case CC_OP_ADDU:
/* The carry value is already in cc_src (1,0). */
break;
case CC_OP_SUBU:
tcg_gen_addi_i64(cc_src, cc_src, 1);
break;
default:
gen_op_calc_cc(s);
- /* fall through */
+ fallthrough;
case CC_OP_STATIC:
/* The carry flag is the msb of CC; compute into cc_src. */
tcg_gen_extu_i32_i64(cc_src, cc_op);
tcg_gen_shri_i64(cc_src, cc_src, 1);
break;
}
}
@@ -2602,53 +2604,53 @@ static DisasJumpType op_iske(DisasContext *s, DisasOps *o)
static DisasJumpType op_msa(DisasContext *s, DisasOps *o)
{
int r1 = have_field(s, r1) ? get_field(s, r1) : 0;
int r2 = have_field(s, r2) ? get_field(s, r2) : 0;
int r3 = have_field(s, r3) ? get_field(s, r3) : 0;
TCGv_i32 t_r1, t_r2, t_r3, type;
switch (s->insn->data) {
case S390_FEAT_TYPE_KMA:
if (r3 == r1 || r3 == r2) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- /* FALL THROUGH */
+ fallthrough;
case S390_FEAT_TYPE_KMCTR:
if (r3 & 1 || !r3) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- /* FALL THROUGH */
+ fallthrough;
case S390_FEAT_TYPE_PPNO:
case S390_FEAT_TYPE_KMF:
case S390_FEAT_TYPE_KMC:
case S390_FEAT_TYPE_KMO:
case S390_FEAT_TYPE_KM:
if (r1 & 1 || !r1) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- /* FALL THROUGH */
+ fallthrough;
case S390_FEAT_TYPE_KMAC:
case S390_FEAT_TYPE_KIMD:
case S390_FEAT_TYPE_KLMD:
if (r2 & 1 || !r2) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- /* FALL THROUGH */
+ fallthrough;
case S390_FEAT_TYPE_PCKMO:
case S390_FEAT_TYPE_PCC:
break;
default:
g_assert_not_reached();
};
t_r1 = tcg_constant_i32(r1);
t_r2 = tcg_constant_i32(r2);
t_r3 = tcg_constant_i32(r3);
type = tcg_constant_i32(s->insn->data);
gen_helper_msa(cc_op, tcg_env, t_r1, t_r2, t_r3, type);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -4579,21 +4581,21 @@ static DisasJumpType op_subu64(DisasContext *s, DisasOps *o)
/* Compute borrow (0, -1) into cc_src. */
static void compute_borrow(DisasContext *s)
{
switch (s->cc_op) {
case CC_OP_SUBU:
/* The borrow value is already in cc_src (0,-1). */
break;
default:
gen_op_calc_cc(s);
- /* fall through */
+ fallthrough;
case CC_OP_STATIC:
/* The carry flag is the msb of CC; compute into cc_src. */
tcg_gen_extu_i32_i64(cc_src, cc_op);
tcg_gen_shri_i64(cc_src, cc_src, 1);
- /* fall through */
+ fallthrough;
case CC_OP_ADDU:
/* Convert carry (1,0) to borrow (0,-1). */
tcg_gen_subi_i64(cc_src, cc_src, 1);
break;
}
}
@@ -6479,27 +6481,29 @@ static void s390x_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
static void s390x_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
switch (dc->base.is_jmp) {
case DISAS_NORETURN:
break;
case DISAS_TOO_MANY:
update_psw_addr(dc);
/* FALLTHRU */
+ fallthrough;
case DISAS_PC_UPDATED:
/* Next TB starts off with CC_OP_DYNAMIC, so make sure the
cc op type is in env */
update_cc_op(dc);
/* FALLTHRU */
+ fallthrough;
case DISAS_PC_CC_UPDATED:
/* Exit the TB, either by raising a debug exception or by return. */
if (dc->exit_to_mainloop) {
tcg_gen_exit_tb(NULL, 0);
} else {
tcg_gen_lookup_and_goto_ptr();
}
break;
default:
g_assert_not_reached();
}
}
diff --git a/target/s390x/tcg/translate_vx.c.inc b/target/s390x/tcg/translate_vx.c.inc
index e073e5ad3a..75463b4f5c 100644
--- a/target/s390x/tcg/translate_vx.c.inc
+++ b/target/s390x/tcg/translate_vx.c.inc
@@ -662,39 +662,39 @@ static DisasJumpType op_vlgv(DisasContext *s, DisasOps *o)
static DisasJumpType op_vllez(DisasContext *s, DisasOps *o)
{
uint8_t es = get_field(s, m3);
uint8_t enr;
TCGv_i64 t;
switch (es) {
/* rightmost sub-element of leftmost doubleword */
case ES_8:
enr = 7;
break;
case ES_16:
enr = 3;
break;
case ES_32:
enr = 1;
break;
case ES_64:
enr = 0;
break;
/* leftmost sub-element of leftmost doubleword */
case 6:
if (s390_has_feat(S390_FEAT_VECTOR_ENH)) {
es = ES_32;
enr = 0;
break;
}
- /* fallthrough */
+ fallthrough;
default:
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
t = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es);
gen_gvec_dup_imm(es, get_field(s, v1), 0);
write_vec_element_i64(t, get_field(s, v1), enr, es);
return DISAS_NEXT;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 27/78] target/riscv: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (25 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 26/78] target/s390x: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 28/78] target/avr: " Emmanouil Pitsidianakis
` (51 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
open list:RISC-V TCG CPUs
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
target/riscv/insn_trans/trans_rvi.c.inc | 2 +-
target/riscv/insn_trans/trans_rvzce.c.inc | 22 +++++++++++-----------
target/riscv/translate.c | 4 ++--
3 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 25cb60558a..98dd2e3cf6 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -89,61 +89,61 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
static TCGCond gen_compare_i128(bool bz, TCGv rl,
TCGv al, TCGv ah, TCGv bl, TCGv bh,
TCGCond cond)
{
TCGv rh = tcg_temp_new();
bool invert = false;
switch (cond) {
case TCG_COND_EQ:
case TCG_COND_NE:
if (bz) {
tcg_gen_or_tl(rl, al, ah);
} else {
tcg_gen_xor_tl(rl, al, bl);
tcg_gen_xor_tl(rh, ah, bh);
tcg_gen_or_tl(rl, rl, rh);
}
break;
case TCG_COND_GE:
case TCG_COND_LT:
if (bz) {
tcg_gen_mov_tl(rl, ah);
} else {
TCGv tmp = tcg_temp_new();
tcg_gen_sub2_tl(rl, rh, al, ah, bl, bh);
tcg_gen_xor_tl(rl, rh, ah);
tcg_gen_xor_tl(tmp, ah, bh);
tcg_gen_and_tl(rl, rl, tmp);
tcg_gen_xor_tl(rl, rh, rl);
}
break;
case TCG_COND_LTU:
invert = true;
- /* fallthrough */
+ fallthrough;
case TCG_COND_GEU:
{
TCGv tmp = tcg_temp_new();
TCGv zero = tcg_constant_tl(0);
TCGv one = tcg_constant_tl(1);
cond = TCG_COND_NE;
/* borrow in to second word */
tcg_gen_setcond_tl(TCG_COND_LTU, tmp, al, bl);
/* seed third word with 1, which will be result */
tcg_gen_sub2_tl(tmp, rh, ah, one, tmp, zero);
tcg_gen_sub2_tl(tmp, rl, tmp, rh, bh, zero);
}
break;
default:
g_assert_not_reached();
}
if (invert) {
cond = tcg_invert_cond(cond);
}
return cond;
}
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
index 2d992e14c4..f0bcbb4f72 100644
--- a/target/riscv/insn_trans/trans_rvzce.c.inc
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
@@ -116,52 +116,52 @@ static bool trans_c_sh(DisasContext *ctx, arg_c_sh *a)
static uint32_t decode_push_pop_list(DisasContext *ctx, target_ulong rlist)
{
uint32_t reg_bitmap = 0;
if (has_ext(ctx, RVE) && rlist > 6) {
return 0;
}
switch (rlist) {
case 15:
reg_bitmap |= 1 << (X_Sn + 11) ;
reg_bitmap |= 1 << (X_Sn + 10) ;
- /* FALL THROUGH */
+ fallthrough;
case 14:
reg_bitmap |= 1 << (X_Sn + 9) ;
- /* FALL THROUGH */
+ fallthrough;
case 13:
reg_bitmap |= 1 << (X_Sn + 8) ;
- /* FALL THROUGH */
+ fallthrough;
case 12:
reg_bitmap |= 1 << (X_Sn + 7) ;
- /* FALL THROUGH */
+ fallthrough;
case 11:
reg_bitmap |= 1 << (X_Sn + 6) ;
- /* FALL THROUGH */
+ fallthrough;
case 10:
reg_bitmap |= 1 << (X_Sn + 5) ;
- /* FALL THROUGH */
+ fallthrough;
case 9:
reg_bitmap |= 1 << (X_Sn + 4) ;
- /* FALL THROUGH */
+ fallthrough;
case 8:
reg_bitmap |= 1 << (X_Sn + 3) ;
- /* FALL THROUGH */
+ fallthrough;
case 7:
reg_bitmap |= 1 << (X_Sn + 2) ;
- /* FALL THROUGH */
+ fallthrough;
case 6:
reg_bitmap |= 1 << X_S1 ;
- /* FALL THROUGH */
+ fallthrough;
case 5:
reg_bitmap |= 1 << X_S0;
- /* FALL THROUGH */
+ fallthrough;
case 4:
reg_bitmap |= 1 << xRA;
break;
default:
break;
}
return reg_bitmap;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f0be79bb16..c99e513221 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -431,26 +431,26 @@ static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh)
static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num)
{
if (!ctx->cfg_ptr->ext_zfinx) {
return cpu_fpr[reg_num];
}
if (reg_num == 0) {
return tcg_constant_i64(0);
}
switch (get_xl(ctx)) {
case MXL_RV32:
#ifdef TARGET_RISCV32
{
TCGv_i64 t = tcg_temp_new_i64();
tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]);
return t;
}
#else
- /* fall through */
+ fallthrough;
case MXL_RV64:
return cpu_gpr[reg_num];
#endif
default:
g_assert_not_reached();
}
}
@@ -505,24 +505,24 @@ static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num)
/* assume it is nanboxing (for normal) or sign-extended (for zfinx) */
static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t)
{
if (!ctx->cfg_ptr->ext_zfinx) {
tcg_gen_mov_i64(cpu_fpr[reg_num], t);
return;
}
if (reg_num != 0) {
switch (get_xl(ctx)) {
case MXL_RV32:
#ifdef TARGET_RISCV32
tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t);
break;
#else
- /* fall through */
+ fallthrough;
case MXL_RV64:
tcg_gen_mov_i64(cpu_gpr[reg_num], t);
break;
#endif
default:
g_assert_not_reached();
}
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 28/78] target/avr: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (26 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 27/78] target/riscv: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 29/78] target/cris: " Emmanouil Pitsidianakis
` (50 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Michael Rolnik
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
target/avr/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index cdffa04519..2043677745 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -2753,37 +2753,37 @@ static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
static void avr_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
bool nonconst_skip = canonicalize_skip(ctx);
/*
* Because we disable interrupts while env->skip is set,
* we must return to the main loop to re-evaluate afterward.
*/
bool force_exit = ctx->base.tb->flags & TB_FLAGS_SKIP;
switch (ctx->base.is_jmp) {
case DISAS_NORETURN:
assert(!nonconst_skip);
break;
case DISAS_NEXT:
case DISAS_TOO_MANY:
case DISAS_CHAIN:
if (!nonconst_skip && !force_exit) {
/* Note gen_goto_tb checks singlestep. */
gen_goto_tb(ctx, 1, ctx->npc);
break;
}
tcg_gen_movi_tl(cpu_pc, ctx->npc);
- /* fall through */
+ fallthrough;
case DISAS_LOOKUP:
if (!force_exit) {
tcg_gen_lookup_and_goto_ptr();
break;
}
- /* fall through */
+ fallthrough;
case DISAS_EXIT:
tcg_gen_exit_tb(NULL, 0);
break;
default:
g_assert_not_reached();
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 29/78] target/cris: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (27 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 28/78] target/avr: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 30/78] target/nios2: " Emmanouil Pitsidianakis
` (49 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Edgar E. Iglesias
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
target/cris/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/cris/translate.c b/target/cris/translate.c
index b3974ba0bb..bdd128db23 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -3061,94 +3061,94 @@ static void cris_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
static void cris_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
DisasJumpType is_jmp = dc->base.is_jmp;
target_ulong npc = dc->pc;
if (is_jmp == DISAS_NORETURN) {
/* If we have a broken branch+delayslot sequence, it's too late. */
assert(dc->delayed_branch != 1);
return;
}
if (dc->clear_locked_irq) {
t_gen_movi_env_TN(locked_irq, 0);
}
/* Broken branch+delayslot sequence. */
if (dc->delayed_branch == 1) {
/* Set env->dslot to the size of the branch insn. */
t_gen_movi_env_TN(dslot, dc->pc - dc->ppc);
cris_store_direct_jmp(dc);
}
cris_evaluate_flags(dc);
/* Evaluate delayed branch destination and fold to another is_jmp case. */
if (is_jmp == DISAS_DBRANCH) {
if (dc->base.tb->flags & 7) {
t_gen_movi_env_TN(dslot, 0);
}
switch (dc->jmp) {
case JMP_DIRECT:
npc = dc->jmp_pc;
is_jmp = dc->cpustate_changed ? DISAS_UPDATE_NEXT : DISAS_TOO_MANY;
break;
case JMP_DIRECT_CC:
/*
* Use a conditional branch if either taken or not-taken path
* can use goto_tb. If neither can, then treat it as indirect.
*/
if (likely(!dc->cpustate_changed)
&& (use_goto_tb(dc, dc->jmp_pc) || use_goto_tb(dc, npc))) {
TCGLabel *not_taken = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, not_taken);
gen_goto_tb(dc, 1, dc->jmp_pc);
gen_set_label(not_taken);
/* not-taken case handled below. */
is_jmp = DISAS_TOO_MANY;
break;
}
tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
- /* fall through */
+ fallthrough;
case JMP_INDIRECT:
tcg_gen_movcond_tl(TCG_COND_NE, env_pc,
env_btaken, tcg_constant_tl(0),
env_btarget, tcg_constant_tl(npc));
is_jmp = dc->cpustate_changed ? DISAS_UPDATE : DISAS_JUMP;
/*
* We have now consumed btaken and btarget. Hint to the
* tcg compiler that the writeback to env may be dropped.
*/
tcg_gen_discard_tl(env_btaken);
tcg_gen_discard_tl(env_btarget);
break;
default:
g_assert_not_reached();
}
}
switch (is_jmp) {
case DISAS_TOO_MANY:
gen_goto_tb(dc, 0, npc);
break;
case DISAS_UPDATE_NEXT:
tcg_gen_movi_tl(env_pc, npc);
- /* fall through */
+ fallthrough;
case DISAS_JUMP:
tcg_gen_lookup_and_goto_ptr();
break;
case DISAS_UPDATE:
/* Indicate that interrupts must be re-evaluated before the next TB. */
tcg_gen_exit_tb(NULL, 0);
break;
default:
g_assert_not_reached();
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 30/78] target/nios2: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (28 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 29/78] target/cris: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:56 ` [RFC PATCH v2 31/78] target/xtensa: " Emmanouil Pitsidianakis
` (48 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Chris Wulff, Marek Vasut
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
target/nios2/helper.c | 6 +++---
target/nios2/translate.c | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index bb3b09e5a7..b44e73768e 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -125,136 +125,136 @@ static void do_eic_irq(Nios2CPU *cpu)
void nios2_cpu_do_interrupt(CPUState *cs)
{
Nios2CPU *cpu = NIOS2_CPU(cs);
CPUNios2State *env = &cpu->env;
uint32_t tlbmisc_set = 0;
if (qemu_loglevel_mask(CPU_LOG_INT)) {
const char *name = NULL;
switch (cs->exception_index) {
case EXCP_IRQ:
name = "interrupt";
break;
case EXCP_TLB_X:
case EXCP_TLB_D:
if (env->ctrl[CR_STATUS] & CR_STATUS_EH) {
name = "TLB MISS (double)";
} else {
name = "TLB MISS (fast)";
}
break;
case EXCP_PERM_R:
case EXCP_PERM_W:
case EXCP_PERM_X:
name = "TLB PERM";
break;
case EXCP_SUPERA_X:
case EXCP_SUPERA_D:
name = "SUPERVISOR (address)";
break;
case EXCP_SUPERI:
name = "SUPERVISOR (insn)";
break;
case EXCP_ILLEGAL:
name = "ILLEGAL insn";
break;
case EXCP_UNALIGN:
name = "Misaligned (data)";
break;
case EXCP_UNALIGND:
name = "Misaligned (destination)";
break;
case EXCP_DIV:
name = "DIV error";
break;
case EXCP_TRAP:
name = "TRAP insn";
break;
case EXCP_BREAK:
name = "BREAK insn";
break;
case EXCP_SEMIHOST:
name = "SEMIHOST insn";
break;
}
if (name) {
qemu_log("%s at pc=0x%08x\n", name, env->pc);
} else {
qemu_log("Unknown exception %d at pc=0x%08x\n",
cs->exception_index, env->pc);
}
}
switch (cs->exception_index) {
case EXCP_IRQ:
/* Note that PC is advanced for interrupts as well. */
env->pc += 4;
if (cpu->eic_present) {
do_eic_irq(cpu);
} else {
do_iic_irq(cpu);
}
break;
case EXCP_TLB_D:
tlbmisc_set = CR_TLBMISC_D;
- /* fall through */
+ fallthrough;
case EXCP_TLB_X:
if (env->ctrl[CR_STATUS] & CR_STATUS_EH) {
tlbmisc_set |= CR_TLBMISC_DBL;
/*
* Normally, we don't write to tlbmisc unless !EH,
* so do it manually for the double-tlb miss exception.
*/
env->ctrl[CR_TLBMISC] &= ~(CR_TLBMISC_D |
CR_TLBMISC_PERM |
CR_TLBMISC_BAD);
env->ctrl[CR_TLBMISC] |= tlbmisc_set;
do_exception(cpu, cpu->exception_addr, 0, false);
} else {
tlbmisc_set |= CR_TLBMISC_WE;
do_exception(cpu, cpu->fast_tlb_miss_addr, tlbmisc_set, false);
}
break;
case EXCP_PERM_R:
case EXCP_PERM_W:
tlbmisc_set = CR_TLBMISC_D;
- /* fall through */
+ fallthrough;
case EXCP_PERM_X:
tlbmisc_set |= CR_TLBMISC_PERM;
if (!(env->ctrl[CR_STATUS] & CR_STATUS_EH)) {
tlbmisc_set |= CR_TLBMISC_WE;
}
do_exception(cpu, cpu->exception_addr, tlbmisc_set, false);
break;
case EXCP_SUPERA_D:
case EXCP_UNALIGN:
tlbmisc_set = CR_TLBMISC_D;
- /* fall through */
+ fallthrough;
case EXCP_SUPERA_X:
case EXCP_UNALIGND:
tlbmisc_set |= CR_TLBMISC_BAD;
do_exception(cpu, cpu->exception_addr, tlbmisc_set, false);
break;
case EXCP_SUPERI:
case EXCP_ILLEGAL:
case EXCP_DIV:
case EXCP_TRAP:
do_exception(cpu, cpu->exception_addr, 0, false);
break;
case EXCP_BREAK:
do_exception(cpu, cpu->exception_addr, 0, true);
break;
case EXCP_SEMIHOST:
do_nios2_semihosting(env);
break;
default:
cpu_abort(cs, "unhandled exception type=%d\n", cs->exception_index);
}
}
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index e806623594..2cfe77c90a 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -617,64 +617,64 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
/* ctlN <- rA */
static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
{
if (!gen_check_supervisor(dc)) {
return;
}
#ifdef CONFIG_USER_ONLY
g_assert_not_reached();
#else
R_TYPE(instr, code);
TCGv v = load_gpr(dc, instr.a);
uint32_t ofs = offsetof(CPUNios2State, ctrl[instr.imm5]);
uint32_t wr = dc->cr_state[instr.imm5].writable;
uint32_t ro = dc->cr_state[instr.imm5].readonly;
/* Skip reserved or readonly registers. */
if (wr == 0) {
return;
}
switch (instr.imm5) {
case CR_PTEADDR:
gen_helper_mmu_write_pteaddr(tcg_env, v);
break;
case CR_TLBACC:
gen_helper_mmu_write_tlbacc(tcg_env, v);
break;
case CR_TLBMISC:
gen_helper_mmu_write_tlbmisc(tcg_env, v);
break;
case CR_STATUS:
case CR_IENABLE:
/* If interrupts were enabled using WRCTL, trigger them. */
dc->base.is_jmp = DISAS_UPDATE;
- /* fall through */
+ fallthrough;
default:
if (wr == -1) {
/* The register is entirely writable. */
tcg_gen_st_tl(v, tcg_env, ofs);
} else {
/*
* The register is partially read-only or reserved:
* merge the value.
*/
TCGv n = tcg_temp_new();
tcg_gen_andi_tl(n, v, wr);
if (ro != 0) {
TCGv o = tcg_temp_new();
tcg_gen_ld_tl(o, tcg_env, ofs);
tcg_gen_andi_tl(o, o, ro);
tcg_gen_or_tl(n, n, o);
}
tcg_gen_st_tl(n, tcg_env, ofs);
}
break;
}
#endif
}
/* prs.rC <- rA */
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 31/78] target/xtensa: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (29 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 30/78] target/nios2: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 8:01 ` Max Filippov
2023-10-13 7:56 ` [RFC PATCH v2 32/78] target/m68k: " Emmanouil Pitsidianakis
` (47 subsequent siblings)
78 siblings, 1 reply; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Max Filippov
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
target/xtensa/op_helper.c | 8 ++++----
target/xtensa/translate.c | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
index 7bb8cd6726..69b72f474d 100644
--- a/target/xtensa/op_helper.c
+++ b/target/xtensa/op_helper.c
@@ -73,58 +73,58 @@ void HELPER(update_ccompare)(CPUXtensaState *env, uint32_t i)
/*!
* Check vaddr accessibility/cache attributes and raise an exception if
* specified by the ATOMCTL SR.
*
* Note: local memory exclusion is not implemented
*/
void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr)
{
uint32_t paddr, page_size, access;
uint32_t atomctl = env->sregs[ATOMCTL];
int rc = xtensa_get_physical_addr(env, true, vaddr, 1,
xtensa_get_cring(env), &paddr, &page_size, &access);
/*
* s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions,
* see opcode description in the ISA
*/
if (rc == 0 &&
(access & (PAGE_READ | PAGE_WRITE)) != (PAGE_READ | PAGE_WRITE)) {
rc = STORE_PROHIBITED_CAUSE;
}
if (rc) {
HELPER(exception_cause_vaddr)(env, pc, rc, vaddr);
}
/*
* When data cache is not configured use ATOMCTL bypass field.
* See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL)
* under the Conditional Store Option.
*/
if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) {
access = PAGE_CACHE_BYPASS;
}
switch (access & PAGE_CACHE_MASK) {
case PAGE_CACHE_WB:
atomctl >>= 2;
- /* fall through */
+ fallthrough;
case PAGE_CACHE_WT:
atomctl >>= 2;
- /* fall through */
+ fallthrough;
case PAGE_CACHE_BYPASS:
if ((atomctl & 0x3) == 0) {
HELPER(exception_cause_vaddr)(env, pc,
LOAD_STORE_ERROR_CAUSE, vaddr);
}
break;
case PAGE_CACHE_ISOLATE:
HELPER(exception_cause_vaddr)(env, pc,
LOAD_STORE_ERROR_CAUSE, vaddr);
break;
default:
break;
}
}
@@ -132,41 +132,41 @@ void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr)
void HELPER(check_exclusive)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr,
uint32_t is_write)
{
uint32_t paddr, page_size, access;
uint32_t atomctl = env->sregs[ATOMCTL];
int rc = xtensa_get_physical_addr(env, true, vaddr, is_write,
xtensa_get_cring(env), &paddr,
&page_size, &access);
if (rc) {
HELPER(exception_cause_vaddr)(env, pc, rc, vaddr);
}
/* When data cache is not configured use ATOMCTL bypass field. */
if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) {
access = PAGE_CACHE_BYPASS;
}
switch (access & PAGE_CACHE_MASK) {
case PAGE_CACHE_WB:
atomctl >>= 2;
- /* fall through */
+ fallthrough;
case PAGE_CACHE_WT:
atomctl >>= 2;
- /* fall through */
+ fallthrough;
case PAGE_CACHE_BYPASS:
if ((atomctl & 0x3) == 0) {
HELPER(exception_cause_vaddr)(env, pc,
EXCLUSIVE_ERROR_CAUSE, vaddr);
}
break;
case PAGE_CACHE_ISOLATE:
HELPER(exception_cause_vaddr)(env, pc,
LOAD_STORE_ERROR_CAUSE, vaddr);
break;
default:
break;
}
}
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 54bee7ddba..8ef940933c 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -795,24 +795,24 @@ again:
static void opcode_add_resource(struct slot_prop *op,
uint32_t resource, char direction,
int index)
{
switch (direction) {
case 'm':
case 'i':
assert(op->n_in < ARRAY_SIZE(op->in));
op->in[op->n_in].resource = resource;
op->in[op->n_in].index = index;
++op->n_in;
- /* fall through */
+ fallthrough;
case 'o':
if (direction == 'm' || direction == 'o') {
assert(op->n_out < ARRAY_SIZE(op->out));
op->out[op->n_out].resource = resource;
op->out[op->n_out].index = index;
++op->n_out;
}
break;
default:
g_assert_not_reached();
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* Re: [RFC PATCH v2 31/78] target/xtensa: add fallthrough pseudo-keyword
2023-10-13 7:56 ` [RFC PATCH v2 31/78] target/xtensa: " Emmanouil Pitsidianakis
@ 2023-10-13 8:01 ` Max Filippov
0 siblings, 0 replies; 91+ messages in thread
From: Max Filippov @ 2023-10-13 8:01 UTC (permalink / raw)
To: Emmanouil Pitsidianakis; +Cc: qemu-devel
On Fri, Oct 13, 2023 at 12:58 AM Emmanouil Pitsidianakis
<manos.pitsidianakis@linaro.org> wrote:
>
> In preparation of raising -Wimplicit-fallthrough to 5, replace all
> fall-through comments with the fallthrough attribute pseudo-keyword.
>
> Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
> ---
> target/xtensa/op_helper.c | 8 ++++----
> target/xtensa/translate.c | 2 +-
> 2 files changed, 5 insertions(+), 5 deletions(-)
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com>
--
Thanks.
-- Max
^ permalink raw reply [flat|nested] 91+ messages in thread
* [RFC PATCH v2 32/78] target/m68k: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (30 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 31/78] target/xtensa: " Emmanouil Pitsidianakis
@ 2023-10-13 7:56 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 33/78] target/rx: " Emmanouil Pitsidianakis
` (46 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Laurent Vivier
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
target/m68k/op_helper.c | 3 ++-
target/m68k/translate.c | 10 +++++-----
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index 1ce850bbc5..65058b9e2f 100644
--- a/target/m68k/op_helper.c
+++ b/target/m68k/op_helper.c
@@ -285,147 +285,147 @@ static inline void do_stack_frame(CPUM68KState *env, uint32_t *sp,
static void m68k_interrupt_all(CPUM68KState *env, int is_hw)
{
CPUState *cs = env_cpu(env);
uint32_t sp;
uint32_t vector;
uint16_t sr, oldsr;
if (!is_hw) {
switch (cs->exception_index) {
case EXCP_RTE:
/* Return from an exception. */
m68k_rte(env);
return;
}
}
vector = cs->exception_index << 2;
sr = env->sr | cpu_m68k_get_ccr(env);
if (qemu_loglevel_mask(CPU_LOG_INT)) {
static int count;
qemu_log("INT %6d: %s(%#x) pc=%08x sp=%08x sr=%04x\n",
++count, m68k_exception_name(cs->exception_index),
vector, env->pc, env->aregs[7], sr);
}
/*
* MC68040UM/AD, chapter 9.3.10
*/
/* "the processor first make an internal copy" */
oldsr = sr;
/* "set the mode to supervisor" */
sr |= SR_S;
/* "suppress tracing" */
sr &= ~SR_T;
/* "sets the processor interrupt mask" */
if (is_hw) {
sr |= (env->sr & ~SR_I) | (env->pending_level << SR_I_SHIFT);
}
cpu_m68k_set_sr(env, sr);
sp = env->aregs[7];
if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) {
sp &= ~1;
}
switch (cs->exception_index) {
case EXCP_ACCESS:
if (env->mmu.fault) {
cpu_abort(cs, "DOUBLE MMU FAULT\n");
}
env->mmu.fault = true;
/* push data 3 */
sp -= 4;
cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* push data 2 */
sp -= 4;
cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* push data 1 */
sp -= 4;
cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* write back 1 / push data 0 */
sp -= 4;
cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* write back 1 address */
sp -= 4;
cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* write back 2 data */
sp -= 4;
cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* write back 2 address */
sp -= 4;
cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* write back 3 data */
sp -= 4;
cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* write back 3 address */
sp -= 4;
cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
/* fault address */
sp -= 4;
cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
/* write back 1 status */
sp -= 2;
cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* write back 2 status */
sp -= 2;
cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* write back 3 status */
sp -= 2;
cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* special status word */
sp -= 2;
cpu_stw_mmuidx_ra(env, sp, env->mmu.ssw, MMU_KERNEL_IDX, 0);
/* effective address */
sp -= 4;
cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
do_stack_frame(env, &sp, 7, oldsr, 0, env->pc);
env->mmu.fault = false;
if (qemu_loglevel_mask(CPU_LOG_INT)) {
qemu_log(" "
"ssw: %08x ea: %08x sfc: %d dfc: %d\n",
env->mmu.ssw, env->mmu.ar, env->sfc, env->dfc);
}
break;
case EXCP_ILLEGAL:
do_stack_frame(env, &sp, 0, oldsr, 0, env->pc);
break;
case EXCP_ADDRESS:
do_stack_frame(env, &sp, 2, oldsr, 0, env->pc);
break;
case EXCP_CHK:
case EXCP_DIV0:
case EXCP_TRACE:
case EXCP_TRAPCC:
do_stack_frame(env, &sp, 2, oldsr, env->mmu.ar, env->pc);
break;
case EXCP_SPURIOUS ... EXCP_INT_LEVEL_7:
if (is_hw && (oldsr & SR_M)) {
do_stack_frame(env, &sp, 0, oldsr, 0, env->pc);
oldsr = sr;
env->aregs[7] = sp;
cpu_m68k_set_sr(env, sr & ~SR_M);
sp = env->aregs[7];
if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) {
sp &= ~1;
}
do_stack_frame(env, &sp, 1, oldsr, 0, env->pc);
break;
}
- /* fall through */
+ fallthrough;
default:
do_stack_frame(env, &sp, 0, oldsr, 0, env->pc);
break;
}
env->aregs[7] = sp;
/* Jump to vector. */
env->pc = cpu_ldl_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0);
}
@@ -880,60 +880,61 @@ struct bf_data {
static struct bf_data bf_prep(uint32_t addr, int32_t ofs, uint32_t len)
{
int bofs, blen;
/* Bound length; map 0 to 32. */
len = ((len - 1) & 31) + 1;
/* Note that ofs is signed. */
addr += ofs / 8;
bofs = ofs % 8;
if (bofs < 0) {
bofs += 8;
addr -= 1;
}
/*
* Compute the number of bytes required (minus one) to
* satisfy the bitfield.
*/
blen = (bofs + len - 1) / 8;
/*
* Canonicalize the bit offset for data loaded into a 64-bit big-endian
* word. For the cases where BLEN is not a power of 2, adjust ADDR so
* that we can use the next power of two sized load without crossing a
* page boundary, unless the field itself crosses the boundary.
*/
switch (blen) {
case 0:
bofs += 56;
break;
case 1:
bofs += 48;
break;
case 2:
if (addr & 1) {
bofs += 8;
addr -= 1;
}
/* fallthru */
+ fallthrough;
case 3:
bofs += 32;
break;
case 4:
if (addr & 3) {
bofs += 8 * (addr & 3);
addr &= -4;
}
break;
default:
g_assert_not_reached();
}
return (struct bf_data){
.addr = addr,
.bofs = bofs,
.blen = blen,
.len = len,
};
}
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 4d0110de95..ce102dc585 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -715,67 +715,67 @@ static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
/*
* Generate code for an "effective address". Does not adjust the base
* register for autoincrement addressing modes.
*/
static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
int mode, int reg0, int opsize)
{
TCGv reg;
TCGv tmp;
uint16_t ext;
uint32_t offset;
switch (mode) {
case 0: /* Data register direct. */
case 1: /* Address register direct. */
return NULL_QREG;
case 3: /* Indirect postincrement. */
if (opsize == OS_UNSIZED) {
return NULL_QREG;
}
- /* fallthru */
+ fallthrough;
case 2: /* Indirect register */
return get_areg(s, reg0);
case 4: /* Indirect predecrememnt. */
if (opsize == OS_UNSIZED) {
return NULL_QREG;
}
reg = get_areg(s, reg0);
tmp = tcg_temp_new();
if (reg0 == 7 && opsize == OS_BYTE &&
m68k_feature(s->env, M68K_FEATURE_M68K)) {
tcg_gen_subi_i32(tmp, reg, 2);
} else {
tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
}
return tmp;
case 5: /* Indirect displacement. */
reg = get_areg(s, reg0);
tmp = tcg_temp_new();
ext = read_im16(env, s);
tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
return tmp;
case 6: /* Indirect index + displacement. */
reg = get_areg(s, reg0);
return gen_lea_indexed(env, s, reg);
case 7: /* Other */
switch (reg0) {
case 0: /* Absolute short. */
offset = (int16_t)read_im16(env, s);
return tcg_constant_i32(offset);
case 1: /* Absolute long. */
offset = read_im32(env, s);
return tcg_constant_i32(offset);
case 2: /* pc displacement */
offset = s->pc;
offset += (int16_t)read_im16(env, s);
return tcg_constant_i32(offset);
case 3: /* pc index+displacement. */
return gen_lea_indexed(env, s, NULL_QREG);
case 4: /* Immediate. */
default:
return NULL_QREG;
}
}
/* Should never happen. */
return NULL_QREG;
}
@@ -1195,171 +1195,171 @@ typedef struct {
static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
{
TCGv tmp, tmp2;
TCGCond tcond;
CCOp op = s->cc_op;
/* The CC_OP_CMP form can handle most normal comparisons directly. */
if (op == CC_OP_CMPB || op == CC_OP_CMPW || op == CC_OP_CMPL) {
c->v1 = QREG_CC_N;
c->v2 = QREG_CC_V;
switch (cond) {
case 2: /* HI */
case 3: /* LS */
tcond = TCG_COND_LEU;
goto done;
case 4: /* CC */
case 5: /* CS */
tcond = TCG_COND_LTU;
goto done;
case 6: /* NE */
case 7: /* EQ */
tcond = TCG_COND_EQ;
goto done;
case 10: /* PL */
case 11: /* MI */
c->v2 = tcg_constant_i32(0);
c->v1 = tmp = tcg_temp_new();
tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V);
gen_ext(tmp, tmp, op - CC_OP_CMPB, 1);
- /* fallthru */
+ fallthrough;
case 12: /* GE */
case 13: /* LT */
tcond = TCG_COND_LT;
goto done;
case 14: /* GT */
case 15: /* LE */
tcond = TCG_COND_LE;
goto done;
}
}
c->v2 = tcg_constant_i32(0);
switch (cond) {
case 0: /* T */
case 1: /* F */
c->v1 = c->v2;
tcond = TCG_COND_NEVER;
goto done;
case 14: /* GT (!(Z || (N ^ V))) */
case 15: /* LE (Z || (N ^ V)) */
/*
* Logic operations clear V, which simplifies LE to (Z || N),
* and since Z and N are co-located, this becomes a normal
* comparison vs N.
*/
if (op == CC_OP_LOGIC) {
c->v1 = QREG_CC_N;
tcond = TCG_COND_LE;
goto done;
}
break;
case 12: /* GE (!(N ^ V)) */
case 13: /* LT (N ^ V) */
/* Logic operations clear V, which simplifies this to N. */
if (op != CC_OP_LOGIC) {
break;
}
- /* fallthru */
+ fallthrough;
case 10: /* PL (!N) */
case 11: /* MI (N) */
/* Several cases represent N normally. */
if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
op == CC_OP_LOGIC) {
c->v1 = QREG_CC_N;
tcond = TCG_COND_LT;
goto done;
}
break;
case 6: /* NE (!Z) */
case 7: /* EQ (Z) */
/* Some cases fold Z into N. */
if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
op == CC_OP_LOGIC) {
tcond = TCG_COND_EQ;
c->v1 = QREG_CC_N;
goto done;
}
break;
case 4: /* CC (!C) */
case 5: /* CS (C) */
/* Some cases fold C into X. */
if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL) {
tcond = TCG_COND_NE;
c->v1 = QREG_CC_X;
goto done;
}
- /* fallthru */
+ fallthrough;
case 8: /* VC (!V) */
case 9: /* VS (V) */
/* Logic operations clear V and C. */
if (op == CC_OP_LOGIC) {
tcond = TCG_COND_NEVER;
c->v1 = c->v2;
goto done;
}
break;
}
/* Otherwise, flush flag state to CC_OP_FLAGS. */
gen_flush_flags(s);
switch (cond) {
case 0: /* T */
case 1: /* F */
default:
/* Invalid, or handled above. */
abort();
case 2: /* HI (!C && !Z) -> !(C || Z)*/
case 3: /* LS (C || Z) */
c->v1 = tmp = tcg_temp_new();
tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
tcg_gen_or_i32(tmp, tmp, QREG_CC_C);
tcond = TCG_COND_NE;
break;
case 4: /* CC (!C) */
case 5: /* CS (C) */
c->v1 = QREG_CC_C;
tcond = TCG_COND_NE;
break;
case 6: /* NE (!Z) */
case 7: /* EQ (Z) */
c->v1 = QREG_CC_Z;
tcond = TCG_COND_EQ;
break;
case 8: /* VC (!V) */
case 9: /* VS (V) */
c->v1 = QREG_CC_V;
tcond = TCG_COND_LT;
break;
case 10: /* PL (!N) */
case 11: /* MI (N) */
c->v1 = QREG_CC_N;
tcond = TCG_COND_LT;
break;
case 12: /* GE (!(N ^ V)) */
case 13: /* LT (N ^ V) */
c->v1 = tmp = tcg_temp_new();
tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V);
tcond = TCG_COND_LT;
break;
case 14: /* GT (!(Z || (N ^ V))) */
case 15: /* LE (Z || (N ^ V)) */
c->v1 = tmp = tcg_temp_new();
tcg_gen_negsetcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
tmp2 = tcg_temp_new();
tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V);
tcg_gen_or_i32(tmp, tmp, tmp2);
tcond = TCG_COND_LT;
break;
}
done:
if ((cond & 1) == 0) {
tcond = tcg_invert_cond(tcond);
}
c->tcond = tcond;
}
@@ -4223,25 +4223,25 @@ DISAS_INSN(ff1)
DISAS_INSN(chk)
{
TCGv src, reg;
int opsize;
switch ((insn >> 7) & 3) {
case 3:
opsize = OS_WORD;
break;
case 2:
if (m68k_feature(env, M68K_FEATURE_CHK2)) {
opsize = OS_LONG;
break;
}
- /* fallthru */
+ fallthrough;
default:
gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
return;
}
SRC_EA(env, src, opsize, 1, NULL);
reg = gen_extend(s, DREG(insn, 9), opsize, 1);
gen_flush_flags(s);
gen_helper_chk(tcg_env, reg, src);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 33/78] target/rx: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (31 preceding siblings ...)
2023-10-13 7:56 ` [RFC PATCH v2 32/78] target/m68k: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 34/78] target/tricore: " Emmanouil Pitsidianakis
` (45 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Yoshinori Sato
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
target/rx/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/rx/translate.c b/target/rx/translate.c
index f8860830ae..b00c0a21fb 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -2232,24 +2232,24 @@ static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
static void rx_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
switch (ctx->base.is_jmp) {
case DISAS_NEXT:
case DISAS_TOO_MANY:
gen_goto_tb(ctx, 0, dcbase->pc_next);
break;
case DISAS_JUMP:
tcg_gen_lookup_and_goto_ptr();
break;
case DISAS_UPDATE:
tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
- /* fall through */
+ fallthrough;
case DISAS_EXIT:
tcg_gen_exit_tb(NULL, 0);
break;
case DISAS_NORETURN:
break;
default:
g_assert_not_reached();
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 34/78] target/tricore: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (32 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 33/78] target/rx: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 35/78] target/sh4: " Emmanouil Pitsidianakis
` (44 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Bastian Koppelmann
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
target/tricore/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index dd812ec0f0..4e42f06ec8 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -2899,259 +2899,259 @@ static void gen_fret(DisasContext *ctx)
static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
int r2 , int32_t constant , int32_t offset)
{
TCGv temp, temp2;
int n;
switch (opc) {
/* SB-format jumps */
case OPC1_16_SB_J:
case OPC1_32_B_J:
gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
break;
case OPC1_32_B_CALL:
case OPC1_16_SB_CALL:
gen_helper_1arg(call, ctx->pc_succ_insn);
gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
break;
case OPC1_16_SB_JZ:
gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
break;
case OPC1_16_SB_JNZ:
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
break;
/* SBC-format jumps */
case OPC1_16_SBC_JEQ:
gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
break;
case OPC1_16_SBC_JEQ2:
gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant,
offset + 16);
break;
case OPC1_16_SBC_JNE:
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
break;
case OPC1_16_SBC_JNE2:
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15],
constant, offset + 16);
break;
/* SBRN-format jumps */
case OPC1_16_SBRN_JZ_T:
temp = tcg_temp_new();
tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
break;
case OPC1_16_SBRN_JNZ_T:
temp = tcg_temp_new();
tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
break;
/* SBR-format jumps */
case OPC1_16_SBR_JEQ:
gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
offset);
break;
case OPC1_16_SBR_JEQ2:
gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
offset + 16);
break;
case OPC1_16_SBR_JNE:
gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
offset);
break;
case OPC1_16_SBR_JNE2:
gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
offset + 16);
break;
case OPC1_16_SBR_JNZ:
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
break;
case OPC1_16_SBR_JNZ_A:
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
break;
case OPC1_16_SBR_JGEZ:
gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
break;
case OPC1_16_SBR_JGTZ:
gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
break;
case OPC1_16_SBR_JLEZ:
gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
break;
case OPC1_16_SBR_JLTZ:
gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
break;
case OPC1_16_SBR_JZ:
gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
break;
case OPC1_16_SBR_JZ_A:
gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
break;
case OPC1_16_SBR_LOOP:
gen_loop(ctx, r1, offset * 2 - 32);
break;
/* SR-format jumps */
case OPC1_16_SR_JI:
tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
ctx->base.is_jmp = DISAS_EXIT;
break;
case OPC2_32_SYS_RET:
case OPC2_16_SR_RET:
gen_helper_ret(tcg_env);
ctx->base.is_jmp = DISAS_EXIT;
break;
/* B-format */
case OPC1_32_B_CALLA:
gen_helper_1arg(call, ctx->pc_succ_insn);
gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
break;
case OPC1_32_B_FCALL:
gen_fcall_save_ctx(ctx);
gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
break;
case OPC1_32_B_FCALLA:
gen_fcall_save_ctx(ctx);
gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
break;
case OPC1_32_B_JLA:
tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
- /* fall through */
+ fallthrough;
case OPC1_32_B_JA:
gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
break;
case OPC1_32_B_JL:
tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
break;
/* BOL format */
case OPCM_32_BRC_EQ_NEQ:
if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) {
gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset);
} else {
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset);
}
break;
case OPCM_32_BRC_GE:
if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) {
gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset);
} else {
constant = MASK_OP_BRC_CONST4(ctx->opcode);
gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant,
offset);
}
break;
case OPCM_32_BRC_JLT:
if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) {
gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset);
} else {
constant = MASK_OP_BRC_CONST4(ctx->opcode);
gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant,
offset);
}
break;
case OPCM_32_BRC_JNE:
temp = tcg_temp_new();
if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) {
tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
/* subi is unconditional */
tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
} else {
tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
/* addi is unconditional */
tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
}
break;
/* BRN format */
case OPCM_32_BRN_JTT:
n = MASK_OP_BRN_N(ctx->opcode);
temp = tcg_temp_new();
tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n));
if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) {
gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
} else {
gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
}
break;
/* BRR Format */
case OPCM_32_BRR_EQ_NEQ:
if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) {
gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2],
offset);
} else {
gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
offset);
}
break;
case OPCM_32_BRR_ADDR_EQ_NEQ:
if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) {
gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2],
offset);
} else {
gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2],
offset);
}
break;
case OPCM_32_BRR_GE:
if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) {
gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2],
offset);
} else {
gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2],
offset);
}
break;
case OPCM_32_BRR_JLT:
if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) {
gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2],
offset);
} else {
gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2],
offset);
}
break;
case OPCM_32_BRR_LOOP:
if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
gen_loop(ctx, r2, offset * 2);
} else {
/* OPC2_32_BRR_LOOPU */
gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
}
break;
case OPCM_32_BRR_JNE:
temp = tcg_temp_new();
temp2 = tcg_temp_new();
if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) {
tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
/* also save r2, in case of r1 == r2, so r2 is not decremented */
tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
/* subi is unconditional */
tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
} else {
tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
/* also save r2, in case of r1 == r2, so r2 is not decremented */
tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
/* addi is unconditional */
tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
}
break;
case OPCM_32_BRR_JNZ:
if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) {
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
} else {
gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
}
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
/*
* Functions for decoding instructions
*/
@@ -8445,23 +8445,23 @@ static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
static void tricore_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
switch (ctx->base.is_jmp) {
case DISAS_TOO_MANY:
gen_goto_tb(ctx, 0, ctx->base.pc_next);
break;
case DISAS_EXIT_UPDATE:
gen_save_pc(ctx->base.pc_next);
- /* fall through */
+ fallthrough;
case DISAS_EXIT:
tcg_gen_exit_tb(NULL, 0);
break;
case DISAS_JUMP:
tcg_gen_lookup_and_goto_ptr();
break;
case DISAS_NORETURN:
break;
default:
g_assert_not_reached();
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 35/78] target/sh4: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (33 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 34/78] target/tricore: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 36/78] target/openrisc: " Emmanouil Pitsidianakis
` (43 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Yoshinori Sato
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
target/sh4/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index e02e7af607..c1cc5e82f4 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -56,131 +56,131 @@ int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr)
void superh_cpu_do_interrupt(CPUState *cs)
{
SuperHCPU *cpu = SUPERH_CPU(cs);
CPUSH4State *env = &cpu->env;
int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD;
int do_exp, irq_vector = cs->exception_index;
/* prioritize exceptions over interrupts */
do_exp = cs->exception_index != -1;
do_irq = do_irq && (cs->exception_index == -1);
if (env->sr & (1u << SR_BL)) {
if (do_exp && cs->exception_index != 0x1e0) {
/* In theory a masked exception generates a reset exception,
which in turn jumps to the reset vector. However this only
works when using a bootloader. When using a kernel and an
initrd, they need to be reloaded and the program counter
should be loaded with the kernel entry point.
qemu_system_reset_request takes care of that. */
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
return;
}
if (do_irq && !env->in_sleep) {
return; /* masked */
}
}
env->in_sleep = 0;
if (do_irq) {
irq_vector = sh_intc_get_pending_vector(env->intc_handle,
(env->sr >> 4) & 0xf);
if (irq_vector == -1) {
return; /* masked */
}
}
if (qemu_loglevel_mask(CPU_LOG_INT)) {
const char *expname;
switch (cs->exception_index) {
case 0x0e0:
expname = "addr_error";
break;
case 0x040:
expname = "tlb_miss";
break;
case 0x0a0:
expname = "tlb_violation";
break;
case 0x180:
expname = "illegal_instruction";
break;
case 0x1a0:
expname = "slot_illegal_instruction";
break;
case 0x800:
expname = "fpu_disable";
break;
case 0x820:
expname = "slot_fpu";
break;
case 0x100:
expname = "data_write";
break;
case 0x060:
expname = "dtlb_miss_write";
break;
case 0x0c0:
expname = "dtlb_violation_write";
break;
case 0x120:
expname = "fpu_exception";
break;
case 0x080:
expname = "initial_page_write";
break;
case 0x160:
expname = "trapa";
break;
default:
expname = do_irq ? "interrupt" : "???";
break;
}
qemu_log("exception 0x%03x [%s] raised\n",
irq_vector, expname);
log_cpu_state(cs, 0);
}
env->ssr = cpu_read_sr(env);
env->spc = env->pc;
env->sgr = env->gregs[15];
env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB);
env->lock_addr = -1;
if (env->flags & TB_FLAG_DELAY_SLOT_MASK) {
/* Branch instruction should be executed again before delay slot. */
env->spc -= 2;
/* Clear flags for exception/interrupt routine. */
env->flags &= ~TB_FLAG_DELAY_SLOT_MASK;
}
if (do_exp) {
env->expevt = cs->exception_index;
switch (cs->exception_index) {
case 0x000:
case 0x020:
case 0x140:
env->sr &= ~(1u << SR_FD);
env->sr |= 0xf << 4; /* IMASK */
env->pc = 0xa0000000;
break;
case 0x040:
case 0x060:
env->pc = env->vbr + 0x400;
break;
case 0x160:
env->spc += 2; /* special case for TRAPA */
- /* fall through */
+ fallthrough;
default:
env->pc = env->vbr + 0x100;
break;
}
return;
}
if (do_irq) {
env->intevt = irq_vector;
env->pc = env->vbr + 0x600;
return;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 36/78] target/openrisc: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (34 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 35/78] target/sh4: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 37/78] target/hexagon: " Emmanouil Pitsidianakis
` (42 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Stafford Horne
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
target/openrisc/mmu.c | 2 +-
target/openrisc/translate.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index 603c26715e..7ed744e81b 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -141,38 +141,38 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
int prot, excp, sr = cpu->env.sr;
hwaddr phys_addr;
switch (sr & (SR_DME | SR_IME)) {
case SR_DME | SR_IME:
/* The mmu is definitely enabled. */
excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
PAGE_READ,
(sr & SR_SM) != 0);
if (!excp) {
return phys_addr;
}
excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
PAGE_EXEC,
(sr & SR_SM) != 0);
return excp ? -1 : phys_addr;
default:
/* The mmu is partially enabled, and we don't really have
a "real" access type. Begin by trying the mmu, but if
that fails try again without. */
excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
PAGE_EXEC | PAGE_READ | PAGE_WRITE,
(sr & SR_SM) != 0);
if (!excp) {
return phys_addr;
}
- /* fallthru */
+ fallthrough;
case 0:
/* The mmu is definitely disabled; lookups never fail. */
get_phys_nommu(&phys_addr, &prot, addr);
return phys_addr;
}
}
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index ecff4412b7..de77014d60 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1588,53 +1588,53 @@ static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
target_ulong jmp_dest;
/* If we have already exited the TB, nothing following has effect. */
if (dc->base.is_jmp == DISAS_NORETURN) {
return;
}
/* Adjust the delayed branch state for the next TB. */
if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) != (dc->delayed_branch != 0)) {
tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0);
}
/* For DISAS_TOO_MANY, jump to the next insn. */
jmp_dest = dc->base.pc_next;
tcg_gen_movi_tl(cpu_ppc, jmp_dest - 4);
switch (dc->base.is_jmp) {
case DISAS_JUMP:
jmp_dest = dc->jmp_pc_imm;
if (jmp_dest == -1) {
/* The jump destination is indirect/computed; use jmp_pc. */
tcg_gen_mov_tl(cpu_pc, jmp_pc);
tcg_gen_discard_tl(jmp_pc);
tcg_gen_lookup_and_goto_ptr();
break;
}
/* The jump destination is direct; use jmp_pc_imm.
However, we will have stored into jmp_pc as well;
we know now that it wasn't needed. */
tcg_gen_discard_tl(jmp_pc);
- /* fallthru */
+ fallthrough;
case DISAS_TOO_MANY:
if (translator_use_goto_tb(&dc->base, jmp_dest)) {
tcg_gen_goto_tb(0);
tcg_gen_movi_tl(cpu_pc, jmp_dest);
tcg_gen_exit_tb(dc->base.tb, 0);
break;
}
tcg_gen_movi_tl(cpu_pc, jmp_dest);
tcg_gen_lookup_and_goto_ptr();
break;
case DISAS_EXIT:
tcg_gen_exit_tb(NULL, 0);
break;
default:
g_assert_not_reached();
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 37/78] target/hexagon: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (35 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 36/78] target/openrisc: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 38/78] system/rtc.c: " Emmanouil Pitsidianakis
` (41 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Alessandro Di Federico, Anton Johansson
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
target/hexagon/idef-parser/parser-helpers.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/idef-parser/parser-helpers.c
index 4af020933a..0f1713ae4c 100644
--- a/target/hexagon/idef-parser/parser-helpers.c
+++ b/target/hexagon/idef-parser/parser-helpers.c
@@ -1,34 +1,35 @@
/*
* Copyright(c) 2019-2023 rev.ng Labs Srl. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include <assert.h>
#include <inttypes.h>
#include <stdarg.h>
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include "idef-parser.h"
#include "parser-helpers.h"
#include "idef-parser.tab.h"
#include "idef-parser.yy.h"
+#include "qemu/compiler.h"
void yyerror(YYLTYPE *locp,
yyscan_t scanner __attribute__((unused)),
@@ -621,51 +622,51 @@ static void gen_sub_op(Context *c, YYLTYPE *locp, unsigned bit_width,
static void gen_asl_op(Context *c, YYLTYPE *locp, unsigned bit_width,
bool op_is64bit, const char *bit_suffix,
HexValue *res, enum OpTypes op_types,
HexValue *op1, HexValue *op2)
{
HexValue op1_m = *op1;
HexValue op2_m = *op2;
switch (op_types) {
case IMM_IMM: {
HexSignedness signedness = bin_op_signedness(c, locp,
op1->signedness,
op2->signedness);
gen_c_int_type(c, locp, bit_width, signedness);
OUT(c, locp, " ", res,
" = ", op1, " << ", op2, ";\n");
} break;
case REG_IMM: {
OUT(c, locp, "if (", op2, " >= ", &bit_width, ") {\n");
OUT(c, locp, "tcg_gen_movi_", bit_suffix, "(", res, ", 0);\n");
OUT(c, locp, "} else {\n");
OUT(c, locp, "tcg_gen_shli_", bit_suffix,
"(", res, ", ", op1, ", ", op2, ");\n");
OUT(c, locp, "}\n");
} break;
case IMM_REG:
op1_m.bit_width = bit_width;
op1_m = rvalue_materialize(c, locp, &op1_m);
- /* fallthrough */
+ fallthrough;
case REG_REG: {
OUT(c, locp, "tcg_gen_shl_", bit_suffix,
"(", res, ", ", &op1_m, ", ", op2, ");\n");
} break;
}
if (op_types == IMM_REG || op_types == REG_REG) {
/*
* Handle left shift by 64/32 which hexagon-sim expects to clear out
* register
*/
HexValue zero = gen_constant(c, locp, "0", bit_width, UNSIGNED);
HexValue edge = gen_imm_value(c, locp, bit_width, bit_width, UNSIGNED);
edge = rvalue_materialize(c, locp, &edge);
if (op_is64bit) {
op2_m = gen_rvalue_extend(c, locp, &op2_m);
}
op1_m = rvalue_materialize(c, locp, &op1_m);
op2_m = rvalue_materialize(c, locp, &op2_m);
OUT(c, locp, "tcg_gen_movcond_i", &bit_width);
OUT(c, locp, "(TCG_COND_GEU, ", res, ", ", &op2_m, ", ", &edge);
OUT(c, locp, ", ", &zero, ", ", res, ");\n");
}
}
@@ -800,41 +801,41 @@ static void gen_andl_op(Context *c, YYLTYPE *locp, unsigned bit_width,
static void gen_minmax_op(Context *c, YYLTYPE *locp, unsigned bit_width,
HexValue *res, enum OpTypes op_types,
HexValue *op1, HexValue *op2, bool minmax)
{
const char *mm;
HexValue op1_m = *op1;
HexValue op2_m = *op2;
bool is_unsigned;
assert_signedness(c, locp, res->signedness);
is_unsigned = res->signedness == UNSIGNED;
if (minmax) {
/* Max */
mm = is_unsigned ? "tcg_gen_umax" : "tcg_gen_smax";
} else {
/* Min */
mm = is_unsigned ? "tcg_gen_umin" : "tcg_gen_smin";
}
switch (op_types) {
case IMM_IMM:
yyassert(c, locp, false, "MINMAX between IMM op IMM, not handled!");
break;
case IMM_REG:
op1_m.bit_width = bit_width;
op1_m = rvalue_materialize(c, locp, &op1_m);
OUT(c, locp, mm, "_i", &bit_width, "(");
OUT(c, locp, res, ", ", &op1_m, ", ", op2, ");\n");
break;
case REG_IMM:
op2_m.bit_width = bit_width;
op2_m = rvalue_materialize(c, locp, &op2_m);
- /* Fallthrough */
+ fallthrough;
case REG_REG:
OUT(c, locp, mm, "_i", &bit_width, "(");
OUT(c, locp, res, ", ", op1, ", ", &op2_m, ");\n");
break;
}
}
/* Code generation functions */
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 38/78] system/rtc.c: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (36 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 37/78] target/hexagon: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 39/78] hw/scsi: " Emmanouil Pitsidianakis
` (40 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
system/rtc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/system/rtc.c b/system/rtc.c
index 4904581abe..bb406542c8 100644
--- a/system/rtc.c
+++ b/system/rtc.c
@@ -48,22 +48,22 @@ QEMUClockType rtc_clock;
/***********************************************************/
/* RTC reference time/date access */
static time_t qemu_ref_timedate(QEMUClockType clock)
{
time_t value = qemu_clock_get_ms(clock) / 1000;
switch (clock) {
case QEMU_CLOCK_REALTIME:
value -= rtc_realtime_clock_offset;
- /* fall through */
+ fallthrough;
case QEMU_CLOCK_VIRTUAL:
value += rtc_ref_start_datetime;
break;
case QEMU_CLOCK_HOST:
if (rtc_base_type == RTC_BASE_DATETIME) {
value -= rtc_host_datetime_offset;
}
break;
default:
assert(0);
}
return value;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 39/78] hw/scsi: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (37 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 38/78] system/rtc.c: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 40/78] hw/sd/sdhci.c: " Emmanouil Pitsidianakis
` (39 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Paolo Bonzini, Fam Zheng,
Hannes Reinecke, open list:megasas
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/scsi/esp.c | 2 +-
hw/scsi/megasas.c | 2 +-
hw/scsi/scsi-bus.c | 4 ++--
hw/scsi/scsi-disk.c | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 9b11d8c573..d6c8298f51 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -1022,130 +1022,130 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
{
trace_esp_mem_writeb(saddr, s->wregs[saddr], val);
switch (saddr) {
case ESP_TCHI:
s->tchi_written = true;
- /* fall through */
+ fallthrough;
case ESP_TCLO:
case ESP_TCMID:
s->rregs[ESP_RSTAT] &= ~STAT_TC;
break;
case ESP_FIFO:
if (s->do_cmd) {
esp_fifo_push(&s->cmdfifo, val);
/*
* If any unexpected message out/command phase data is
* transferred using non-DMA, raise the interrupt
*/
if (s->rregs[ESP_CMD] == CMD_TI) {
s->rregs[ESP_RINTR] |= INTR_BS;
esp_raise_irq(s);
}
} else {
esp_fifo_push(&s->fifo, val);
}
break;
case ESP_CMD:
s->rregs[saddr] = val;
if (val & CMD_DMA) {
s->dma = 1;
/* Reload DMA counter. */
if (esp_get_stc(s) == 0) {
esp_set_tc(s, 0x10000);
} else {
esp_set_tc(s, esp_get_stc(s));
}
} else {
s->dma = 0;
}
switch (val & CMD_CMD) {
case CMD_NOP:
trace_esp_mem_writeb_cmd_nop(val);
break;
case CMD_FLUSH:
trace_esp_mem_writeb_cmd_flush(val);
fifo8_reset(&s->fifo);
break;
case CMD_RESET:
trace_esp_mem_writeb_cmd_reset(val);
esp_soft_reset(s);
break;
case CMD_BUSRESET:
trace_esp_mem_writeb_cmd_bus_reset(val);
esp_bus_reset(s);
if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
s->rregs[ESP_RINTR] |= INTR_RST;
esp_raise_irq(s);
}
break;
case CMD_TI:
trace_esp_mem_writeb_cmd_ti(val);
handle_ti(s);
break;
case CMD_ICCS:
trace_esp_mem_writeb_cmd_iccs(val);
write_response(s);
s->rregs[ESP_RINTR] |= INTR_FC;
s->rregs[ESP_RSTAT] |= STAT_MI;
break;
case CMD_MSGACC:
trace_esp_mem_writeb_cmd_msgacc(val);
s->rregs[ESP_RINTR] |= INTR_DC;
s->rregs[ESP_RSEQ] = 0;
s->rregs[ESP_RFLAGS] = 0;
esp_raise_irq(s);
break;
case CMD_PAD:
trace_esp_mem_writeb_cmd_pad(val);
s->rregs[ESP_RSTAT] = STAT_TC;
s->rregs[ESP_RINTR] |= INTR_FC;
s->rregs[ESP_RSEQ] = 0;
break;
case CMD_SATN:
trace_esp_mem_writeb_cmd_satn(val);
break;
case CMD_RSTATN:
trace_esp_mem_writeb_cmd_rstatn(val);
break;
case CMD_SEL:
trace_esp_mem_writeb_cmd_sel(val);
handle_s_without_atn(s);
break;
case CMD_SELATN:
trace_esp_mem_writeb_cmd_selatn(val);
handle_satn(s);
break;
case CMD_SELATNS:
trace_esp_mem_writeb_cmd_selatns(val);
handle_satn_stop(s);
break;
case CMD_ENSEL:
trace_esp_mem_writeb_cmd_ensel(val);
s->rregs[ESP_RINTR] = 0;
break;
case CMD_DISSEL:
trace_esp_mem_writeb_cmd_dissel(val);
s->rregs[ESP_RINTR] = 0;
esp_raise_irq(s);
break;
default:
trace_esp_error_unhandled_command(val);
break;
}
break;
case ESP_WBUSID ... ESP_WSYNO:
break;
case ESP_CFG1:
case ESP_CFG2: case ESP_CFG3:
case ESP_RES3: case ESP_RES4:
s->rregs[saddr] = val;
break;
case ESP_WCCF ... ESP_WTEST:
break;
default:
trace_esp_error_invalid_write(val, saddr);
return;
}
s->wregs[saddr] = val;
}
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
index 32c70c9e99..54e4d7c8b6 100644
--- a/hw/scsi/megasas.c
+++ b/hw/scsi/megasas.c
@@ -2084,113 +2084,113 @@ static int adp_reset_seq[] = {0x00, 0x04, 0x0b, 0x02, 0x07, 0x0d};
static void megasas_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MegasasState *s = opaque;
PCIDevice *pci_dev = PCI_DEVICE(s);
uint64_t frame_addr;
uint32_t frame_count;
int i;
switch (addr) {
case MFI_IDB:
trace_megasas_mmio_writel("MFI_IDB", val);
if (val & MFI_FWINIT_ABORT) {
/* Abort all pending cmds */
for (i = 0; i < s->fw_cmds; i++) {
megasas_abort_command(&s->frames[i]);
}
}
if (val & MFI_FWINIT_READY) {
/* move to FW READY */
megasas_soft_reset(s);
}
if (val & MFI_FWINIT_MFIMODE) {
/* discard MFIs */
}
if (val & MFI_FWINIT_STOP_ADP) {
/* Terminal error, stop processing */
s->fw_state = MFI_FWSTATE_FAULT;
}
break;
case MFI_OMSK:
trace_megasas_mmio_writel("MFI_OMSK", val);
s->intr_mask = val;
if (!megasas_intr_enabled(s) &&
!msi_enabled(pci_dev) &&
!msix_enabled(pci_dev)) {
trace_megasas_irq_lower();
pci_irq_deassert(pci_dev);
}
if (megasas_intr_enabled(s)) {
if (msix_enabled(pci_dev)) {
trace_megasas_msix_enabled(0);
} else if (msi_enabled(pci_dev)) {
trace_megasas_msi_enabled(0);
} else {
trace_megasas_intr_enabled();
}
} else {
trace_megasas_intr_disabled();
megasas_soft_reset(s);
}
break;
case MFI_ODCR0:
trace_megasas_mmio_writel("MFI_ODCR0", val);
s->doorbell = 0;
if (megasas_intr_enabled(s)) {
if (!msix_enabled(pci_dev) && !msi_enabled(pci_dev)) {
trace_megasas_irq_lower();
pci_irq_deassert(pci_dev);
}
}
break;
case MFI_IQPH:
trace_megasas_mmio_writel("MFI_IQPH", val);
/* Received high 32 bits of a 64 bit MFI frame address */
s->frame_hi = val;
break;
case MFI_IQPL:
trace_megasas_mmio_writel("MFI_IQPL", val);
/* Received low 32 bits of a 64 bit MFI frame address */
- /* Fallthrough */
+ fallthrough;
case MFI_IQP:
if (addr == MFI_IQP) {
trace_megasas_mmio_writel("MFI_IQP", val);
/* Received 64 bit MFI frame address */
s->frame_hi = 0;
}
frame_addr = (val & ~0x1F);
/* Add possible 64 bit offset */
frame_addr |= ((uint64_t)s->frame_hi << 32);
s->frame_hi = 0;
frame_count = (val >> 1) & 0xF;
megasas_handle_frame(s, frame_addr, frame_count);
break;
case MFI_SEQ:
trace_megasas_mmio_writel("MFI_SEQ", val);
/* Magic sequence to start ADP reset */
if (adp_reset_seq[s->adp_reset++] == val) {
if (s->adp_reset == 6) {
s->adp_reset = 0;
s->diag = MFI_DIAG_WRITE_ENABLE;
}
} else {
s->adp_reset = 0;
s->diag = 0;
}
break;
case MFI_DIAG:
trace_megasas_mmio_writel("MFI_DIAG", val);
/* ADP reset */
if ((s->diag & MFI_DIAG_WRITE_ENABLE) &&
(val & MFI_DIAG_RESET_ADP)) {
s->diag |= MFI_DIAG_RESET_ADP;
megasas_soft_reset(s);
s->adp_reset = 0;
s->diag = 0;
}
break;
default:
trace_megasas_mmio_invalid_writel(addr, val);
break;
}
}
diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c
index fc4b77fdb0..a1c298a92c 100644
--- a/hw/scsi/scsi-bus.c
+++ b/hw/scsi/scsi-bus.c
@@ -1015,141 +1015,141 @@ static int ata_passthrough_16_xfer(SCSIDevice *dev, uint8_t *buf)
static int scsi_req_xfer(SCSICommand *cmd, SCSIDevice *dev, uint8_t *buf)
{
cmd->xfer = scsi_cdb_xfer(buf);
switch (buf[0]) {
case TEST_UNIT_READY:
case REWIND:
case START_STOP:
case SET_CAPACITY:
case WRITE_FILEMARKS:
case WRITE_FILEMARKS_16:
case SPACE:
case RESERVE:
case RELEASE:
case ERASE:
case ALLOW_MEDIUM_REMOVAL:
case SEEK_10:
case SYNCHRONIZE_CACHE:
case SYNCHRONIZE_CACHE_16:
case LOCATE_16:
case LOCK_UNLOCK_CACHE:
case SET_CD_SPEED:
case SET_LIMITS:
case WRITE_LONG_10:
case UPDATE_BLOCK:
case RESERVE_TRACK:
case SET_READ_AHEAD:
case PRE_FETCH:
case PRE_FETCH_16:
case ALLOW_OVERWRITE:
cmd->xfer = 0;
break;
case VERIFY_10:
case VERIFY_12:
case VERIFY_16:
if ((buf[1] & 2) == 0) {
cmd->xfer = 0;
} else if ((buf[1] & 4) != 0) {
cmd->xfer = 1;
}
cmd->xfer *= dev->blocksize;
break;
case MODE_SENSE:
break;
case WRITE_SAME_10:
case WRITE_SAME_16:
cmd->xfer = buf[1] & 1 ? 0 : dev->blocksize;
break;
case READ_CAPACITY_10:
cmd->xfer = 8;
break;
case READ_BLOCK_LIMITS:
cmd->xfer = 6;
break;
case SEND_VOLUME_TAG:
/* GPCMD_SET_STREAMING from multimedia commands. */
if (dev->type == TYPE_ROM) {
cmd->xfer = buf[10] | (buf[9] << 8);
} else {
cmd->xfer = buf[9] | (buf[8] << 8);
}
break;
case WRITE_6:
/* length 0 means 256 blocks */
if (cmd->xfer == 0) {
cmd->xfer = 256;
}
- /* fall through */
+ fallthrough;
case WRITE_10:
case WRITE_VERIFY_10:
case WRITE_12:
case WRITE_VERIFY_12:
case WRITE_16:
case WRITE_VERIFY_16:
cmd->xfer *= dev->blocksize;
break;
case READ_6:
case READ_REVERSE:
/* length 0 means 256 blocks */
if (cmd->xfer == 0) {
cmd->xfer = 256;
}
- /* fall through */
+ fallthrough;
case READ_10:
case READ_12:
case READ_16:
cmd->xfer *= dev->blocksize;
break;
case FORMAT_UNIT:
/* MMC mandates the parameter list to be 12-bytes long. Parameters
* for block devices are restricted to the header right now. */
if (dev->type == TYPE_ROM && (buf[1] & 16)) {
cmd->xfer = 12;
} else {
cmd->xfer = (buf[1] & 16) == 0 ? 0 : (buf[1] & 32 ? 8 : 4);
}
break;
case INQUIRY:
case RECEIVE_DIAGNOSTIC:
case SEND_DIAGNOSTIC:
cmd->xfer = buf[4] | (buf[3] << 8);
break;
case READ_CD:
case READ_BUFFER:
case WRITE_BUFFER:
case SEND_CUE_SHEET:
cmd->xfer = buf[8] | (buf[7] << 8) | (buf[6] << 16);
break;
case PERSISTENT_RESERVE_OUT:
cmd->xfer = ldl_be_p(&buf[5]) & 0xffffffffULL;
break;
case ERASE_12:
if (dev->type == TYPE_ROM) {
/* MMC command GET PERFORMANCE. */
cmd->xfer = scsi_get_performance_length(buf[9] | (buf[8] << 8),
buf[10], buf[1] & 0x1f);
}
break;
case MECHANISM_STATUS:
case READ_DVD_STRUCTURE:
case SEND_DVD_STRUCTURE:
case MAINTENANCE_OUT:
case MAINTENANCE_IN:
if (dev->type == TYPE_ROM) {
/* GPCMD_REPORT_KEY and GPCMD_SEND_KEY from multi media commands */
cmd->xfer = buf[9] | (buf[8] << 8);
}
break;
case ATA_PASSTHROUGH_12:
if (dev->type == TYPE_ROM) {
/* BLANK command of MMC */
cmd->xfer = 0;
} else {
cmd->xfer = ata_passthrough_12_xfer(dev, buf);
}
break;
case ATA_PASSTHROUGH_16:
cmd->xfer = ata_passthrough_16_xfer(dev, buf);
break;
}
return 0;
}
diff --git a/hw/scsi/scsi-disk.c b/hw/scsi/scsi-disk.c
index 6691f5edb8..6564ca638c 100644
--- a/hw/scsi/scsi-disk.c
+++ b/hw/scsi/scsi-disk.c
@@ -2256,86 +2256,86 @@ illegal_lba:
static int32_t scsi_disk_dma_command(SCSIRequest *req, uint8_t *buf)
{
SCSIDiskReq *r = DO_UPCAST(SCSIDiskReq, req, req);
SCSIDiskState *s = DO_UPCAST(SCSIDiskState, qdev, req->dev);
SCSIDiskClass *sdc = (SCSIDiskClass *) object_get_class(OBJECT(s));
uint32_t len;
uint8_t command;
command = buf[0];
if (!blk_is_available(s->qdev.conf.blk)) {
scsi_check_condition(r, SENSE_CODE(NO_MEDIUM));
return 0;
}
len = scsi_data_cdb_xfer(r->req.cmd.buf);
switch (command) {
case READ_6:
case READ_10:
case READ_12:
case READ_16:
trace_scsi_disk_dma_command_READ(r->req.cmd.lba, len);
/* Protection information is not supported. For SCSI versions 2 and
* older (as determined by snooping the guest's INQUIRY commands),
* there is no RD/WR/VRPROTECT, so skip this check in these versions.
*/
if (s->qdev.scsi_version > 2 && (r->req.cmd.buf[1] & 0xe0)) {
goto illegal_request;
}
if (!check_lba_range(s, r->req.cmd.lba, len)) {
goto illegal_lba;
}
r->sector = r->req.cmd.lba * (s->qdev.blocksize / BDRV_SECTOR_SIZE);
r->sector_count = len * (s->qdev.blocksize / BDRV_SECTOR_SIZE);
break;
case WRITE_6:
case WRITE_10:
case WRITE_12:
case WRITE_16:
case WRITE_VERIFY_10:
case WRITE_VERIFY_12:
case WRITE_VERIFY_16:
if (!blk_is_writable(s->qdev.conf.blk)) {
scsi_check_condition(r, SENSE_CODE(WRITE_PROTECTED));
return 0;
}
trace_scsi_disk_dma_command_WRITE(
(command & 0xe) == 0xe ? "And Verify " : "",
r->req.cmd.lba, len);
- /* fall through */
+ fallthrough;
case VERIFY_10:
case VERIFY_12:
case VERIFY_16:
/* We get here only for BYTCHK == 0x01 and only for scsi-block.
* As far as DMA is concerned, we can treat it the same as a write;
* scsi_block_do_sgio will send VERIFY commands.
*/
if (s->qdev.scsi_version > 2 && (r->req.cmd.buf[1] & 0xe0)) {
goto illegal_request;
}
if (!check_lba_range(s, r->req.cmd.lba, len)) {
goto illegal_lba;
}
r->sector = r->req.cmd.lba * (s->qdev.blocksize / BDRV_SECTOR_SIZE);
r->sector_count = len * (s->qdev.blocksize / BDRV_SECTOR_SIZE);
break;
default:
abort();
illegal_request:
scsi_check_condition(r, SENSE_CODE(INVALID_FIELD));
return 0;
illegal_lba:
scsi_check_condition(r, SENSE_CODE(LBA_OUT_OF_RANGE));
return 0;
}
r->need_fua_emulation = sdc->need_fua_emulation(&r->req.cmd);
if (r->sector_count == 0) {
scsi_req_complete(&r->req, GOOD);
}
assert(r->iov.iov_len == 0);
if (r->req.cmd.mode == SCSI_XFER_TO_DEV) {
return -r->sector_count * BDRV_SECTOR_SIZE;
} else {
return r->sector_count * BDRV_SECTOR_SIZE;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 40/78] hw/sd/sdhci.c: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (38 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 39/78] hw/scsi: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 41/78] linux-user: " Emmanouil Pitsidianakis
` (38 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Philippe Mathieu-Daudé, Bin Meng,
open list:SD (Secure Card)
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/sd/sdhci.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 5564765a9b..5c641d24de 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -75,138 +75,138 @@ static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc,
static void sdhci_check_capareg(SDHCIState *s, Error **errp)
{
uint64_t msk = s->capareg;
uint32_t val;
bool y;
switch (s->sd_spec_version) {
case 4:
val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4);
trace_sdhci_capareg("64-bit system bus (v4)", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II);
trace_sdhci_capareg("UHS-II", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3);
trace_sdhci_capareg("ADMA3", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0);
- /* fallthrough */
+ fallthrough;
case 3:
val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT);
trace_sdhci_capareg("async interrupt", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE);
if (val) {
error_setg(errp, "slot-type not supported");
return;
}
trace_sdhci_capareg("slot type", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0);
if (val != 2) {
val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT);
trace_sdhci_capareg("8-bit bus", val);
}
msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED);
trace_sdhci_capareg("bus speed mask", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH);
trace_sdhci_capareg("driver strength mask", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING);
trace_sdhci_capareg("timer re-tuning", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING);
trace_sdhci_capareg("use SDR50 tuning", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE);
trace_sdhci_capareg("re-tuning mode", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT);
trace_sdhci_capareg("clock multiplier", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0);
- /* fallthrough */
+ fallthrough;
case 2: /* default version */
val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2);
trace_sdhci_capareg("ADMA2", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1);
trace_sdhci_capareg("ADMA1", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT);
trace_sdhci_capareg("64-bit system bus (v3)", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0);
- /* fallthrough */
+ fallthrough;
case 1:
y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT);
msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ);
trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val);
if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) {
return;
}
msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ);
trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val);
if (sdhci_check_capab_freq_range(s, "base", val, errp)) {
return;
}
msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH);
if (val >= 3) {
error_setg(errp, "block size can be 512, 1024 or 2048 only");
return;
}
trace_sdhci_capareg("max block length", sdhci_get_fifolen(s));
msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED);
trace_sdhci_capareg("high speed", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA);
trace_sdhci_capareg("SDMA", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME);
trace_sdhci_capareg("suspend/resume", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33);
trace_sdhci_capareg("3.3v", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30);
trace_sdhci_capareg("3.0v", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18);
trace_sdhci_capareg("1.8v", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0);
break;
default:
error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version);
}
if (msk) {
qemu_log_mask(LOG_UNIMP,
"SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk);
}
}
@@ -1688,160 +1688,160 @@ static void
usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
{
SDHCIState *s = SYSBUS_SDHCI(opaque);
uint8_t hostctl1;
uint32_t value = (uint32_t)val;
switch (offset) {
case USDHC_DLL_CTRL:
case USDHC_TUNE_CTRL_STATUS:
case USDHC_UNDOCUMENTED_REG27:
case USDHC_TUNING_CTRL:
case USDHC_WTMK_LVL:
break;
case USDHC_VENDOR_SPEC:
s->vendor_spec = value;
switch (s->vendor) {
case SDHCI_VENDOR_IMX:
if (value & USDHC_IMX_FRC_SDCLK_ON) {
s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF;
} else {
s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF;
}
break;
default:
break;
}
break;
case SDHC_HOSTCTL:
/*
* Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL)
*
* 7 6 5 4 3 2 1 0
* |-----------+--------+--------+-----------+----------+---------|
* | Card | Card | Endian | DATA3 | Data | Led |
* | Detect | Detect | Mode | as Card | Transfer | Control |
* | Signal | Test | | Detection | Width | |
* | Selection | Level | | Pin | | |
* |-----------+--------+--------+-----------+----------+---------|
*
* and 0x29
*
* 15 10 9 8
* |----------+------|
* | Reserved | DMA |
* | | Sel. |
* | | |
* |----------+------|
*
* and here's what SDCHI spec expects those offsets to be:
*
* 0x28 (Host Control Register)
*
* 7 6 5 4 3 2 1 0
* |--------+--------+----------+------+--------+----------+---------|
* | Card | Card | Extended | DMA | High | Data | LED |
* | Detect | Detect | Data | Sel. | Speed | Transfer | Control |
* | Signal | Test | Transfer | | Enable | Width | |
* | Sel. | Level | Width | | | | |
* |--------+--------+----------+------+--------+----------+---------|
*
* and 0x29 (Power Control Register)
*
* |----------------------------------|
* | Power Control Register |
* | |
* | Description omitted, |
* | since it has no analog in ESDHCI |
* | |
* |----------------------------------|
*
* Since offsets 0x2A and 0x2B should be compatible between
* both IP specs we only need to reconcile least 16-bit of the
* word we've been given.
*/
/*
* First, save bits 7 6 and 0 since they are identical
*/
hostctl1 = value & (SDHC_CTRL_LED |
SDHC_CTRL_CDTEST_INS |
SDHC_CTRL_CDTEST_EN);
/*
* Second, split "Data Transfer Width" from bits 2 and 1 in to
* bits 5 and 1
*/
if (value & USDHC_CTRL_8BITBUS) {
hostctl1 |= SDHC_CTRL_8BITBUS;
}
if (value & USDHC_CTRL_4BITBUS) {
hostctl1 |= USDHC_CTRL_4BITBUS;
}
/*
* Third, move DMA select from bits 9 and 8 to bits 4 and 3
*/
hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3));
/*
* Now place the corrected value into low 16-bit of the value
* we are going to give standard SDHCI write function
*
* NOTE: This transformation should be the inverse of what can
* be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux
* kernel
*/
value &= ~UINT16_MAX;
value |= hostctl1;
value |= (uint16_t)s->pwrcon << 8;
sdhci_write(opaque, offset, value, size);
break;
case USDHC_MIX_CTRL:
/*
* So, when SD/MMC stack in Linux tries to write to "Transfer
* Mode Register", ESDHC i.MX quirk code will translate it
* into a write to ESDHC_MIX_CTRL, so we do the opposite in
* order to get where we started
*
* Note that Auto CMD23 Enable bit is located in a wrong place
* on i.MX, but since it is not used by QEMU we do not care.
*
* We don't want to call sdhci_write(.., SDHC_TRNMOD, ...)
* here because it will result in a call to
* sdhci_send_command(s) which we don't want.
*
*/
s->trnmod = value & UINT16_MAX;
break;
case SDHC_TRNMOD:
/*
* Similar to above, but this time a write to "Command
* Register" will be translated into a 4-byte write to
* "Transfer Mode register" where lower 16-bit of value would
* be set to zero. So what we do is fill those bits with
* cached value from s->trnmod and let the SDHCI
* infrastructure handle the rest
*/
sdhci_write(opaque, offset, val | s->trnmod, size);
break;
case SDHC_BLKSIZE:
/*
* ESDHCI does not implement "Host SDMA Buffer Boundary", and
* Linux driver will try to zero this field out which will
* break the rest of SDHCI emulation.
*
* Linux defaults to maximum possible setting (512K boundary)
* and it seems to be the only option that i.MX IP implements,
* so we artificially set it to that value.
*/
val |= 0x7 << 12;
- /* FALLTHROUGH */
+ fallthrough;
default:
sdhci_write(opaque, offset, val, size);
break;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 41/78] linux-user: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (39 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 40/78] hw/sd/sdhci.c: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 42/78] hw/i386: " Emmanouil Pitsidianakis
` (37 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Laurent Vivier
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
linux-user/mips/cpu_loop.c | 8 ++++----
linux-user/mmap.c | 2 +-
linux-user/syscall.c | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index 8735e58bad..38ddcadfc6 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -63,68 +63,68 @@ static void do_tr_or_bp(CPUMIPSState *env, unsigned int code, bool trap)
void cpu_loop(CPUMIPSState *env)
{
CPUState *cs = env_cpu(env);
int trapnr, si_code;
unsigned int code;
abi_long ret;
# ifdef TARGET_ABI_MIPSO32
unsigned int syscall_num;
# endif
for(;;) {
cpu_exec_start(cs);
trapnr = cpu_exec(cs);
cpu_exec_end(cs);
process_queued_cpu_work(cs);
switch(trapnr) {
case EXCP_SYSCALL:
env->active_tc.PC += 4;
# ifdef TARGET_ABI_MIPSO32
syscall_num = env->active_tc.gpr[2] - 4000;
if (syscall_num >= sizeof(mips_syscall_args)) {
/* syscall_num is larger that any defined for MIPS O32 */
ret = -TARGET_ENOSYS;
} else if (mips_syscall_args[syscall_num] ==
MIPS_SYSCALL_NUMBER_UNUSED) {
/* syscall_num belongs to the range not defined for MIPS O32 */
ret = -TARGET_ENOSYS;
} else {
/* syscall_num is valid */
int nb_args;
abi_ulong sp_reg;
abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
nb_args = mips_syscall_args[syscall_num];
sp_reg = env->active_tc.gpr[29];
switch (nb_args) {
/* these arguments are taken from the stack */
case 8:
if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
goto done_syscall;
}
- /* fall through */
+ fallthrough;
case 7:
if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
goto done_syscall;
}
- /* fall through */
+ fallthrough;
case 6:
if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
goto done_syscall;
}
- /* fall through */
+ fallthrough;
case 5:
if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
goto done_syscall;
}
- /* fall through */
+ fallthrough;
default:
break;
}
ret = do_syscall(env, env->active_tc.gpr[2],
env->active_tc.gpr[4],
env->active_tc.gpr[5],
env->active_tc.gpr[6],
env->active_tc.gpr[7],
arg5, arg6, arg7, arg8);
}
diff --git a/linux-user/mmap.c b/linux-user/mmap.c
index 8ccaab7859..ff33b4ccf6 100644
--- a/linux-user/mmap.c
+++ b/linux-user/mmap.c
@@ -960,84 +960,84 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong old_size,
abi_long target_madvise(abi_ulong start, abi_ulong len_in, int advice)
{
abi_ulong len;
int ret = 0;
if (start & ~TARGET_PAGE_MASK) {
return -TARGET_EINVAL;
}
if (len_in == 0) {
return 0;
}
len = TARGET_PAGE_ALIGN(len_in);
if (len == 0 || !guest_range_valid_untagged(start, len)) {
return -TARGET_EINVAL;
}
/* Translate for some architectures which have different MADV_xxx values */
switch (advice) {
case TARGET_MADV_DONTNEED: /* alpha */
advice = MADV_DONTNEED;
break;
case TARGET_MADV_WIPEONFORK: /* parisc */
advice = MADV_WIPEONFORK;
break;
case TARGET_MADV_KEEPONFORK: /* parisc */
advice = MADV_KEEPONFORK;
break;
/* we do not care about the other MADV_xxx values yet */
}
/*
* Most advice values are hints, so ignoring and returning success is ok.
*
* However, some advice values such as MADV_DONTNEED, MADV_WIPEONFORK and
* MADV_KEEPONFORK are not hints and need to be emulated.
*
* A straight passthrough for those may not be safe because qemu sometimes
* turns private file-backed mappings into anonymous mappings.
* If all guest pages have PAGE_PASSTHROUGH set, mappings have the
* same semantics for the host as for the guest.
*
* We pass through MADV_WIPEONFORK and MADV_KEEPONFORK if possible and
* return failure if not.
*
* MADV_DONTNEED is passed through as well, if possible.
* If passthrough isn't possible, we nevertheless (wrongly!) return
* success, which is broken but some userspace programs fail to work
* otherwise. Completely implementing such emulation is quite complicated
* though.
*/
mmap_lock();
switch (advice) {
case MADV_WIPEONFORK:
case MADV_KEEPONFORK:
ret = -EINVAL;
- /* fall through */
+ fallthrough;
case MADV_DONTNEED:
if (page_check_range(start, len, PAGE_PASSTHROUGH)) {
ret = get_errno(madvise(g2h_untagged(start), len, advice));
if ((advice == MADV_DONTNEED) && (ret == 0)) {
page_reset_target_data(start, start + len - 1);
}
}
}
mmap_unlock();
return ret;
}
#ifndef TARGET_FORCE_SHMLBA
/*
* For most architectures, SHMLBA is the same as the page size;
* some architectures have larger values, in which case they should
* define TARGET_FORCE_SHMLBA and provide a target_shmlba() function.
* This corresponds to the kernel arch code defining __ARCH_FORCE_SHMLBA
* and defining its own value for SHMLBA.
*
* The kernel also permits SHMLBA to be set by the architecture to a
* value larger than the page size without setting __ARCH_FORCE_SHMLBA;
* this means that addresses are rounded to the large size if
* SHM_RND is set but addresses not aligned to that size are not rejected
* as long as they are at least page-aligned. Since the only architecture
* which uses this is ia64 this code doesn't provide for that oddity.
*/
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index d49cd314a2..d15817846c 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -7740,74 +7740,74 @@ static int do_safe_futex(int *uaddr, int op, int val,
/* ??? Using host futex calls even when target atomic operations
are not really atomic probably breaks things. However implementing
futexes locally would make futexes shared between multiple processes
tricky. However they're probably useless because guest atomic
operations won't work either. */
#if defined(TARGET_NR_futex) || defined(TARGET_NR_futex_time64)
static int do_futex(CPUState *cpu, bool time64, target_ulong uaddr,
int op, int val, target_ulong timeout,
target_ulong uaddr2, int val3)
{
struct timespec ts, *pts = NULL;
void *haddr2 = NULL;
int base_op;
/* We assume FUTEX_* constants are the same on both host and target. */
#ifdef FUTEX_CMD_MASK
base_op = op & FUTEX_CMD_MASK;
#else
base_op = op;
#endif
switch (base_op) {
case FUTEX_WAIT:
case FUTEX_WAIT_BITSET:
val = tswap32(val);
break;
case FUTEX_WAIT_REQUEUE_PI:
val = tswap32(val);
haddr2 = g2h(cpu, uaddr2);
break;
case FUTEX_LOCK_PI:
case FUTEX_LOCK_PI2:
break;
case FUTEX_WAKE:
case FUTEX_WAKE_BITSET:
case FUTEX_TRYLOCK_PI:
case FUTEX_UNLOCK_PI:
timeout = 0;
break;
case FUTEX_FD:
val = target_to_host_signal(val);
timeout = 0;
break;
case FUTEX_CMP_REQUEUE:
case FUTEX_CMP_REQUEUE_PI:
val3 = tswap32(val3);
- /* fall through */
+ fallthrough;
case FUTEX_REQUEUE:
case FUTEX_WAKE_OP:
/*
* For these, the 4th argument is not TIMEOUT, but VAL2.
* But the prototype of do_safe_futex takes a pointer, so
* insert casts to satisfy the compiler. We do not need
* to tswap VAL2 since it's not compared to guest memory.
*/
pts = (struct timespec *)(uintptr_t)timeout;
timeout = 0;
haddr2 = g2h(cpu, uaddr2);
break;
default:
return -TARGET_ENOSYS;
}
if (timeout) {
pts = &ts;
if (time64
? target_to_host_timespec64(pts, timeout)
: target_to_host_timespec(pts, timeout)) {
return -TARGET_EFAULT;
}
}
return do_safe_futex(g2h(cpu, uaddr), op, val, pts, haddr2, val3);
}
#endif
#if defined(TARGET_NR_name_to_handle_at) && defined(CONFIG_OPEN_BY_HANDLE)
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 42/78] hw/i386: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (40 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 41/78] linux-user: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 43/78] hw/misc: " Emmanouil Pitsidianakis
` (36 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Michael S. Tsirkin, Peter Xu, Jason Wang,
Paolo Bonzini, Richard Henderson, Eduardo Habkost,
Marcel Apfelbaum, David Woodhouse, Paul Durrant
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/i386/intel_iommu.c | 4 ++--
hw/i386/kvm/xen_evtchn.c | 2 +-
hw/i386/x86.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 2c832ab68b..bdb2ea3ac5 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2100,29 +2100,29 @@ static void vtd_context_device_invalidate(IntelIOMMUState *s,
/* Context-cache invalidation
* Returns the Context Actual Invalidation Granularity.
* @val: the content of the CCMD_REG
*/
static uint64_t vtd_context_cache_invalidate(IntelIOMMUState *s, uint64_t val)
{
uint64_t caig;
uint64_t type = val & VTD_CCMD_CIRG_MASK;
switch (type) {
case VTD_CCMD_DOMAIN_INVL:
- /* Fall through */
+ fallthrough;
case VTD_CCMD_GLOBAL_INVL:
caig = VTD_CCMD_GLOBAL_INVL_A;
vtd_context_global_invalidate(s);
break;
case VTD_CCMD_DEVICE_INVL:
caig = VTD_CCMD_DEVICE_INVL_A;
vtd_context_device_invalidate(s, VTD_CCMD_SID(val), VTD_CCMD_FM(val));
break;
default:
error_report_once("%s: invalid context: 0x%" PRIx64,
__func__, val);
caig = 0;
}
return caig;
}
@@ -2513,34 +2513,34 @@ static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
static bool vtd_process_context_cache_desc(IntelIOMMUState *s,
VTDInvDesc *inv_desc)
{
uint16_t sid, fmask;
if ((inv_desc->lo & VTD_INV_DESC_CC_RSVD) || inv_desc->hi) {
error_report_once("%s: invalid cc inv desc: hi=%"PRIx64", lo=%"PRIx64
" (reserved nonzero)", __func__, inv_desc->hi,
inv_desc->lo);
return false;
}
switch (inv_desc->lo & VTD_INV_DESC_CC_G) {
case VTD_INV_DESC_CC_DOMAIN:
trace_vtd_inv_desc_cc_domain(
(uint16_t)VTD_INV_DESC_CC_DID(inv_desc->lo));
- /* Fall through */
+ fallthrough;
case VTD_INV_DESC_CC_GLOBAL:
vtd_context_global_invalidate(s);
break;
case VTD_INV_DESC_CC_DEVICE:
sid = VTD_INV_DESC_CC_SID(inv_desc->lo);
fmask = VTD_INV_DESC_CC_FM(inv_desc->lo);
vtd_context_device_invalidate(s, sid, fmask);
break;
default:
error_report_once("%s: invalid cc inv desc: hi=%"PRIx64", lo=%"PRIx64
" (invalid type)", __func__, inv_desc->hi,
inv_desc->lo);
return false;
}
return true;
}
diff --git a/hw/i386/kvm/xen_evtchn.c b/hw/i386/kvm/xen_evtchn.c
index a731738411..d15e324f6e 100644
--- a/hw/i386/kvm/xen_evtchn.c
+++ b/hw/i386/kvm/xen_evtchn.c
@@ -2028,71 +2028,71 @@ static int find_be_port(XenEvtchnState *s, struct xenevtchn_handle *xc)
int xen_be_evtchn_bind_interdomain(struct xenevtchn_handle *xc, uint32_t domid,
evtchn_port_t guest_port)
{
XenEvtchnState *s = xen_evtchn_singleton;
XenEvtchnPort *gp;
uint16_t be_port = 0;
int ret;
if (!s) {
return -ENOTSUP;
}
if (!xc) {
return -EFAULT;
}
if (domid != xen_domid) {
return -ESRCH;
}
if (!valid_port(guest_port)) {
return -EINVAL;
}
qemu_mutex_lock(&s->port_lock);
/* The guest has to have an unbound port waiting for us to bind */
gp = &s->port_table[guest_port];
switch (gp->type) {
case EVTCHNSTAT_interdomain:
/* Allow rebinding after migration, preserve port # if possible */
be_port = gp->type_val & ~PORT_INFO_TYPEVAL_REMOTE_QEMU;
assert(be_port != 0);
if (!s->be_handles[be_port]) {
s->be_handles[be_port] = xc;
xc->guest_port = guest_port;
ret = xc->be_port = be_port;
if (kvm_xen_has_cap(EVTCHN_SEND)) {
assign_kernel_eventfd(gp->type, guest_port, xc->fd);
}
break;
}
- /* fall through */
+ fallthrough;
case EVTCHNSTAT_unbound:
be_port = find_be_port(s, xc);
if (!be_port) {
ret = -ENOSPC;
goto out;
}
gp->type = EVTCHNSTAT_interdomain;
gp->type_val = be_port | PORT_INFO_TYPEVAL_REMOTE_QEMU;
xc->guest_port = guest_port;
if (kvm_xen_has_cap(EVTCHN_SEND)) {
assign_kernel_eventfd(gp->type, guest_port, xc->fd);
}
ret = be_port;
break;
default:
ret = -EINVAL;
break;
}
out:
qemu_mutex_unlock(&s->port_lock);
return ret;
}
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index b3d054889b..c1fd0a966a 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -597,32 +597,32 @@ DeviceState *cpu_get_current_apic(void)
void gsi_handler(void *opaque, int n, int level)
{
GSIState *s = opaque;
trace_x86_gsi_interrupt(n, level);
switch (n) {
case 0 ... ISA_NUM_IRQS - 1:
if (s->i8259_irq[n]) {
/* Under KVM, Kernel will forward to both PIC and IOAPIC */
qemu_set_irq(s->i8259_irq[n], level);
}
- /* fall through */
+ fallthrough;
case ISA_NUM_IRQS ... IOAPIC_NUM_PINS - 1:
#ifdef CONFIG_XEN_EMU
/*
* Xen delivers the GSI to the Legacy PIC (not that Legacy PIC
* routing actually works properly under Xen). And then to
* *either* the PIRQ handling or the I/OAPIC depending on
* whether the former wants it.
*/
if (xen_mode == XEN_EMULATE && xen_evtchn_set_gsi(n, level)) {
break;
}
#endif
qemu_set_irq(s->ioapic_irq[n], level);
break;
case IO_APIC_SECONDARY_IRQBASE
... IO_APIC_SECONDARY_IRQBASE + IOAPIC_NUM_PINS - 1:
qemu_set_irq(s->ioapic2_irq[n - IO_APIC_SECONDARY_IRQBASE], level);
break;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 43/78] hw/misc: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (41 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 42/78] hw/i386: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 44/78] hw/m68k/mcf_intc.c: " Emmanouil Pitsidianakis
` (35 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Peter Maydell, Cédric Le Goater,
Andrew Jeffery, Joel Stanley, Philippe Mathieu-Daudé,
Mark Cave-Ayland, open list:ARM cores,
open list:New World (mac99)
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/misc/a9scu.c | 2 ++
hw/misc/aspeed_scu.c | 2 +-
hw/misc/bcm2835_property.c | 12 ++++++------
hw/misc/mos6522.c | 4 ++--
4 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c
index a375ebc987..b422bec3c4 100644
--- a/hw/misc/a9scu.c
+++ b/hw/misc/a9scu.c
@@ -21,26 +21,27 @@
static uint64_t a9_scu_read(void *opaque, hwaddr offset,
unsigned size)
{
A9SCUState *s = (A9SCUState *)opaque;
switch (offset) {
case 0x00: /* Control */
return s->control;
case 0x04: /* Configuration */
return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1);
case 0x08: /* CPU Power Status */
return s->status;
case 0x0c: /* Invalidate All Registers In Secure State */
return 0;
case 0x40: /* Filtering Start Address Register */
case 0x44: /* Filtering End Address Register */
/* RAZ/WI, like an implementation with only one AXI master */
return 0;
case 0x50: /* SCU Access Control Register */
case 0x54: /* SCU Non-secure Access Control Register */
/* unimplemented, fall through */
+ fallthrough;
default:
qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx"\n",
__func__, offset);
return 0;
}
}
@@ -48,31 +49,32 @@ static uint64_t a9_scu_read(void *opaque, hwaddr offset,
static void a9_scu_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
A9SCUState *s = (A9SCUState *)opaque;
switch (offset) {
case 0x00: /* Control */
s->control = value & 1;
break;
case 0x4: /* Configuration: RO */
break;
case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */
s->status = value;
break;
case 0x0c: /* Invalidate All Registers In Secure State */
/* no-op as we do not implement caches */
break;
case 0x40: /* Filtering Start Address Register */
case 0x44: /* Filtering End Address Register */
/* RAZ/WI, like an implementation with only one AXI master */
break;
case 0x50: /* SCU Access Control Register */
case 0x54: /* SCU Non-secure Access Control Register */
/* unimplemented, fall through */
+ fallthrough;
default:
qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx
" value 0x%"PRIx64"\n",
__func__, offset, value);
break;
}
}
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 8335364906..4a1ea2fa21 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -645,65 +645,65 @@ static uint64_t aspeed_ast2600_scu_read(void *opaque, hwaddr offset,
static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset,
uint64_t data64, unsigned size)
{
AspeedSCUState *s = ASPEED_SCU(opaque);
int reg = TO_REG(offset);
/* Truncate here so bitwise operations below behave as expected */
uint32_t data = data64;
if (reg >= ASPEED_AST2600_SCU_NR_REGS) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
__func__, offset);
return;
}
if (reg > PROT_KEY && !s->regs[PROT_KEY]) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
}
trace_aspeed_scu_write(offset, size, data);
switch (reg) {
case AST2600_PROT_KEY:
s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
return;
case AST2600_HW_STRAP1:
case AST2600_HW_STRAP2:
if (s->regs[reg + 2]) {
return;
}
- /* fall through */
+ fallthrough;
case AST2600_SYS_RST_CTRL:
case AST2600_SYS_RST_CTRL2:
case AST2600_CLK_STOP_CTRL:
case AST2600_CLK_STOP_CTRL2:
/* W1S (Write 1 to set) registers */
s->regs[reg] |= data;
return;
case AST2600_SYS_RST_CTRL_CLR:
case AST2600_SYS_RST_CTRL2_CLR:
case AST2600_CLK_STOP_CTRL_CLR:
case AST2600_CLK_STOP_CTRL2_CLR:
case AST2600_HW_STRAP1_CLR:
case AST2600_HW_STRAP2_CLR:
/*
* W1C (Write 1 to clear) registers are offset by one address from
* the data register
*/
s->regs[reg - 1] &= ~data;
return;
case AST2600_RNG_DATA:
case AST2600_SILICON_REV:
case AST2600_SILICON_REV2:
case AST2600_CHIP_ID0:
case AST2600_CHIP_ID1:
/* Add read only registers here */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
__func__, offset);
return;
}
s->regs[reg] = data;
}
diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c
index 4ed9faa54a..98170f34a6 100644
--- a/hw/misc/bcm2835_property.c
+++ b/hw/misc/bcm2835_property.c
@@ -24,303 +24,303 @@
static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value)
{
uint32_t tag;
uint32_t bufsize;
uint32_t tot_len;
size_t resplen;
uint32_t tmp;
int n;
uint32_t offset, length, color;
/*
* Copy the current state of the framebuffer config; we will update
* this copy as we process tags and then ask the framebuffer to use
* it at the end.
*/
BCM2835FBConfig fbconfig = s->fbdev->config;
bool fbconfig_updated = false;
value &= ~0xf;
s->addr = value;
tot_len = ldl_le_phys(&s->dma_as, value);
/* @(addr + 4) : Buffer response code */
value = s->addr + 8;
while (value + 8 <= s->addr + tot_len) {
tag = ldl_le_phys(&s->dma_as, value);
bufsize = ldl_le_phys(&s->dma_as, value + 4);
/* @(value + 8) : Request/response indicator */
resplen = 0;
switch (tag) {
case RPI_FWREQ_PROPERTY_END:
break;
case RPI_FWREQ_GET_FIRMWARE_REVISION:
stl_le_phys(&s->dma_as, value + 12, 346337);
resplen = 4;
break;
case RPI_FWREQ_GET_BOARD_MODEL:
qemu_log_mask(LOG_UNIMP,
"bcm2835_property: 0x%08x get board model NYI\n",
tag);
resplen = 4;
break;
case RPI_FWREQ_GET_BOARD_REVISION:
stl_le_phys(&s->dma_as, value + 12, s->board_rev);
resplen = 4;
break;
case RPI_FWREQ_GET_BOARD_MAC_ADDRESS:
resplen = sizeof(s->macaddr.a);
dma_memory_write(&s->dma_as, value + 12, s->macaddr.a, resplen,
MEMTXATTRS_UNSPECIFIED);
break;
case RPI_FWREQ_GET_BOARD_SERIAL:
qemu_log_mask(LOG_UNIMP,
"bcm2835_property: 0x%08x get board serial NYI\n",
tag);
resplen = 8;
break;
case RPI_FWREQ_GET_ARM_MEMORY:
/* base */
stl_le_phys(&s->dma_as, value + 12, 0);
/* size */
stl_le_phys(&s->dma_as, value + 16, s->fbdev->vcram_base);
resplen = 8;
break;
case RPI_FWREQ_GET_VC_MEMORY:
/* base */
stl_le_phys(&s->dma_as, value + 12, s->fbdev->vcram_base);
/* size */
stl_le_phys(&s->dma_as, value + 16, s->fbdev->vcram_size);
resplen = 8;
break;
case RPI_FWREQ_SET_POWER_STATE:
/* Assume that whatever device they asked for exists,
* and we'll just claim we set it to the desired state
*/
tmp = ldl_le_phys(&s->dma_as, value + 16);
stl_le_phys(&s->dma_as, value + 16, (tmp & 1));
resplen = 8;
break;
/* Clocks */
case RPI_FWREQ_GET_CLOCK_STATE:
stl_le_phys(&s->dma_as, value + 16, 0x1);
resplen = 8;
break;
case RPI_FWREQ_SET_CLOCK_STATE:
qemu_log_mask(LOG_UNIMP,
"bcm2835_property: 0x%08x set clock state NYI\n",
tag);
resplen = 8;
break;
case RPI_FWREQ_GET_CLOCK_RATE:
case RPI_FWREQ_GET_MAX_CLOCK_RATE:
case RPI_FWREQ_GET_MIN_CLOCK_RATE:
switch (ldl_le_phys(&s->dma_as, value + 12)) {
case RPI_FIRMWARE_EMMC_CLK_ID:
stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_EMMC_CLK_RATE);
break;
case RPI_FIRMWARE_UART_CLK_ID:
stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_UART_CLK_RATE);
break;
case RPI_FIRMWARE_CORE_CLK_ID:
stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_CORE_CLK_RATE);
break;
default:
stl_le_phys(&s->dma_as, value + 16,
RPI_FIRMWARE_DEFAULT_CLK_RATE);
break;
}
resplen = 8;
break;
case RPI_FWREQ_SET_CLOCK_RATE:
case RPI_FWREQ_SET_MAX_CLOCK_RATE:
case RPI_FWREQ_SET_MIN_CLOCK_RATE:
qemu_log_mask(LOG_UNIMP,
"bcm2835_property: 0x%08x set clock rate NYI\n",
tag);
resplen = 8;
break;
/* Temperature */
case RPI_FWREQ_GET_TEMPERATURE:
stl_le_phys(&s->dma_as, value + 16, 25000);
resplen = 8;
break;
case RPI_FWREQ_GET_MAX_TEMPERATURE:
stl_le_phys(&s->dma_as, value + 16, 99000);
resplen = 8;
break;
/* Frame buffer */
case RPI_FWREQ_FRAMEBUFFER_ALLOCATE:
stl_le_phys(&s->dma_as, value + 12, fbconfig.base);
stl_le_phys(&s->dma_as, value + 16,
bcm2835_fb_get_size(&fbconfig));
resplen = 8;
break;
case RPI_FWREQ_FRAMEBUFFER_RELEASE:
resplen = 0;
break;
case RPI_FWREQ_FRAMEBUFFER_BLANK:
resplen = 4;
break;
case RPI_FWREQ_FRAMEBUFFER_TEST_PHYSICAL_WIDTH_HEIGHT:
case RPI_FWREQ_FRAMEBUFFER_TEST_VIRTUAL_WIDTH_HEIGHT:
resplen = 8;
break;
case RPI_FWREQ_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT:
fbconfig.xres = ldl_le_phys(&s->dma_as, value + 12);
fbconfig.yres = ldl_le_phys(&s->dma_as, value + 16);
bcm2835_fb_validate_config(&fbconfig);
fbconfig_updated = true;
- /* fall through */
+ fallthrough;
case RPI_FWREQ_FRAMEBUFFER_GET_PHYSICAL_WIDTH_HEIGHT:
stl_le_phys(&s->dma_as, value + 12, fbconfig.xres);
stl_le_phys(&s->dma_as, value + 16, fbconfig.yres);
resplen = 8;
break;
case RPI_FWREQ_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT:
fbconfig.xres_virtual = ldl_le_phys(&s->dma_as, value + 12);
fbconfig.yres_virtual = ldl_le_phys(&s->dma_as, value + 16);
bcm2835_fb_validate_config(&fbconfig);
fbconfig_updated = true;
- /* fall through */
+ fallthrough;
case RPI_FWREQ_FRAMEBUFFER_GET_VIRTUAL_WIDTH_HEIGHT:
stl_le_phys(&s->dma_as, value + 12, fbconfig.xres_virtual);
stl_le_phys(&s->dma_as, value + 16, fbconfig.yres_virtual);
resplen = 8;
break;
case RPI_FWREQ_FRAMEBUFFER_TEST_DEPTH:
resplen = 4;
break;
case RPI_FWREQ_FRAMEBUFFER_SET_DEPTH:
fbconfig.bpp = ldl_le_phys(&s->dma_as, value + 12);
bcm2835_fb_validate_config(&fbconfig);
fbconfig_updated = true;
- /* fall through */
+ fallthrough;
case RPI_FWREQ_FRAMEBUFFER_GET_DEPTH:
stl_le_phys(&s->dma_as, value + 12, fbconfig.bpp);
resplen = 4;
break;
case RPI_FWREQ_FRAMEBUFFER_TEST_PIXEL_ORDER:
resplen = 4;
break;
case RPI_FWREQ_FRAMEBUFFER_SET_PIXEL_ORDER:
fbconfig.pixo = ldl_le_phys(&s->dma_as, value + 12);
bcm2835_fb_validate_config(&fbconfig);
fbconfig_updated = true;
- /* fall through */
+ fallthrough;
case RPI_FWREQ_FRAMEBUFFER_GET_PIXEL_ORDER:
stl_le_phys(&s->dma_as, value + 12, fbconfig.pixo);
resplen = 4;
break;
case RPI_FWREQ_FRAMEBUFFER_TEST_ALPHA_MODE:
resplen = 4;
break;
case RPI_FWREQ_FRAMEBUFFER_SET_ALPHA_MODE:
fbconfig.alpha = ldl_le_phys(&s->dma_as, value + 12);
bcm2835_fb_validate_config(&fbconfig);
fbconfig_updated = true;
- /* fall through */
+ fallthrough;
case RPI_FWREQ_FRAMEBUFFER_GET_ALPHA_MODE:
stl_le_phys(&s->dma_as, value + 12, fbconfig.alpha);
resplen = 4;
break;
case RPI_FWREQ_FRAMEBUFFER_GET_PITCH:
stl_le_phys(&s->dma_as, value + 12,
bcm2835_fb_get_pitch(&fbconfig));
resplen = 4;
break;
case RPI_FWREQ_FRAMEBUFFER_TEST_VIRTUAL_OFFSET:
resplen = 8;
break;
case RPI_FWREQ_FRAMEBUFFER_SET_VIRTUAL_OFFSET:
fbconfig.xoffset = ldl_le_phys(&s->dma_as, value + 12);
fbconfig.yoffset = ldl_le_phys(&s->dma_as, value + 16);
bcm2835_fb_validate_config(&fbconfig);
fbconfig_updated = true;
- /* fall through */
+ fallthrough;
case RPI_FWREQ_FRAMEBUFFER_GET_VIRTUAL_OFFSET:
stl_le_phys(&s->dma_as, value + 12, fbconfig.xoffset);
stl_le_phys(&s->dma_as, value + 16, fbconfig.yoffset);
resplen = 8;
break;
case RPI_FWREQ_FRAMEBUFFER_GET_OVERSCAN:
case RPI_FWREQ_FRAMEBUFFER_TEST_OVERSCAN:
case RPI_FWREQ_FRAMEBUFFER_SET_OVERSCAN:
stl_le_phys(&s->dma_as, value + 12, 0);
stl_le_phys(&s->dma_as, value + 16, 0);
stl_le_phys(&s->dma_as, value + 20, 0);
stl_le_phys(&s->dma_as, value + 24, 0);
resplen = 16;
break;
case RPI_FWREQ_FRAMEBUFFER_SET_PALETTE:
offset = ldl_le_phys(&s->dma_as, value + 12);
length = ldl_le_phys(&s->dma_as, value + 16);
n = 0;
while (n < length - offset) {
color = ldl_le_phys(&s->dma_as, value + 20 + (n << 2));
stl_le_phys(&s->dma_as,
s->fbdev->vcram_base + ((offset + n) << 2), color);
n++;
}
stl_le_phys(&s->dma_as, value + 12, 0);
resplen = 4;
break;
case RPI_FWREQ_FRAMEBUFFER_GET_NUM_DISPLAYS:
stl_le_phys(&s->dma_as, value + 12, 1);
resplen = 4;
break;
case RPI_FWREQ_GET_DMA_CHANNELS:
/* channels 2-5 */
stl_le_phys(&s->dma_as, value + 12, 0x003C);
resplen = 4;
break;
case RPI_FWREQ_GET_COMMAND_LINE:
/*
* We follow the firmware behaviour: no NUL terminator is
* written to the buffer, and if the buffer is too short
* we report the required length in the response header
* and copy nothing to the buffer.
*/
resplen = strlen(s->command_line);
if (bufsize >= resplen)
address_space_write(&s->dma_as, value + 12,
MEMTXATTRS_UNSPECIFIED, s->command_line,
resplen);
break;
default:
qemu_log_mask(LOG_UNIMP,
"bcm2835_property: unhandled tag 0x%08x\n", tag);
break;
}
trace_bcm2835_mbox_property(tag, bufsize, resplen);
if (tag == 0) {
break;
}
stl_le_phys(&s->dma_as, value + 8, (1 << 31) | resplen);
value += bufsize + 12;
}
/* Reconfigure framebuffer if required */
if (fbconfig_updated) {
bcm2835_fb_reconfigure(s->fbdev, &fbconfig);
}
/* Buffer response code */
stl_le_phys(&s->dma_as, s->addr + 4, (1 << 31));
}
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index d6ba47bde9..a62349e6a0 100644
--- a/hw/misc/mos6522.c
+++ b/hw/misc/mos6522.c
@@ -296,97 +296,97 @@ static void mos6522_portB_write(MOS6522State *s)
uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size)
{
MOS6522State *s = opaque;
uint32_t val;
int ctrl;
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (now >= s->timers[0].next_irq_time) {
mos6522_timer1_update(s, &s->timers[0], now);
s->ifr |= T1_INT;
}
if (now >= s->timers[1].next_irq_time) {
mos6522_timer2_update(s, &s->timers[1], now);
s->ifr |= T2_INT;
}
switch (addr) {
case VIA_REG_B:
val = s->b;
ctrl = (s->pcr & CB2_CTRL_MASK) >> CB2_CTRL_SHIFT;
if (!(ctrl & C2_IND)) {
s->ifr &= ~CB2_INT;
}
s->ifr &= ~CB1_INT;
mos6522_update_irq(s);
break;
case VIA_REG_A:
qemu_log_mask(LOG_UNIMP, "Read access to register A with handshake");
- /* fall through */
+ fallthrough;
case VIA_REG_ANH:
val = s->a;
ctrl = (s->pcr & CA2_CTRL_MASK) >> CA2_CTRL_SHIFT;
if (!(ctrl & C2_IND)) {
s->ifr &= ~CA2_INT;
}
s->ifr &= ~CA1_INT;
mos6522_update_irq(s);
break;
case VIA_REG_DIRB:
val = s->dirb;
break;
case VIA_REG_DIRA:
val = s->dira;
break;
case VIA_REG_T1CL:
val = get_counter(s, &s->timers[0]) & 0xff;
s->ifr &= ~T1_INT;
mos6522_update_irq(s);
break;
case VIA_REG_T1CH:
val = get_counter(s, &s->timers[0]) >> 8;
mos6522_update_irq(s);
break;
case VIA_REG_T1LL:
val = s->timers[0].latch & 0xff;
break;
case VIA_REG_T1LH:
/* XXX: check this */
val = (s->timers[0].latch >> 8) & 0xff;
break;
case VIA_REG_T2CL:
val = get_counter(s, &s->timers[1]) & 0xff;
s->ifr &= ~T2_INT;
mos6522_update_irq(s);
break;
case VIA_REG_T2CH:
val = get_counter(s, &s->timers[1]) >> 8;
break;
case VIA_REG_SR:
val = s->sr;
s->ifr &= ~SR_INT;
mos6522_update_irq(s);
break;
case VIA_REG_ACR:
val = s->acr;
break;
case VIA_REG_PCR:
val = s->pcr;
break;
case VIA_REG_IFR:
val = s->ifr;
if (s->ifr & s->ier) {
val |= 0x80;
}
break;
case VIA_REG_IER:
val = s->ier | 0x80;
break;
default:
g_assert_not_reached();
}
if (addr != VIA_REG_IFR || val != 0) {
trace_mos6522_read(addr, mos6522_reg_names[addr], val);
}
return val;
}
@@ -394,105 +394,105 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size)
void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
{
MOS6522State *s = opaque;
MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s);
int ctrl;
trace_mos6522_write(addr, mos6522_reg_names[addr], val);
switch (addr) {
case VIA_REG_B:
s->b = (s->b & ~s->dirb) | (val & s->dirb);
mdc->portB_write(s);
ctrl = (s->pcr & CB2_CTRL_MASK) >> CB2_CTRL_SHIFT;
if (!(ctrl & C2_IND)) {
s->ifr &= ~CB2_INT;
}
s->ifr &= ~CB1_INT;
mos6522_update_irq(s);
break;
case VIA_REG_A:
qemu_log_mask(LOG_UNIMP, "Write access to register A with handshake");
- /* fall through */
+ fallthrough;
case VIA_REG_ANH:
s->a = (s->a & ~s->dira) | (val & s->dira);
mdc->portA_write(s);
ctrl = (s->pcr & CA2_CTRL_MASK) >> CA2_CTRL_SHIFT;
if (!(ctrl & C2_IND)) {
s->ifr &= ~CA2_INT;
}
s->ifr &= ~CA1_INT;
mos6522_update_irq(s);
break;
case VIA_REG_DIRB:
s->dirb = val;
break;
case VIA_REG_DIRA:
s->dira = val;
break;
case VIA_REG_T1CL:
s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
mos6522_timer1_update(s, &s->timers[0],
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
break;
case VIA_REG_T1CH:
s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
s->ifr &= ~T1_INT;
set_counter(s, &s->timers[0], s->timers[0].latch);
break;
case VIA_REG_T1LL:
s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
mos6522_timer1_update(s, &s->timers[0],
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
break;
case VIA_REG_T1LH:
s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
s->ifr &= ~T1_INT;
mos6522_timer1_update(s, &s->timers[0],
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
break;
case VIA_REG_T2CL:
s->timers[1].latch = (s->timers[1].latch & 0xff00) | val;
break;
case VIA_REG_T2CH:
/* To ensure T2 generates an interrupt on zero crossing with the
common timer code, write the value directly from the latch to
the counter */
s->timers[1].latch = (s->timers[1].latch & 0xff) | (val << 8);
s->ifr &= ~T2_INT;
set_counter(s, &s->timers[1], s->timers[1].latch);
break;
case VIA_REG_SR:
s->sr = val;
break;
case VIA_REG_ACR:
s->acr = val;
mos6522_timer1_update(s, &s->timers[0],
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
break;
case VIA_REG_PCR:
s->pcr = val;
break;
case VIA_REG_IFR:
/* reset bits */
s->ifr &= ~val;
mos6522_update_irq(s);
break;
case VIA_REG_IER:
if (val & IER_SET) {
/* set bits */
s->ier |= val & 0x7f;
} else {
/* reset bits */
s->ier &= ~val;
}
mos6522_update_irq(s);
/* if IER is modified starts needed timers */
mos6522_timer1_update(s, &s->timers[0],
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
mos6522_timer2_update(s, &s->timers[1],
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
break;
default:
g_assert_not_reached();
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 44/78] hw/m68k/mcf_intc.c: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (42 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 43/78] hw/misc: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 45/78] hw/dma: " Emmanouil Pitsidianakis
` (34 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Thomas Huth
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/m68k/mcf_intc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/m68k/mcf_intc.c b/hw/m68k/mcf_intc.c
index 4cd30188c0..9556a0ccb7 100644
--- a/hw/m68k/mcf_intc.c
+++ b/hw/m68k/mcf_intc.c
@@ -58,34 +58,34 @@ static void mcf_intc_update(mcf_intc_state *s)
static uint64_t mcf_intc_read(void *opaque, hwaddr addr,
unsigned size)
{
int offset;
mcf_intc_state *s = (mcf_intc_state *)opaque;
offset = addr & 0xff;
if (offset >= 0x40 && offset < 0x80) {
return s->icr[offset - 0x40];
}
switch (offset) {
case 0x00:
return (uint32_t)(s->ipr >> 32);
case 0x04:
return (uint32_t)s->ipr;
case 0x08:
return (uint32_t)(s->imr >> 32);
case 0x0c:
return (uint32_t)s->imr;
case 0x10:
return (uint32_t)(s->ifr >> 32);
case 0x14:
return (uint32_t)s->ifr;
case 0xe0: /* SWIACK. */
return s->active_vector;
case 0xe1: case 0xe2: case 0xe3: case 0xe4:
case 0xe5: case 0xe6: case 0xe7:
/* LnIACK */
qemu_log_mask(LOG_UNIMP, "%s: LnIACK not implemented (offset 0x%02x)\n",
__func__, offset);
- /* fallthru */
+ fallthrough;
default:
return 0;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 45/78] hw/dma: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (43 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 44/78] hw/m68k/mcf_intc.c: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 46/78] disas: " Emmanouil Pitsidianakis
` (33 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Peter Maydell, Mark Cave-Ayland,
open list:OMAP
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/dma/omap_dma.c | 32 ++++++++++++++++----------------
hw/dma/pxa2xx_dma.c | 4 ++--
hw/dma/sparc32_dma.c | 2 +-
3 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c
index 77797a67b5..dd43dbf3d2 100644
--- a/hw/dma/omap_dma.c
+++ b/hw/dma/omap_dma.c
@@ -1457,46 +1457,46 @@ static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
static uint64_t omap_dma_read(void *opaque, hwaddr addr, unsigned size)
{
struct omap_dma_s *s = opaque;
int reg, ch;
uint16_t ret;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (addr) {
case 0x300 ... 0x3fe:
if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret))
break;
return ret;
}
- /* Fall through. */
+ fallthrough;
case 0x000 ... 0x2fe:
reg = addr & 0x3f;
ch = (addr >> 6) & 0x0f;
if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
break;
return ret;
case 0x404 ... 0x4fe:
if (s->model <= omap_dma_3_1)
break;
- /* Fall through. */
+ fallthrough;
case 0x400:
if (omap_dma_sys_read(s, addr, &ret))
break;
return ret;
case 0xb00 ... 0xbfe:
if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
if (omap_dma_3_2_lcd_read(&s->lcd_ch, addr, &ret))
break;
return ret;
}
break;
}
OMAP_BAD_REG(addr);
return 0;
}
@@ -1504,46 +1504,46 @@ static uint64_t omap_dma_read(void *opaque, hwaddr addr, unsigned size)
static void omap_dma_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dma_s *s = opaque;
int reg, ch;
if (size != 2) {
omap_badwidth_write16(opaque, addr, value);
return;
}
switch (addr) {
case 0x300 ... 0x3fe:
if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value))
break;
return;
}
- /* Fall through. */
+ fallthrough;
case 0x000 ... 0x2fe:
reg = addr & 0x3f;
ch = (addr >> 6) & 0x0f;
if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
break;
return;
case 0x404 ... 0x4fe:
if (s->model <= omap_dma_3_1)
break;
- /* fall through */
+ fallthrough;
case 0x400:
if (omap_dma_sys_write(s, addr, value))
break;
return;
case 0xb00 ... 0xbfe:
if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
if (omap_dma_3_2_lcd_write(&s->lcd_ch, addr, value))
break;
return;
}
break;
}
OMAP_BAD_REG(addr);
}
@@ -1702,155 +1702,155 @@ static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_dma_s *s = opaque;
int irqn = 0, chnum;
struct omap_dma_channel_s *ch;
if (size == 1) {
return omap_badwidth_read16(opaque, addr);
}
switch (addr) {
case 0x00: /* DMA4_REVISION */
return 0x40;
case 0x14: /* DMA4_IRQSTATUS_L3 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x10: /* DMA4_IRQSTATUS_L2 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x0c: /* DMA4_IRQSTATUS_L1 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x08: /* DMA4_IRQSTATUS_L0 */
return s->irqstat[irqn];
case 0x24: /* DMA4_IRQENABLE_L3 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x20: /* DMA4_IRQENABLE_L2 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x1c: /* DMA4_IRQENABLE_L1 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x18: /* DMA4_IRQENABLE_L0 */
return s->irqen[irqn];
case 0x28: /* DMA4_SYSSTATUS */
return 1; /* RESETDONE */
case 0x2c: /* DMA4_OCP_SYSCONFIG */
return s->ocp;
case 0x64: /* DMA4_CAPS_0 */
return s->caps[0];
case 0x6c: /* DMA4_CAPS_2 */
return s->caps[2];
case 0x70: /* DMA4_CAPS_3 */
return s->caps[3];
case 0x74: /* DMA4_CAPS_4 */
return s->caps[4];
case 0x78: /* DMA4_GCR */
return s->gcr;
case 0x80 ... 0xfff:
addr -= 0x80;
chnum = addr / 0x60;
ch = s->ch + chnum;
addr -= chnum * 0x60;
break;
default:
OMAP_BAD_REG(addr);
return 0;
}
/* Per-channel registers */
switch (addr) {
case 0x00: /* DMA4_CCR */
return (ch->buf_disable << 25) |
(ch->src_sync << 24) |
(ch->prefetch << 23) |
((ch->sync & 0x60) << 14) |
(ch->bs << 18) |
(ch->transparent_copy << 17) |
(ch->constant_fill << 16) |
(ch->mode[1] << 14) |
(ch->mode[0] << 12) |
(0 << 10) | (0 << 9) |
(ch->suspend << 8) |
(ch->enable << 7) |
(ch->priority << 6) |
(ch->fs << 5) | (ch->sync & 0x1f);
case 0x04: /* DMA4_CLNK_CTRL */
return (ch->link_enabled << 15) | ch->link_next_ch;
case 0x08: /* DMA4_CICR */
return ch->interrupts;
case 0x0c: /* DMA4_CSR */
return ch->cstatus;
case 0x10: /* DMA4_CSDP */
return (ch->endian[0] << 21) |
(ch->endian_lock[0] << 20) |
(ch->endian[1] << 19) |
(ch->endian_lock[1] << 18) |
(ch->write_mode << 16) |
(ch->burst[1] << 14) |
(ch->pack[1] << 13) |
(ch->translate[1] << 9) |
(ch->burst[0] << 7) |
(ch->pack[0] << 6) |
(ch->translate[0] << 2) |
(ch->data_type >> 1);
case 0x14: /* DMA4_CEN */
return ch->elements;
case 0x18: /* DMA4_CFN */
return ch->frames;
case 0x1c: /* DMA4_CSSA */
return ch->addr[0];
case 0x20: /* DMA4_CDSA */
return ch->addr[1];
case 0x24: /* DMA4_CSEI */
return ch->element_index[0];
case 0x28: /* DMA4_CSFI */
return ch->frame_index[0];
case 0x2c: /* DMA4_CDEI */
return ch->element_index[1];
case 0x30: /* DMA4_CDFI */
return ch->frame_index[1];
case 0x34: /* DMA4_CSAC */
return ch->active_set.src & 0xffff;
case 0x38: /* DMA4_CDAC */
return ch->active_set.dest & 0xffff;
case 0x3c: /* DMA4_CCEN */
return ch->active_set.element;
case 0x40: /* DMA4_CCFN */
return ch->active_set.frame;
case 0x44: /* DMA4_COLOR */
/* XXX only in sDMA */
return ch->color;
default:
OMAP_BAD_REG(addr);
return 0;
}
}
@@ -1858,213 +1858,213 @@ static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
static void omap_dma4_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dma_s *s = opaque;
int chnum, irqn = 0;
struct omap_dma_channel_s *ch;
if (size == 1) {
omap_badwidth_write16(opaque, addr, value);
return;
}
switch (addr) {
case 0x14: /* DMA4_IRQSTATUS_L3 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x10: /* DMA4_IRQSTATUS_L2 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x0c: /* DMA4_IRQSTATUS_L1 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x08: /* DMA4_IRQSTATUS_L0 */
s->irqstat[irqn] &= ~value;
if (!s->irqstat[irqn])
qemu_irq_lower(s->irq[irqn]);
return;
case 0x24: /* DMA4_IRQENABLE_L3 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x20: /* DMA4_IRQENABLE_L2 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x1c: /* DMA4_IRQENABLE_L1 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x18: /* DMA4_IRQENABLE_L0 */
s->irqen[irqn] = value;
return;
case 0x2c: /* DMA4_OCP_SYSCONFIG */
if (value & 2) /* SOFTRESET */
omap_dma_reset(s->dma);
s->ocp = value & 0x3321;
if (((s->ocp >> 12) & 3) == 3) { /* MIDLEMODE */
qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid DMA power mode\n",
__func__);
}
return;
case 0x78: /* DMA4_GCR */
s->gcr = value & 0x00ff00ff;
if ((value & 0xff) == 0x00) { /* MAX_CHANNEL_FIFO_DEPTH */
qemu_log_mask(LOG_GUEST_ERROR, "%s: wrong FIFO depth in GCR\n",
__func__);
}
return;
case 0x80 ... 0xfff:
addr -= 0x80;
chnum = addr / 0x60;
ch = s->ch + chnum;
addr -= chnum * 0x60;
break;
case 0x00: /* DMA4_REVISION */
case 0x28: /* DMA4_SYSSTATUS */
case 0x64: /* DMA4_CAPS_0 */
case 0x6c: /* DMA4_CAPS_2 */
case 0x70: /* DMA4_CAPS_3 */
case 0x74: /* DMA4_CAPS_4 */
OMAP_RO_REG(addr);
return;
default:
OMAP_BAD_REG(addr);
return;
}
/* Per-channel registers */
switch (addr) {
case 0x00: /* DMA4_CCR */
ch->buf_disable = (value >> 25) & 1;
ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */
if (ch->buf_disable && !ch->src_sync) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Buffering disable is not allowed in "
"destination synchronised mode\n", __func__);
}
ch->prefetch = (value >> 23) & 1;
ch->bs = (value >> 18) & 1;
ch->transparent_copy = (value >> 17) & 1;
ch->constant_fill = (value >> 16) & 1;
ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
ch->suspend = (value & 0x0100) >> 8;
ch->priority = (value & 0x0040) >> 6;
ch->fs = (value & 0x0020) >> 5;
if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1]) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: For a packet transfer at least one port "
"must be constant-addressed\n", __func__);
}
ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060);
/* XXX must be 0x01 for CamDMA */
if (value & 0x0080)
omap_dma_enable_channel(s, ch);
else
omap_dma_disable_channel(s, ch);
break;
case 0x04: /* DMA4_CLNK_CTRL */
ch->link_enabled = (value >> 15) & 0x1;
ch->link_next_ch = value & 0x1f;
break;
case 0x08: /* DMA4_CICR */
ch->interrupts = value & 0x09be;
break;
case 0x0c: /* DMA4_CSR */
ch->cstatus &= ~value;
break;
case 0x10: /* DMA4_CSDP */
ch->endian[0] =(value >> 21) & 1;
ch->endian_lock[0] =(value >> 20) & 1;
ch->endian[1] =(value >> 19) & 1;
ch->endian_lock[1] =(value >> 18) & 1;
if (ch->endian[0] != ch->endian[1]) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: DMA endianness conversion enable attempt\n",
__func__);
}
ch->write_mode = (value >> 16) & 3;
ch->burst[1] = (value & 0xc000) >> 14;
ch->pack[1] = (value & 0x2000) >> 13;
ch->translate[1] = (value & 0x1e00) >> 9;
ch->burst[0] = (value & 0x0180) >> 7;
ch->pack[0] = (value & 0x0040) >> 6;
ch->translate[0] = (value & 0x003c) >> 2;
if (ch->translate[0] | ch->translate[1]) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: bad MReqAddressTranslate sideband signal\n",
__func__);
}
ch->data_type = 1 << (value & 3);
if ((value & 3) == 3) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: bad data_type for DMA channel\n", __func__);
ch->data_type >>= 1;
}
break;
case 0x14: /* DMA4_CEN */
ch->set_update = 1;
ch->elements = value & 0xffffff;
break;
case 0x18: /* DMA4_CFN */
ch->frames = value & 0xffff;
ch->set_update = 1;
break;
case 0x1c: /* DMA4_CSSA */
ch->addr[0] = (hwaddr) (uint32_t) value;
ch->set_update = 1;
break;
case 0x20: /* DMA4_CDSA */
ch->addr[1] = (hwaddr) (uint32_t) value;
ch->set_update = 1;
break;
case 0x24: /* DMA4_CSEI */
ch->element_index[0] = (int16_t) value;
ch->set_update = 1;
break;
case 0x28: /* DMA4_CSFI */
ch->frame_index[0] = (int32_t) value;
ch->set_update = 1;
break;
case 0x2c: /* DMA4_CDEI */
ch->element_index[1] = (int16_t) value;
ch->set_update = 1;
break;
case 0x30: /* DMA4_CDFI */
ch->frame_index[1] = (int32_t) value;
ch->set_update = 1;
break;
case 0x44: /* DMA4_COLOR */
/* XXX only in sDMA */
ch->color = value;
break;
case 0x34: /* DMA4_CSAC */
case 0x38: /* DMA4_CDAC */
case 0x3c: /* DMA4_CCEN */
case 0x40: /* DMA4_CCFN */
OMAP_RO_REG(addr);
break;
default:
OMAP_BAD_REG(addr);
}
}
diff --git a/hw/dma/pxa2xx_dma.c b/hw/dma/pxa2xx_dma.c
index fa896f7edf..ac47256572 100644
--- a/hw/dma/pxa2xx_dma.c
+++ b/hw/dma/pxa2xx_dma.c
@@ -266,59 +266,59 @@ static void pxa2xx_dma_run(PXA2xxDMAState *s)
static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
unsigned size)
{
PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
unsigned int channel;
if (size != 4) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad access width %u\n",
__func__, size);
return 5;
}
switch (offset) {
case DRCMR64 ... DRCMR74:
offset -= DRCMR64 - DRCMR0 - (64 << 2);
- /* Fall through */
+ fallthrough;
case DRCMR0 ... DRCMR63:
channel = (offset - DRCMR0) >> 2;
return s->req[channel];
case DRQSR0:
case DRQSR1:
case DRQSR2:
return 0;
case DCSR0 ... DCSR31:
channel = offset >> 2;
if (s->chan[channel].request)
return s->chan[channel].state | DCSR_REQPEND;
return s->chan[channel].state;
case DINT:
return s->stopintr | s->eorintr | s->rasintr |
s->startintr | s->endintr;
case DALGN:
return s->align;
case DPCSR:
return s->pio;
}
if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
channel = (offset - D_CH0) >> 4;
switch ((offset & 0x0f) >> 2) {
case DDADR:
return s->chan[channel].descr;
case DSADR:
return s->chan[channel].src;
case DTADR:
return s->chan[channel].dest;
case DCMD:
return s->chan[channel].cmd;
}
}
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
__func__, offset);
return 7;
}
@@ -326,105 +326,105 @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
static void pxa2xx_dma_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
unsigned int channel;
if (size != 4) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad access width %u\n",
__func__, size);
return;
}
switch (offset) {
case DRCMR64 ... DRCMR74:
offset -= DRCMR64 - DRCMR0 - (64 << 2);
- /* Fall through */
+ fallthrough;
case DRCMR0 ... DRCMR63:
channel = (offset - DRCMR0) >> 2;
if (value & DRCMR_MAPVLD)
if ((value & DRCMR_CHLNUM) > s->channels)
hw_error("%s: Bad DMA channel %i\n",
__func__, (unsigned)value & DRCMR_CHLNUM);
s->req[channel] = value;
break;
case DRQSR0:
case DRQSR1:
case DRQSR2:
/* Nothing to do */
break;
case DCSR0 ... DCSR31:
channel = offset >> 2;
s->chan[channel].state &= 0x0000071f & ~(value &
(DCSR_EORINT | DCSR_ENDINTR |
DCSR_STARTINTR | DCSR_BUSERRINTR));
s->chan[channel].state |= value & 0xfc800000;
if (s->chan[channel].state & DCSR_STOPIRQEN)
s->chan[channel].state &= ~DCSR_STOPINTR;
if (value & DCSR_NODESCFETCH) {
/* No-descriptor-fetch mode */
if (value & DCSR_RUN) {
s->chan[channel].state &= ~DCSR_STOPINTR;
pxa2xx_dma_run(s);
}
} else {
/* Descriptor-fetch mode */
if (value & DCSR_RUN) {
s->chan[channel].state &= ~DCSR_STOPINTR;
pxa2xx_dma_descriptor_fetch(s, channel);
pxa2xx_dma_run(s);
}
}
/* Shouldn't matter as our DMA is synchronous. */
if (!(value & (DCSR_RUN | DCSR_MASKRUN)))
s->chan[channel].state |= DCSR_STOPINTR;
if (value & DCSR_CLRCMPST)
s->chan[channel].state &= ~DCSR_CMPST;
if (value & DCSR_SETCMPST)
s->chan[channel].state |= DCSR_CMPST;
pxa2xx_dma_update(s, channel);
break;
case DALGN:
s->align = value;
break;
case DPCSR:
s->pio = value & 0x80000001;
break;
default:
if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
channel = (offset - D_CH0) >> 4;
switch ((offset & 0x0f) >> 2) {
case DDADR:
s->chan[channel].descr = value;
break;
case DSADR:
s->chan[channel].src = value;
break;
case DTADR:
s->chan[channel].dest = value;
break;
case DCMD:
s->chan[channel].cmd = value;
break;
default:
goto fail;
}
break;
}
fail:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
__func__, offset);
}
}
diff --git a/hw/dma/sparc32_dma.c b/hw/dma/sparc32_dma.c
index 0ef13c5e9a..c68e068cc9 100644
--- a/hw/dma/sparc32_dma.c
+++ b/hw/dma/sparc32_dma.c
@@ -180,49 +180,49 @@ static uint64_t dma_mem_read(void *opaque, hwaddr addr,
static void dma_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
DMADeviceState *s = opaque;
uint32_t saddr;
saddr = (addr & DMA_MASK) >> 2;
trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val);
switch (saddr) {
case 0:
if (val & DMA_INTREN) {
if (s->dmaregs[0] & DMA_INTR) {
trace_sparc32_dma_set_irq_raise();
qemu_irq_raise(s->irq);
}
} else {
if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) {
trace_sparc32_dma_set_irq_lower();
qemu_irq_lower(s->irq);
}
}
if (val & DMA_RESET) {
qemu_irq_raise(s->gpio[GPIO_RESET]);
qemu_irq_lower(s->gpio[GPIO_RESET]);
} else if (val & DMA_DRAIN_FIFO) {
val &= ~DMA_DRAIN_FIFO;
} else if (val == 0)
val = DMA_DRAIN_FIFO;
if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) {
trace_sparc32_dma_enable_raise();
qemu_irq_raise(s->gpio[GPIO_DMA]);
} else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) {
trace_sparc32_dma_enable_lower();
qemu_irq_lower(s->gpio[GPIO_DMA]);
}
val &= ~DMA_CSR_RO_MASK;
val |= DMA_VER;
s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val;
break;
case 1:
s->dmaregs[0] |= DMA_LOADED;
- /* fall through */
+ fallthrough;
default:
s->dmaregs[saddr] = val;
break;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 46/78] disas: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (44 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 45/78] hw/dma: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 47/78] contrib/rdmacm-mux: " Emmanouil Pitsidianakis
` (32 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Richard Henderson, Laurent Vivier,
Yoshinori Sato, Mark Cave-Ayland, Artyom Tarasenko
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
disas/hppa.c | 4 ++--
disas/m68k.c | 2 +-
disas/sh4.c | 6 +++---
disas/sparc.c | 2 +-
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/disas/hppa.c b/disas/hppa.c
index dcf9a47f34..1a2bdb8d39 100644
--- a/disas/hppa.c
+++ b/disas/hppa.c
@@ -1954,878 +1954,878 @@ int
print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
{
bfd_byte buffer[4];
unsigned int insn, i;
{
int status =
(*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
}
insn = bfd_getb32 (buffer);
for (i = 0; i < NUMOPCODES; ++i)
{
const struct pa_opcode *opcode = &pa_opcodes[i];
if ((insn & opcode->mask) == opcode->match)
{
const char *s;
#ifndef BFD64
if (opcode->arch == pa20w)
continue;
#endif
(*info->fprintf_func) (info->stream, "%s", opcode->name);
if (!strchr ("cfCY?-+nHNZFIuv{", opcode->args[0]))
(*info->fprintf_func) (info->stream, " ");
for (s = opcode->args; *s != '\0'; ++s)
{
switch (*s)
{
case 'x':
fput_reg (GET_FIELD (insn, 11, 15), info);
break;
case 'a':
case 'b':
fput_reg (GET_FIELD (insn, 6, 10), info);
break;
case '^':
fput_creg (GET_FIELD (insn, 6, 10), info);
break;
case 't':
fput_reg (GET_FIELD (insn, 27, 31), info);
break;
/* Handle floating point registers. */
case 'f':
switch (*++s)
{
case 't':
fput_fp_reg (GET_FIELD (insn, 27, 31), info);
break;
case 'T':
if (GET_FIELD (insn, 25, 25))
fput_fp_reg_r (GET_FIELD (insn, 27, 31), info);
else
fput_fp_reg (GET_FIELD (insn, 27, 31), info);
break;
case 'a':
if (GET_FIELD (insn, 25, 25))
fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
else
fput_fp_reg (GET_FIELD (insn, 6, 10), info);
break;
/* 'fA' will not generate a space before the register
name. Normally that is fine. Except that it
causes problems with xmpyu which has no FP format
completer. */
case 'X':
fputs_filtered (" ", info);
- /* FALLTHRU */
+ fallthrough;
case 'A':
if (GET_FIELD (insn, 24, 24))
fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
else
fput_fp_reg (GET_FIELD (insn, 6, 10), info);
break;
case 'b':
if (GET_FIELD (insn, 25, 25))
fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
else
fput_fp_reg (GET_FIELD (insn, 11, 15), info);
break;
case 'B':
if (GET_FIELD (insn, 19, 19))
fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
else
fput_fp_reg (GET_FIELD (insn, 11, 15), info);
break;
case 'C':
{
int reg = GET_FIELD (insn, 21, 22);
reg |= GET_FIELD (insn, 16, 18) << 2;
if (GET_FIELD (insn, 23, 23) != 0)
fput_fp_reg_r (reg, info);
else
fput_fp_reg (reg, info);
break;
}
case 'i':
{
int reg = GET_FIELD (insn, 6, 10);
reg |= (GET_FIELD (insn, 26, 26) << 4);
fput_fp_reg (reg, info);
break;
}
case 'j':
{
int reg = GET_FIELD (insn, 11, 15);
reg |= (GET_FIELD (insn, 26, 26) << 4);
fput_fp_reg (reg, info);
break;
}
case 'k':
{
int reg = GET_FIELD (insn, 27, 31);
reg |= (GET_FIELD (insn, 26, 26) << 4);
fput_fp_reg (reg, info);
break;
}
case 'l':
{
int reg = GET_FIELD (insn, 21, 25);
reg |= (GET_FIELD (insn, 26, 26) << 4);
fput_fp_reg (reg, info);
break;
}
case 'm':
{
int reg = GET_FIELD (insn, 16, 20);
reg |= (GET_FIELD (insn, 26, 26) << 4);
fput_fp_reg (reg, info);
break;
}
/* 'fe' will not generate a space before the register
name. Normally that is fine. Except that it
causes problems with fstw fe,y(b) which has no FP
format completer. */
case 'E':
fputs_filtered (" ", info);
- /* FALLTHRU */
+ fallthrough;
case 'e':
if (GET_FIELD (insn, 30, 30))
fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
else
fput_fp_reg (GET_FIELD (insn, 11, 15), info);
break;
case 'x':
fput_fp_reg (GET_FIELD (insn, 11, 15), info);
break;
}
break;
case '5':
fput_const (extract_5_load (insn), info);
break;
case 's':
{
int space = GET_FIELD (insn, 16, 17);
/* Zero means implicit addressing, not use of sr0. */
if (space != 0)
(*info->fprintf_func) (info->stream, "sr%d", space);
}
break;
case 'S':
(*info->fprintf_func) (info->stream, "sr%d",
extract_3 (insn));
break;
/* Handle completers. */
case 'c':
switch (*++s)
{
case 'x':
(*info->fprintf_func)
(info->stream, "%s",
index_compl_names[GET_COMPL (insn)]);
break;
case 'X':
(*info->fprintf_func)
(info->stream, "%s ",
index_compl_names[GET_COMPL (insn)]);
break;
case 'm':
(*info->fprintf_func)
(info->stream, "%s",
short_ldst_compl_names[GET_COMPL (insn)]);
break;
case 'M':
(*info->fprintf_func)
(info->stream, "%s ",
short_ldst_compl_names[GET_COMPL (insn)]);
break;
case 'A':
(*info->fprintf_func)
(info->stream, "%s ",
short_bytes_compl_names[GET_COMPL (insn)]);
break;
case 's':
(*info->fprintf_func)
(info->stream, "%s",
short_bytes_compl_names[GET_COMPL (insn)]);
break;
case 'c':
case 'C':
switch (GET_FIELD (insn, 20, 21))
{
case 1:
(*info->fprintf_func) (info->stream, ",bc ");
break;
case 2:
(*info->fprintf_func) (info->stream, ",sl ");
break;
default:
(*info->fprintf_func) (info->stream, " ");
}
break;
case 'd':
switch (GET_FIELD (insn, 20, 21))
{
case 1:
(*info->fprintf_func) (info->stream, ",co ");
break;
default:
(*info->fprintf_func) (info->stream, " ");
}
break;
case 'o':
(*info->fprintf_func) (info->stream, ",o");
break;
case 'g':
(*info->fprintf_func) (info->stream, ",gate");
break;
case 'p':
(*info->fprintf_func) (info->stream, ",l,push");
break;
case 'P':
(*info->fprintf_func) (info->stream, ",pop");
break;
case 'l':
case 'L':
(*info->fprintf_func) (info->stream, ",l");
break;
case 'w':
(*info->fprintf_func)
(info->stream, "%s ",
read_write_names[GET_FIELD (insn, 25, 25)]);
break;
case 'W':
(*info->fprintf_func) (info->stream, ",w ");
break;
case 'r':
if (GET_FIELD (insn, 23, 26) == 5)
(*info->fprintf_func) (info->stream, ",r");
break;
case 'Z':
if (GET_FIELD (insn, 26, 26))
(*info->fprintf_func) (info->stream, ",m ");
else
(*info->fprintf_func) (info->stream, " ");
break;
case 'i':
if (GET_FIELD (insn, 25, 25))
(*info->fprintf_func) (info->stream, ",i");
break;
case 'z':
if (!GET_FIELD (insn, 21, 21))
(*info->fprintf_func) (info->stream, ",z");
break;
case 'a':
(*info->fprintf_func)
(info->stream, "%s",
add_compl_names[GET_FIELD (insn, 20, 21)]);
break;
case 'Y':
(*info->fprintf_func)
(info->stream, ",dc%s",
add_compl_names[GET_FIELD (insn, 20, 21)]);
break;
case 'y':
(*info->fprintf_func)
(info->stream, ",c%s",
add_compl_names[GET_FIELD (insn, 20, 21)]);
break;
case 'v':
if (GET_FIELD (insn, 20, 20))
(*info->fprintf_func) (info->stream, ",tsv");
break;
case 't':
(*info->fprintf_func) (info->stream, ",tc");
if (GET_FIELD (insn, 20, 20))
(*info->fprintf_func) (info->stream, ",tsv");
break;
case 'B':
(*info->fprintf_func) (info->stream, ",db");
if (GET_FIELD (insn, 20, 20))
(*info->fprintf_func) (info->stream, ",tsv");
break;
case 'b':
(*info->fprintf_func) (info->stream, ",b");
if (GET_FIELD (insn, 20, 20))
(*info->fprintf_func) (info->stream, ",tsv");
break;
case 'T':
if (GET_FIELD (insn, 25, 25))
(*info->fprintf_func) (info->stream, ",tc");
break;
case 'S':
/* EXTRD/W has a following condition. */
if (*(s + 1) == '?')
(*info->fprintf_func)
(info->stream, "%s",
signed_unsigned_names[GET_FIELD (insn, 21, 21)]);
else
(*info->fprintf_func)
(info->stream, "%s ",
signed_unsigned_names[GET_FIELD (insn, 21, 21)]);
break;
case 'h':
(*info->fprintf_func)
(info->stream, "%s",
mix_half_names[GET_FIELD (insn, 17, 17)]);
break;
case 'H':
(*info->fprintf_func)
(info->stream, "%s ",
saturation_names[GET_FIELD (insn, 24, 25)]);
break;
case '*':
(*info->fprintf_func)
(info->stream, ",%d%d%d%d ",
GET_FIELD (insn, 17, 18), GET_FIELD (insn, 20, 21),
GET_FIELD (insn, 22, 23), GET_FIELD (insn, 24, 25));
break;
case 'q':
{
int m, a;
m = GET_FIELD (insn, 28, 28);
a = GET_FIELD (insn, 29, 29);
if (m && !a)
fputs_filtered (",ma ", info);
else if (m && a)
fputs_filtered (",mb ", info);
else
fputs_filtered (" ", info);
break;
}
case 'J':
{
int opc = GET_FIELD (insn, 0, 5);
if (opc == 0x16 || opc == 0x1e)
{
if (GET_FIELD (insn, 29, 29) == 0)
fputs_filtered (",ma ", info);
else
fputs_filtered (",mb ", info);
}
else
fputs_filtered (" ", info);
break;
}
case 'e':
{
int opc = GET_FIELD (insn, 0, 5);
if (opc == 0x13 || opc == 0x1b)
{
if (GET_FIELD (insn, 18, 18) == 1)
fputs_filtered (",mb ", info);
else
fputs_filtered (",ma ", info);
}
else if (opc == 0x17 || opc == 0x1f)
{
if (GET_FIELD (insn, 31, 31) == 1)
fputs_filtered (",ma ", info);
else
fputs_filtered (",mb ", info);
}
else
fputs_filtered (" ", info);
break;
}
}
break;
/* Handle conditions. */
case '?':
{
s++;
switch (*s)
{
case 'f':
(*info->fprintf_func)
(info->stream, "%s ",
float_comp_names[GET_FIELD (insn, 27, 31)]);
break;
/* These four conditions are for the set of instructions
which distinguish true/false conditions by opcode
rather than by the 'f' bit (sigh): comb, comib,
addb, addib. */
case 't':
fputs_filtered
(compare_cond_names[GET_FIELD (insn, 16, 18)], info);
break;
case 'n':
fputs_filtered
(compare_cond_names[GET_FIELD (insn, 16, 18)
+ GET_FIELD (insn, 4, 4) * 8],
info);
break;
case 'N':
fputs_filtered
(compare_cond_64_names[GET_FIELD (insn, 16, 18)
+ GET_FIELD (insn, 2, 2) * 8],
info);
break;
case 'Q':
fputs_filtered
(cmpib_cond_64_names[GET_FIELD (insn, 16, 18)],
info);
break;
case '@':
fputs_filtered
(add_cond_names[GET_FIELD (insn, 16, 18)
+ GET_FIELD (insn, 4, 4) * 8],
info);
break;
case 's':
(*info->fprintf_func)
(info->stream, "%s ",
compare_cond_names[GET_COND (insn)]);
break;
case 'S':
(*info->fprintf_func)
(info->stream, "%s ",
compare_cond_64_names[GET_COND (insn)]);
break;
case 'a':
(*info->fprintf_func)
(info->stream, "%s ",
add_cond_names[GET_COND (insn)]);
break;
case 'A':
(*info->fprintf_func)
(info->stream, "%s ",
add_cond_64_names[GET_COND (insn)]);
break;
case 'd':
(*info->fprintf_func)
(info->stream, "%s",
add_cond_names[GET_FIELD (insn, 16, 18)]);
break;
case 'W':
(*info->fprintf_func)
(info->stream, "%s",
wide_add_cond_names[GET_FIELD (insn, 16, 18) +
GET_FIELD (insn, 4, 4) * 8]);
break;
case 'l':
(*info->fprintf_func)
(info->stream, "%s ",
logical_cond_names[GET_COND (insn)]);
break;
case 'L':
(*info->fprintf_func)
(info->stream, "%s ",
logical_cond_64_names[GET_COND (insn)]);
break;
case 'u':
(*info->fprintf_func)
(info->stream, "%s ",
unit_cond_names[GET_COND (insn)]);
break;
case 'U':
(*info->fprintf_func)
(info->stream, "%s ",
unit_cond_64_names[GET_COND (insn)]);
break;
case 'y':
case 'x':
case 'b':
(*info->fprintf_func)
(info->stream, "%s",
shift_cond_names[GET_FIELD (insn, 16, 18)]);
/* If the next character in args is 'n', it will handle
putting out the space. */
if (s[1] != 'n')
(*info->fprintf_func) (info->stream, " ");
break;
case 'X':
(*info->fprintf_func)
(info->stream, "%s ",
shift_cond_64_names[GET_FIELD (insn, 16, 18)]);
break;
case 'B':
(*info->fprintf_func)
(info->stream, "%s",
bb_cond_64_names[GET_FIELD (insn, 16, 16)]);
/* If the next character in args is 'n', it will handle
putting out the space. */
if (s[1] != 'n')
(*info->fprintf_func) (info->stream, " ");
break;
}
break;
}
case 'V':
fput_const (extract_5_store (insn), info);
break;
case 'r':
fput_const (extract_5r_store (insn), info);
break;
case 'R':
fput_const (extract_5R_store (insn), info);
break;
case 'U':
fput_const (extract_10U_store (insn), info);
break;
case 'B':
case 'Q':
fput_const (extract_5Q_store (insn), info);
break;
case 'i':
fput_const (extract_11 (insn), info);
break;
case 'j':
fput_const (extract_14 (insn), info);
break;
case 'k':
fputs_filtered ("L%", info);
fput_const (extract_21 (insn), info);
break;
case '<':
case 'l':
/* 16-bit long disp., PA2.0 wide only. */
fput_const (extract_16 (insn), info);
break;
case 'n':
if (insn & 0x2)
(*info->fprintf_func) (info->stream, ",n ");
else
(*info->fprintf_func) (info->stream, " ");
break;
case 'N':
if ((insn & 0x20) && s[1])
(*info->fprintf_func) (info->stream, ",n ");
else if (insn & 0x20)
(*info->fprintf_func) (info->stream, ",n");
else if (s[1])
(*info->fprintf_func) (info->stream, " ");
break;
case 'w':
(*info->print_address_func)
(memaddr + 8 + extract_12 (insn), info);
break;
case 'W':
/* 17 bit PC-relative branch. */
(*info->print_address_func)
((memaddr + 8 + extract_17 (insn)), info);
break;
case 'z':
/* 17 bit displacement. This is an offset from a register
so it gets disasssembled as just a number, not any sort
of address. */
fput_const (extract_17 (insn), info);
break;
case 'Z':
/* addil %r1 implicit output. */
fputs_filtered ("r1", info);
break;
case 'Y':
/* be,l %sr0,%r31 implicit output. */
fputs_filtered ("sr0,r31", info);
break;
case '@':
(*info->fprintf_func) (info->stream, "0");
break;
case '.':
(*info->fprintf_func) (info->stream, "%d",
GET_FIELD (insn, 24, 25));
break;
case '*':
(*info->fprintf_func) (info->stream, "%d",
GET_FIELD (insn, 22, 25));
break;
case '!':
fputs_filtered ("sar", info);
break;
case 'p':
(*info->fprintf_func) (info->stream, "%d",
31 - GET_FIELD (insn, 22, 26));
break;
case '~':
{
int num;
num = GET_FIELD (insn, 20, 20) << 5;
num |= GET_FIELD (insn, 22, 26);
(*info->fprintf_func) (info->stream, "%d", 63 - num);
break;
}
case 'P':
(*info->fprintf_func) (info->stream, "%d",
GET_FIELD (insn, 22, 26));
break;
case 'q':
{
int num;
num = GET_FIELD (insn, 20, 20) << 5;
num |= GET_FIELD (insn, 22, 26);
(*info->fprintf_func) (info->stream, "%d", num);
break;
}
case 'T':
(*info->fprintf_func) (info->stream, "%d",
32 - GET_FIELD (insn, 27, 31));
break;
case '%':
{
int num;
num = (GET_FIELD (insn, 23, 23) + 1) * 32;
num -= GET_FIELD (insn, 27, 31);
(*info->fprintf_func) (info->stream, "%d", num);
break;
}
case '|':
{
int num;
num = (GET_FIELD (insn, 19, 19) + 1) * 32;
num -= GET_FIELD (insn, 27, 31);
(*info->fprintf_func) (info->stream, "%d", num);
break;
}
case '$':
fput_const (GET_FIELD (insn, 20, 28), info);
break;
case 'A':
fput_const (GET_FIELD (insn, 6, 18), info);
break;
case 'D':
fput_const (GET_FIELD (insn, 6, 31), info);
break;
case 'v':
(*info->fprintf_func) (info->stream, ",%d",
GET_FIELD (insn, 23, 25));
break;
case 'O':
fput_const ((GET_FIELD (insn, 6,20) << 5 |
GET_FIELD (insn, 27, 31)), info);
break;
case 'o':
fput_const (GET_FIELD (insn, 6, 20), info);
break;
case '2':
fput_const ((GET_FIELD (insn, 6, 22) << 5 |
GET_FIELD (insn, 27, 31)), info);
break;
case '1':
fput_const ((GET_FIELD (insn, 11, 20) << 5 |
GET_FIELD (insn, 27, 31)), info);
break;
case '0':
fput_const ((GET_FIELD (insn, 16, 20) << 5 |
GET_FIELD (insn, 27, 31)), info);
break;
case 'u':
(*info->fprintf_func) (info->stream, ",%d",
GET_FIELD (insn, 23, 25));
break;
case 'F':
/* If no destination completer and not before a completer
for fcmp, need a space here. */
if (s[1] == 'G' || s[1] == '?')
fputs_filtered
(float_format_names[GET_FIELD (insn, 19, 20)], info);
else
(*info->fprintf_func)
(info->stream, "%s ",
float_format_names[GET_FIELD (insn, 19, 20)]);
break;
case 'G':
(*info->fprintf_func)
(info->stream, "%s ",
float_format_names[GET_FIELD (insn, 17, 18)]);
break;
case 'H':
if (GET_FIELD (insn, 26, 26) == 1)
(*info->fprintf_func) (info->stream, "%s ",
float_format_names[0]);
else
(*info->fprintf_func) (info->stream, "%s ",
float_format_names[1]);
break;
case 'I':
/* If no destination completer and not before a completer
for fcmp, need a space here. */
if (s[1] == '?')
fputs_filtered
(float_format_names[GET_FIELD (insn, 20, 20)], info);
else
(*info->fprintf_func)
(info->stream, "%s ",
float_format_names[GET_FIELD (insn, 20, 20)]);
break;
case 'J':
fput_const (extract_14 (insn), info);
break;
case '#':
{
int sign = GET_FIELD (insn, 31, 31);
int imm10 = GET_FIELD (insn, 18, 27);
int disp;
if (sign)
disp = (-1 << 10) | imm10;
else
disp = imm10;
disp <<= 3;
fput_const (disp, info);
break;
}
case 'K':
case 'd':
{
int sign = GET_FIELD (insn, 31, 31);
int imm11 = GET_FIELD (insn, 18, 28);
int disp;
if (sign)
disp = (-1 << 11) | imm11;
else
disp = imm11;
disp <<= 2;
fput_const (disp, info);
break;
}
case '>':
case 'y':
{
/* 16-bit long disp., PA2.0 wide only. */
int disp = extract_16 (insn);
disp &= ~3;
fput_const (disp, info);
break;
}
case '&':
{
/* 16-bit long disp., PA2.0 wide only. */
int disp = extract_16 (insn);
disp &= ~7;
fput_const (disp, info);
break;
}
case '_':
break; /* Dealt with by '{' */
case '{':
{
int sub = GET_FIELD (insn, 14, 16);
int df = GET_FIELD (insn, 17, 18);
int sf = GET_FIELD (insn, 19, 20);
const char * const * source = float_format_names;
const char * const * dest = float_format_names;
const char *t = "";
if (sub == 4)
{
fputs_filtered (",UND ", info);
break;
}
if ((sub & 3) == 3)
t = ",t";
if ((sub & 3) == 1)
source = sub & 4 ? fcnv_ufixed_names : fcnv_fixed_names;
if (sub & 2)
dest = sub & 4 ? fcnv_ufixed_names : fcnv_fixed_names;
(*info->fprintf_func) (info->stream, "%s%s%s ",
t, source[sf], dest[df]);
break;
}
case 'm':
{
int y = GET_FIELD (insn, 16, 18);
if (y != 1)
fput_const ((y ^ 1) - 1, info);
}
break;
case 'h':
{
int cbit;
cbit = GET_FIELD (insn, 16, 18);
if (cbit > 0)
(*info->fprintf_func) (info->stream, ",%d", cbit - 1);
break;
}
case '=':
{
int cond = GET_FIELD (insn, 27, 31);
switch (cond)
{
case 0: fputs_filtered (" ", info); break;
case 1: fputs_filtered ("acc ", info); break;
case 2: fputs_filtered ("rej ", info); break;
case 5: fputs_filtered ("acc8 ", info); break;
case 6: fputs_filtered ("rej8 ", info); break;
case 9: fputs_filtered ("acc6 ", info); break;
case 13: fputs_filtered ("acc4 ", info); break;
case 17: fputs_filtered ("acc2 ", info); break;
default: break;
}
break;
}
case 'X':
(*info->print_address_func)
(memaddr + 8 + extract_22 (insn), info);
break;
case 'L':
fputs_filtered (",rp", info);
break;
default:
(*info->fprintf_func) (info->stream, "%c", *s);
break;
}
}
return sizeof (insn);
}
}
(*info->fprintf_func) (info->stream, "#%8x", insn);
return sizeof (insn);
}
diff --git a/disas/m68k.c b/disas/m68k.c
index 1f16e295ab..a755951bb7 100644
--- a/disas/m68k.c
+++ b/disas/m68k.c
@@ -1087,634 +1087,634 @@ static int
print_insn_arg (const char *d,
unsigned char *buffer,
unsigned char *p0,
bfd_vma addr,
disassemble_info *info)
{
int val = 0;
int place = d[1];
unsigned char *p = p0;
int regno;
const char *regname;
unsigned char *p1;
double flval;
int flt_p;
bfd_signed_vma disp;
unsigned int uval;
switch (*d)
{
case 'c': /* Cache identifier. */
{
static const char *const cacheFieldName[] = { "nc", "dc", "ic", "bc" };
val = fetch_arg (buffer, place, 2, info);
(*info->fprintf_func) (info->stream, "%s", cacheFieldName[val]);
break;
}
case 'a': /* Address register indirect only. Cf. case '+'. */
{
(*info->fprintf_func)
(info->stream,
"%s@",
reg_names[fetch_arg (buffer, place, 3, info) + 8]);
break;
}
case '_': /* 32-bit absolute address for move16. */
{
uval = NEXTULONG (p);
(*info->print_address_func) (uval, info);
break;
}
case 'C':
(*info->fprintf_func) (info->stream, "%%ccr");
break;
case 'S':
(*info->fprintf_func) (info->stream, "%%sr");
break;
case 'U':
(*info->fprintf_func) (info->stream, "%%usp");
break;
case 'E':
(*info->fprintf_func) (info->stream, "%%acc");
break;
case 'G':
(*info->fprintf_func) (info->stream, "%%macsr");
break;
case 'H':
(*info->fprintf_func) (info->stream, "%%mask");
break;
case 'J':
{
/* FIXME: There's a problem here, different m68k processors call the
same address different names. This table can't get it right
because it doesn't know which processor it's disassembling for. */
static const struct { const char *name; int value; } names[]
= {{"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002},
{"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005},
{"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008},
{"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802},
{"%msp", 0x803}, {"%isp", 0x804},
{"%flashbar", 0xc04}, {"%rambar", 0xc05}, /* mcf528x added these. */
/* Should we be calling this psr like we do in case 'Y'? */
{"%mmusr",0x805},
{"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808}};
val = fetch_arg (buffer, place, 12, info);
for (regno = sizeof names / sizeof names[0] - 1; regno >= 0; regno--)
if (names[regno].value == val)
{
(*info->fprintf_func) (info->stream, "%s", names[regno].name);
break;
}
if (regno < 0)
(*info->fprintf_func) (info->stream, "%d", val);
}
break;
case 'Q':
val = fetch_arg (buffer, place, 3, info);
/* 0 means 8, except for the bkpt instruction... */
if (val == 0 && d[1] != 's')
val = 8;
(*info->fprintf_func) (info->stream, "#%d", val);
break;
case 'x':
val = fetch_arg (buffer, place, 3, info);
/* 0 means -1. */
if (val == 0)
val = -1;
(*info->fprintf_func) (info->stream, "#%d", val);
break;
case 'M':
if (place == 'h')
{
static const char *const scalefactor_name[] = { "<<", ">>" };
val = fetch_arg (buffer, place, 1, info);
(*info->fprintf_func) (info->stream, "%s", scalefactor_name[val]);
}
else
{
val = fetch_arg (buffer, place, 8, info);
if (val & 0x80)
val = val - 0x100;
(*info->fprintf_func) (info->stream, "#%d", val);
}
break;
case 'T':
val = fetch_arg (buffer, place, 4, info);
(*info->fprintf_func) (info->stream, "#%d", val);
break;
case 'D':
(*info->fprintf_func) (info->stream, "%s",
reg_names[fetch_arg (buffer, place, 3, info)]);
break;
case 'A':
(*info->fprintf_func)
(info->stream, "%s",
reg_names[fetch_arg (buffer, place, 3, info) + 010]);
break;
case 'R':
(*info->fprintf_func)
(info->stream, "%s",
reg_names[fetch_arg (buffer, place, 4, info)]);
break;
case 'r':
regno = fetch_arg (buffer, place, 4, info);
if (regno > 7)
(*info->fprintf_func) (info->stream, "%s@", reg_names[regno]);
else
(*info->fprintf_func) (info->stream, "@(%s)", reg_names[regno]);
break;
case 'F':
(*info->fprintf_func)
(info->stream, "%%fp%d",
fetch_arg (buffer, place, 3, info));
break;
case 'O':
val = fetch_arg (buffer, place, 6, info);
if (val & 0x20)
(*info->fprintf_func) (info->stream, "%s", reg_names[val & 7]);
else
(*info->fprintf_func) (info->stream, "%d", val);
break;
case '+':
(*info->fprintf_func)
(info->stream, "%s@+",
reg_names[fetch_arg (buffer, place, 3, info) + 8]);
break;
case '-':
(*info->fprintf_func)
(info->stream, "%s@-",
reg_names[fetch_arg (buffer, place, 3, info) + 8]);
break;
case 'k':
if (place == 'k')
(*info->fprintf_func)
(info->stream, "{%s}",
reg_names[fetch_arg (buffer, place, 3, info)]);
else if (place == 'C')
{
val = fetch_arg (buffer, place, 7, info);
if (val > 63) /* This is a signed constant. */
val -= 128;
(*info->fprintf_func) (info->stream, "{#%d}", val);
}
else
return -2;
break;
case '#':
case '^':
p1 = buffer + (*d == '#' ? 2 : 4);
if (place == 's')
val = fetch_arg (buffer, place, 4, info);
else if (place == 'C')
val = fetch_arg (buffer, place, 7, info);
else if (place == '8')
val = fetch_arg (buffer, place, 3, info);
else if (place == '3')
val = fetch_arg (buffer, place, 8, info);
else if (place == 'b')
val = NEXTBYTE (p1);
else if (place == 'w' || place == 'W')
val = NEXTWORD (p1);
else if (place == 'l')
val = NEXTLONG (p1);
else
return -2;
(*info->fprintf_func) (info->stream, "#%d", val);
break;
case 'B':
if (place == 'b')
disp = NEXTBYTE (p);
else if (place == 'B')
disp = COERCE_SIGNED_CHAR (buffer[1]);
else if (place == 'w' || place == 'W')
disp = NEXTWORD (p);
else if (place == 'l' || place == 'L' || place == 'C')
disp = NEXTLONG (p);
else if (place == 'g')
{
disp = NEXTBYTE (buffer);
if (disp == 0)
disp = NEXTWORD (p);
else if (disp == -1)
disp = NEXTLONG (p);
}
else if (place == 'c')
{
if (buffer[1] & 0x40) /* If bit six is one, long offset. */
disp = NEXTLONG (p);
else
disp = NEXTWORD (p);
}
else
return -2;
(*info->print_address_func) (addr + disp, info);
break;
case 'd':
val = NEXTWORD (p);
(*info->fprintf_func)
(info->stream, "%s@(%d)",
reg_names[fetch_arg (buffer, place, 3, info) + 8], val);
break;
case 's':
(*info->fprintf_func) (info->stream, "%s",
fpcr_names[fetch_arg (buffer, place, 3, info)]);
break;
case 'e':
val = fetch_arg(buffer, place, 2, info);
(*info->fprintf_func) (info->stream, "%%acc%d", val);
break;
case 'g':
val = fetch_arg(buffer, place, 1, info);
(*info->fprintf_func) (info->stream, "%%accext%s", val==0 ? "01" : "23");
break;
case 'i':
val = fetch_arg(buffer, place, 2, info);
if (val == 1)
(*info->fprintf_func) (info->stream, "<<");
else if (val == 3)
(*info->fprintf_func) (info->stream, ">>");
else
return -1;
break;
case 'I':
/* Get coprocessor ID... */
val = fetch_arg (buffer, 'd', 3, info);
if (val != 1) /* Unusual coprocessor ID? */
(*info->fprintf_func) (info->stream, "(cpid=%d) ", val);
break;
case '4':
case '*':
case '~':
case '%':
case ';':
case '@':
case '!':
case '$':
case '?':
case '/':
case '&':
case '|':
case '<':
case '>':
case 'm':
case 'n':
case 'o':
case 'p':
case 'q':
case 'v':
case 'b':
case 'w':
case 'y':
case 'z':
if (place == 'd')
{
val = fetch_arg (buffer, 'x', 6, info);
val = ((val & 7) << 3) + ((val >> 3) & 7);
}
else
val = fetch_arg (buffer, 's', 6, info);
/* If the <ea> is invalid for *d, then reject this match. */
if (!m68k_valid_ea (*d, val))
return -1;
/* Get register number assuming address register. */
regno = (val & 7) + 8;
regname = reg_names[regno];
switch (val >> 3)
{
case 0:
(*info->fprintf_func) (info->stream, "%s", reg_names[val]);
break;
case 1:
(*info->fprintf_func) (info->stream, "%s", regname);
break;
case 2:
(*info->fprintf_func) (info->stream, "%s@", regname);
break;
case 3:
(*info->fprintf_func) (info->stream, "%s@+", regname);
break;
case 4:
(*info->fprintf_func) (info->stream, "%s@-", regname);
break;
case 5:
val = NEXTWORD (p);
(*info->fprintf_func) (info->stream, "%s@(%d)", regname, val);
break;
case 6:
p = print_indexed (regno, p, addr, info);
break;
case 7:
switch (val & 7)
{
case 0:
val = NEXTWORD (p);
(*info->print_address_func) (val, info);
break;
case 1:
uval = NEXTULONG (p);
(*info->print_address_func) (uval, info);
break;
case 2:
val = NEXTWORD (p);
(*info->fprintf_func) (info->stream, "%%pc@(");
(*info->print_address_func) (addr + val, info);
(*info->fprintf_func) (info->stream, ")");
break;
case 3:
p = print_indexed (-1, p, addr, info);
break;
case 4:
flt_p = 1; /* Assume it's a float... */
switch (place)
{
case 'b':
val = NEXTBYTE (p);
flt_p = 0;
break;
case 'w':
val = NEXTWORD (p);
flt_p = 0;
break;
case 'l':
val = NEXTLONG (p);
flt_p = 0;
break;
case 'f':
NEXTSINGLE (flval, p);
break;
case 'F':
NEXTDOUBLE (flval, p);
break;
case 'x':
NEXTEXTEND (flval, p);
break;
case 'p':
flval = NEXTPACKED (p);
break;
default:
return -1;
}
if (flt_p) /* Print a float? */
(*info->fprintf_func) (info->stream, "#%g", flval);
else
(*info->fprintf_func) (info->stream, "#%d", val);
break;
default:
return -1;
}
}
/* If place is '/', then this is the case of the mask bit for
mac/emac loads. Now that the arg has been printed, grab the
mask bit and if set, add a '&' to the arg. */
if (place == '/')
{
val = fetch_arg (buffer, place, 1, info);
if (val)
info->fprintf_func (info->stream, "&");
}
break;
case 'L':
case 'l':
if (place == 'w')
{
char doneany;
p1 = buffer + 2;
val = NEXTWORD (p1);
/* Move the pointer ahead if this point is farther ahead
than the last. */
p = p1 > p ? p1 : p;
if (val == 0)
{
(*info->fprintf_func) (info->stream, "#0");
break;
}
if (*d == 'l')
{
int newval = 0;
for (regno = 0; regno < 16; ++regno)
if (val & (0x8000 >> regno))
newval |= 1 << regno;
val = newval;
}
val &= 0xffff;
doneany = 0;
for (regno = 0; regno < 16; ++regno)
if (val & (1 << regno))
{
int first_regno;
if (doneany)
(*info->fprintf_func) (info->stream, "/");
doneany = 1;
(*info->fprintf_func) (info->stream, "%s", reg_names[regno]);
first_regno = regno;
while (val & (1 << (regno + 1)))
++regno;
if (regno > first_regno)
(*info->fprintf_func) (info->stream, "-%s",
reg_names[regno]);
}
}
else if (place == '3')
{
/* `fmovem' insn. */
char doneany;
val = fetch_arg (buffer, place, 8, info);
if (val == 0)
{
(*info->fprintf_func) (info->stream, "#0");
break;
}
if (*d == 'l')
{
int newval = 0;
for (regno = 0; regno < 8; ++regno)
if (val & (0x80 >> regno))
newval |= 1 << regno;
val = newval;
}
val &= 0xff;
doneany = 0;
for (regno = 0; regno < 8; ++regno)
if (val & (1 << regno))
{
int first_regno;
if (doneany)
(*info->fprintf_func) (info->stream, "/");
doneany = 1;
(*info->fprintf_func) (info->stream, "%%fp%d", regno);
first_regno = regno;
while (val & (1 << (regno + 1)))
++regno;
if (regno > first_regno)
(*info->fprintf_func) (info->stream, "-%%fp%d", regno);
}
}
else if (place == '8')
{
/* fmoveml for FP status registers. */
(*info->fprintf_func) (info->stream, "%s",
fpcr_names[fetch_arg (buffer, place, 3,
info)]);
}
else
return -2;
break;
case 'X':
place = '8';
- /* fall through */
+ fallthrough;
case 'Y':
case 'Z':
case 'W':
case '0':
case '1':
case '2':
case '3':
{
int reg = fetch_arg (buffer, place, 5, info);
const char *name = 0;
switch (reg)
{
case 2: name = "%tt0"; break;
case 3: name = "%tt1"; break;
case 0x10: name = "%tc"; break;
case 0x11: name = "%drp"; break;
case 0x12: name = "%srp"; break;
case 0x13: name = "%crp"; break;
case 0x14: name = "%cal"; break;
case 0x15: name = "%val"; break;
case 0x16: name = "%scc"; break;
case 0x17: name = "%ac"; break;
case 0x18: name = "%psr"; break;
case 0x19: name = "%pcsr"; break;
case 0x1c:
case 0x1d:
{
int break_reg = ((buffer[3] >> 2) & 7);
(*info->fprintf_func)
(info->stream, reg == 0x1c ? "%%bad%d" : "%%bac%d",
break_reg);
}
break;
default:
(*info->fprintf_func) (info->stream, "<mmu register %d>", reg);
}
if (name)
(*info->fprintf_func) (info->stream, "%s", name);
}
break;
case 'f':
{
int fc = fetch_arg (buffer, place, 5, info);
if (fc == 1)
(*info->fprintf_func) (info->stream, "%%dfc");
else if (fc == 0)
(*info->fprintf_func) (info->stream, "%%sfc");
else
/* xgettext:c-format */
(*info->fprintf_func) (info->stream, "<function code %d>", fc);
}
break;
case 'V':
(*info->fprintf_func) (info->stream, "%%val");
break;
case 't':
{
int level = fetch_arg (buffer, place, 3, info);
(*info->fprintf_func) (info->stream, "%d", level);
}
break;
case 'u':
{
short is_upper = 0;
int reg = fetch_arg (buffer, place, 5, info);
if (reg & 0x10)
{
is_upper = 1;
reg &= 0xf;
}
(*info->fprintf_func) (info->stream, "%s%s",
reg_half_names[reg],
is_upper ? "u" : "l");
}
break;
default:
return -2;
}
return p - p0;
}
/* Try to match the current instruction to best and if so, return the
number of bytes consumed from the instruction stream, else zero. */
diff --git a/disas/sh4.c b/disas/sh4.c
index dcdbdf26d8..f7c95407ca 100644
--- a/disas/sh4.c
+++ b/disas/sh4.c
@@ -1509,565 +1509,565 @@ int
print_insn_sh (bfd_vma memaddr, struct disassemble_info *info)
{
fprintf_function fprintf_fn = info->fprintf_func;
void *stream = info->stream;
unsigned char insn[4];
unsigned char nibs[8];
int status;
bfd_vma relmask = ~(bfd_vma) 0;
const sh_opcode_info *op;
unsigned int target_arch;
int allow_op32;
switch (info->mach)
{
case bfd_mach_sh:
target_arch = arch_sh1;
break;
case bfd_mach_sh4:
target_arch = arch_sh4;
break;
case bfd_mach_sh5:
#ifdef INCLUDE_SHMEDIA
status = print_insn_sh64 (memaddr, info);
if (status != -2)
return status;
#endif
/* When we get here for sh64, it's because we want to disassemble
SHcompact, i.e. arch_sh4. */
target_arch = arch_sh4;
break;
default:
fprintf (stderr, "sh architecture not supported\n");
return -1;
}
status = info->read_memory_func (memaddr, insn, 2, info);
if (status != 0)
{
info->memory_error_func (status, memaddr, info);
return -1;
}
if (info->endian == BFD_ENDIAN_LITTLE)
{
nibs[0] = (insn[1] >> 4) & 0xf;
nibs[1] = insn[1] & 0xf;
nibs[2] = (insn[0] >> 4) & 0xf;
nibs[3] = insn[0] & 0xf;
}
else
{
nibs[0] = (insn[0] >> 4) & 0xf;
nibs[1] = insn[0] & 0xf;
nibs[2] = (insn[1] >> 4) & 0xf;
nibs[3] = insn[1] & 0xf;
}
status = info->read_memory_func (memaddr + 2, insn + 2, 2, info);
if (status != 0)
allow_op32 = 0;
else
{
allow_op32 = 1;
if (info->endian == BFD_ENDIAN_LITTLE)
{
nibs[4] = (insn[3] >> 4) & 0xf;
nibs[5] = insn[3] & 0xf;
nibs[6] = (insn[2] >> 4) & 0xf;
nibs[7] = insn[2] & 0xf;
}
else
{
nibs[4] = (insn[2] >> 4) & 0xf;
nibs[5] = insn[2] & 0xf;
nibs[6] = (insn[3] >> 4) & 0xf;
nibs[7] = insn[3] & 0xf;
}
}
if (nibs[0] == 0xf && (nibs[1] & 4) == 0
&& SH_MERGE_ARCH_SET_VALID (target_arch, arch_sh_dsp_up))
{
if (nibs[1] & 8)
{
int field_b;
status = info->read_memory_func (memaddr + 2, insn, 2, info);
if (status != 0)
{
info->memory_error_func (status, memaddr + 2, info);
return -1;
}
if (info->endian == BFD_ENDIAN_LITTLE)
field_b = insn[1] << 8 | insn[0];
else
field_b = insn[0] << 8 | insn[1];
print_insn_ppi (field_b, info);
print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
return 4;
}
print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
return 2;
}
for (op = sh_table; op->name; op++)
{
int n;
int imm = 0;
int rn = 0;
int rm = 0;
int rb = 0;
int disp_pc;
bfd_vma disp_pc_addr = 0;
int disp = 0;
int has_disp = 0;
int max_n = SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 8 : 4;
if (!allow_op32
&& SH_MERGE_ARCH_SET (op->arch, arch_op32))
goto fail;
if (!SH_MERGE_ARCH_SET_VALID (op->arch, target_arch))
goto fail;
for (n = 0; n < max_n; n++)
{
int i = op->nibbles[n];
if (i < 16)
{
if (nibs[n] == i)
continue;
goto fail;
}
switch (i)
{
case BRANCH_8:
imm = (nibs[2] << 4) | (nibs[3]);
if (imm & 0x80)
imm |= ~0xff;
imm = ((char) imm) * 2 + 4;
goto ok;
case BRANCH_12:
imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]);
if (imm & 0x800)
imm |= ~0xfff;
imm = imm * 2 + 4;
goto ok;
case IMM0_3c:
if (nibs[3] & 0x8)
goto fail;
imm = nibs[3] & 0x7;
break;
case IMM0_3s:
if (!(nibs[3] & 0x8))
goto fail;
imm = nibs[3] & 0x7;
break;
case IMM0_3Uc:
if (nibs[2] & 0x8)
goto fail;
imm = nibs[2] & 0x7;
break;
case IMM0_3Us:
if (!(nibs[2] & 0x8))
goto fail;
imm = nibs[2] & 0x7;
break;
case DISP0_12:
case DISP1_12:
disp = (nibs[5] << 8) | (nibs[6] << 4) | nibs[7];
has_disp = 1;
goto ok;
case DISP0_12BY2:
case DISP1_12BY2:
disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 1;
relmask = ~(bfd_vma) 1;
has_disp = 1;
goto ok;
case DISP0_12BY4:
case DISP1_12BY4:
disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 2;
relmask = ~(bfd_vma) 3;
has_disp = 1;
goto ok;
case DISP0_12BY8:
case DISP1_12BY8:
disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 3;
relmask = ~(bfd_vma) 7;
has_disp = 1;
goto ok;
case IMM0_20_4:
break;
case IMM0_20:
imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8)
| (nibs[6] << 4) | nibs[7]);
if (imm & 0x80000)
imm -= 0x100000;
goto ok;
case IMM0_20BY8:
imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8)
| (nibs[6] << 4) | nibs[7]);
imm <<= 8;
if (imm & 0x8000000)
imm -= 0x10000000;
goto ok;
case IMM0_4:
case IMM1_4:
imm = nibs[3];
goto ok;
case IMM0_4BY2:
case IMM1_4BY2:
imm = nibs[3] << 1;
goto ok;
case IMM0_4BY4:
case IMM1_4BY4:
imm = nibs[3] << 2;
goto ok;
case IMM0_8:
case IMM1_8:
imm = (nibs[2] << 4) | nibs[3];
disp = imm;
has_disp = 1;
if (imm & 0x80)
imm -= 0x100;
goto ok;
case PCRELIMM_8BY2:
imm = ((nibs[2] << 4) | nibs[3]) << 1;
relmask = ~(bfd_vma) 1;
goto ok;
case PCRELIMM_8BY4:
imm = ((nibs[2] << 4) | nibs[3]) << 2;
relmask = ~(bfd_vma) 3;
goto ok;
case IMM0_8BY2:
case IMM1_8BY2:
imm = ((nibs[2] << 4) | nibs[3]) << 1;
goto ok;
case IMM0_8BY4:
case IMM1_8BY4:
imm = ((nibs[2] << 4) | nibs[3]) << 2;
goto ok;
case REG_N_D:
if ((nibs[n] & 1) != 0)
goto fail;
- /* fall through */
+ fallthrough;
case REG_N:
rn = nibs[n];
break;
case REG_M:
rm = nibs[n];
break;
case REG_N_B01:
if ((nibs[n] & 0x3) != 1 /* binary 01 */)
goto fail;
rn = (nibs[n] & 0xc) >> 2;
break;
case REG_NM:
rn = (nibs[n] & 0xc) >> 2;
rm = (nibs[n] & 0x3);
break;
case REG_B:
rb = nibs[n] & 0x07;
break;
case SDT_REG_N:
/* sh-dsp: single data transfer. */
rn = nibs[n];
if ((rn & 0xc) != 4)
goto fail;
rn = rn & 0x3;
rn |= (!(rn & 2)) << 2;
break;
case PPI:
case REPEAT:
goto fail;
default:
abort ();
}
}
ok:
/* sh2a has D_REG but not X_REG. We don't know the pattern
doesn't match unless we check the output args to see if they
make sense. */
if (target_arch == arch_sh2a
&& ((op->arg[0] == DX_REG_M && (rm & 1) != 0)
|| (op->arg[1] == DX_REG_N && (rn & 1) != 0)))
goto fail;
fprintf_fn (stream, "%s\t", op->name);
disp_pc = 0;
for (n = 0; n < 3 && op->arg[n] != A_END; n++)
{
if (n && op->arg[1] != A_END)
fprintf_fn (stream, ",");
switch (op->arg[n])
{
case A_IMM:
fprintf_fn (stream, "#%d", imm);
break;
case A_R0:
fprintf_fn (stream, "r0");
break;
case A_REG_N:
fprintf_fn (stream, "r%d", rn);
break;
case A_INC_N:
case AS_INC_N:
fprintf_fn (stream, "@r%d+", rn);
break;
case A_DEC_N:
case AS_DEC_N:
fprintf_fn (stream, "@-r%d", rn);
break;
case A_IND_N:
case AS_IND_N:
fprintf_fn (stream, "@r%d", rn);
break;
case A_DISP_REG_N:
fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rn);
break;
case AS_PMOD_N:
fprintf_fn (stream, "@r%d+r8", rn);
break;
case A_REG_M:
fprintf_fn (stream, "r%d", rm);
break;
case A_INC_M:
fprintf_fn (stream, "@r%d+", rm);
break;
case A_DEC_M:
fprintf_fn (stream, "@-r%d", rm);
break;
case A_IND_M:
fprintf_fn (stream, "@r%d", rm);
break;
case A_DISP_REG_M:
fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rm);
break;
case A_REG_B:
fprintf_fn (stream, "r%d_bank", rb);
break;
case A_DISP_PC:
disp_pc = 1;
disp_pc_addr = imm + 4 + (memaddr & relmask);
(*info->print_address_func) (disp_pc_addr, info);
break;
case A_IND_R0_REG_N:
fprintf_fn (stream, "@(r0,r%d)", rn);
break;
case A_IND_R0_REG_M:
fprintf_fn (stream, "@(r0,r%d)", rm);
break;
case A_DISP_GBR:
fprintf_fn (stream, "@(%d,gbr)", has_disp?disp:imm);
break;
case A_TBR:
fprintf_fn (stream, "tbr");
break;
case A_DISP2_TBR:
fprintf_fn (stream, "@@(%d,tbr)", has_disp?disp:imm);
break;
case A_INC_R15:
fprintf_fn (stream, "@r15+");
break;
case A_DEC_R15:
fprintf_fn (stream, "@-r15");
break;
case A_R0_GBR:
fprintf_fn (stream, "@(r0,gbr)");
break;
case A_BDISP12:
case A_BDISP8:
{
bfd_vma addr;
addr = imm + memaddr;
(*info->print_address_func) (addr, info);
}
break;
case A_SR:
fprintf_fn (stream, "sr");
break;
case A_GBR:
fprintf_fn (stream, "gbr");
break;
case A_VBR:
fprintf_fn (stream, "vbr");
break;
case A_DSR:
fprintf_fn (stream, "dsr");
break;
case A_MOD:
fprintf_fn (stream, "mod");
break;
case A_RE:
fprintf_fn (stream, "re");
break;
case A_RS:
fprintf_fn (stream, "rs");
break;
case A_A0:
fprintf_fn (stream, "a0");
break;
case A_X0:
fprintf_fn (stream, "x0");
break;
case A_X1:
fprintf_fn (stream, "x1");
break;
case A_Y0:
fprintf_fn (stream, "y0");
break;
case A_Y1:
fprintf_fn (stream, "y1");
break;
case DSP_REG_M:
print_dsp_reg (rm, fprintf_fn, stream);
break;
case A_SSR:
fprintf_fn (stream, "ssr");
break;
case A_SPC:
fprintf_fn (stream, "spc");
break;
case A_MACH:
fprintf_fn (stream, "mach");
break;
case A_MACL:
fprintf_fn (stream, "macl");
break;
case A_PR:
fprintf_fn (stream, "pr");
break;
case A_SGR:
fprintf_fn (stream, "sgr");
break;
case A_DBR:
fprintf_fn (stream, "dbr");
break;
case F_REG_N:
fprintf_fn (stream, "fr%d", rn);
break;
case F_REG_M:
fprintf_fn (stream, "fr%d", rm);
break;
case DX_REG_N:
if (rn & 1)
{
fprintf_fn (stream, "xd%d", rn & ~1);
break;
}
- /* fallthrough */
+ fallthrough;
case D_REG_N:
fprintf_fn (stream, "dr%d", rn);
break;
case DX_REG_M:
if (rm & 1)
{
fprintf_fn (stream, "xd%d", rm & ~1);
break;
}
- /* fallthrough */
+ fallthrough;
case D_REG_M:
fprintf_fn (stream, "dr%d", rm);
break;
case FPSCR_M:
case FPSCR_N:
fprintf_fn (stream, "fpscr");
break;
case FPUL_M:
case FPUL_N:
fprintf_fn (stream, "fpul");
break;
case F_FR0:
fprintf_fn (stream, "fr0");
break;
case V_REG_N:
fprintf_fn (stream, "fv%d", rn * 4);
break;
case V_REG_M:
fprintf_fn (stream, "fv%d", rm * 4);
break;
case XMTRX_M4:
fprintf_fn (stream, "xmtrx");
break;
default:
abort ();
}
}
#if 0
/* This code prints instructions in delay slots on the same line
as the instruction which needs the delay slots. This can be
confusing, since other disassembler don't work this way, and
it means that the instructions are not all in a line. So I
disabled it. Ian. */
if (!(info->flags & 1)
&& (op->name[0] == 'j'
|| (op->name[0] == 'b'
&& (op->name[1] == 'r'
|| op->name[1] == 's'))
|| (op->name[0] == 'r' && op->name[1] == 't')
|| (op->name[0] == 'b' && op->name[2] == '.')))
{
info->flags |= 1;
fprintf_fn (stream, "\t(slot ");
print_insn_sh (memaddr + 2, info);
info->flags &= ~1;
fprintf_fn (stream, ")");
return 4;
}
#endif
if (disp_pc && strcmp (op->name, "mova") != 0)
{
int size;
bfd_byte bytes[4];
if (relmask == ~(bfd_vma) 1)
size = 2;
else
size = 4;
status = info->read_memory_func (disp_pc_addr, bytes, size, info);
if (status == 0)
{
unsigned int val;
if (size == 2)
{
if (info->endian == BFD_ENDIAN_LITTLE)
val = bfd_getl16 (bytes);
else
val = bfd_getb16 (bytes);
}
else
{
if (info->endian == BFD_ENDIAN_LITTLE)
val = bfd_getl32 (bytes);
else
val = bfd_getb32 (bytes);
}
if ((*info->symbol_at_address_func) (val, info))
{
fprintf_fn (stream, "\t! ");
(*info->print_address_func) (val, info);
}
else
fprintf_fn (stream, "\t! 0x%x", val);
}
}
return SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 4 : 2;
fail:
;
}
fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]);
return 2;
}
diff --git a/disas/sparc.c b/disas/sparc.c
index 5689533ce1..61139256b0 100644
--- a/disas/sparc.c
+++ b/disas/sparc.c
@@ -2667,570 +2667,570 @@ int
print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
{
FILE *stream = info->stream;
bfd_byte buffer[4];
unsigned long insn;
sparc_opcode_hash *op;
/* Nonzero of opcode table has been initialized. */
static int opcodes_initialized = 0;
/* bfd mach number of last call. */
static unsigned long current_mach = 0;
bfd_vma (*getword) (const unsigned char *);
if (!opcodes_initialized
|| info->mach != current_mach)
{
int i;
current_arch_mask = compute_arch_mask (info->mach);
if (!opcodes_initialized)
sorted_opcodes =
malloc (sparc_num_opcodes * sizeof (sparc_opcode *));
/* Reset the sorted table so we can resort it. */
for (i = 0; i < sparc_num_opcodes; ++i)
sorted_opcodes[i] = &sparc_opcodes[i];
qsort ((char *) sorted_opcodes, sparc_num_opcodes,
sizeof (sorted_opcodes[0]), compare_opcodes);
build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
current_mach = info->mach;
opcodes_initialized = 1;
}
{
int status =
(*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
}
/* On SPARClite variants such as DANlite (sparc86x), instructions
are always big-endian even when the machine is in little-endian mode. */
if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
getword = bfd_getb32;
else
getword = bfd_getl32;
insn = getword (buffer);
info->insn_info_valid = 1; /* We do return this info. */
info->insn_type = dis_nonbranch; /* Assume non branch insn. */
info->branch_delay_insns = 0; /* Assume no delay. */
info->target = 0; /* Assume no target known. */
for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
{
const sparc_opcode *opcode = op->opcode;
/* If the insn isn't supported by the current architecture, skip it. */
if (! (opcode->architecture & current_arch_mask))
continue;
if ((opcode->match & insn) == opcode->match
&& (opcode->lose & insn) == 0)
{
/* Nonzero means that we have found an instruction which has
the effect of adding or or'ing the imm13 field to rs1. */
int imm_added_to_rs1 = 0;
int imm_ored_to_rs1 = 0;
/* Nonzero means that we have found a plus sign in the args
field of the opcode table. */
int found_plus = 0;
/* Nonzero means we have an annulled branch. */
/* int is_annulled = 0; */ /* see FIXME below */
/* Do we have an `add' or `or' instruction combining an
immediate with rs1? */
if (opcode->match == 0x80102000) /* or */
imm_ored_to_rs1 = 1;
if (opcode->match == 0x80002000) /* add */
imm_added_to_rs1 = 1;
if (X_RS1 (insn) != X_RD (insn)
&& strchr (opcode->args, 'r') != NULL)
/* Can't do simple format if source and dest are different. */
continue;
if (X_RS2 (insn) != X_RD (insn)
&& strchr (opcode->args, 'O') != NULL)
/* Can't do simple format if source and dest are different. */
continue;
(*info->fprintf_func) (stream, "%s", opcode->name);
{
const char *s;
if (opcode->args[0] != ',')
(*info->fprintf_func) (stream, " ");
for (s = opcode->args; *s != '\0'; ++s)
{
while (*s == ',')
{
(*info->fprintf_func) (stream, ",");
++s;
switch (*s)
{
case 'a':
(*info->fprintf_func) (stream, "a");
/* is_annulled = 1; */ /* see FIXME below */
++s;
continue;
case 'N':
(*info->fprintf_func) (stream, "pn");
++s;
continue;
case 'T':
(*info->fprintf_func) (stream, "pt");
++s;
continue;
default:
break;
}
}
(*info->fprintf_func) (stream, " ");
switch (*s)
{
case '+':
found_plus = 1;
- /* Fall through. */
+ fallthrough;
default:
(*info->fprintf_func) (stream, "%c", *s);
break;
case '#':
(*info->fprintf_func) (stream, "0");
break;
#define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
case '1':
case 'r':
reg (X_RS1 (insn));
break;
case '2':
case 'O':
reg (X_RS2 (insn));
break;
case 'd':
reg (X_RD (insn));
break;
#undef reg
#define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
#define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
case 'e':
freg (X_RS1 (insn));
break;
case 'v': /* Double/even. */
case 'V': /* Quad/multiple of 4. */
fregx (X_RS1 (insn));
break;
case 'f':
freg (X_RS2 (insn));
break;
case 'B': /* Double/even. */
case 'R': /* Quad/multiple of 4. */
fregx (X_RS2 (insn));
break;
case 'g':
freg (X_RD (insn));
break;
case 'H': /* Double/even. */
case 'J': /* Quad/multiple of 4. */
fregx (X_RD (insn));
break;
#undef freg
#undef fregx
#define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
case 'b':
creg (X_RS1 (insn));
break;
case 'c':
creg (X_RS2 (insn));
break;
case 'D':
creg (X_RD (insn));
break;
#undef creg
case 'h':
(*info->fprintf_func) (stream, "%%hi(%#x)",
((unsigned) 0xFFFFFFFF
& ((int) X_IMM22 (insn) << 10)));
break;
case 'i': /* 13 bit immediate. */
case 'I': /* 11 bit immediate. */
case 'j': /* 10 bit immediate. */
{
int imm;
if (*s == 'i')
imm = X_SIMM (insn, 13);
else if (*s == 'I')
imm = X_SIMM (insn, 11);
else
imm = X_SIMM (insn, 10);
/* Check to see whether we have a 1+i, and take
note of that fact.
Note: because of the way we sort the table,
we will be matching 1+i rather than i+1,
so it is OK to assume that i is after +,
not before it. */
if (found_plus)
imm_added_to_rs1 = 1;
if (imm <= 9)
(*info->fprintf_func) (stream, "%d", imm);
else
(*info->fprintf_func) (stream, "%#x", imm);
}
break;
case 'X': /* 5 bit unsigned immediate. */
case 'Y': /* 6 bit unsigned immediate. */
{
int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
if (imm <= 9)
(info->fprintf_func) (stream, "%d", imm);
else
(info->fprintf_func) (stream, "%#x", (unsigned) imm);
}
break;
case '3':
(info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
break;
case 'K':
{
int mask = X_MEMBAR (insn);
int bit = 0x40, printed_one = 0;
const char *name;
if (mask == 0)
(info->fprintf_func) (stream, "0");
else
while (bit)
{
if (mask & bit)
{
if (printed_one)
(info->fprintf_func) (stream, "|");
name = sparc_decode_membar (bit);
(info->fprintf_func) (stream, "%s", name);
printed_one = 1;
}
bit >>= 1;
}
break;
}
case 'k':
info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
(*info->print_address_func) (info->target, info);
break;
case 'G':
info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
(*info->print_address_func) (info->target, info);
break;
case '6':
case '7':
case '8':
case '9':
(*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
break;
case 'z':
(*info->fprintf_func) (stream, "%%icc");
break;
case 'Z':
(*info->fprintf_func) (stream, "%%xcc");
break;
case 'E':
(*info->fprintf_func) (stream, "%%ccr");
break;
case 's':
(*info->fprintf_func) (stream, "%%fprs");
break;
case 'o':
(*info->fprintf_func) (stream, "%%asi");
break;
case 'W':
(*info->fprintf_func) (stream, "%%tick");
break;
case 'P':
(*info->fprintf_func) (stream, "%%pc");
break;
case '?':
if (X_RS1 (insn) == 31)
(*info->fprintf_func) (stream, "%%ver");
else if ((unsigned) X_RS1 (insn) < 17)
(*info->fprintf_func) (stream, "%%%s",
v9_priv_reg_names[X_RS1 (insn)]);
else
(*info->fprintf_func) (stream, "%%reserved");
break;
case '!':
if ((unsigned) X_RD (insn) < 17)
(*info->fprintf_func) (stream, "%%%s",
v9_priv_reg_names[X_RD (insn)]);
else
(*info->fprintf_func) (stream, "%%reserved");
break;
case '$':
if ((unsigned) X_RS1 (insn) < 32)
(*info->fprintf_func) (stream, "%%%s",
v9_hpriv_reg_names[X_RS1 (insn)]);
else
(*info->fprintf_func) (stream, "%%reserved");
break;
case '%':
if ((unsigned) X_RD (insn) < 32)
(*info->fprintf_func) (stream, "%%%s",
v9_hpriv_reg_names[X_RD (insn)]);
else
(*info->fprintf_func) (stream, "%%reserved");
break;
case '/':
if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25)
(*info->fprintf_func) (stream, "%%reserved");
else
(*info->fprintf_func) (stream, "%%%s",
v9a_asr_reg_names[X_RS1 (insn)-16]);
break;
case '_':
if (X_RD (insn) < 16 || X_RD (insn) > 25)
(*info->fprintf_func) (stream, "%%reserved");
else
(*info->fprintf_func) (stream, "%%%s",
v9a_asr_reg_names[X_RD (insn)-16]);
break;
case '*':
{
const char *name = sparc_decode_prefetch (X_RD (insn));
if (name)
(*info->fprintf_func) (stream, "%s", name);
else
(*info->fprintf_func) (stream, "%ld", X_RD (insn));
break;
}
case 'M':
(*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
break;
case 'm':
(*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
break;
case 'L':
info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
(*info->print_address_func) (info->target, info);
break;
case 'n':
(*info->fprintf_func)
(stream, "%#x", SEX (X_DISP22 (insn), 22));
break;
case 'l':
info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
(*info->print_address_func) (info->target, info);
break;
case 'A':
{
const char *name;
if ((info->mach == bfd_mach_sparc_v8plusa) ||
((info->mach >= bfd_mach_sparc_v9) &&
(info->mach <= bfd_mach_sparc_v9b)))
name = sparc_decode_asi_v9 (X_ASI (insn));
else
name = sparc_decode_asi_v8 (X_ASI (insn));
if (name)
(*info->fprintf_func) (stream, "%s", name);
else
(*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
break;
}
case 'C':
(*info->fprintf_func) (stream, "%%csr");
break;
case 'F':
(*info->fprintf_func) (stream, "%%fsr");
break;
case 'p':
(*info->fprintf_func) (stream, "%%psr");
break;
case 'q':
(*info->fprintf_func) (stream, "%%fq");
break;
case 'Q':
(*info->fprintf_func) (stream, "%%cq");
break;
case 't':
(*info->fprintf_func) (stream, "%%tbr");
break;
case 'w':
(*info->fprintf_func) (stream, "%%wim");
break;
case 'x':
(*info->fprintf_func) (stream, "%ld",
((X_LDST_I (insn) << 8)
+ X_ASI (insn)));
break;
case 'y':
(*info->fprintf_func) (stream, "%%y");
break;
case 'u':
case 'U':
{
int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
const char *name = sparc_decode_sparclet_cpreg (val);
if (name)
(*info->fprintf_func) (stream, "%s", name);
else
(*info->fprintf_func) (stream, "%%cpreg(%d)", val);
break;
}
}
}
}
/* If we are adding or or'ing something to rs1, then
check to see whether the previous instruction was
a sethi to the same register as in the sethi.
If so, attempt to print the result of the add or
or (in this context add and or do the same thing)
and its symbolic value. */
if (imm_ored_to_rs1 || imm_added_to_rs1)
{
unsigned long prev_insn;
int errcode;
if (memaddr >= 4)
errcode =
(*info->read_memory_func)
(memaddr - 4, buffer, sizeof (buffer), info);
else
errcode = 1;
prev_insn = getword (buffer);
if (errcode == 0)
{
/* If it is a delayed branch, we need to look at the
instruction before the delayed branch. This handles
sequences such as:
sethi %o1, %hi(_foo), %o1
call _printf
or %o1, %lo(_foo), %o1 */
if (is_delayed_branch (prev_insn))
{
if (memaddr >= 8)
errcode = (*info->read_memory_func)
(memaddr - 8, buffer, sizeof (buffer), info);
else
errcode = 1;
prev_insn = getword (buffer);
}
}
/* If there was a problem reading memory, then assume
the previous instruction was not sethi. */
if (errcode == 0)
{
/* Is it sethi to the same register? */
if ((prev_insn & 0xc1c00000) == 0x01000000
&& X_RD (prev_insn) == X_RS1 (insn))
{
(*info->fprintf_func) (stream, "\t! ");
info->target =
((unsigned) 0xFFFFFFFF
& ((int) X_IMM22 (prev_insn) << 10));
if (imm_added_to_rs1)
info->target += X_SIMM (insn, 13);
else
info->target |= X_SIMM (insn, 13);
(*info->print_address_func) (info->target, info);
info->insn_type = dis_dref;
info->data_size = 4; /* FIXME!!! */
}
}
}
if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
{
/* FIXME -- check is_annulled flag. */
if (opcode->flags & F_UNBR)
info->insn_type = dis_branch;
if (opcode->flags & F_CONDBR)
info->insn_type = dis_condbranch;
if (opcode->flags & F_JSR)
info->insn_type = dis_jsr;
if (opcode->flags & F_DELAYED)
info->branch_delay_insns = 1;
}
return sizeof (buffer);
}
}
info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */
(*info->fprintf_func) (stream, ".long %#08lx", insn);
return sizeof (buffer);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 47/78] contrib/rdmacm-mux: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (45 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 46/78] disas: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 48/78] contrib/vhost-user-scsi: " Emmanouil Pitsidianakis
` (31 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Yuval Shaia, Marcel Apfelbaum
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
contrib/rdmacm-mux/main.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/contrib/rdmacm-mux/main.c b/contrib/rdmacm-mux/main.c
index 771ca01e03..dda6917d58 100644
--- a/contrib/rdmacm-mux/main.c
+++ b/contrib/rdmacm-mux/main.c
@@ -303,72 +303,72 @@ static void hash_tbl_remove_fd_ifid_pair(int fd)
static int get_fd(const char *mad, int umad_len, int *fd, __be64 *gid_ifid)
{
struct umad_hdr *hdr = (struct umad_hdr *)mad;
char *data = (char *)hdr + sizeof(*hdr);
int32_t comm_id = 0;
uint16_t attr_id = be16toh(hdr->attr_id);
int rc = 0;
if (umad_len <= sizeof(*hdr)) {
rc = -EINVAL;
syslog(LOG_DEBUG, "Ignoring MAD packets with header only\n");
goto out;
}
switch (attr_id) {
case UMAD_CM_ATTR_REQ:
if (unlikely(umad_len < sizeof(*hdr) + CM_REQ_DGID_POS +
sizeof(*gid_ifid))) {
rc = -EINVAL;
syslog(LOG_WARNING,
"Invalid MAD packet size (%d) for attr_id 0x%x\n", umad_len,
attr_id);
goto out;
}
memcpy(gid_ifid, data + CM_REQ_DGID_POS, sizeof(*gid_ifid));
rc = hash_tbl_search_fd_by_ifid(fd, gid_ifid);
break;
case UMAD_CM_ATTR_SIDR_REQ:
if (unlikely(umad_len < sizeof(*hdr) + CM_SIDR_REQ_DGID_POS +
sizeof(*gid_ifid))) {
rc = -EINVAL;
syslog(LOG_WARNING,
"Invalid MAD packet size (%d) for attr_id 0x%x\n", umad_len,
attr_id);
goto out;
}
memcpy(gid_ifid, data + CM_SIDR_REQ_DGID_POS, sizeof(*gid_ifid));
rc = hash_tbl_search_fd_by_ifid(fd, gid_ifid);
break;
case UMAD_CM_ATTR_REP:
- /* Fall through */
+ fallthrough;
case UMAD_CM_ATTR_REJ:
- /* Fall through */
+ fallthrough;
case UMAD_CM_ATTR_DREQ:
- /* Fall through */
+ fallthrough;
case UMAD_CM_ATTR_DREP:
- /* Fall through */
+ fallthrough;
case UMAD_CM_ATTR_RTU:
data += sizeof(comm_id);
- /* Fall through */
+ fallthrough;
case UMAD_CM_ATTR_SIDR_REP:
if (unlikely(umad_len < sizeof(*hdr) + sizeof(comm_id))) {
rc = -EINVAL;
syslog(LOG_WARNING,
"Invalid MAD packet size (%d) for attr_id 0x%x\n", umad_len,
attr_id);
goto out;
}
memcpy(&comm_id, data, sizeof(comm_id));
if (comm_id) {
rc = hash_tbl_search_fd_by_comm_id(comm_id, fd, gid_ifid);
}
break;
default:
rc = -EINVAL;
syslog(LOG_WARNING, "Unsupported attr_id 0x%x\n", attr_id);
}
syslog(LOG_DEBUG, "mad_to_vm: %d 0x%x 0x%x\n", *fd, attr_id, comm_id);
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 48/78] contrib/vhost-user-scsi: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (46 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 47/78] contrib/rdmacm-mux: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 49/78] hw/arm: " Emmanouil Pitsidianakis
` (30 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Michael S. Tsirkin, Raphael Norwitz
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
contrib/vhost-user-scsi/vhost-user-scsi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/contrib/vhost-user-scsi/vhost-user-scsi.c b/contrib/vhost-user-scsi/vhost-user-scsi.c
index 9ef61cf5a7..71076f579b 100644
--- a/contrib/vhost-user-scsi/vhost-user-scsi.c
+++ b/contrib/vhost-user-scsi/vhost-user-scsi.c
@@ -109,14 +109,15 @@ static struct scsi_task *scsi_task_new(int cdb_len, uint8_t *cdb, int dir,
static int get_cdb_len(uint8_t *cdb)
{
assert(cdb);
switch (cdb[0] >> 5) {
case 0: return 6;
- case 1: /* fall through */
+ case 1:
+ fallthrough;
case 2: return 10;
case 4: return 16;
case 5: return 12;
}
g_warning("Unable to determine cdb len (0x%02hhX)", (uint8_t)(cdb[0] >> 5));
return -1;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 49/78] hw/arm: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (47 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 48/78] contrib/vhost-user-scsi: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 50/78] hw/audio: " Emmanouil Pitsidianakis
` (29 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Peter Maydell, open list:OMAP
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/arm/omap1.c | 8 ++++----
hw/arm/pxa2xx.c | 6 +++---
hw/arm/stellaris.c | 1 +
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
index d5438156ee..c54a4ec553 100644
--- a/hw/arm/omap1.c
+++ b/hw/arm/omap1.c
@@ -531,46 +531,46 @@ static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
/* Ultra Low-Power Device Module */
static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = opaque;
uint16_t ret;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (addr) {
case 0x14: /* IT_STATUS */
ret = s->ulpd_pm_regs[addr >> 2];
s->ulpd_pm_regs[addr >> 2] = 0;
qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
return ret;
case 0x18: /* Reserved */
case 0x1c: /* Reserved */
case 0x20: /* Reserved */
case 0x28: /* Reserved */
case 0x2c: /* Reserved */
OMAP_BAD_REG(addr);
- /* fall through */
+ fallthrough;
case 0x00: /* COUNTER_32_LSB */
case 0x04: /* COUNTER_32_MSB */
case 0x08: /* COUNTER_HIGH_FREQ_LSB */
case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
case 0x10: /* GAUGING_CTRL */
case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
case 0x30: /* CLOCK_CTRL */
case 0x34: /* SOFT_REQ */
case 0x38: /* COUNTER_32_FIQ */
case 0x3c: /* DPLL_CTRL */
case 0x40: /* STATUS_REQ */
/* XXX: check clk::usecount state for every clock */
case 0x48: /* LOCL_TIME */
case 0x4c: /* APLL_CTRL */
case 0x50: /* POWER_CTRL */
return s->ulpd_pm_regs[addr >> 2];
}
OMAP_BAD_REG(addr);
return 0;
}
@@ -600,120 +600,120 @@ static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = opaque;
int64_t now, ticks;
int div, mult;
static const int bypass_div[4] = { 1, 2, 4, 4 };
uint16_t diff;
if (size != 2) {
omap_badwidth_write16(opaque, addr, value);
return;
}
switch (addr) {
case 0x00: /* COUNTER_32_LSB */
case 0x04: /* COUNTER_32_MSB */
case 0x08: /* COUNTER_HIGH_FREQ_LSB */
case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
case 0x14: /* IT_STATUS */
case 0x40: /* STATUS_REQ */
OMAP_RO_REG(addr);
break;
case 0x10: /* GAUGING_CTRL */
/* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) {
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (value & 1)
s->ulpd_gauge_start = now;
else {
now -= s->ulpd_gauge_start;
/* 32-kHz ticks */
ticks = muldiv64(now, 32768, NANOSECONDS_PER_SECOND);
s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
if (ticks >> 32) /* OVERFLOW_32K */
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
/* High frequency ticks */
ticks = muldiv64(now, 12000000, NANOSECONDS_PER_SECOND);
s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
if (ticks >> 32) /* OVERFLOW_HI_FREQ */
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
}
}
s->ulpd_pm_regs[addr >> 2] = value;
break;
case 0x18: /* Reserved */
case 0x1c: /* Reserved */
case 0x20: /* Reserved */
case 0x28: /* Reserved */
case 0x2c: /* Reserved */
OMAP_BAD_REG(addr);
- /* fall through */
+ fallthrough;
case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
case 0x38: /* COUNTER_32_FIQ */
case 0x48: /* LOCL_TIME */
case 0x50: /* POWER_CTRL */
s->ulpd_pm_regs[addr >> 2] = value;
break;
case 0x30: /* CLOCK_CTRL */
diff = s->ulpd_pm_regs[addr >> 2] ^ value;
s->ulpd_pm_regs[addr >> 2] = value & 0x3f;
omap_ulpd_clk_update(s, diff, value);
break;
case 0x34: /* SOFT_REQ */
diff = s->ulpd_pm_regs[addr >> 2] ^ value;
s->ulpd_pm_regs[addr >> 2] = value & 0x1f;
omap_ulpd_req_update(s, diff, value);
break;
case 0x3c: /* DPLL_CTRL */
/* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
* omitted altogether, probably a typo. */
/* This register has identical semantics with DPLL(1:3) control
* registers, see omap_dpll_write() */
diff = s->ulpd_pm_regs[addr >> 2] & value;
s->ulpd_pm_regs[addr >> 2] = value & 0x2fff;
if (diff & (0x3ff << 2)) {
if (value & (1 << 4)) { /* PLL_ENABLE */
div = ((value >> 5) & 3) + 1; /* PLL_DIV */
mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
} else {
div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
mult = 1;
}
omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
}
/* Enter the desired mode. */
s->ulpd_pm_regs[addr >> 2] =
(s->ulpd_pm_regs[addr >> 2] & 0xfffe) |
((s->ulpd_pm_regs[addr >> 2] >> 4) & 1);
/* Act as if the lock is restored. */
s->ulpd_pm_regs[addr >> 2] |= 2;
break;
case 0x4c: /* APLL_CTRL */
diff = s->ulpd_pm_regs[addr >> 2] & value;
s->ulpd_pm_regs[addr >> 2] = value & 0xf;
if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
(value & (1 << 0)) ? "apll" : "dpll4"));
break;
default:
OMAP_BAD_REG(addr);
}
}
@@ -3169,97 +3169,97 @@ static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mcbsp_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t ret;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (offset) {
case 0x00: /* DRR2 */
if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */
return 0x0000;
- /* Fall through. */
+ fallthrough;
case 0x02: /* DRR1 */
if (s->rx_req < 2) {
printf("%s: Rx FIFO underrun\n", __func__);
omap_mcbsp_rx_done(s);
} else {
s->tx_req -= 2;
if (s->codec && s->codec->in.len >= 2) {
ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
ret |= s->codec->in.fifo[s->codec->in.start ++];
s->codec->in.len -= 2;
} else
ret = 0x0000;
if (!s->tx_req)
omap_mcbsp_rx_done(s);
return ret;
}
return 0x0000;
case 0x04: /* DXR2 */
case 0x06: /* DXR1 */
return 0x0000;
case 0x08: /* SPCR2 */
return s->spcr[1];
case 0x0a: /* SPCR1 */
return s->spcr[0];
case 0x0c: /* RCR2 */
return s->rcr[1];
case 0x0e: /* RCR1 */
return s->rcr[0];
case 0x10: /* XCR2 */
return s->xcr[1];
case 0x12: /* XCR1 */
return s->xcr[0];
case 0x14: /* SRGR2 */
return s->srgr[1];
case 0x16: /* SRGR1 */
return s->srgr[0];
case 0x18: /* MCR2 */
return s->mcr[1];
case 0x1a: /* MCR1 */
return s->mcr[0];
case 0x1c: /* RCERA */
return s->rcer[0];
case 0x1e: /* RCERB */
return s->rcer[1];
case 0x20: /* XCERA */
return s->xcer[0];
case 0x22: /* XCERB */
return s->xcer[1];
case 0x24: /* PCR0 */
return s->pcr;
case 0x26: /* RCERC */
return s->rcer[2];
case 0x28: /* RCERD */
return s->rcer[3];
case 0x2a: /* XCERC */
return s->xcer[2];
case 0x2c: /* XCERD */
return s->xcer[3];
case 0x2e: /* RCERE */
return s->rcer[4];
case 0x30: /* RCERF */
return s->rcer[5];
case 0x32: /* XCERE */
return s->xcer[4];
case 0x34: /* XCERF */
return s->xcer[5];
case 0x36: /* RCERG */
return s->rcer[6];
case 0x38: /* RCERH */
return s->rcer[7];
case 0x3a: /* XCERG */
return s->xcer[6];
case 0x3c: /* XCERH */
return s->xcer[7];
}
OMAP_BAD_REG(addr);
return 0;
}
@@ -3267,135 +3267,135 @@ static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap_mcbsp_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
switch (offset) {
case 0x00: /* DRR2 */
case 0x02: /* DRR1 */
OMAP_RO_REG(addr);
return;
case 0x04: /* DXR2 */
if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
return;
- /* Fall through. */
+ fallthrough;
case 0x06: /* DXR1 */
if (s->tx_req > 1) {
s->tx_req -= 2;
if (s->codec && s->codec->cts) {
s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff;
s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff;
}
if (s->tx_req < 2)
omap_mcbsp_tx_done(s);
} else
printf("%s: Tx FIFO overrun\n", __func__);
return;
case 0x08: /* SPCR2 */
s->spcr[1] &= 0x0002;
s->spcr[1] |= 0x03f9 & value;
s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */
if (~value & 1) /* XRST */
s->spcr[1] &= ~6;
omap_mcbsp_req_update(s);
return;
case 0x0a: /* SPCR1 */
s->spcr[0] &= 0x0006;
s->spcr[0] |= 0xf8f9 & value;
if (value & (1 << 15)) /* DLB */
printf("%s: Digital Loopback mode enable attempt\n", __func__);
if (~value & 1) { /* RRST */
s->spcr[0] &= ~6;
s->rx_req = 0;
omap_mcbsp_rx_done(s);
}
omap_mcbsp_req_update(s);
return;
case 0x0c: /* RCR2 */
s->rcr[1] = value & 0xffff;
return;
case 0x0e: /* RCR1 */
s->rcr[0] = value & 0x7fe0;
return;
case 0x10: /* XCR2 */
s->xcr[1] = value & 0xffff;
return;
case 0x12: /* XCR1 */
s->xcr[0] = value & 0x7fe0;
return;
case 0x14: /* SRGR2 */
s->srgr[1] = value & 0xffff;
omap_mcbsp_req_update(s);
return;
case 0x16: /* SRGR1 */
s->srgr[0] = value & 0xffff;
omap_mcbsp_req_update(s);
return;
case 0x18: /* MCR2 */
s->mcr[1] = value & 0x03e3;
if (value & 3) /* XMCM */
printf("%s: Tx channel selection mode enable attempt\n", __func__);
return;
case 0x1a: /* MCR1 */
s->mcr[0] = value & 0x03e1;
if (value & 1) /* RMCM */
printf("%s: Rx channel selection mode enable attempt\n", __func__);
return;
case 0x1c: /* RCERA */
s->rcer[0] = value & 0xffff;
return;
case 0x1e: /* RCERB */
s->rcer[1] = value & 0xffff;
return;
case 0x20: /* XCERA */
s->xcer[0] = value & 0xffff;
return;
case 0x22: /* XCERB */
s->xcer[1] = value & 0xffff;
return;
case 0x24: /* PCR0 */
s->pcr = value & 0x7faf;
return;
case 0x26: /* RCERC */
s->rcer[2] = value & 0xffff;
return;
case 0x28: /* RCERD */
s->rcer[3] = value & 0xffff;
return;
case 0x2a: /* XCERC */
s->xcer[2] = value & 0xffff;
return;
case 0x2c: /* XCERD */
s->xcer[3] = value & 0xffff;
return;
case 0x2e: /* RCERE */
s->rcer[4] = value & 0xffff;
return;
case 0x30: /* RCERF */
s->rcer[5] = value & 0xffff;
return;
case 0x32: /* XCERE */
s->xcer[4] = value & 0xffff;
return;
case 0x34: /* XCERF */
s->xcer[5] = value & 0xffff;
return;
case 0x36: /* RCERG */
s->rcer[6] = value & 0xffff;
return;
case 0x38: /* RCERH */
s->rcer[7] = value & 0xffff;
return;
case 0x3a: /* XCERG */
s->xcer[6] = value & 0xffff;
return;
case 0x3c: /* XCERH */
s->xcer[7] = value & 0xffff;
return;
}
OMAP_BAD_REG(addr);
}
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index 07d5dd8691..eaa6684243 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -265,68 +265,68 @@ static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
PXA2xxState *s = (PXA2xxState *)ri->opaque;
static const char *pwrmode[8] = {
"Normal", "Idle", "Deep-idle", "Standby",
"Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
};
if (value & 8) {
printf("%s: CPU voltage change attempt\n", __func__);
}
switch (value & 7) {
case 0:
/* Do nothing */
break;
case 1:
/* Idle */
if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */
cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
break;
}
- /* Fall through. */
+ fallthrough;
case 2:
/* Deep-Idle */
cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
goto message;
case 3:
s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC;
s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I;
s->cpu->env.cp15.sctlr_ns = 0;
s->cpu->env.cp15.cpacr_el1 = 0;
s->cpu->env.cp15.ttbr0_el[1] = 0;
s->cpu->env.cp15.dacr_ns = 0;
s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
/*
* The scratch-pad register is almost universally used
* for storing the return address on suspend. For the
* lack of a resuming bootloader, perform a jump
* directly to that address.
*/
memset(s->cpu->env.regs, 0, 4 * 15);
s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2];
#if 0
buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
cpu_physical_memory_write(0, &buffer, 4);
buffer = s->pm_regs[PSPR >> 2];
cpu_physical_memory_write(8, &buffer, 4);
#endif
/* Suspend */
cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
goto message;
default:
message:
printf("%s: machine entered %s mode\n", __func__,
pwrmode[value & 7]);
}
}
@@ -419,18 +419,18 @@ static void pxa2xx_setup_cp14(PXA2xxState *s)
static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case MDCNFG ... SA1110:
if ((addr & 3) == 0)
return s->mm_regs[addr >> 2];
- /* fall through */
+ fallthrough;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad read offset 0x%"HWADDR_PRIx"\n",
__func__, addr);
break;
}
return 0;
}
@@ -438,19 +438,19 @@ static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
static void pxa2xx_mm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case MDCNFG ... SA1110:
if ((addr & 3) == 0) {
s->mm_regs[addr >> 2] = value;
break;
}
- /* fallthrough */
+ fallthrough;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad write offset 0x%"HWADDR_PRIx"\n",
__func__, addr);
break;
}
}
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index aa5b0ddfaa..d68602ab71 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -147,20 +147,21 @@ static uint32_t pllcfg_fury[16] = {
static int ssys_board_class(const ssys_state *s)
{
uint32_t did0 = s->did0;
switch (did0 & DID0_VER_MASK) {
case DID0_VER_0:
return DID0_CLASS_SANDSTORM;
case DID0_VER_1:
switch (did0 & DID0_CLASS_MASK) {
case DID0_CLASS_SANDSTORM:
case DID0_CLASS_FURY:
return did0 & DID0_CLASS_MASK;
}
/* for unknown classes, fall through */
+ fallthrough;
default:
/* This can only happen if the hardwired constant did0 value
* in this board's stellaris_board_info struct is wrong.
*/
g_assert_not_reached();
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 50/78] hw/audio: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (48 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 49/78] hw/arm: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 51/78] chardev: " Emmanouil Pitsidianakis
` (28 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Laurent Vivier, Gerd Hoffmann
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/audio/asc.c | 2 +-
hw/audio/cs4231a.c | 2 +-
hw/audio/gusemu_hal.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/audio/asc.c b/hw/audio/asc.c
index 0f36b4ce9b..336da09509 100644
--- a/hw/audio/asc.c
+++ b/hw/audio/asc.c
@@ -154,126 +154,126 @@ static uint8_t asc_fifo_get(ASCFIFOState *fs)
static int generate_fifo(ASCState *s, int maxsamples)
{
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
uint8_t *buf = s->mixbuf;
int i, wcount = 0;
while (wcount < maxsamples) {
uint8_t val;
int16_t d, f0, f1;
int32_t t;
int shift, filter;
bool hasdata = false;
for (i = 0; i < 2; i++) {
ASCFIFOState *fs = &s->fifos[i];
switch (fs->extregs[ASC_EXTREGS_FIFOCTRL] & 0x83) {
case 0x82:
/*
* CD-XA BRR mode: decompress 15 bytes into 28 16-bit
* samples
*/
if (!fs->cnt) {
val = 0x80;
break;
}
if (fs->xa_cnt == -1) {
/* Start of packet, get flags */
fs->xa_flags = asc_fifo_get(fs);
fs->xa_cnt = 0;
}
shift = fs->xa_flags & 0xf;
filter = fs->xa_flags >> 4;
f0 = (int8_t)fs->extregs[ASC_EXTREGS_CDXA_DECOMP_FILT +
(filter << 1) + 1];
f1 = (int8_t)fs->extregs[ASC_EXTREGS_CDXA_DECOMP_FILT +
(filter << 1)];
if ((fs->xa_cnt & 1) == 0) {
if (!fs->cnt) {
val = 0x80;
break;
}
fs->xa_val = asc_fifo_get(fs);
d = (fs->xa_val & 0xf) << 12;
} else {
d = (fs->xa_val & 0xf0) << 8;
}
t = (d >> shift) + (((fs->xa_last[0] * f0) +
(fs->xa_last[1] * f1) + 32) >> 6);
if (t < -32768) {
t = -32768;
} else if (t > 32767) {
t = 32767;
}
/*
* CD-XA BRR generates 16-bit signed output, so convert to
* 8-bit before writing to buffer. Does real hardware do the
* same?
*/
val = (uint8_t)(t / 256) ^ 0x80;
hasdata = true;
fs->xa_cnt++;
fs->xa_last[1] = fs->xa_last[0];
fs->xa_last[0] = (int16_t)t;
if (fs->xa_cnt == 28) {
/* End of packet */
fs->xa_cnt = -1;
}
break;
default:
- /* fallthrough */
+ fallthrough;
case 0x80:
/* Raw mode */
if (fs->cnt) {
val = asc_fifo_get(fs);
hasdata = true;
} else {
val = 0x80;
}
break;
}
buf[wcount * 2 + i] = val;
}
if (!hasdata) {
break;
}
wcount++;
}
/*
* MacOS (un)helpfully leaves the FIFO engine running even when it has
* finished writing out samples, but still expects the FIFO empty
* interrupts to be generated for each FIFO cycle (without these interrupts
* MacOS will freeze)
*/
if (s->fifos[0].cnt == 0 && s->fifos[1].cnt == 0) {
if (!s->fifo_empty_ns) {
/* FIFO has completed first empty cycle */
s->fifo_empty_ns = now;
} else if (now > (s->fifo_empty_ns + ASC_FIFO_CYCLE_TIME)) {
/* FIFO has completed entire cycle with no data */
s->fifos[0].int_status |= ASC_FIFO_STATUS_HALF_FULL |
ASC_FIFO_STATUS_FULL_EMPTY;
s->fifos[1].int_status |= ASC_FIFO_STATUS_HALF_FULL |
ASC_FIFO_STATUS_FULL_EMPTY;
s->fifo_empty_ns = now;
asc_raise_irq(s);
}
} else {
/* FIFO contains data, reset empty time */
s->fifo_empty_ns = 0;
}
return wcount;
}
diff --git a/hw/audio/cs4231a.c b/hw/audio/cs4231a.c
index 3aa105748d..3bf0116c68 100644
--- a/hw/audio/cs4231a.c
+++ b/hw/audio/cs4231a.c
@@ -272,90 +272,90 @@ static void cs_audio_callback (void *opaque, int free)
static void cs_reset_voices (CSState *s, uint32_t val)
{
int xtal;
struct audsettings as;
IsaDmaClass *k = ISADMA_GET_CLASS(s->isa_dma);
#ifdef DEBUG_XLAW
if (val == 0 || val == 32)
val = (1 << 4) | (1 << 5);
#endif
xtal = val & 1;
as.freq = freqs[xtal][(val >> 1) & 7];
if (as.freq == -1) {
lerr ("unsupported frequency (val=%#x)\n", val);
goto error;
}
as.nchannels = (val & (1 << 4)) ? 2 : 1;
as.endianness = 0;
s->tab = NULL;
switch ((val >> 5) & ((s->dregs[MODE_And_ID] & MODE2) ? 7 : 3)) {
case 0:
as.fmt = AUDIO_FORMAT_U8;
s->shift = as.nchannels == 2;
break;
case 1:
s->tab = MuLawDecompressTable;
goto x_law;
case 3:
s->tab = ALawDecompressTable;
x_law:
as.fmt = AUDIO_FORMAT_S16;
as.endianness = AUDIO_HOST_ENDIANNESS;
s->shift = as.nchannels == 2;
break;
case 6:
as.endianness = 1;
- /* fall through */
+ fallthrough;
case 2:
as.fmt = AUDIO_FORMAT_S16;
s->shift = as.nchannels;
break;
case 7:
case 4:
lerr ("attempt to use reserved format value (%#x)\n", val);
goto error;
case 5:
lerr ("ADPCM 4 bit IMA compatible format is not supported\n");
goto error;
}
s->voice = AUD_open_out (
&s->card,
s->voice,
"cs4231a",
s,
cs_audio_callback,
&as
);
if (s->dregs[Interface_Configuration] & PEN) {
if (!s->dma_running) {
k->hold_DREQ(s->isa_dma, s->dma);
AUD_set_active_out (s->voice, 1);
s->transferred = 0;
}
s->dma_running = 1;
}
else {
if (s->dma_running) {
k->release_DREQ(s->isa_dma, s->dma);
AUD_set_active_out (s->voice, 0);
}
s->dma_running = 0;
}
return;
error:
if (s->dma_running) {
k->release_DREQ(s->isa_dma, s->dma);
AUD_set_active_out (s->voice, 0);
}
}
diff --git a/hw/audio/gusemu_hal.c b/hw/audio/gusemu_hal.c
index f159978b49..76dd906ea1 100644
--- a/hw/audio/gusemu_hal.c
+++ b/hw/audio/gusemu_hal.c
@@ -190,311 +190,311 @@ unsigned int gus_read(GUSEmuState * state, int port, int size)
void gus_write(GUSEmuState * state, int port, int size, unsigned int data)
{
uint8_t *gusptr;
gusptr = state->gusdatapos;
GUSregd(portaccesses)++;
switch (port & 0xff0f)
{
case 0x200: /* MixerCtrlReg */
GUSregb(MixerCtrlReg2x0) = (uint8_t) data;
break;
case 0x206: /* IRQstatReg / SB2x6IRQ */
if (GUSregb(GUS45TimerCtrl) & 0x20) /* SB IRQ enabled? -> set 2x6IRQ bit */
{
GUSregb(TimerStatus2x8) |= 0x08;
GUSregb(IRQStatReg2x6) = 0x10;
GUS_irqrequest(state, state->gusirq, 1);
}
break;
case 0x308: /* AdLib 388h */
case 0x208: /* AdLibCommandReg */
GUSregb(AdLibCommand2xA) = (uint8_t) data;
break;
case 0x309: /* AdLib 389h */
case 0x209: /* AdLibDataReg */
if ((GUSregb(AdLibCommand2xA) == 0x04) && (!(GUSregb(GUS45TimerCtrl) & 1))) /* GUS auto timer mode enabled? */
{
if (data & 0x80)
GUSregb(TimerStatus2x8) &= 0x1f; /* AdLib IRQ reset? -> clear maskable adl. timer int regs */
else
GUSregb(TimerDataReg2x9) = (uint8_t) data;
}
else
{
GUSregb(AdLibData2x9) = (uint8_t) data;
if (GUSregb(GUS45TimerCtrl) & 0x02)
{
GUSregb(TimerStatus2x8) |= 0x01;
GUSregb(IRQStatReg2x6) = 0x10;
GUS_irqrequest(state, state->gusirq, 1);
}
}
break;
case 0x20A:
GUSregb(AdLibStatus2x8) = (uint8_t) data;
break; /* AdLibStatus2x8 */
case 0x20B: /* GUS hidden registers */
switch (GUSregb(RegCtrl_2xF) & 0x7)
{
case 0:
if (GUSregb(MixerCtrlReg2x0) & 0x40)
GUSregb(IRQ_2xB) = (uint8_t) data; /* control register select bit */
else
GUSregb(DMA_2xB) = (uint8_t) data;
break;
/* case 1-4: general purpose emulation regs */
case 5: /* clear stat reg 2xF */
GUSregb(StatRead_2xF) = 0; /* ToDo: is this identical with GUS classic? */
if (!GUSregb(IRQStatReg2x6))
GUS_irqclear(state, state->gusirq);
break;
case 6: /* Jumper reg (Joystick/MIDI enable) */
GUSregb(Jumper_2xB) = (uint8_t) data;
break;
default:;
}
break;
case 0x20C: /* SB2xCd */
if (GUSregb(GUS45TimerCtrl) & 0x20)
{
GUSregb(TimerStatus2x8) |= 0x10; /* SB IRQ enabled? -> set 2xCIRQ bit */
GUSregb(IRQStatReg2x6) = 0x10;
GUS_irqrequest(state, state->gusirq, 1);
}
- /* fall through */
+ fallthrough;
case 0x20D: /* SB2xCd no IRQ */
GUSregb(SB2xCd) = (uint8_t) data;
break;
case 0x20E: /* SB2xE */
GUSregb(SB2xE) = (uint8_t) data;
break;
case 0x20F:
GUSregb(RegCtrl_2xF) = (uint8_t) data;
break; /* CtrlReg2xF */
case 0x302: /* VoiceSelReg */
GUSregb(VoiceSelReg3x2) = (uint8_t) data;
break;
case 0x303: /* FunkSelReg */
GUSregb(FunkSelReg3x3) = (uint8_t) data;
if ((uint8_t) data == 0x8f) /* set irqstatreg, get voicereg and clear IRQ */
{
int voice;
if (GUSregd(voicewavetableirq)) /* WavetableIRQ */
{
for (voice = 0; voice < 31; voice++)
{
if (GUSregd(voicewavetableirq) & (1 << voice))
{
GUSregd(voicewavetableirq) ^= (1 << voice); /* clear IRQ bit */
GUSregb(voice << 5) &= 0x7f; /* clear voice reg irq bit */
if (!GUSregd(voicewavetableirq))
GUSregb(IRQStatReg2x6) &= 0xdf;
if (!GUSregb(IRQStatReg2x6))
GUS_irqclear(state, state->gusirq);
GUSregb(SynVoiceIRQ8f) = voice | 0x60; /* (bit==0 => IRQ wartend) */
return;
}
}
}
else if (GUSregd(voicevolrampirq)) /* VolRamp IRQ */
{
for (voice = 0; voice < 31; voice++)
{
if (GUSregd(voicevolrampirq) & (1 << voice))
{
GUSregd(voicevolrampirq) ^= (1 << voice); /* clear IRQ bit */
GUSregb((voice << 5) + VSRVolRampControl) &= 0x7f; /* clear voice volume reg irq bit */
if (!GUSregd(voicevolrampirq))
GUSregb(IRQStatReg2x6) &= 0xbf;
if (!GUSregb(IRQStatReg2x6))
GUS_irqclear(state, state->gusirq);
GUSregb(SynVoiceIRQ8f) = voice | 0x80; /* (bit==0 => IRQ wartend) */
return;
}
}
}
GUSregb(SynVoiceIRQ8f) = 0xe8; /* kein IRQ wartet */
}
break;
case 0x304:
case 0x305:
{
uint16_t writedata = (uint16_t) data;
uint16_t readmask = 0x0000;
if (size == 1)
{
readmask = 0xff00;
writedata &= 0xff;
if ((port & 0xff0f) == 0x305)
{
writedata = (uint16_t) (writedata << 8);
readmask = 0x00ff;
}
}
switch (GUSregb(FunkSelReg3x3))
{
/* voice specific functions */
case 0x00:
case 0x01:
case 0x02:
case 0x03:
case 0x04:
case 0x05:
case 0x06:
case 0x07:
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
case 0x0c:
case 0x0d:
{
int offset;
if (!(GUSregb(GUS4cReset) & 0x01))
break; /* reset flag active? */
offset = 2 * (GUSregb(FunkSelReg3x3) & 0x0f);
offset += (GUSregb(VoiceSelReg3x2) & 0x1f) << 5; /* = Voice*32 + Function*2 */
GUSregw(offset) = (uint16_t) ((GUSregw(offset) & readmask) | writedata);
}
break;
/* voice unspecific functions */
case 0x0e: /* NumVoices */
GUSregb(NumVoices) = (uint8_t) data;
break;
/* case 0x0f: */ /* read only */
/* common functions */
case 0x41: /* DramDMAContrReg */
GUSregb(GUS41DMACtrl) = (uint8_t) data;
if (data & 0x01)
GUS_dmarequest(state);
break;
case 0x42: /* DramDMAmemPosReg */
GUSregw(GUS42DMAStart) = (GUSregw(GUS42DMAStart) & readmask) | writedata;
GUSregb(GUS50DMAHigh) &= 0xf; /* compatibility stuff... */
break;
case 0x43: /* DRAMaddrLo */
GUSregd(GUSDRAMPOS24bit) =
(GUSregd(GUSDRAMPOS24bit) & (readmask | 0xff0000)) | writedata;
break;
case 0x44: /* DRAMaddrHi */
GUSregd(GUSDRAMPOS24bit) =
(GUSregd(GUSDRAMPOS24bit) & 0xffff) | ((data & 0x0f) << 16);
break;
case 0x45: /* TCtrlReg */
GUSregb(GUS45TimerCtrl) = (uint8_t) data;
if (!(data & 0x20))
GUSregb(TimerStatus2x8) &= 0xe7; /* sb IRQ dis? -> clear 2x8/2xC sb IRQ flags */
if (!(data & 0x02))
GUSregb(TimerStatus2x8) &= 0xfe; /* adlib data IRQ dis? -> clear 2x8 adlib IRQ flag */
if (!(GUSregb(TimerStatus2x8) & 0x19))
GUSregb(IRQStatReg2x6) &= 0xef; /* 0xe6; $$clear IRQ if both IRQ bits are inactive or cleared */
/* catch up delayed timer IRQs: */
if ((GUSregw(TimerIRQs) > 1) && (GUSregb(TimerDataReg2x9) & 3))
{
if (GUSregb(TimerDataReg2x9) & 1) /* start timer 1 (80us decrement rate) */
{
if (!(GUSregb(TimerDataReg2x9) & 0x40))
GUSregb(TimerStatus2x8) |= 0xc0; /* maskable bits */
if (data & 4) /* timer1 irq enable */
{
GUSregb(TimerStatus2x8) |= 4; /* nonmaskable bit */
GUSregb(IRQStatReg2x6) |= 4; /* timer 1 irq pending */
}
}
if (GUSregb(TimerDataReg2x9) & 2) /* start timer 2 (320us decrement rate) */
{
if (!(GUSregb(TimerDataReg2x9) & 0x20))
GUSregb(TimerStatus2x8) |= 0xa0; /* maskable bits */
if (data & 8) /* timer2 irq enable */
{
GUSregb(TimerStatus2x8) |= 2; /* nonmaskable bit */
GUSregb(IRQStatReg2x6) |= 8; /* timer 2 irq pending */
}
}
GUSregw(TimerIRQs)--;
if (GUSregw(BusyTimerIRQs) > 1)
GUSregw(BusyTimerIRQs)--;
else
GUSregw(BusyTimerIRQs) =
GUS_irqrequest(state, state->gusirq, GUSregw(TimerIRQs));
}
else
GUSregw(TimerIRQs) = 0;
if (!(data & 0x04))
{
GUSregb(TimerStatus2x8) &= 0xfb; /* clear non-maskable timer1 bit */
GUSregb(IRQStatReg2x6) &= 0xfb;
}
if (!(data & 0x08))
{
GUSregb(TimerStatus2x8) &= 0xfd; /* clear non-maskable timer2 bit */
GUSregb(IRQStatReg2x6) &= 0xf7;
}
if (!GUSregb(IRQStatReg2x6))
GUS_irqclear(state, state->gusirq);
break;
case 0x46: /* Counter1 */
GUSregb(GUS46Counter1) = (uint8_t) data;
break;
case 0x47: /* Counter2 */
GUSregb(GUS47Counter2) = (uint8_t) data;
break;
/* case 0x48: */ /* sampling freq reg not emulated (same as interwave) */
case 0x49: /* SampCtrlReg */
GUSregb(GUS49SampCtrl) = (uint8_t) data;
break;
/* case 0x4b: */ /* joystick trim not emulated */
case 0x4c: /* GUSreset */
GUSregb(GUS4cReset) = (uint8_t) data;
if (!(GUSregb(GUS4cReset) & 1)) /* reset... */
{
GUSregd(voicewavetableirq) = 0;
GUSregd(voicevolrampirq) = 0;
GUSregw(TimerIRQs) = 0;
GUSregw(BusyTimerIRQs) = 0;
GUSregb(NumVoices) = 0xcd;
GUSregb(IRQStatReg2x6) = 0;
GUSregb(TimerStatus2x8) = 0;
GUSregb(AdLibData2x9) = 0;
GUSregb(TimerDataReg2x9) = 0;
GUSregb(GUS41DMACtrl) = 0;
GUSregb(GUS45TimerCtrl) = 0;
GUSregb(GUS49SampCtrl) = 0;
GUSregb(GUS4cReset) &= 0xf9; /* clear IRQ and DAC enable bits */
GUS_irqclear(state, state->gusirq);
}
/* IRQ enable bit checked elsewhere */
/* EnableDAC bit may be used by external callers */
break;
}
}
break;
case 0x307: /* DRAMaccess */
{
uint8_t *adr;
adr = state->himemaddr + (GUSregd(GUSDRAMPOS24bit) & 0xfffff);
*adr = (uint8_t) data;
}
break;
}
}
/* Attention when breaking up a single DMA transfer to multiple ones:
* it may lead to multiple terminal count interrupts and broken transfers:
*
* 1. Whenever you transfer a piece of data, the gusemu callback is invoked
* 2. The callback may generate a TC irq (if the register was set up to do so)
* 3. The irq may result in the program using the GUS to reprogram the GUS
*
* Some programs also decide to upload by just checking if TC occurs
* (via interrupt or a cleared GUS dma flag)
* and then start the next transfer, without checking DMA state
*
* Thus: Always make sure to set the TC flag correctly!
*
* Note that the genuine GUS had a granularity of 16 bytes/words for low/high DMA
* while later cards had atomic granularity provided by an additional GUS50DMAHigh register
* GUSemu also uses this register to support byte-granular transfers for better compatibility
* with emulators other than GUSemu32
*/
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 51/78] chardev: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (49 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 50/78] hw/audio: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 52/78] hw/char: " Emmanouil Pitsidianakis
` (27 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Marc-André Lureau, Paolo Bonzini
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
chardev/char-socket.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/chardev/char-socket.c b/chardev/char-socket.c
index 73947da188..1562e066a4 100644
--- a/chardev/char-socket.c
+++ b/chardev/char-socket.c
@@ -549,34 +549,34 @@ static int tcp_chr_sync_read(Chardev *chr, const uint8_t *buf, int len)
static char *qemu_chr_compute_filename(SocketChardev *s)
{
struct sockaddr_storage *ss = &s->sioc->localAddr;
struct sockaddr_storage *ps = &s->sioc->remoteAddr;
socklen_t ss_len = s->sioc->localAddrLen;
socklen_t ps_len = s->sioc->remoteAddrLen;
char shost[NI_MAXHOST], sserv[NI_MAXSERV];
char phost[NI_MAXHOST], pserv[NI_MAXSERV];
const char *left = "", *right = "";
switch (ss->ss_family) {
case AF_UNIX:
return g_strdup_printf("unix:%s%s",
((struct sockaddr_un *)(ss))->sun_path,
s->is_listen ? ",server=on" : "");
case AF_INET6:
left = "[";
right = "]";
- /* fall through */
+ fallthrough;
case AF_INET:
getnameinfo((struct sockaddr *) ss, ss_len, shost, sizeof(shost),
sserv, sizeof(sserv), NI_NUMERICHOST | NI_NUMERICSERV);
getnameinfo((struct sockaddr *) ps, ps_len, phost, sizeof(phost),
pserv, sizeof(pserv), NI_NUMERICHOST | NI_NUMERICSERV);
return g_strdup_printf("%s:%s%s%s:%s%s <-> %s%s%s:%s",
qemu_chr_socket_protocol(s),
left, shost, right, sserv,
s->is_listen ? ",server=on" : "",
left, phost, right, pserv);
default:
return g_strdup_printf("unknown");
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 52/78] hw/char: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (50 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 51/78] chardev: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 53/78] nbd: " Emmanouil Pitsidianakis
` (26 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Joel Stanley, Peter Maydell,
Marc-André Lureau, Paolo Bonzini, open list:NRF51
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/char/nrf51_uart.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/char/nrf51_uart.c b/hw/char/nrf51_uart.c
index dfe2276d71..3e2b35c7ad 100644
--- a/hw/char/nrf51_uart.c
+++ b/hw/char/nrf51_uart.c
@@ -113,79 +113,79 @@ static void uart_cancel_transmit(NRF51UARTState *s)
static void uart_write(void *opaque, hwaddr addr,
uint64_t value, unsigned int size)
{
NRF51UARTState *s = NRF51_UART(opaque);
trace_nrf51_uart_write(addr, value, size);
if (!s->enabled && (addr != A_UART_ENABLE)) {
return;
}
switch (addr) {
case A_UART_TXD:
if (!s->pending_tx_byte && s->tx_started) {
s->reg[R_UART_TXD] = value;
s->pending_tx_byte = true;
uart_transmit(NULL, G_IO_OUT, s);
}
break;
case A_UART_INTEN:
s->reg[R_UART_INTEN] = value;
break;
case A_UART_INTENSET:
s->reg[R_UART_INTEN] |= value;
break;
case A_UART_INTENCLR:
s->reg[R_UART_INTEN] &= ~value;
break;
case A_UART_TXDRDY ... A_UART_RXTO:
s->reg[addr / 4] = value;
break;
case A_UART_ERRORSRC:
s->reg[addr / 4] &= ~value;
break;
case A_UART_RXD:
break;
case A_UART_RXDRDY:
if (value == 0) {
s->reg[R_UART_RXDRDY] = 0;
}
break;
case A_UART_STARTTX:
if (value == 1) {
s->tx_started = true;
}
break;
case A_UART_STARTRX:
if (value == 1) {
s->rx_started = true;
}
break;
case A_UART_ENABLE:
if (value) {
if (value == 4) {
s->enabled = true;
}
break;
}
s->enabled = false;
value = 1;
- /* fall through */
+ fallthrough;
case A_UART_SUSPEND:
case A_UART_STOPTX:
if (value == 1) {
s->tx_started = false;
}
- /* fall through */
+ fallthrough;
case A_UART_STOPRX:
if (addr != A_UART_STOPTX && value == 1) {
s->rx_started = false;
s->reg[R_UART_RXTO] = 1;
}
break;
default:
s->reg[addr / 4] = value;
break;
}
nrf51_uart_update_irq(s);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 53/78] nbd: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (51 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 52/78] hw/char: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 54/78] hw/core: " Emmanouil Pitsidianakis
` (25 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Eric Blake, Vladimir Sementsov-Ogievskiy,
open list:Network Block Dev...
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
nbd/client.c | 4 ++--
nbd/common.c | 2 +-
qemu-nbd.c | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/nbd/client.c b/nbd/client.c
index 29ffc609a4..04507249b2 100644
--- a/nbd/client.c
+++ b/nbd/client.c
@@ -1014,102 +1014,102 @@ static int nbd_negotiate_finish_oldstyle(QIOChannel *ioc, NBDExportInfo *info,
/*
* nbd_receive_negotiate:
* Connect to server, complete negotiation, and move into transmission phase.
* Returns: negative errno: failure talking to server
* 0: server is connected
*/
int nbd_receive_negotiate(QIOChannel *ioc, QCryptoTLSCreds *tlscreds,
const char *hostname, QIOChannel **outioc,
NBDExportInfo *info, Error **errp)
{
ERRP_GUARD();
int result;
bool zeroes;
bool base_allocation = info->base_allocation;
assert(info->name && strlen(info->name) <= NBD_MAX_STRING_SIZE);
trace_nbd_receive_negotiate_name(info->name);
result = nbd_start_negotiate(ioc, tlscreds, hostname, outioc,
info->mode, &zeroes, errp);
if (result < 0) {
return result;
}
info->mode = result;
info->base_allocation = false;
if (tlscreds && *outioc) {
ioc = *outioc;
}
switch (info->mode) {
case NBD_MODE_EXTENDED:
case NBD_MODE_STRUCTURED:
if (base_allocation) {
result = nbd_negotiate_simple_meta_context(ioc, info, errp);
if (result < 0) {
return -EINVAL;
}
info->base_allocation = result == 1;
}
- /* fall through */
+ fallthrough;
case NBD_MODE_SIMPLE:
/* Try NBD_OPT_GO first - if it works, we are done (it
* also gives us a good message if the server requires
* TLS). If it is not available, fall back to
* NBD_OPT_LIST for nicer error messages about a missing
* export, then use NBD_OPT_EXPORT_NAME. */
result = nbd_opt_info_or_go(ioc, NBD_OPT_GO, info, errp);
if (result < 0) {
return -EINVAL;
}
if (result > 0) {
return 0;
}
/* Check our desired export is present in the
* server export list. Since NBD_OPT_EXPORT_NAME
* cannot return an error message, running this
* query gives us better error reporting if the
* export name is not available.
*/
if (nbd_receive_query_exports(ioc, info->name, errp) < 0) {
return -EINVAL;
}
- /* fall through */
+ fallthrough;
case NBD_MODE_EXPORT_NAME:
/* write the export name request */
if (nbd_send_option_request(ioc, NBD_OPT_EXPORT_NAME, -1, info->name,
errp) < 0) {
return -EINVAL;
}
/* Read the response */
if (nbd_read64(ioc, &info->size, "export length", errp) < 0) {
return -EINVAL;
}
if (nbd_read16(ioc, &info->flags, "export flags", errp) < 0) {
return -EINVAL;
}
break;
case NBD_MODE_OLDSTYLE:
if (*info->name) {
error_setg(errp, "Server does not support non-empty export names");
return -EINVAL;
}
if (nbd_negotiate_finish_oldstyle(ioc, info, errp) < 0) {
return -EINVAL;
}
break;
default:
g_assert_not_reached();
}
trace_nbd_receive_negotiate_size_flags(info->size, info->flags);
if (zeroes && nbd_drop(ioc, 124, errp) < 0) {
error_prepend(errp, "Failed to read reserved block: ");
return -EINVAL;
}
return 0;
}
/* Clean up result of nbd_receive_export_list */
diff --git a/nbd/common.c b/nbd/common.c
index 3247c1d618..1140ea0888 100644
--- a/nbd/common.c
+++ b/nbd/common.c
@@ -222,37 +222,37 @@ const char *nbd_err_lookup(int err)
int nbd_errno_to_system_errno(int err)
{
int ret;
switch (err) {
case NBD_SUCCESS:
ret = 0;
break;
case NBD_EPERM:
ret = EPERM;
break;
case NBD_EIO:
ret = EIO;
break;
case NBD_ENOMEM:
ret = ENOMEM;
break;
case NBD_ENOSPC:
ret = ENOSPC;
break;
case NBD_EOVERFLOW:
ret = EOVERFLOW;
break;
case NBD_ENOTSUP:
ret = ENOTSUP;
break;
case NBD_ESHUTDOWN:
ret = ESHUTDOWN;
break;
default:
trace_nbd_unknown_error(err);
- /* fallthrough */
+ fallthrough;
case NBD_EINVAL:
ret = EINVAL;
break;
}
return ret;
}
diff --git a/qemu-nbd.c b/qemu-nbd.c
index 186e6468b1..41e50208a5 100644
--- a/qemu-nbd.c
+++ b/qemu-nbd.c
@@ -528,704 +528,704 @@ static void qemu_nbd_shutdown(void)
int main(int argc, char **argv)
{
BlockBackend *blk;
BlockDriverState *bs;
uint64_t dev_offset = 0;
bool readonly = false;
bool disconnect = false;
const char *bindto = NULL;
const char *port = NULL;
char *sockpath = NULL;
QemuOpts *sn_opts = NULL;
const char *sn_id_or_name = NULL;
const char *sopt = "hVb:o:p:rsnc:dvk:e:f:tl:x:T:D:AB:L";
struct option lopt[] = {
{ "help", no_argument, NULL, 'h' },
{ "version", no_argument, NULL, 'V' },
{ "bind", required_argument, NULL, 'b' },
{ "port", required_argument, NULL, 'p' },
{ "socket", required_argument, NULL, 'k' },
{ "offset", required_argument, NULL, 'o' },
{ "read-only", no_argument, NULL, 'r' },
{ "allocation-depth", no_argument, NULL, 'A' },
{ "bitmap", required_argument, NULL, 'B' },
{ "connect", required_argument, NULL, 'c' },
{ "disconnect", no_argument, NULL, 'd' },
{ "list", no_argument, NULL, 'L' },
{ "snapshot", no_argument, NULL, 's' },
{ "load-snapshot", required_argument, NULL, 'l' },
{ "nocache", no_argument, NULL, 'n' },
{ "cache", required_argument, NULL, QEMU_NBD_OPT_CACHE },
{ "aio", required_argument, NULL, QEMU_NBD_OPT_AIO },
{ "discard", required_argument, NULL, QEMU_NBD_OPT_DISCARD },
{ "detect-zeroes", required_argument, NULL,
QEMU_NBD_OPT_DETECT_ZEROES },
{ "shared", required_argument, NULL, 'e' },
{ "format", required_argument, NULL, 'f' },
{ "persistent", no_argument, NULL, 't' },
{ "verbose", no_argument, NULL, 'v' },
{ "object", required_argument, NULL, QEMU_NBD_OPT_OBJECT },
{ "export-name", required_argument, NULL, 'x' },
{ "description", required_argument, NULL, 'D' },
{ "tls-creds", required_argument, NULL, QEMU_NBD_OPT_TLSCREDS },
{ "tls-hostname", required_argument, NULL, QEMU_NBD_OPT_TLSHOSTNAME },
{ "tls-authz", required_argument, NULL, QEMU_NBD_OPT_TLSAUTHZ },
{ "image-opts", no_argument, NULL, QEMU_NBD_OPT_IMAGE_OPTS },
{ "trace", required_argument, NULL, 'T' },
{ "fork", no_argument, NULL, QEMU_NBD_OPT_FORK },
{ "pid-file", required_argument, NULL, QEMU_NBD_OPT_PID_FILE },
{ "selinux-label", required_argument, NULL,
QEMU_NBD_OPT_SELINUX_LABEL },
{ NULL, 0, NULL, 0 }
};
int ch;
int opt_ind = 0;
int flags = BDRV_O_RDWR;
int ret = 0;
bool seen_cache = false;
bool seen_discard = false;
bool seen_aio = false;
pthread_t client_thread;
const char *fmt = NULL;
Error *local_err = NULL;
BlockdevDetectZeroesOptions detect_zeroes = BLOCKDEV_DETECT_ZEROES_OPTIONS_OFF;
QDict *options = NULL;
const char *export_name = NULL; /* defaults to "" later for server mode */
const char *export_description = NULL;
BlockDirtyBitmapOrStrList *bitmaps = NULL;
bool alloc_depth = false;
const char *tlscredsid = NULL;
const char *tlshostname = NULL;
bool imageOpts = false;
bool writethrough = false; /* Client will flush as needed. */
bool list = false;
unsigned socket_activation;
const char *pid_file_name = NULL;
const char *selinux_label = NULL;
BlockExportOptions *export_opts;
struct NbdClientOpts opts = {
.fork_process = false,
.verbose = false,
.device = NULL,
.srcpath = NULL,
.saddr = NULL,
.old_stderr = STDOUT_FILENO,
};
#ifdef CONFIG_POSIX
os_setup_early_signal_handling();
os_setup_signal_handling();
#endif
socket_init();
error_init(argv[0]);
module_call_init(MODULE_INIT_TRACE);
qcrypto_init(&error_fatal);
module_call_init(MODULE_INIT_QOM);
qemu_add_opts(&qemu_trace_opts);
qemu_init_exec_dir(argv[0]);
while ((ch = getopt_long(argc, argv, sopt, lopt, &opt_ind)) != -1) {
switch (ch) {
case 's':
flags |= BDRV_O_SNAPSHOT;
break;
case 'n':
optarg = (char *) "none";
- /* fallthrough */
+ fallthrough;
case QEMU_NBD_OPT_CACHE:
if (seen_cache) {
error_report("-n and --cache can only be specified once");
exit(EXIT_FAILURE);
}
seen_cache = true;
if (bdrv_parse_cache_mode(optarg, &flags, &writethrough) == -1) {
error_report("Invalid cache mode `%s'", optarg);
exit(EXIT_FAILURE);
}
break;
case QEMU_NBD_OPT_AIO:
if (seen_aio) {
error_report("--aio can only be specified once");
exit(EXIT_FAILURE);
}
seen_aio = true;
if (bdrv_parse_aio(optarg, &flags) < 0) {
error_report("Invalid aio mode '%s'", optarg);
exit(EXIT_FAILURE);
}
break;
case QEMU_NBD_OPT_DISCARD:
if (seen_discard) {
error_report("--discard can only be specified once");
exit(EXIT_FAILURE);
}
seen_discard = true;
if (bdrv_parse_discard_flags(optarg, &flags) == -1) {
error_report("Invalid discard mode `%s'", optarg);
exit(EXIT_FAILURE);
}
break;
case QEMU_NBD_OPT_DETECT_ZEROES:
detect_zeroes =
qapi_enum_parse(&BlockdevDetectZeroesOptions_lookup,
optarg,
BLOCKDEV_DETECT_ZEROES_OPTIONS_OFF,
&local_err);
if (local_err) {
error_reportf_err(local_err,
"Failed to parse detect_zeroes mode: ");
exit(EXIT_FAILURE);
}
if (detect_zeroes == BLOCKDEV_DETECT_ZEROES_OPTIONS_UNMAP &&
!(flags & BDRV_O_UNMAP)) {
error_report("setting detect-zeroes to unmap is not allowed "
"without setting discard operation to unmap");
exit(EXIT_FAILURE);
}
break;
case 'b':
bindto = optarg;
break;
case 'p':
port = optarg;
break;
case 'o':
if (qemu_strtou64(optarg, NULL, 0, &dev_offset) < 0) {
error_report("Invalid offset '%s'", optarg);
exit(EXIT_FAILURE);
}
break;
case 'l':
if (strstart(optarg, SNAPSHOT_OPT_BASE, NULL)) {
sn_opts = qemu_opts_parse_noisily(&internal_snapshot_opts,
optarg, false);
if (!sn_opts) {
error_report("Failed in parsing snapshot param `%s'",
optarg);
exit(EXIT_FAILURE);
}
} else {
sn_id_or_name = optarg;
}
- /* fall through */
+ fallthrough;
case 'r':
readonly = true;
flags &= ~BDRV_O_RDWR;
break;
case 'A':
alloc_depth = true;
break;
case 'B':
{
BlockDirtyBitmapOrStr *el = g_new(BlockDirtyBitmapOrStr, 1);
*el = (BlockDirtyBitmapOrStr) {
.type = QTYPE_QSTRING,
.u.local = g_strdup(optarg),
};
QAPI_LIST_PREPEND(bitmaps, el);
}
break;
case 'k':
sockpath = optarg;
if (sockpath[0] != '/') {
error_report("socket path must be absolute");
exit(EXIT_FAILURE);
}
break;
case 'd':
disconnect = true;
break;
case 'c':
opts.device = optarg;
break;
case 'e':
if (qemu_strtoi(optarg, NULL, 0, &shared) < 0 ||
shared < 0) {
error_report("Invalid shared device number '%s'", optarg);
exit(EXIT_FAILURE);
}
break;
case 'f':
fmt = optarg;
break;
case 't':
persistent = 1;
break;
case 'x':
export_name = optarg;
if (strlen(export_name) > NBD_MAX_STRING_SIZE) {
error_report("export name '%s' too long", export_name);
exit(EXIT_FAILURE);
}
break;
case 'D':
export_description = optarg;
if (strlen(export_description) > NBD_MAX_STRING_SIZE) {
error_report("export description '%s' too long",
export_description);
exit(EXIT_FAILURE);
}
break;
case 'v':
opts.verbose = true;
break;
case 'V':
version(argv[0]);
exit(0);
break;
case 'h':
usage(argv[0]);
exit(0);
break;
case '?':
error_report("Try `%s --help' for more information.", argv[0]);
exit(EXIT_FAILURE);
case QEMU_NBD_OPT_OBJECT:
user_creatable_process_cmdline(optarg);
break;
case QEMU_NBD_OPT_TLSCREDS:
tlscredsid = optarg;
break;
case QEMU_NBD_OPT_TLSHOSTNAME:
tlshostname = optarg;
break;
case QEMU_NBD_OPT_IMAGE_OPTS:
imageOpts = true;
break;
case 'T':
trace_opt_parse(optarg);
break;
case QEMU_NBD_OPT_TLSAUTHZ:
tlsauthz = optarg;
break;
case QEMU_NBD_OPT_FORK:
opts.fork_process = true;
break;
case 'L':
list = true;
break;
case QEMU_NBD_OPT_PID_FILE:
pid_file_name = optarg;
break;
case QEMU_NBD_OPT_SELINUX_LABEL:
selinux_label = optarg;
break;
}
}
if (list) {
if (argc != optind) {
error_report("List mode is incompatible with a file name");
exit(EXIT_FAILURE);
}
if (export_name || export_description || dev_offset ||
opts.device || disconnect || fmt || sn_id_or_name || bitmaps ||
alloc_depth || seen_aio || seen_discard || seen_cache) {
error_report("List mode is incompatible with per-device settings");
exit(EXIT_FAILURE);
}
if (opts.fork_process) {
error_report("List mode is incompatible with forking");
exit(EXIT_FAILURE);
}
} else if ((argc - optind) != 1) {
error_report("Invalid number of arguments");
error_printf("Try `%s --help' for more information.\n", argv[0]);
exit(EXIT_FAILURE);
} else if (!export_name) {
export_name = "";
}
if (!trace_init_backends()) {
exit(1);
}
trace_init_file();
qemu_set_log(LOG_TRACE, &error_fatal);
socket_activation = check_socket_activation();
if (socket_activation == 0) {
if (!sockpath) {
setup_address_and_port(&bindto, &port);
}
} else {
/* Using socket activation - check user didn't use -p etc. */
const char *err_msg = socket_activation_validate_opts(opts.device,
sockpath,
bindto, port,
selinux_label,
list);
if (err_msg != NULL) {
error_report("%s", err_msg);
exit(EXIT_FAILURE);
}
/* qemu-nbd can only listen on a single socket. */
if (socket_activation > 1) {
error_report("qemu-nbd does not support socket activation with %s > 1",
"LISTEN_FDS");
exit(EXIT_FAILURE);
}
}
if (tlscredsid) {
if (opts.device) {
error_report("TLS is not supported with a host device");
exit(EXIT_FAILURE);
}
if (tlsauthz && list) {
error_report("TLS authorization is incompatible with export list");
exit(EXIT_FAILURE);
}
if (tlshostname && !list) {
error_report("TLS hostname is only supported with export list");
exit(EXIT_FAILURE);
}
tlscreds = nbd_get_tls_creds(tlscredsid, list, &local_err);
if (local_err) {
error_reportf_err(local_err, "Failed to get TLS creds: ");
exit(EXIT_FAILURE);
}
} else {
if (tlsauthz) {
error_report("--tls-authz is not permitted without --tls-creds");
exit(EXIT_FAILURE);
}
if (tlshostname) {
error_report("--tls-hostname is not permitted without --tls-creds");
exit(EXIT_FAILURE);
}
}
if (selinux_label) {
#ifdef CONFIG_SELINUX
if (sockpath == NULL && opts.device == NULL) {
error_report("--selinux-label is not permitted without --socket");
exit(EXIT_FAILURE);
}
#else
error_report("SELinux support not enabled in this binary");
exit(EXIT_FAILURE);
#endif
}
if (list) {
opts.saddr = nbd_build_socket_address(sockpath, bindto, port);
return qemu_nbd_client_list(opts.saddr, tlscreds,
tlshostname ? tlshostname : bindto);
}
#if !HAVE_NBD_DEVICE
if (disconnect || opts.device) {
error_report("Kernel /dev/nbdN support not available");
exit(EXIT_FAILURE);
}
#else /* HAVE_NBD_DEVICE */
if (disconnect) {
int nbdfd = open(argv[optind], O_RDWR);
if (nbdfd < 0) {
error_report("Cannot open %s: %s", argv[optind],
strerror(errno));
exit(EXIT_FAILURE);
}
nbd_disconnect(nbdfd);
close(nbdfd);
printf("%s disconnected\n", argv[optind]);
return 0;
}
#endif
if ((opts.device && !opts.verbose) || opts.fork_process) {
#ifndef WIN32
g_autoptr(GError) err = NULL;
int stderr_fd[2];
pid_t pid;
if (!g_unix_open_pipe(stderr_fd, FD_CLOEXEC, &err)) {
error_report("Error setting up communication pipe: %s",
err->message);
exit(EXIT_FAILURE);
}
/* Now daemonize, but keep a communication channel open to
* print errors and exit with the proper status code.
*/
pid = fork();
if (pid < 0) {
error_report("Failed to fork: %s", strerror(errno));
exit(EXIT_FAILURE);
} else if (pid == 0) {
int saved_errno;
close(stderr_fd[0]);
/* Remember parent's stderr if we will be restoring it. */
if (opts.verbose /* fork_process is set */) {
opts.old_stderr = dup(STDERR_FILENO);
if (opts.old_stderr < 0) {
error_report("Could not dup original stderr: %s",
strerror(errno));
exit(EXIT_FAILURE);
}
}
ret = qemu_daemon(1, 0);
saved_errno = errno; /* dup2 will overwrite error below */
/* Temporarily redirect stderr to the parent's pipe... */
if (dup2(stderr_fd[1], STDERR_FILENO) < 0) {
char str[256];
snprintf(str, sizeof(str),
"%s: Failed to link stderr to the pipe: %s\n",
g_get_prgname(), strerror(errno));
/*
* We are unable to use error_report() here as we need to get
* stderr pointed to the parent's pipe. Write to that pipe
* manually.
*/
ret = write(stderr_fd[1], str, strlen(str));
exit(EXIT_FAILURE);
}
if (ret < 0) {
error_report("Failed to daemonize: %s", strerror(saved_errno));
exit(EXIT_FAILURE);
}
/* ... close the descriptor we inherited and go on. */
close(stderr_fd[1]);
} else {
bool errors = false;
char *buf;
/* In the parent. Print error messages from the child until
* it closes the pipe.
*/
close(stderr_fd[1]);
buf = g_malloc(1024);
while ((ret = read(stderr_fd[0], buf, 1024)) > 0) {
errors = true;
ret = qemu_write_full(STDERR_FILENO, buf, ret);
if (ret < 0) {
exit(EXIT_FAILURE);
}
}
if (ret < 0) {
error_report("Cannot read from daemon: %s",
strerror(errno));
exit(EXIT_FAILURE);
}
/* Usually the daemon should not print any message.
* Exit with zero status in that case.
*/
exit(errors);
}
#else /* WIN32 */
error_report("Unable to fork into background on Windows hosts");
exit(EXIT_FAILURE);
#endif /* WIN32 */
}
if (opts.device != NULL && sockpath == NULL) {
sockpath = g_malloc(128);
snprintf(sockpath, 128, SOCKET_PATH, basename(opts.device));
}
server = qio_net_listener_new();
if (socket_activation == 0) {
int backlog;
if (persistent || shared == 0) {
backlog = SOMAXCONN;
} else {
backlog = MIN(shared, SOMAXCONN);
}
#ifdef CONFIG_SELINUX
if (selinux_label && setsockcreatecon_raw(selinux_label) == -1) {
error_report("Cannot set SELinux socket create context to %s: %s",
selinux_label, strerror(errno));
exit(EXIT_FAILURE);
}
#endif
opts.saddr = nbd_build_socket_address(sockpath, bindto, port);
if (qio_net_listener_open_sync(server, opts.saddr, backlog,
&local_err) < 0) {
object_unref(OBJECT(server));
error_report_err(local_err);
exit(EXIT_FAILURE);
}
#ifdef CONFIG_SELINUX
if (selinux_label && setsockcreatecon_raw(NULL) == -1) {
error_report("Cannot clear SELinux socket create context: %s",
strerror(errno));
exit(EXIT_FAILURE);
}
#endif
} else {
size_t i;
/* See comment in check_socket_activation above. */
for (i = 0; i < socket_activation; i++) {
QIOChannelSocket *sioc;
sioc = qio_channel_socket_new_fd(FIRST_SOCKET_ACTIVATION_FD + i,
&local_err);
if (sioc == NULL) {
object_unref(OBJECT(server));
error_reportf_err(local_err,
"Failed to use socket activation: ");
exit(EXIT_FAILURE);
}
qio_net_listener_add(server, sioc);
object_unref(OBJECT(sioc));
}
}
qemu_init_main_loop(&error_fatal);
bdrv_init();
atexit(qemu_nbd_shutdown);
opts.srcpath = argv[optind];
if (imageOpts) {
QemuOpts *o;
if (fmt) {
error_report("--image-opts and -f are mutually exclusive");
exit(EXIT_FAILURE);
}
o = qemu_opts_parse_noisily(&file_opts, opts.srcpath, true);
if (!o) {
qemu_opts_reset(&file_opts);
exit(EXIT_FAILURE);
}
options = qemu_opts_to_qdict(o, NULL);
qemu_opts_reset(&file_opts);
blk = blk_new_open(NULL, NULL, options, flags, &local_err);
} else {
if (fmt) {
options = qdict_new();
qdict_put_str(options, "driver", fmt);
}
blk = blk_new_open(opts.srcpath, NULL, options, flags, &local_err);
}
if (!blk) {
error_reportf_err(local_err, "Failed to blk_new_open '%s': ",
argv[optind]);
exit(EXIT_FAILURE);
}
bs = blk_bs(blk);
if (dev_offset) {
QDict *raw_opts = qdict_new();
qdict_put_str(raw_opts, "driver", "raw");
qdict_put_str(raw_opts, "file", bs->node_name);
qdict_put_int(raw_opts, "offset", dev_offset);
aio_context_acquire(qemu_get_aio_context());
bs = bdrv_open(NULL, NULL, raw_opts, flags, &error_fatal);
aio_context_release(qemu_get_aio_context());
blk_remove_bs(blk);
blk_insert_bs(blk, bs, &error_fatal);
bdrv_unref(bs);
}
blk_set_enable_write_cache(blk, !writethrough);
if (sn_opts) {
ret = bdrv_snapshot_load_tmp(bs,
qemu_opt_get(sn_opts, SNAPSHOT_OPT_ID),
qemu_opt_get(sn_opts, SNAPSHOT_OPT_NAME),
&local_err);
} else if (sn_id_or_name) {
ret = bdrv_snapshot_load_tmp_by_id_or_name(bs, sn_id_or_name,
&local_err);
}
if (ret < 0) {
error_reportf_err(local_err, "Failed to load snapshot: ");
exit(EXIT_FAILURE);
}
bs->detect_zeroes = detect_zeroes;
nbd_server_is_qemu_nbd(shared);
export_opts = g_new(BlockExportOptions, 1);
*export_opts = (BlockExportOptions) {
.type = BLOCK_EXPORT_TYPE_NBD,
.id = g_strdup("qemu-nbd-export"),
.node_name = g_strdup(bdrv_get_node_name(bs)),
.has_writethrough = true,
.writethrough = writethrough,
.has_writable = true,
.writable = !readonly,
.u.nbd = {
.name = g_strdup(export_name),
.description = g_strdup(export_description),
.has_bitmaps = !!bitmaps,
.bitmaps = bitmaps,
.has_allocation_depth = alloc_depth,
.allocation_depth = alloc_depth,
},
};
blk_exp_add(export_opts, &error_fatal);
qapi_free_BlockExportOptions(export_opts);
if (opts.device) {
#if HAVE_NBD_DEVICE
ret = pthread_create(&client_thread, NULL, nbd_client_thread, &opts);
if (ret != 0) {
error_report("Failed to create client thread: %s", strerror(ret));
exit(EXIT_FAILURE);
}
#endif
} else {
/* Shut up GCC warnings. */
memset(&client_thread, 0, sizeof(client_thread));
}
nbd_update_server_watch();
if (pid_file_name) {
qemu_write_pidfile(pid_file_name, &error_fatal);
}
/* now when the initialization is (almost) complete, chdir("/")
* to free any busy filesystems */
if (chdir("/") < 0) {
error_report("Could not chdir to root directory: %s",
strerror(errno));
exit(EXIT_FAILURE);
}
if (opts.fork_process) {
nbd_client_release_pipe(opts.old_stderr);
}
state = RUNNING;
do {
main_loop_wait(false);
if (state == TERMINATE) {
blk_exp_close_all();
state = TERMINATED;
}
} while (state != TERMINATED);
blk_unref(blk);
if (sockpath) {
unlink(sockpath);
}
qemu_opts_del(sn_opts);
if (opts.device) {
void *result;
pthread_join(client_thread, &result);
ret = (intptr_t)result;
exit(ret);
} else {
exit(EXIT_SUCCESS);
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 54/78] hw/core: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (52 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 53/78] nbd: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 55/78] hw/display: " Emmanouil Pitsidianakis
` (24 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/core/loader.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 4dd5a71fb7..559d63a1e2 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -625,138 +625,138 @@ toosmall:
/* Load a U-Boot image. */
static ssize_t load_uboot_image(const char *filename, hwaddr *ep,
hwaddr *loadaddr, int *is_linux,
uint8_t image_type,
uint64_t (*translate_fn)(void *, uint64_t),
void *translate_opaque, AddressSpace *as)
{
int fd;
ssize_t size;
hwaddr address;
uboot_image_header_t h;
uboot_image_header_t *hdr = &h;
uint8_t *data = NULL;
int ret = -1;
int do_uncompress = 0;
fd = open(filename, O_RDONLY | O_BINARY);
if (fd < 0)
return -1;
size = read(fd, hdr, sizeof(uboot_image_header_t));
if (size < sizeof(uboot_image_header_t)) {
goto out;
}
bswap_uboot_header(hdr);
if (hdr->ih_magic != IH_MAGIC)
goto out;
if (hdr->ih_type != image_type) {
if (!(image_type == IH_TYPE_KERNEL &&
hdr->ih_type == IH_TYPE_KERNEL_NOLOAD)) {
fprintf(stderr, "Wrong image type %d, expected %d\n", hdr->ih_type,
image_type);
goto out;
}
}
/* TODO: Implement other image types. */
switch (hdr->ih_type) {
case IH_TYPE_KERNEL_NOLOAD:
if (!loadaddr || *loadaddr == LOAD_UIMAGE_LOADADDR_INVALID) {
fprintf(stderr, "this image format (kernel_noload) cannot be "
"loaded on this machine type");
goto out;
}
hdr->ih_load = *loadaddr + sizeof(*hdr);
hdr->ih_ep += hdr->ih_load;
- /* fall through */
+ fallthrough;
case IH_TYPE_KERNEL:
address = hdr->ih_load;
if (translate_fn) {
address = translate_fn(translate_opaque, address);
}
if (loadaddr) {
*loadaddr = hdr->ih_load;
}
switch (hdr->ih_comp) {
case IH_COMP_NONE:
break;
case IH_COMP_GZIP:
do_uncompress = 1;
break;
default:
fprintf(stderr,
"Unable to load u-boot images with compression type %d\n",
hdr->ih_comp);
goto out;
}
if (ep) {
*ep = hdr->ih_ep;
}
/* TODO: Check CPU type. */
if (is_linux) {
if (hdr->ih_os == IH_OS_LINUX) {
*is_linux = 1;
} else if (hdr->ih_os == IH_OS_VXWORKS) {
/*
* VxWorks 7 uses the same boot interface as the Linux kernel
* on Arm (64-bit only), PowerPC and RISC-V architectures.
*/
switch (hdr->ih_arch) {
case IH_ARCH_ARM64:
case IH_ARCH_PPC:
case IH_ARCH_RISCV:
*is_linux = 1;
break;
default:
*is_linux = 0;
break;
}
} else {
*is_linux = 0;
}
}
break;
case IH_TYPE_RAMDISK:
address = *loadaddr;
break;
default:
fprintf(stderr, "Unsupported u-boot image type %d\n", hdr->ih_type);
goto out;
}
data = g_malloc(hdr->ih_size);
if (read(fd, data, hdr->ih_size) != hdr->ih_size) {
fprintf(stderr, "Error reading file\n");
goto out;
}
if (do_uncompress) {
uint8_t *compressed_data;
size_t max_bytes;
ssize_t bytes;
compressed_data = data;
max_bytes = UBOOT_MAX_GUNZIP_BYTES;
data = g_malloc(max_bytes);
bytes = gunzip(data, max_bytes, compressed_data, hdr->ih_size);
g_free(compressed_data);
if (bytes < 0) {
fprintf(stderr, "Unable to decompress gzipped image!\n");
goto out;
}
hdr->ih_size = bytes;
}
rom_add_blob_fixed_as(filename, data, hdr->ih_size, address, as);
ret = hdr->ih_size;
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 55/78] hw/display: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (53 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 54/78] hw/core: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 56/78] hw/input: " Emmanouil Pitsidianakis
` (23 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Mark Cave-Ayland, Gerd Hoffmann
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/display/cg3.c | 2 +-
hw/display/cirrus_vga.c | 2 +-
hw/display/tcx.c | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/display/cg3.c b/hw/display/cg3.c
index 2e9656ae1c..53eb9831b2 100644
--- a/hw/display/cg3.c
+++ b/hw/display/cg3.c
@@ -199,65 +199,65 @@ static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size)
static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
CG3State *s = opaque;
uint8_t regval;
int i;
trace_cg3_write(addr, val, size);
switch (addr) {
case CG3_REG_BT458_ADDR:
s->dac_index = val;
s->dac_state = 0;
break;
case CG3_REG_BT458_COLMAP:
/* This register can be written to as either a long word or a byte */
if (size == 1) {
val <<= 24;
}
for (i = 0; i < size; i++) {
regval = val >> 24;
switch (s->dac_state) {
case 0:
s->r[s->dac_index] = regval;
s->dac_state++;
break;
case 1:
s->g[s->dac_index] = regval;
s->dac_state++;
break;
case 2:
s->b[s->dac_index] = regval;
/* Index autoincrement */
s->dac_index = (s->dac_index + 1) & 0xff;
- /* fall through */
+ fallthrough;
default:
s->dac_state = 0;
break;
}
val <<= 8;
}
s->full_update = 1;
break;
case CG3_REG_FBC_CTRL:
s->regs[0] = val;
break;
case CG3_REG_FBC_STATUS:
if (s->regs[1] & CG3_SR_PENDING_INT) {
/* clear interrupt */
s->regs[1] &= ~CG3_SR_PENDING_INT;
qemu_irq_lower(s->irq);
}
break;
case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1:
s->regs[addr - 0x10] = val;
break;
default:
qemu_log_mask(LOG_UNIMP,
"cg3: Unimplemented register write "
"reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
addr, size, val);
break;
}
}
diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c
index b80f98b6c4..f1513a084c 100644
--- a/hw/display/cirrus_vga.c
+++ b/hw/display/cirrus_vga.c
@@ -1319,97 +1319,97 @@ static int cirrus_vga_read_sr(CirrusVGAState * s)
static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
{
switch (s->vga.sr_index) {
case 0x00: // Standard VGA
case 0x01: // Standard VGA
case 0x02: // Standard VGA
case 0x03: // Standard VGA
case 0x04: // Standard VGA
s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
if (s->vga.sr_index == 1)
s->vga.update_retrace_info(&s->vga);
break;
case 0x06: // Unlock Cirrus extensions
val &= 0x17;
if (val == 0x12) {
s->vga.sr[s->vga.sr_index] = 0x12;
} else {
s->vga.sr[s->vga.sr_index] = 0x0f;
}
break;
case 0x10:
case 0x30:
case 0x50:
case 0x70: // Graphics Cursor X
case 0x90:
case 0xb0:
case 0xd0:
case 0xf0: // Graphics Cursor X
s->vga.sr[0x10] = val;
s->vga.hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
break;
case 0x11:
case 0x31:
case 0x51:
case 0x71: // Graphics Cursor Y
case 0x91:
case 0xb1:
case 0xd1:
case 0xf1: // Graphics Cursor Y
s->vga.sr[0x11] = val;
s->vga.hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
break;
case 0x07: // Extended Sequencer Mode
cirrus_update_memory_access(s);
- /* fall through */
+ fallthrough;
case 0x08: // EEPROM Control
case 0x09: // Scratch Register 0
case 0x0a: // Scratch Register 1
case 0x0b: // VCLK 0
case 0x0c: // VCLK 1
case 0x0d: // VCLK 2
case 0x0e: // VCLK 3
case 0x0f: // DRAM Control
case 0x13: // Graphics Cursor Pattern Address
case 0x14: // Scratch Register 2
case 0x15: // Scratch Register 3
case 0x16: // Performance Tuning Register
case 0x18: // Signature Generator Control
case 0x19: // Signature Generator Result
case 0x1a: // Signature Generator Result
case 0x1b: // VCLK 0 Denominator & Post
case 0x1c: // VCLK 1 Denominator & Post
case 0x1d: // VCLK 2 Denominator & Post
case 0x1e: // VCLK 3 Denominator & Post
case 0x1f: // BIOS Write Enable and MCLK select
s->vga.sr[s->vga.sr_index] = val;
#ifdef DEBUG_CIRRUS
printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
s->vga.sr_index, val);
#endif
break;
case 0x12: // Graphics Cursor Attribute
s->vga.sr[0x12] = val;
s->vga.force_shadow = !!(val & CIRRUS_CURSOR_SHOW);
#ifdef DEBUG_CIRRUS
printf("cirrus: cursor ctl SR12=%02x (force shadow: %d)\n",
val, s->vga.force_shadow);
#endif
break;
case 0x17: // Configuration Readback and Extended Control
s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
| (val & 0xc7);
cirrus_update_memory_access(s);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"cirrus: outport sr_index 0x%02x, sr_value 0x%02x\n",
s->vga.sr_index, val);
break;
}
}
/***************************************
*
* I/O access at 0x3c6
*
***************************************/
diff --git a/hw/display/tcx.c b/hw/display/tcx.c
index 1b27b64f6d..e21450d726 100644
--- a/hw/display/tcx.c
+++ b/hw/display/tcx.c
@@ -381,26 +381,26 @@ static void tcx_reset(DeviceState *d)
static uint64_t tcx_dac_readl(void *opaque, hwaddr addr,
unsigned size)
{
TCXState *s = opaque;
uint32_t val = 0;
switch (s->dac_state) {
case 0:
val = s->r[s->dac_index] << 24;
s->dac_state++;
break;
case 1:
val = s->g[s->dac_index] << 24;
s->dac_state++;
break;
case 2:
val = s->b[s->dac_index] << 24;
s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */
- /* fall through */
+ fallthrough;
default:
s->dac_state = 0;
break;
}
return val;
}
@@ -408,43 +408,43 @@ static uint64_t tcx_dac_readl(void *opaque, hwaddr addr,
static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
TCXState *s = opaque;
unsigned index;
switch (addr) {
case 0: /* Address */
s->dac_index = val >> 24;
s->dac_state = 0;
break;
case 4: /* Pixel colours */
case 12: /* Overlay (cursor) colours */
if (addr & 8) {
index = (s->dac_index & 3) + 256;
} else {
index = s->dac_index;
}
switch (s->dac_state) {
case 0:
s->r[index] = val >> 24;
update_palette_entries(s, index, index + 1);
s->dac_state++;
break;
case 1:
s->g[index] = val >> 24;
update_palette_entries(s, index, index + 1);
s->dac_state++;
break;
case 2:
s->b[index] = val >> 24;
update_palette_entries(s, index, index + 1);
s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */
- /* fall through */
+ fallthrough;
default:
s->dac_state = 0;
break;
}
break;
default: /* Control registers */
break;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 56/78] hw/input: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (54 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 55/78] hw/display: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 57/78] hw/net: " Emmanouil Pitsidianakis
` (22 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Peter Maydell, open list:nSeries
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/input/hid.c | 3 ++-
hw/input/tsc2005.c | 4 ++--
hw/input/tsc210x.c | 2 +-
3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/input/hid.c b/hw/input/hid.c
index a9c7dd1ce1..15fffc5dfb 100644
--- a/hw/input/hid.c
+++ b/hw/input/hid.c
@@ -250,88 +250,89 @@ static void hid_keyboard_event(DeviceState *dev, QemuConsole *src,
static void hid_keyboard_process_keycode(HIDState *hs)
{
uint8_t hid_code, index, key;
int i, keycode, slot;
if (hs->n == 0) {
return;
}
slot = hs->head & QUEUE_MASK; QUEUE_INCR(hs->head); hs->n--;
keycode = hs->kbd.keycodes[slot];
if (!hs->n) {
trace_hid_kbd_queue_empty();
}
key = keycode & 0x7f;
index = key | ((hs->kbd.modifiers & (1 << 8)) >> 1);
hid_code = hid_usage_keys[index];
hs->kbd.modifiers &= ~(1 << 8);
switch (hid_code) {
case 0x00:
return;
case 0xe0:
assert(key == 0x1d);
if (hs->kbd.modifiers & (1 << 9)) {
/* The hid_codes for the 0xe1/0x1d scancode sequence are 0xe9/0xe0.
* Here we're processing the second hid_code. By dropping bit 9
* and setting bit 8, the scancode after 0x1d will access the
* second half of the table.
*/
hs->kbd.modifiers ^= (1 << 8) | (1 << 9);
return;
}
/* fall through to process Ctrl_L */
+ fallthrough;
case 0xe1 ... 0xe7:
/* Ctrl_L/Ctrl_R, Shift_L/Shift_R, Alt_L/Alt_R, Win_L/Win_R.
* Handle releases here, or fall through to process presses.
*/
if (keycode & (1 << 7)) {
hs->kbd.modifiers &= ~(1 << (hid_code & 0x0f));
return;
}
- /* fall through */
+ fallthrough;
case 0xe8 ... 0xe9:
/* USB modifiers are just 1 byte long. Bits 8 and 9 of
* hs->kbd.modifiers implement a state machine that detects the
* 0xe0 and 0xe1/0x1d sequences. These bits do not follow the
* usual rules where bit 7 marks released keys; they are cleared
* elsewhere in the function as the state machine dictates.
*/
hs->kbd.modifiers |= 1 << (hid_code & 0x0f);
return;
case 0xea ... 0xef:
abort();
default:
break;
}
if (keycode & (1 << 7)) {
for (i = hs->kbd.keys - 1; i >= 0; i--) {
if (hs->kbd.key[i] == hid_code) {
hs->kbd.key[i] = hs->kbd.key[-- hs->kbd.keys];
hs->kbd.key[hs->kbd.keys] = 0x00;
break;
}
}
if (i < 0) {
return;
}
} else {
for (i = hs->kbd.keys - 1; i >= 0; i--) {
if (hs->kbd.key[i] == hid_code) {
break;
}
}
if (i < 0) {
if (hs->kbd.keys < sizeof(hs->kbd.key)) {
hs->kbd.key[hs->kbd.keys++] = hid_code;
}
} else {
return;
}
}
}
diff --git a/hw/input/tsc2005.c b/hw/input/tsc2005.c
index db2b80e35f..4f3f1d9d12 100644
--- a/hw/input/tsc2005.c
+++ b/hw/input/tsc2005.c
@@ -234,70 +234,70 @@ static void tsc2005_write(TSC2005State *s, int reg, uint16_t data)
/* This handles most of the chip's logic. */
static void tsc2005_pin_update(TSC2005State *s)
{
int64_t expires;
bool pin_state;
switch (s->pin_func) {
case 0:
pin_state = !s->pressure && !!s->dav;
break;
case 1:
case 3:
default:
pin_state = !s->dav;
break;
case 2:
pin_state = !s->pressure;
}
if (pin_state != s->irq) {
s->irq = pin_state;
qemu_set_irq(s->pint, s->irq);
}
switch (s->nextfunction) {
case TSC_MODE_XYZ_SCAN:
case TSC_MODE_XY_SCAN:
if (!s->host_mode && s->dav)
s->enabled = false;
if (!s->pressure)
return;
- /* Fall through */
+ fallthrough;
case TSC_MODE_AUX_SCAN:
break;
case TSC_MODE_X:
case TSC_MODE_Y:
case TSC_MODE_Z:
if (!s->pressure)
return;
- /* Fall through */
+ fallthrough;
case TSC_MODE_AUX:
case TSC_MODE_TEMP1:
case TSC_MODE_TEMP2:
case TSC_MODE_X_TEST:
case TSC_MODE_Y_TEST:
case TSC_MODE_TS_TEST:
if (s->dav)
s->enabled = false;
break;
case TSC_MODE_RESERVED:
case TSC_MODE_XX_DRV:
case TSC_MODE_YY_DRV:
case TSC_MODE_YX_DRV:
default:
return;
}
if (!s->enabled || s->busy)
return;
s->busy = true;
s->precision = s->nextprecision;
s->function = s->nextfunction;
s->pdst = !s->pnd0; /* Synchronised on internal clock */
expires = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
(NANOSECONDS_PER_SECOND >> 7);
timer_mod(s->timer, expires);
}
diff --git a/hw/input/tsc210x.c b/hw/input/tsc210x.c
index 950506fb38..9ae426e1a6 100644
--- a/hw/input/tsc210x.c
+++ b/hw/input/tsc210x.c
@@ -774,70 +774,70 @@ static void tsc2102_audio_register_write(
/* This handles most of the chip logic. */
static void tsc210x_pin_update(TSC210xState *s)
{
int64_t expires;
bool pin_state;
switch (s->pin_func) {
case 0:
pin_state = s->pressure;
break;
case 1:
pin_state = !!s->dav;
break;
case 2:
default:
pin_state = s->pressure && !s->dav;
}
if (!s->enabled)
pin_state = false;
if (pin_state != s->irq) {
s->irq = pin_state;
qemu_set_irq(s->pint, !s->irq);
}
switch (s->nextfunction) {
case TSC_MODE_XY_SCAN:
case TSC_MODE_XYZ_SCAN:
if (!s->pressure)
return;
break;
case TSC_MODE_X:
case TSC_MODE_Y:
case TSC_MODE_Z:
if (!s->pressure)
return;
- /* Fall through */
+ fallthrough;
case TSC_MODE_BAT1:
case TSC_MODE_BAT2:
case TSC_MODE_AUX:
case TSC_MODE_TEMP1:
case TSC_MODE_TEMP2:
if (s->dav)
s->enabled = false;
break;
case TSC_MODE_AUX_SCAN:
case TSC_MODE_PORT_SCAN:
break;
case TSC_MODE_NO_SCAN:
case TSC_MODE_XX_DRV:
case TSC_MODE_YY_DRV:
case TSC_MODE_YX_DRV:
default:
return;
}
if (!s->enabled || s->busy || s->dav)
return;
s->busy = true;
s->precision = s->nextprecision;
s->function = s->nextfunction;
expires = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
(NANOSECONDS_PER_SECOND >> 10);
timer_mod(s->timer, expires);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 57/78] hw/net: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (55 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 56/78] hw/input: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 58/78] hw/ppc: " Emmanouil Pitsidianakis
` (21 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Edgar E. Iglesias, Alistair Francis,
Peter Maydell, Jason Wang, Pavel Pisa, Vikram Garhwal,
Akihiko Odaki, Sriram Yagnaraman, Dmitry Fleytman,
open list:Xilinx Zynq
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/net/cadence_gem.c | 4 ++--
hw/net/can/can_sja1000.c | 4 ++--
hw/net/igb_core.c | 2 +-
hw/net/igbvf.c | 2 +-
hw/net/imx_fec.c | 2 +-
hw/net/net_rx_pkt.c | 2 +-
hw/net/pcnet.c | 2 +-
hw/net/rtl8139.c | 6 ++++--
hw/net/xilinx_ethlite.c | 2 +-
9 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index f445d8bb5e..a59991af5b 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -748,119 +748,119 @@ static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
/* Figure out which queue the received data should be sent to */
static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
unsigned rxbufsize)
{
uint32_t reg;
bool matched, mismatched;
int i, j;
for (i = 0; i < s->num_type1_screeners; i++) {
reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i];
matched = false;
mismatched = false;
/* Screening is based on UDP Port */
if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) {
uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23];
if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT,
GEM_ST1R_UDP_PORT_MATCH_WIDTH)) {
matched = true;
} else {
mismatched = true;
}
}
/* Screening is based on DS/TC */
if (reg & GEM_ST1R_DSTC_ENABLE) {
uint8_t dscp = rxbuf_ptr[14 + 1];
if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT,
GEM_ST1R_DSTC_MATCH_WIDTH)) {
matched = true;
} else {
mismatched = true;
}
}
if (matched && !mismatched) {
return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH);
}
}
for (i = 0; i < s->num_type2_screeners; i++) {
reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i];
matched = false;
mismatched = false;
if (reg & GEM_ST2R_ETHERTYPE_ENABLE) {
uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13];
int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT,
GEM_ST2R_ETHERTYPE_INDEX_WIDTH);
if (et_idx > s->num_type2_screeners) {
qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype "
"register index: %d\n", et_idx);
}
if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 +
et_idx]) {
matched = true;
} else {
mismatched = true;
}
}
/* Compare A, B, C */
for (j = 0; j < 3; j++) {
uint32_t cr0, cr1, mask;
uint16_t rx_cmp;
int offset;
int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6,
GEM_ST2R_COMPARE_WIDTH);
if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) {
continue;
}
if (cr_idx > s->num_type2_screeners) {
qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare "
"register index: %d\n", cr_idx);
}
cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2];
cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1];
offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT,
GEM_T2CW1_OFFSET_VALUE_WIDTH);
switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT,
GEM_T2CW1_COMPARE_OFFSET_WIDTH)) {
case 3: /* Skip UDP header */
qemu_log_mask(LOG_UNIMP, "TCP compare offsets"
"unimplemented - assuming UDP\n");
offset += 8;
- /* Fallthrough */
+ fallthrough;
case 2: /* skip the IP header */
offset += 20;
- /* Fallthrough */
+ fallthrough;
case 1: /* Count from after the ethertype */
offset += 14;
break;
case 0:
/* Offset from start of frame */
break;
}
rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset];
mask = extract32(cr0, 0, 16);
if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) {
matched = true;
} else {
mismatched = true;
}
}
if (matched && !mismatched) {
return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH);
}
}
/* We made it here, assume it's queue 0 */
return 0;
}
diff --git a/hw/net/can/can_sja1000.c b/hw/net/can/can_sja1000.c
index 73201f9139..14052b2700 100644
--- a/hw/net/can/can_sja1000.c
+++ b/hw/net/can/can_sja1000.c
@@ -422,235 +422,235 @@ static void can_sja_update_bas_irq(CanSJA1000State *s)
void can_sja_mem_write(CanSJA1000State *s, hwaddr addr, uint64_t val,
unsigned size)
{
qemu_can_frame frame;
uint32_t tmp;
uint8_t tmp8, count;
DPRINTF("write 0x%02llx addr 0x%02x\n",
(unsigned long long)val, (unsigned int)addr);
if (addr > CAN_SJA_MEM_SIZE) {
return;
}
if (s->clock & 0x80) { /* PeliCAN Mode */
switch (addr) {
case SJA_MOD: /* Mode register */
s->mode = 0x1f & val;
if ((s->mode & 0x01) && ((val & 0x01) == 0)) {
/* Go to operation mode from reset mode. */
if (s->mode & (1 << 3)) { /* Single mode. */
/* For EFF */
can_sja_single_filter(&s->filter[0],
s->code_mask + 0, s->code_mask + 4, 1);
/* For SFF */
can_sja_single_filter(&s->filter[1],
s->code_mask + 0, s->code_mask + 4, 0);
can_bus_client_set_filters(&s->bus_client, s->filter, 2);
} else { /* Dual mode */
/* For EFF */
can_sja_dual_filter(&s->filter[0],
s->code_mask + 0, s->code_mask + 4, 1);
can_sja_dual_filter(&s->filter[1],
s->code_mask + 2, s->code_mask + 6, 1);
/* For SFF */
can_sja_dual_filter(&s->filter[2],
s->code_mask + 0, s->code_mask + 4, 0);
can_sja_dual_filter(&s->filter[3],
s->code_mask + 2, s->code_mask + 6, 0);
can_bus_client_set_filters(&s->bus_client, s->filter, 4);
}
s->rxmsg_cnt = 0;
s->rx_cnt = 0;
}
break;
case SJA_CMR: /* Command register. */
if (0x01 & val) { /* Send transmission request. */
buff2frame_pel(s->tx_buff, &frame);
if (DEBUG_FILTER) {
can_display_msg("[cansja]: Tx request " , &frame);
}
/*
* Clear transmission complete status,
* and Transmit Buffer Status.
* write to the backends.
*/
s->status_pel &= ~(3 << 2);
can_bus_client_send(&s->bus_client, &frame, 1);
/*
* Set transmission complete status
* and Transmit Buffer Status.
*/
s->status_pel |= (3 << 2);
/* Clear transmit status. */
s->status_pel &= ~(1 << 5);
s->interrupt_pel |= 0x02;
can_sja_update_pel_irq(s);
}
if (0x04 & val) { /* Release Receive Buffer */
if (s->rxmsg_cnt <= 0) {
break;
}
tmp8 = s->rx_buff[s->rxbuf_start]; count = 0;
if (tmp8 & (1 << 7)) { /* EFF */
count += 2;
}
count += 3;
if (!(tmp8 & (1 << 6))) { /* DATA */
count += (tmp8 & 0x0f);
}
if (DEBUG_FILTER) {
qemu_log("[cansja]: message released from "
"Rx FIFO cnt=%d, count=%d\n", s->rx_cnt, count);
}
s->rxbuf_start += count;
s->rxbuf_start %= SJA_RCV_BUF_LEN;
s->rx_cnt -= count;
s->rxmsg_cnt--;
if (s->rxmsg_cnt == 0) {
s->status_pel &= ~(1 << 0);
s->interrupt_pel &= ~(1 << 0);
can_sja_update_pel_irq(s);
}
}
if (0x08 & val) { /* Clear data overrun */
s->status_pel &= ~(1 << 1);
s->interrupt_pel &= ~(1 << 3);
can_sja_update_pel_irq(s);
}
break;
case SJA_SR: /* Status register */
case SJA_IR: /* Interrupt register */
break; /* Do nothing */
case SJA_IER: /* Interrupt enable register */
s->interrupt_en = val;
break;
case 16: /* RX frame information addr16-28. */
s->status_pel |= (1 << 5); /* Set transmit status. */
- /* fallthrough */
+ fallthrough;
case 17 ... 28:
if (s->mode & 0x01) { /* Reset mode */
if (addr < 24) {
s->code_mask[addr - 16] = val;
}
} else { /* Operation mode */
s->tx_buff[addr - 16] = val; /* Store to TX buffer directly. */
}
break;
case SJA_CDR:
s->clock = val;
break;
}
} else { /* Basic Mode */
switch (addr) {
case SJA_BCAN_CTR: /* Control register, addr 0 */
if ((s->control & 0x01) && ((val & 0x01) == 0)) {
/* Go to operation mode from reset mode. */
s->filter[0].can_id = (s->code << 3) & (0xff << 3);
tmp = (~(s->mask << 3)) & (0xff << 3);
tmp |= QEMU_CAN_EFF_FLAG; /* Only Basic CAN Frame. */
s->filter[0].can_mask = tmp;
can_bus_client_set_filters(&s->bus_client, s->filter, 1);
s->rxmsg_cnt = 0;
s->rx_cnt = 0;
} else if (!(s->control & 0x01) && !(val & 0x01)) {
can_sja_software_reset(s);
}
s->control = 0x1f & val;
break;
case SJA_BCAN_CMR: /* Command register, addr 1 */
if (0x01 & val) { /* Send transmission request. */
buff2frame_bas(s->tx_buff, &frame);
if (DEBUG_FILTER) {
can_display_msg("[cansja]: Tx request " , &frame);
}
/*
* Clear transmission complete status,
* and Transmit Buffer Status.
*/
s->status_bas &= ~(3 << 2);
/* write to the backends. */
can_bus_client_send(&s->bus_client, &frame, 1);
/*
* Set transmission complete status,
* and Transmit Buffer Status.
*/
s->status_bas |= (3 << 2);
/* Clear transmit status. */
s->status_bas &= ~(1 << 5);
s->interrupt_bas |= 0x02;
can_sja_update_bas_irq(s);
}
if (0x04 & val) { /* Release Receive Buffer */
if (s->rxmsg_cnt <= 0) {
break;
}
tmp8 = s->rx_buff[(s->rxbuf_start + 1) % SJA_RCV_BUF_LEN];
count = 2 + (tmp8 & 0x0f);
if (DEBUG_FILTER) {
qemu_log("[cansja]: message released from "
"Rx FIFO cnt=%d, count=%d\n", s->rx_cnt, count);
}
s->rxbuf_start += count;
s->rxbuf_start %= SJA_RCV_BUF_LEN;
s->rx_cnt -= count;
s->rxmsg_cnt--;
if (s->rxmsg_cnt == 0) {
s->status_bas &= ~(1 << 0);
s->interrupt_bas &= ~(1 << 0);
can_sja_update_bas_irq(s);
}
}
if (0x08 & val) { /* Clear data overrun */
s->status_bas &= ~(1 << 1);
s->interrupt_bas &= ~(1 << 3);
can_sja_update_bas_irq(s);
}
break;
case 4:
s->code = val;
break;
case 5:
s->mask = val;
break;
case 10:
s->status_bas |= (1 << 5); /* Set transmit status. */
- /* fallthrough */
+ fallthrough;
case 11 ... 19:
if ((s->control & 0x01) == 0) { /* Operation mode */
s->tx_buff[addr - 10] = val; /* Store to TX buffer directly. */
}
break;
case SJA_CDR:
s->clock = val;
break;
}
}
}
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index f6a5e2327b..1117f7cb59 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -1362,75 +1362,75 @@ static void
igb_build_rx_metadata_common(IGBCore *core,
struct NetRxPkt *pkt,
bool is_eop,
uint32_t *status_flags,
uint16_t *vlan_tag)
{
struct virtio_net_hdr *vhdr;
bool hasip4, hasip6, csum_valid;
EthL4HdrProto l4hdr_proto;
*status_flags = E1000_RXD_STAT_DD;
/* No additional metadata needed for non-EOP descriptors */
if (!is_eop) {
goto func_exit;
}
*status_flags |= E1000_RXD_STAT_EOP;
net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto);
/* VLAN state */
if (net_rx_pkt_is_vlan_stripped(pkt)) {
*status_flags |= E1000_RXD_STAT_VP;
*vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt));
trace_e1000e_rx_metadata_vlan(*vlan_tag);
}
/* RX CSO information */
if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) {
trace_e1000e_rx_metadata_ipv6_sum_disabled();
goto func_exit;
}
vhdr = net_rx_pkt_get_vhdr(pkt);
if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) &&
!(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
trace_e1000e_rx_metadata_virthdr_no_csum_info();
igb_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto);
goto func_exit;
}
if (igb_rx_l3_cso_enabled(core)) {
*status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0;
} else {
trace_e1000e_rx_metadata_l3_cso_disabled();
}
if (igb_rx_l4_cso_enabled(core)) {
switch (l4hdr_proto) {
case ETH_L4_HDR_PROTO_SCTP:
if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) {
trace_e1000e_rx_metadata_l4_csum_validation_failed();
goto func_exit;
}
if (!csum_valid) {
*status_flags |= E1000_RXDEXT_STATERR_TCPE;
}
- /* fall through */
+ fallthrough;
case ETH_L4_HDR_PROTO_TCP:
*status_flags |= E1000_RXD_STAT_TCPCS;
break;
case ETH_L4_HDR_PROTO_UDP:
*status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS;
break;
default:
break;
}
} else {
trace_e1000e_rx_metadata_l4_cso_disabled();
}
diff --git a/hw/net/igbvf.c b/hw/net/igbvf.c
index d55e1e8a6a..ff68a4f3c5 100644
--- a/hw/net/igbvf.c
+++ b/hw/net/igbvf.c
@@ -62,139 +62,139 @@ struct IgbVfState {
static hwaddr vf_to_pf_addr(hwaddr addr, uint16_t vfn, bool write)
{
switch (addr) {
case E1000_CTRL:
case E1000_CTRL_DUP:
return E1000_PVTCTRL(vfn);
case E1000_EICS:
return E1000_PVTEICS(vfn);
case E1000_EIMS:
return E1000_PVTEIMS(vfn);
case E1000_EIMC:
return E1000_PVTEIMC(vfn);
case E1000_EIAC:
return E1000_PVTEIAC(vfn);
case E1000_EIAM:
return E1000_PVTEIAM(vfn);
case E1000_EICR:
return E1000_PVTEICR(vfn);
case E1000_EITR(0):
case E1000_EITR(1):
case E1000_EITR(2):
return E1000_EITR(22) + (addr - E1000_EITR(0)) - vfn * 0xC;
case E1000_IVAR0:
return E1000_VTIVAR + vfn * 4;
case E1000_IVAR_MISC:
return E1000_VTIVAR_MISC + vfn * 4;
case 0x0F04: /* PBACL */
return E1000_PBACLR;
case 0x0F0C: /* PSRTYPE */
return E1000_PSRTYPE(vfn);
case E1000_V2PMAILBOX(0):
return E1000_V2PMAILBOX(vfn);
case E1000_VMBMEM(0) ... E1000_VMBMEM(0) + 0x3F:
return addr + vfn * 0x40;
case E1000_RDBAL_A(0):
return E1000_RDBAL(vfn);
case E1000_RDBAL_A(1):
return E1000_RDBAL(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_RDBAH_A(0):
return E1000_RDBAH(vfn);
case E1000_RDBAH_A(1):
return E1000_RDBAH(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_RDLEN_A(0):
return E1000_RDLEN(vfn);
case E1000_RDLEN_A(1):
return E1000_RDLEN(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_SRRCTL_A(0):
return E1000_SRRCTL(vfn);
case E1000_SRRCTL_A(1):
return E1000_SRRCTL(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_RDH_A(0):
return E1000_RDH(vfn);
case E1000_RDH_A(1):
return E1000_RDH(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_RXCTL_A(0):
return E1000_RXCTL(vfn);
case E1000_RXCTL_A(1):
return E1000_RXCTL(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_RDT_A(0):
return E1000_RDT(vfn);
case E1000_RDT_A(1):
return E1000_RDT(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_RXDCTL_A(0):
return E1000_RXDCTL(vfn);
case E1000_RXDCTL_A(1):
return E1000_RXDCTL(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_RQDPC_A(0):
return E1000_RQDPC(vfn);
case E1000_RQDPC_A(1):
return E1000_RQDPC(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_TDBAL_A(0):
return E1000_TDBAL(vfn);
case E1000_TDBAL_A(1):
return E1000_TDBAL(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_TDBAH_A(0):
return E1000_TDBAH(vfn);
case E1000_TDBAH_A(1):
return E1000_TDBAH(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_TDLEN_A(0):
return E1000_TDLEN(vfn);
case E1000_TDLEN_A(1):
return E1000_TDLEN(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_TDH_A(0):
return E1000_TDH(vfn);
case E1000_TDH_A(1):
return E1000_TDH(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_TXCTL_A(0):
return E1000_TXCTL(vfn);
case E1000_TXCTL_A(1):
return E1000_TXCTL(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_TDT_A(0):
return E1000_TDT(vfn);
case E1000_TDT_A(1):
return E1000_TDT(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_TXDCTL_A(0):
return E1000_TXDCTL(vfn);
case E1000_TXDCTL_A(1):
return E1000_TXDCTL(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_TDWBAL_A(0):
return E1000_TDWBAL(vfn);
case E1000_TDWBAL_A(1):
return E1000_TDWBAL(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_TDWBAH_A(0):
return E1000_TDWBAH(vfn);
case E1000_TDWBAH_A(1):
return E1000_TDWBAH(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_VFGPRC:
return E1000_PVFGPRC(vfn);
case E1000_VFGPTC:
return E1000_PVFGPTC(vfn);
case E1000_VFGORC:
return E1000_PVFGORC(vfn);
case E1000_VFGOTC:
return E1000_PVFGOTC(vfn);
case E1000_VFMPRC:
return E1000_PVFMPRC(vfn);
case E1000_VFGPRLBC:
return E1000_PVFGPRLBC(vfn);
case E1000_VFGPTLBC:
return E1000_PVFGPTLBC(vfn);
case E1000_VFGORLBC:
return E1000_PVFGORLBC(vfn);
case E1000_VFGOTLBC:
return E1000_PVFGOTLBC(vfn);
case E1000_STATUS:
case E1000_FRTIMER:
if (write) {
return HWADDR_MAX;
}
- /* fallthrough */
+ fallthrough;
case 0x34E8: /* PBTWAC */
case 0x24E8: /* PBRWAC */
return addr;
}
trace_igbvf_wrn_io_addr_unknown(addr);
return HWADDR_MAX;
}
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index 5d1f1f104c..a7e8b06d48 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -888,170 +888,170 @@ static void imx_enet_write(IMXFECState *s, uint32_t index, uint32_t value)
static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
IMXFECState *s = IMX_FEC(opaque);
const bool single_tx_ring = !imx_eth_is_multi_tx_ring(s);
uint32_t index = offset >> 2;
trace_imx_eth_write(index, imx_eth_reg_name(s, index), value);
switch (index) {
case ENET_EIR:
s->regs[index] &= ~value;
break;
case ENET_EIMR:
s->regs[index] = value;
break;
case ENET_RDAR:
if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) {
if (!s->regs[index]) {
imx_eth_enable_rx(s, true);
}
} else {
s->regs[index] = 0;
}
break;
case ENET_TDAR1:
case ENET_TDAR2:
if (unlikely(single_tx_ring)) {
qemu_log_mask(LOG_GUEST_ERROR,
"[%s]%s: trying to access TDAR2 or TDAR1\n",
TYPE_IMX_FEC, __func__);
return;
}
- /* fall through */
+ fallthrough;
case ENET_TDAR:
if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) {
s->regs[index] = ENET_TDAR_TDAR;
imx_eth_do_tx(s, index);
}
s->regs[index] = 0;
break;
case ENET_ECR:
if (value & ENET_ECR_RESET) {
return imx_eth_reset(DEVICE(s));
}
s->regs[index] = value;
if ((s->regs[index] & ENET_ECR_ETHEREN) == 0) {
s->regs[ENET_RDAR] = 0;
s->rx_descriptor = s->regs[ENET_RDSR];
s->regs[ENET_TDAR] = 0;
s->regs[ENET_TDAR1] = 0;
s->regs[ENET_TDAR2] = 0;
s->tx_descriptor[0] = s->regs[ENET_TDSR];
s->tx_descriptor[1] = s->regs[ENET_TDSR1];
s->tx_descriptor[2] = s->regs[ENET_TDSR2];
}
break;
case ENET_MMFR:
s->regs[index] = value;
if (extract32(value, 29, 1)) {
/* This is a read operation */
s->regs[ENET_MMFR] = deposit32(s->regs[ENET_MMFR], 0, 16,
imx_phy_read(s,
extract32(value,
18, 10)));
} else {
/* This is a write operation */
imx_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16));
}
/* raise the interrupt as the PHY operation is done */
s->regs[ENET_EIR] |= ENET_INT_MII;
break;
case ENET_MSCR:
s->regs[index] = value & 0xfe;
break;
case ENET_MIBC:
/* TODO: Implement MIB. */
s->regs[index] = (value & 0x80000000) ? 0xc0000000 : 0;
break;
case ENET_RCR:
s->regs[index] = value & 0x07ff003f;
/* TODO: Implement LOOP mode. */
break;
case ENET_TCR:
/* We transmit immediately, so raise GRA immediately. */
s->regs[index] = value;
if (value & 1) {
s->regs[ENET_EIR] |= ENET_INT_GRA;
}
break;
case ENET_PALR:
s->regs[index] = value;
s->conf.macaddr.a[0] = value >> 24;
s->conf.macaddr.a[1] = value >> 16;
s->conf.macaddr.a[2] = value >> 8;
s->conf.macaddr.a[3] = value;
break;
case ENET_PAUR:
s->regs[index] = (value | 0x0000ffff) & 0xffff8808;
s->conf.macaddr.a[4] = value >> 24;
s->conf.macaddr.a[5] = value >> 16;
break;
case ENET_OPD:
s->regs[index] = (value & 0x0000ffff) | 0x00010000;
break;
case ENET_IAUR:
case ENET_IALR:
case ENET_GAUR:
case ENET_GALR:
/* TODO: implement MAC hash filtering. */
break;
case ENET_TFWR:
if (s->is_fec) {
s->regs[index] = value & 0x3;
} else {
s->regs[index] = value & 0x13f;
}
break;
case ENET_RDSR:
if (s->is_fec) {
s->regs[index] = value & ~3;
} else {
s->regs[index] = value & ~7;
}
s->rx_descriptor = s->regs[index];
break;
case ENET_TDSR:
if (s->is_fec) {
s->regs[index] = value & ~3;
} else {
s->regs[index] = value & ~7;
}
s->tx_descriptor[0] = s->regs[index];
break;
case ENET_TDSR1:
if (unlikely(single_tx_ring)) {
qemu_log_mask(LOG_GUEST_ERROR,
"[%s]%s: trying to access TDSR1\n",
TYPE_IMX_FEC, __func__);
return;
}
s->regs[index] = value & ~7;
s->tx_descriptor[1] = s->regs[index];
break;
case ENET_TDSR2:
if (unlikely(single_tx_ring)) {
qemu_log_mask(LOG_GUEST_ERROR,
"[%s]%s: trying to access TDSR2\n",
TYPE_IMX_FEC, __func__);
return;
}
s->regs[index] = value & ~7;
s->tx_descriptor[2] = s->regs[index];
break;
case ENET_MRBR:
s->regs[index] = value & 0x00003ff0;
break;
default:
if (s->is_fec) {
imx_fec_write(s, index, value);
} else {
imx_enet_write(s, index, value);
}
return;
}
imx_eth_update(s);
}
diff --git a/hw/net/net_rx_pkt.c b/hw/net/net_rx_pkt.c
index 32e5f3f9cf..52e2432c9b 100644
--- a/hw/net/net_rx_pkt.c
+++ b/hw/net/net_rx_pkt.c
@@ -591,36 +591,36 @@ _net_rx_pkt_validate_sctp_sum(struct NetRxPkt *pkt)
bool net_rx_pkt_validate_l4_csum(struct NetRxPkt *pkt, bool *csum_valid)
{
uint32_t csum;
trace_net_rx_pkt_l4_csum_validate_entry();
if (pkt->hasip4 && pkt->ip4hdr_info.fragment) {
trace_net_rx_pkt_l4_csum_validate_ip4_fragment();
return false;
}
switch (pkt->l4hdr_info.proto) {
case ETH_L4_HDR_PROTO_UDP:
if (pkt->l4hdr_info.hdr.udp.uh_sum == 0) {
trace_net_rx_pkt_l4_csum_validate_udp_with_no_checksum();
return false;
}
- /* fall through */
+ fallthrough;
case ETH_L4_HDR_PROTO_TCP:
csum = _net_rx_pkt_calc_l4_csum(pkt);
*csum_valid = ((csum == 0) || (csum == 0xFFFF));
break;
case ETH_L4_HDR_PROTO_SCTP:
*csum_valid = _net_rx_pkt_validate_sctp_sum(pkt);
break;
default:
trace_net_rx_pkt_l4_csum_validate_not_xxp();
return false;
}
trace_net_rx_pkt_l4_csum_validate_csum(*csum_valid);
return true;
}
diff --git a/hw/net/pcnet.c b/hw/net/pcnet.c
index 02828ae716..a32174ef93 100644
--- a/hw/net/pcnet.c
+++ b/hw/net/pcnet.c
@@ -1474,47 +1474,47 @@ static uint32_t pcnet_csr_readw(PCNetState *s, uint32_t rap)
static void pcnet_bcr_writew(PCNetState *s, uint32_t rap, uint32_t val)
{
rap &= 127;
#ifdef PCNET_DEBUG_BCR
printf("pcnet_bcr_writew rap=%d val=0x%04x\n", rap, val);
#endif
switch (rap) {
case BCR_SWS:
if (!(CSR_STOP(s) || CSR_SPND(s)))
return;
val &= ~0x0300;
switch (val & 0x00ff) {
case 0:
val |= 0x0200;
break;
case 1:
val |= 0x0100;
break;
case 2:
case 3:
val |= 0x0300;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "pcnet: Bad SWSTYLE=0x%02x\n",
val & 0xff);
val = 0x0200;
break;
}
#ifdef PCNET_DEBUG
printf("BCR_SWS=0x%04x\n", val);
#endif
- /* fall through */
+ fallthrough;
case BCR_LNKST:
case BCR_LED1:
case BCR_LED2:
case BCR_LED3:
case BCR_MC:
case BCR_FDC:
case BCR_BSBC:
case BCR_EECAS:
case BCR_PLAT:
s->bcr[rap] = val;
break;
default:
break;
}
}
diff --git a/hw/net/rtl8139.c b/hw/net/rtl8139.c
index 4525fda383..42f19618b1 100644
--- a/hw/net/rtl8139.c
+++ b/hw/net/rtl8139.c
@@ -2435,29 +2435,31 @@ static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32
static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[],
uint32_t base, uint8_t addr,
int size)
{
uint32_t reg = (addr - base) / 4;
uint32_t offset = addr & 0x3;
uint32_t ret = 0;
if (addr & (size - 1)) {
DPRINTF("not implemented read for TxStatus/TxAddr "
"addr=0x%x size=0x%x\n", addr, size);
return ret;
}
switch (size) {
- case 1: /* fall through */
- case 2: /* fall through */
+ case 1:
+ fallthrough;
+ case 2:
+ fallthrough;
case 4:
ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1);
DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n",
reg, addr, size, ret);
break;
default:
DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size);
break;
}
return ret;
}
diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index 89f4f3b254..5ae4032ec2 100644
--- a/hw/net/xilinx_ethlite.c
+++ b/hw/net/xilinx_ethlite.c
@@ -113,55 +113,55 @@ static void
eth_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct xlx_ethlite *s = opaque;
unsigned int base = 0;
uint32_t value = val64;
addr >>= 2;
switch (addr)
{
case R_TX_CTRL0:
case R_TX_CTRL1:
if (addr == R_TX_CTRL1)
base = 0x800 / 4;
D(qemu_log("%s addr=" HWADDR_FMT_plx " val=%x\n",
__func__, addr * 4, value));
if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
qemu_send_packet(qemu_get_queue(s->nic),
(void *) &s->regs[base],
s->regs[base + R_TX_LEN0]);
D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0]));
if (s->regs[base + R_TX_CTRL0] & CTRL_I)
eth_pulse_irq(s);
} else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) {
memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6);
if (s->regs[base + R_TX_CTRL0] & CTRL_I)
eth_pulse_irq(s);
}
/* We are fast and get ready pretty much immediately so
we actually never flip the S nor P bits to one. */
s->regs[addr] = value & ~(CTRL_P | CTRL_S);
break;
/* Keep these native. */
case R_RX_CTRL0:
case R_RX_CTRL1:
if (!(value & CTRL_S)) {
qemu_flush_queued_packets(qemu_get_queue(s->nic));
}
- /* fall through */
+ fallthrough;
case R_TX_LEN0:
case R_TX_LEN1:
case R_TX_GIE0:
D(qemu_log("%s addr=" HWADDR_FMT_plx " val=%x\n",
__func__, addr * 4, value));
s->regs[addr] = value;
break;
default:
s->regs[addr] = tswap32(value);
break;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 58/78] hw/ppc: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (56 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 57/78] hw/net: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 8:32 ` Harsh Prateek Bora
2023-10-13 7:57 ` [RFC PATCH v2 59/78] hw/intc: " Emmanouil Pitsidianakis
` (20 subsequent siblings)
78 siblings, 1 reply; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Cédric Le Goater, Nicholas Piggin,
Frédéric Barrat, Daniel Henrique Barboza, David Gibson,
Harsh Prateek Bora
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/ppc/pnv_bmc.c | 2 +-
hw/ppc/spapr_events.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv_bmc.c b/hw/ppc/pnv_bmc.c
index 99f1e8d7f9..9bff7d03cb 100644
--- a/hw/ppc/pnv_bmc.c
+++ b/hw/ppc/pnv_bmc.c
@@ -172,69 +172,69 @@ static int hiomap_erase(PnvPnor *pnor, uint32_t offset, uint32_t size)
static void hiomap_cmd(IPMIBmcSim *ibs, uint8_t *cmd, unsigned int cmd_len,
RspBuffer *rsp)
{
PnvPnor *pnor = PNV_PNOR(object_property_get_link(OBJECT(ibs), "pnor",
&error_abort));
uint32_t pnor_size = pnor->size;
uint32_t pnor_addr = PNOR_SPI_OFFSET;
bool readonly = false;
rsp_buffer_push(rsp, cmd[2]);
rsp_buffer_push(rsp, cmd[3]);
switch (cmd[2]) {
case HIOMAP_C_MARK_DIRTY:
case HIOMAP_C_FLUSH:
case HIOMAP_C_ACK:
break;
case HIOMAP_C_ERASE:
if (hiomap_erase(pnor, blocks_to_bytes(cmd[5] << 8 | cmd[4]),
blocks_to_bytes(cmd[7] << 8 | cmd[6]))) {
rsp_buffer_set_error(rsp, IPMI_CC_UNSPECIFIED);
}
break;
case HIOMAP_C_GET_INFO:
rsp_buffer_push(rsp, 2); /* Version 2 */
rsp_buffer_push(rsp, BLOCK_SHIFT); /* block size */
rsp_buffer_push(rsp, 0); /* Timeout */
rsp_buffer_push(rsp, 0); /* Timeout */
break;
case HIOMAP_C_GET_FLASH_INFO:
rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) & 0xFF);
rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) >> 8);
rsp_buffer_push(rsp, 0x01); /* erase size */
rsp_buffer_push(rsp, 0x00); /* erase size */
break;
case HIOMAP_C_CREATE_READ_WINDOW:
readonly = true;
- /* Fall through */
+ fallthrough;
case HIOMAP_C_CREATE_WRITE_WINDOW:
memory_region_set_readonly(&pnor->mmio, readonly);
memory_region_set_enabled(&pnor->mmio, true);
rsp_buffer_push(rsp, bytes_to_blocks(pnor_addr) & 0xFF);
rsp_buffer_push(rsp, bytes_to_blocks(pnor_addr) >> 8);
rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) & 0xFF);
rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) >> 8);
rsp_buffer_push(rsp, 0x00); /* offset */
rsp_buffer_push(rsp, 0x00); /* offset */
break;
case HIOMAP_C_CLOSE_WINDOW:
memory_region_set_enabled(&pnor->mmio, false);
break;
case HIOMAP_C_DEVICE_NAME:
case HIOMAP_C_RESET:
case HIOMAP_C_LOCK:
default:
qemu_log_mask(LOG_GUEST_ERROR, "HIOMAP: unknown command %02X\n", cmd[2]);
break;
}
}
#define HIOMAP 0x5a
diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c
index 4508e40814..9d51746daf 100644
--- a/hw/ppc/spapr_events.c
+++ b/hw/ppc/spapr_events.c
@@ -411,25 +411,26 @@ static const SpaprEventSource *
rtas_event_log_to_source(SpaprMachineState *spapr, int log_type)
{
const SpaprEventSource *source;
g_assert(spapr->event_sources);
switch (log_type) {
case RTAS_LOG_TYPE_HOTPLUG:
source = spapr_event_sources_get_source(spapr->event_sources,
EVENT_CLASS_HOT_PLUG);
if (spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT)) {
g_assert(source->enabled);
break;
}
/* fall through back to epow for legacy hotplug interrupt source */
+ fallthrough;
case RTAS_LOG_TYPE_EPOW:
source = spapr_event_sources_get_source(spapr->event_sources,
EVENT_CLASS_EPOW);
break;
default:
source = NULL;
}
return source;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* Re: [RFC PATCH v2 58/78] hw/ppc: add fallthrough pseudo-keyword
2023-10-13 7:57 ` [RFC PATCH v2 58/78] hw/ppc: " Emmanouil Pitsidianakis
@ 2023-10-13 8:32 ` Harsh Prateek Bora
2023-10-13 9:40 ` Cédric Le Goater
0 siblings, 1 reply; 91+ messages in thread
From: Harsh Prateek Bora @ 2023-10-13 8:32 UTC (permalink / raw)
To: Emmanouil Pitsidianakis, qemu-devel
Cc: Cédric Le Goater, Nicholas Piggin, Frédéric Barrat,
Daniel Henrique Barboza, David Gibson
On 10/13/23 13:27, Emmanouil Pitsidianakis wrote:
> In preparation of raising -Wimplicit-fallthrough to 5, replace all
> fall-through comments with the fallthrough attribute pseudo-keyword.
>
> Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
One question below, may be Cedric knows better who introduced initial code.
> ---
> hw/ppc/pnv_bmc.c | 2 +-
> hw/ppc/spapr_events.c | 1 +
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/ppc/pnv_bmc.c b/hw/ppc/pnv_bmc.c
> index 99f1e8d7f9..9bff7d03cb 100644
> --- a/hw/ppc/pnv_bmc.c
> +++ b/hw/ppc/pnv_bmc.c
> @@ -172,69 +172,69 @@ static int hiomap_erase(PnvPnor *pnor, uint32_t offset, uint32_t size)
> static void hiomap_cmd(IPMIBmcSim *ibs, uint8_t *cmd, unsigned int cmd_len,
> RspBuffer *rsp)
> {
> PnvPnor *pnor = PNV_PNOR(object_property_get_link(OBJECT(ibs), "pnor",
> &error_abort));
> uint32_t pnor_size = pnor->size;
> uint32_t pnor_addr = PNOR_SPI_OFFSET;
> bool readonly = false;
>
> rsp_buffer_push(rsp, cmd[2]);
> rsp_buffer_push(rsp, cmd[3]);
>
> switch (cmd[2]) {
> case HIOMAP_C_MARK_DIRTY:
> case HIOMAP_C_FLUSH:
> case HIOMAP_C_ACK:
> break;
>
> case HIOMAP_C_ERASE:
> if (hiomap_erase(pnor, blocks_to_bytes(cmd[5] << 8 | cmd[4]),
> blocks_to_bytes(cmd[7] << 8 | cmd[6]))) {
> rsp_buffer_set_error(rsp, IPMI_CC_UNSPECIFIED);
> }
> break;
>
> case HIOMAP_C_GET_INFO:
> rsp_buffer_push(rsp, 2); /* Version 2 */
> rsp_buffer_push(rsp, BLOCK_SHIFT); /* block size */
> rsp_buffer_push(rsp, 0); /* Timeout */
> rsp_buffer_push(rsp, 0); /* Timeout */
> break;
>
> case HIOMAP_C_GET_FLASH_INFO:
> rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) & 0xFF);
> rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) >> 8);
> rsp_buffer_push(rsp, 0x01); /* erase size */
> rsp_buffer_push(rsp, 0x00); /* erase size */
> break;
>
> case HIOMAP_C_CREATE_READ_WINDOW:
> readonly = true;
> - /* Fall through */
> + fallthrough;
>
> case HIOMAP_C_CREATE_WRITE_WINDOW:
> memory_region_set_readonly(&pnor->mmio, readonly);
> memory_region_set_enabled(&pnor->mmio, true);
>
> rsp_buffer_push(rsp, bytes_to_blocks(pnor_addr) & 0xFF);
> rsp_buffer_push(rsp, bytes_to_blocks(pnor_addr) >> 8);
> rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) & 0xFF);
> rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) >> 8);
> rsp_buffer_push(rsp, 0x00); /* offset */
> rsp_buffer_push(rsp, 0x00); /* offset */
> break;
>
> case HIOMAP_C_CLOSE_WINDOW:
> memory_region_set_enabled(&pnor->mmio, false);
> break;
>
> case HIOMAP_C_DEVICE_NAME:
> case HIOMAP_C_RESET:
> case HIOMAP_C_LOCK:
Do we need a break here ?
Otherwise above 3 case statements doesnt add any value.
> default:
> qemu_log_mask(LOG_GUEST_ERROR, "HIOMAP: unknown command %02X\n", cmd[2]);
> break;
> }
> }
>
> #define HIOMAP 0x5a
> diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c
> index 4508e40814..9d51746daf 100644
> --- a/hw/ppc/spapr_events.c
> +++ b/hw/ppc/spapr_events.c
> @@ -411,25 +411,26 @@ static const SpaprEventSource *
> rtas_event_log_to_source(SpaprMachineState *spapr, int log_type)
> {
> const SpaprEventSource *source;
>
> g_assert(spapr->event_sources);
>
> switch (log_type) {
> case RTAS_LOG_TYPE_HOTPLUG:
> source = spapr_event_sources_get_source(spapr->event_sources,
> EVENT_CLASS_HOT_PLUG);
> if (spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT)) {
> g_assert(source->enabled);
> break;
> }
> /* fall through back to epow for legacy hotplug interrupt source */
> + fallthrough;
> case RTAS_LOG_TYPE_EPOW:
> source = spapr_event_sources_get_source(spapr->event_sources,
> EVENT_CLASS_EPOW);
> break;
> default:
> source = NULL;
> }
>
> return source;
> }
^ permalink raw reply [flat|nested] 91+ messages in thread* Re: [RFC PATCH v2 58/78] hw/ppc: add fallthrough pseudo-keyword
2023-10-13 8:32 ` Harsh Prateek Bora
@ 2023-10-13 9:40 ` Cédric Le Goater
0 siblings, 0 replies; 91+ messages in thread
From: Cédric Le Goater @ 2023-10-13 9:40 UTC (permalink / raw)
To: Harsh Prateek Bora, Emmanouil Pitsidianakis, qemu-devel
Cc: Nicholas Piggin, Frédéric Barrat,
Daniel Henrique Barboza, David Gibson
On 10/13/23 10:32, Harsh Prateek Bora wrote:
>
>
> On 10/13/23 13:27, Emmanouil Pitsidianakis wrote:
>> In preparation of raising -Wimplicit-fallthrough to 5, replace all
>> fall-through comments with the fallthrough attribute pseudo-keyword.
>>
>> Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
>
> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
>
> One question below, may be Cedric knows better who introduced initial code.
>
>> ---
>> hw/ppc/pnv_bmc.c | 2 +-
>> hw/ppc/spapr_events.c | 1 +
>> 2 files changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/ppc/pnv_bmc.c b/hw/ppc/pnv_bmc.c
>> index 99f1e8d7f9..9bff7d03cb 100644
>> --- a/hw/ppc/pnv_bmc.c
>> +++ b/hw/ppc/pnv_bmc.c
>> @@ -172,69 +172,69 @@ static int hiomap_erase(PnvPnor *pnor, uint32_t offset, uint32_t size)
>> static void hiomap_cmd(IPMIBmcSim *ibs, uint8_t *cmd, unsigned int cmd_len,
>> RspBuffer *rsp)
>> {
>> PnvPnor *pnor = PNV_PNOR(object_property_get_link(OBJECT(ibs), "pnor",
>> &error_abort));
>> uint32_t pnor_size = pnor->size;
>> uint32_t pnor_addr = PNOR_SPI_OFFSET;
>> bool readonly = false;
>> rsp_buffer_push(rsp, cmd[2]);
>> rsp_buffer_push(rsp, cmd[3]);
>> switch (cmd[2]) {
>> case HIOMAP_C_MARK_DIRTY:
>> case HIOMAP_C_FLUSH:
>> case HIOMAP_C_ACK:
>> break;
>> case HIOMAP_C_ERASE:
>> if (hiomap_erase(pnor, blocks_to_bytes(cmd[5] << 8 | cmd[4]),
>> blocks_to_bytes(cmd[7] << 8 | cmd[6]))) {
>> rsp_buffer_set_error(rsp, IPMI_CC_UNSPECIFIED);
>> }
>> break;
>> case HIOMAP_C_GET_INFO:
>> rsp_buffer_push(rsp, 2); /* Version 2 */
>> rsp_buffer_push(rsp, BLOCK_SHIFT); /* block size */
>> rsp_buffer_push(rsp, 0); /* Timeout */
>> rsp_buffer_push(rsp, 0); /* Timeout */
>> break;
>> case HIOMAP_C_GET_FLASH_INFO:
>> rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) & 0xFF);
>> rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) >> 8);
>> rsp_buffer_push(rsp, 0x01); /* erase size */
>> rsp_buffer_push(rsp, 0x00); /* erase size */
>> break;
>> case HIOMAP_C_CREATE_READ_WINDOW:
>> readonly = true;
>> - /* Fall through */
>> + fallthrough;
>> case HIOMAP_C_CREATE_WRITE_WINDOW:
>> memory_region_set_readonly(&pnor->mmio, readonly);
>> memory_region_set_enabled(&pnor->mmio, true);
>> rsp_buffer_push(rsp, bytes_to_blocks(pnor_addr) & 0xFF);
>> rsp_buffer_push(rsp, bytes_to_blocks(pnor_addr) >> 8);
>> rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) & 0xFF);
>> rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) >> 8);
>> rsp_buffer_push(rsp, 0x00); /* offset */
>> rsp_buffer_push(rsp, 0x00); /* offset */
>> break;
>> case HIOMAP_C_CLOSE_WINDOW:
>> memory_region_set_enabled(&pnor->mmio, false);
>> break;
>> case HIOMAP_C_DEVICE_NAME:
>> case HIOMAP_C_RESET:
>> case HIOMAP_C_LOCK:
>
> Do we need a break here ?
> Otherwise above 3 case statements doesnt add any value.
Indeed. These came from ca661fae81d3 ("ppc/pnv: Add HIOMAP commands").
The RESET command is implemented in skiboot. DEVICE_NAME and LOCK
seem not. Something to check.
Thanks,
C.
>
>> default:
>> qemu_log_mask(LOG_GUEST_ERROR, "HIOMAP: unknown command %02X\n", cmd[2]);
>> break;
>> }
>> }
>> #define HIOMAP 0x5a
>> diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c
>> index 4508e40814..9d51746daf 100644
>> --- a/hw/ppc/spapr_events.c
>> +++ b/hw/ppc/spapr_events.c
>> @@ -411,25 +411,26 @@ static const SpaprEventSource *
>> rtas_event_log_to_source(SpaprMachineState *spapr, int log_type)
>> {
>> const SpaprEventSource *source;
>> g_assert(spapr->event_sources);
>> switch (log_type) {
>> case RTAS_LOG_TYPE_HOTPLUG:
>> source = spapr_event_sources_get_source(spapr->event_sources,
>> EVENT_CLASS_HOT_PLUG);
>> if (spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT)) {
>> g_assert(source->enabled);
>> break;
>> }
>> /* fall through back to epow for legacy hotplug interrupt source */
>> + fallthrough;
>> case RTAS_LOG_TYPE_EPOW:
>> source = spapr_event_sources_get_source(spapr->event_sources,
>> EVENT_CLASS_EPOW);
>> break;
>> default:
>> source = NULL;
>> }
>> return source;
>> }
^ permalink raw reply [flat|nested] 91+ messages in thread
* [RFC PATCH v2 59/78] hw/intc: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (57 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 58/78] hw/ppc: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 60/78] qga: " Emmanouil Pitsidianakis
` (19 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Michael S. Tsirkin, Paolo Bonzini,
Peter Maydell, Edgar E. Iglesias, Alistair Francis,
open list:ARM cores
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/intc/apic.c | 2 +-
hw/intc/arm_gicv3_kvm.c | 16 ++++++++--------
hw/intc/armv7m_nvic.c | 12 ++++++------
hw/intc/xilinx_intc.c | 2 +-
4 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index ac3d47d231..30f341c722 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@ -172,21 +172,21 @@ static void apic_local_deliver(APICCommonState *s, int vector)
void apic_deliver_pic_intr(DeviceState *dev, int level)
{
APICCommonState *s = APIC(dev);
if (level) {
apic_local_deliver(s, APIC_LVT_LINT0);
} else {
uint32_t lvt = s->lvt[APIC_LVT_LINT0];
switch ((lvt >> 8) & 7) {
case APIC_DM_FIXED:
if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
break;
apic_reset_bit(s->irr, lvt & 0xff);
- /* fall through */
+ fallthrough;
case APIC_DM_EXTINT:
apic_update_irq(s);
break;
}
}
}
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index 72ad916d3d..782cef3390 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -323,186 +323,186 @@ static void kvm_arm_gicv3_check(GICv3State *s)
static void kvm_arm_gicv3_put(GICv3State *s)
{
uint32_t regl, regh, reg;
uint64_t reg64, redist_typer;
int ncpu, i;
kvm_arm_gicv3_check(s);
kvm_gicr_access(s, GICR_TYPER, 0, ®l, false);
kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false);
redist_typer = ((uint64_t)regh << 32) | regl;
reg = s->gicd_ctlr;
kvm_gicd_access(s, GICD_CTLR, ®, true);
if (redist_typer & GICR_TYPER_PLPIS) {
/*
* Restore base addresses before LPIs are potentially enabled by
* GICR_CTLR write
*/
for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
GICv3CPUState *c = &s->cpu[ncpu];
reg64 = c->gicr_propbaser;
regl = (uint32_t)reg64;
kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, true);
regh = (uint32_t)(reg64 >> 32);
kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, true);
reg64 = c->gicr_pendbaser;
regl = (uint32_t)reg64;
kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, true);
regh = (uint32_t)(reg64 >> 32);
kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, true);
}
}
/* Redistributor state (one per CPU) */
for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
GICv3CPUState *c = &s->cpu[ncpu];
reg = c->gicr_ctlr;
kvm_gicr_access(s, GICR_CTLR, ncpu, ®, true);
reg = c->gicr_statusr[GICV3_NS];
kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, true);
reg = c->gicr_waker;
kvm_gicr_access(s, GICR_WAKER, ncpu, ®, true);
reg = c->gicr_igroupr0;
kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, true);
reg = ~0;
kvm_gicr_access(s, GICR_ICENABLER0, ncpu, ®, true);
reg = c->gicr_ienabler0;
kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, true);
/* Restore config before pending so we treat level/edge correctly */
reg = half_shuffle32(c->edge_trigger >> 16) << 1;
kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, true);
reg = c->level;
kvm_gic_line_level_access(s, 0, ncpu, ®, true);
reg = ~0;
kvm_gicr_access(s, GICR_ICPENDR0, ncpu, ®, true);
reg = c->gicr_ipendr0;
kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, true);
reg = ~0;
kvm_gicr_access(s, GICR_ICACTIVER0, ncpu, ®, true);
reg = c->gicr_iactiver0;
kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, true);
for (i = 0; i < GIC_INTERNAL; i += 4) {
reg = c->gicr_ipriorityr[i] |
(c->gicr_ipriorityr[i + 1] << 8) |
(c->gicr_ipriorityr[i + 2] << 16) |
(c->gicr_ipriorityr[i + 3] << 24);
kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, true);
}
}
/* Distributor state (shared between all CPUs */
reg = s->gicd_statusr[GICV3_NS];
kvm_gicd_access(s, GICD_STATUSR, ®, true);
/* s->enable bitmap -> GICD_ISENABLERn */
kvm_dist_putbmp(s, GICD_ISENABLER, GICD_ICENABLER, s->enabled);
/* s->group bitmap -> GICD_IGROUPRn */
kvm_dist_putbmp(s, GICD_IGROUPR, 0, s->group);
/* Restore targets before pending to ensure the pending state is set on
* the appropriate CPU interfaces in the kernel
*/
/* s->gicd_irouter[irq] -> GICD_IROUTERn
* We can't use kvm_dist_put() here because the registers are 64-bit
*/
for (i = GIC_INTERNAL; i < s->num_irq; i++) {
uint32_t offset;
offset = GICD_IROUTER + (sizeof(uint32_t) * i);
reg = (uint32_t)s->gicd_irouter[i];
kvm_gicd_access(s, offset, ®, true);
offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4;
reg = (uint32_t)(s->gicd_irouter[i] >> 32);
kvm_gicd_access(s, offset, ®, true);
}
/* s->trigger bitmap -> GICD_ICFGRn
* (restore configuration registers before pending IRQs so we treat
* level/edge correctly)
*/
kvm_dist_put_edge_trigger(s, GICD_ICFGR, s->edge_trigger);
/* s->level bitmap -> line_level */
kvm_gic_put_line_level_bmp(s, s->level);
/* s->pending bitmap -> GICD_ISPENDRn */
kvm_dist_putbmp(s, GICD_ISPENDR, GICD_ICPENDR, s->pending);
/* s->active bitmap -> GICD_ISACTIVERn */
kvm_dist_putbmp(s, GICD_ISACTIVER, GICD_ICACTIVER, s->active);
/* s->gicd_ipriority[] -> GICD_IPRIORITYRn */
kvm_dist_put_priority(s, GICD_IPRIORITYR, s->gicd_ipriority);
/* CPU Interface state (one per CPU) */
for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
GICv3CPUState *c = &s->cpu[ncpu];
int num_pri_bits;
kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, true);
kvm_gicc_access(s, ICC_CTLR_EL1, ncpu,
&c->icc_ctlr_el1[GICV3_NS], true);
kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu,
&c->icc_igrpen[GICV3_G0], true);
kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu,
&c->icc_igrpen[GICV3_G1NS], true);
kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, true);
kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], true);
kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], true);
num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] &
ICC_CTLR_EL1_PRIBITS_MASK) >>
ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
switch (num_pri_bits) {
case 7:
reg64 = c->icc_apr[GICV3_G0][3];
kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, true);
reg64 = c->icc_apr[GICV3_G0][2];
kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, true);
- /* fall through */
+ fallthrough;
case 6:
reg64 = c->icc_apr[GICV3_G0][1];
kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, true);
- /* fall through */
+ fallthrough;
default:
reg64 = c->icc_apr[GICV3_G0][0];
kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, true);
}
switch (num_pri_bits) {
case 7:
reg64 = c->icc_apr[GICV3_G1NS][3];
kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, true);
reg64 = c->icc_apr[GICV3_G1NS][2];
kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, true);
- /* fall through */
+ fallthrough;
case 6:
reg64 = c->icc_apr[GICV3_G1NS][1];
kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, true);
- /* fall through */
+ fallthrough;
default:
reg64 = c->icc_apr[GICV3_G1NS][0];
kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, true);
}
}
}
@@ -510,156 +510,156 @@ static void kvm_arm_gicv3_put(GICv3State *s)
static void kvm_arm_gicv3_get(GICv3State *s)
{
uint32_t regl, regh, reg;
uint64_t reg64, redist_typer;
int ncpu, i;
kvm_arm_gicv3_check(s);
kvm_gicr_access(s, GICR_TYPER, 0, ®l, false);
kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false);
redist_typer = ((uint64_t)regh << 32) | regl;
kvm_gicd_access(s, GICD_CTLR, ®, false);
s->gicd_ctlr = reg;
/* Redistributor state (one per CPU) */
for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
GICv3CPUState *c = &s->cpu[ncpu];
kvm_gicr_access(s, GICR_CTLR, ncpu, ®, false);
c->gicr_ctlr = reg;
kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, false);
c->gicr_statusr[GICV3_NS] = reg;
kvm_gicr_access(s, GICR_WAKER, ncpu, ®, false);
c->gicr_waker = reg;
kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, false);
c->gicr_igroupr0 = reg;
kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, false);
c->gicr_ienabler0 = reg;
kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, false);
c->edge_trigger = half_unshuffle32(reg >> 1) << 16;
kvm_gic_line_level_access(s, 0, ncpu, ®, false);
c->level = reg;
kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, false);
c->gicr_ipendr0 = reg;
kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, false);
c->gicr_iactiver0 = reg;
for (i = 0; i < GIC_INTERNAL; i += 4) {
kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, false);
c->gicr_ipriorityr[i] = extract32(reg, 0, 8);
c->gicr_ipriorityr[i + 1] = extract32(reg, 8, 8);
c->gicr_ipriorityr[i + 2] = extract32(reg, 16, 8);
c->gicr_ipriorityr[i + 3] = extract32(reg, 24, 8);
}
}
if (redist_typer & GICR_TYPER_PLPIS) {
for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
GICv3CPUState *c = &s->cpu[ncpu];
kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, false);
kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, false);
c->gicr_propbaser = ((uint64_t)regh << 32) | regl;
kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, false);
kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, false);
c->gicr_pendbaser = ((uint64_t)regh << 32) | regl;
}
}
/* Distributor state (shared between all CPUs */
kvm_gicd_access(s, GICD_STATUSR, ®, false);
s->gicd_statusr[GICV3_NS] = reg;
/* GICD_IGROUPRn -> s->group bitmap */
kvm_dist_getbmp(s, GICD_IGROUPR, s->group);
/* GICD_ISENABLERn -> s->enabled bitmap */
kvm_dist_getbmp(s, GICD_ISENABLER, s->enabled);
/* Line level of irq */
kvm_gic_get_line_level_bmp(s, s->level);
/* GICD_ISPENDRn -> s->pending bitmap */
kvm_dist_getbmp(s, GICD_ISPENDR, s->pending);
/* GICD_ISACTIVERn -> s->active bitmap */
kvm_dist_getbmp(s, GICD_ISACTIVER, s->active);
/* GICD_ICFGRn -> s->trigger bitmap */
kvm_dist_get_edge_trigger(s, GICD_ICFGR, s->edge_trigger);
/* GICD_IPRIORITYRn -> s->gicd_ipriority[] */
kvm_dist_get_priority(s, GICD_IPRIORITYR, s->gicd_ipriority);
/* GICD_IROUTERn -> s->gicd_irouter[irq] */
for (i = GIC_INTERNAL; i < s->num_irq; i++) {
uint32_t offset;
offset = GICD_IROUTER + (sizeof(uint32_t) * i);
kvm_gicd_access(s, offset, ®l, false);
offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4;
kvm_gicd_access(s, offset, ®h, false);
s->gicd_irouter[i] = ((uint64_t)regh << 32) | regl;
}
/*****************************************************************
* CPU Interface(s) State
*/
for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
GICv3CPUState *c = &s->cpu[ncpu];
int num_pri_bits;
kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, false);
kvm_gicc_access(s, ICC_CTLR_EL1, ncpu,
&c->icc_ctlr_el1[GICV3_NS], false);
kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu,
&c->icc_igrpen[GICV3_G0], false);
kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu,
&c->icc_igrpen[GICV3_G1NS], false);
kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, false);
kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], false);
kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], false);
num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] &
ICC_CTLR_EL1_PRIBITS_MASK) >>
ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
switch (num_pri_bits) {
case 7:
kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, false);
c->icc_apr[GICV3_G0][3] = reg64;
kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, false);
c->icc_apr[GICV3_G0][2] = reg64;
- /* fall through */
+ fallthrough;
case 6:
kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, false);
c->icc_apr[GICV3_G0][1] = reg64;
- /* fall through */
+ fallthrough;
default:
kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, false);
c->icc_apr[GICV3_G0][0] = reg64;
}
switch (num_pri_bits) {
case 7:
kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, false);
c->icc_apr[GICV3_G1NS][3] = reg64;
kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, false);
c->icc_apr[GICV3_G1NS][2] = reg64;
- /* fall through */
+ fallthrough;
case 6:
kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, false);
c->icc_apr[GICV3_G1NS][1] = reg64;
- /* fall through */
+ fallthrough;
default:
kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, false);
c->icc_apr[GICV3_G1NS][0] = reg64;
}
}
}
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 03b6b8c986..72d3ae985e 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2209,128 +2209,128 @@ static int shpr_bank(NVICState *s, int exc, MemTxAttrs attrs)
static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
uint64_t *data, unsigned size,
MemTxAttrs attrs)
{
NVICState *s = (NVICState *)opaque;
uint32_t offset = addr;
unsigned i, startvec, end;
uint32_t val;
if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) {
/* Generate BusFault for unprivileged accesses */
return MEMTX_ERROR;
}
switch (offset) {
/* reads of set and clear both return the status */
case 0x100 ... 0x13f: /* NVIC Set enable */
offset += 0x80;
- /* fall through */
+ fallthrough;
case 0x180 ... 0x1bf: /* NVIC Clear enable */
val = 0;
startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ; /* vector # */
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
if (s->vectors[startvec + i].enabled &&
(attrs.secure || s->itns[startvec + i])) {
val |= (1 << i);
}
}
break;
case 0x200 ... 0x23f: /* NVIC Set pend */
offset += 0x80;
- /* fall through */
+ fallthrough;
case 0x280 ... 0x2bf: /* NVIC Clear pend */
val = 0;
startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
if (s->vectors[startvec + i].pending &&
(attrs.secure || s->itns[startvec + i])) {
val |= (1 << i);
}
}
break;
case 0x300 ... 0x33f: /* NVIC Active */
val = 0;
if (!arm_feature(&s->cpu->env, ARM_FEATURE_V7)) {
break;
}
startvec = 8 * (offset - 0x300) + NVIC_FIRST_IRQ; /* vector # */
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
if (s->vectors[startvec + i].active &&
(attrs.secure || s->itns[startvec + i])) {
val |= (1 << i);
}
}
break;
case 0x400 ... 0x5ef: /* NVIC Priority */
val = 0;
startvec = offset - 0x400 + NVIC_FIRST_IRQ; /* vector # */
for (i = 0; i < size && startvec + i < s->num_irq; i++) {
if (attrs.secure || s->itns[startvec + i]) {
val |= s->vectors[startvec + i].prio << (8 * i);
}
}
break;
case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */
if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {
val = 0;
break;
}
- /* fall through */
+ fallthrough;
case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */
val = 0;
for (i = 0; i < size; i++) {
unsigned hdlidx = (offset - 0xd14) + i;
int sbank = shpr_bank(s, hdlidx, attrs);
if (sbank < 0) {
continue;
}
val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank));
}
break;
case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */
if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {
val = 0;
break;
};
/*
* The BFSR bits [15:8] are shared between security states
* and we store them in the NS copy. They are RAZ/WI for
* NS code if AIRCR.BFHFNMINS is 0.
*/
val = s->cpu->env.v7m.cfsr[attrs.secure];
if (!attrs.secure &&
!(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
val &= ~R_V7M_CFSR_BFSR_MASK;
} else {
val |= s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK;
}
val = extract32(val, (offset - 0xd28) * 8, size * 8);
break;
case 0xfe0 ... 0xfff: /* ID. */
if (offset & 3) {
val = 0;
} else {
val = nvic_id[(offset - 0xfe0) >> 2];
}
break;
default:
if (size == 4) {
val = nvic_readl(s, offset, attrs);
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"NVIC: Bad read of size %d at offset 0x%x\n",
size, offset);
val = 0;
}
}
trace_nvic_sysreg_read(addr, val, size);
*data = val;
return MEMTX_OK;
}
@@ -2338,126 +2338,126 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size,
MemTxAttrs attrs)
{
NVICState *s = (NVICState *)opaque;
uint32_t offset = addr;
unsigned i, startvec, end;
unsigned setval = 0;
trace_nvic_sysreg_write(addr, value, size);
if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) {
/* Generate BusFault for unprivileged accesses */
return MEMTX_ERROR;
}
switch (offset) {
case 0x100 ... 0x13f: /* NVIC Set enable */
offset += 0x80;
setval = 1;
- /* fall through */
+ fallthrough;
case 0x180 ... 0x1bf: /* NVIC Clear enable */
startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ;
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
if (value & (1 << i) &&
(attrs.secure || s->itns[startvec + i])) {
s->vectors[startvec + i].enabled = setval;
}
}
nvic_irq_update(s);
goto exit_ok;
case 0x200 ... 0x23f: /* NVIC Set pend */
/* the special logic in armv7m_nvic_set_pending()
* is not needed since IRQs are never escalated
*/
offset += 0x80;
setval = 1;
- /* fall through */
+ fallthrough;
case 0x280 ... 0x2bf: /* NVIC Clear pend */
startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
/*
* Note that if the input line is still held high and the interrupt
* is not active then rule R_CVJS requires that the Pending state
* remains set; in that case we mustn't let it be cleared.
*/
if (value & (1 << i) &&
(attrs.secure || s->itns[startvec + i]) &&
!(setval == 0 && s->vectors[startvec + i].level &&
!s->vectors[startvec + i].active)) {
s->vectors[startvec + i].pending = setval;
}
}
nvic_irq_update(s);
goto exit_ok;
case 0x300 ... 0x33f: /* NVIC Active */
goto exit_ok; /* R/O */
case 0x400 ... 0x5ef: /* NVIC Priority */
startvec = (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */
for (i = 0; i < size && startvec + i < s->num_irq; i++) {
if (attrs.secure || s->itns[startvec + i]) {
set_prio(s, startvec + i, false, (value >> (i * 8)) & 0xff);
}
}
nvic_irq_update(s);
goto exit_ok;
case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */
if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {
goto exit_ok;
}
- /* fall through */
+ fallthrough;
case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */
for (i = 0; i < size; i++) {
unsigned hdlidx = (offset - 0xd14) + i;
int newprio = extract32(value, i * 8, 8);
int sbank = shpr_bank(s, hdlidx, attrs);
if (sbank < 0) {
continue;
}
set_prio(s, hdlidx, sbank, newprio);
}
nvic_irq_update(s);
goto exit_ok;
case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */
if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {
goto exit_ok;
}
/* All bits are W1C, so construct 32 bit value with 0s in
* the parts not written by the access size
*/
value <<= ((offset - 0xd28) * 8);
if (!attrs.secure &&
!(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
/* BFSR bits are RAZ/WI for NS if BFHFNMINS is set */
value &= ~R_V7M_CFSR_BFSR_MASK;
}
s->cpu->env.v7m.cfsr[attrs.secure] &= ~value;
if (attrs.secure) {
/* The BFSR bits [15:8] are shared between security states
* and we store them in the NS copy.
*/
s->cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK);
}
goto exit_ok;
}
if (size == 4) {
nvic_writel(s, offset, value, attrs);
goto exit_ok;
}
qemu_log_mask(LOG_GUEST_ERROR,
"NVIC: Bad write of size %d at offset 0x%x\n", size, offset);
/* This is UNPREDICTABLE; treat as RAZ/WI */
exit_ok:
if (tcg_enabled()) {
/* Ensure any changes made are reflected in the cached hflags. */
arm_rebuild_hflags(&s->cpu->env);
}
return MEMTX_OK;
}
diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
index 6e5012e66e..245f452898 100644
--- a/hw/intc/xilinx_intc.c
+++ b/hw/intc/xilinx_intc.c
@@ -108,34 +108,34 @@ static uint64_t pic_read(void *opaque, hwaddr addr, unsigned int size)
static void pic_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
XpsIntc *p = opaque;
uint32_t value = val64;
addr >>= 2;
D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
switch (addr)
{
case R_IAR:
p->regs[R_ISR] &= ~value; /* ACK. */
break;
case R_SIE:
p->regs[R_IER] |= value; /* Atomic set ie. */
break;
case R_CIE:
p->regs[R_IER] &= ~value; /* Atomic clear ie. */
break;
case R_MER:
p->regs[R_MER] = value & 0x3;
break;
case R_ISR:
if ((p->regs[R_MER] & 2)) {
break;
}
- /* fallthrough */
+ fallthrough;
default:
if (addr < ARRAY_SIZE(p->regs))
p->regs[addr] = value;
break;
}
update_irq(p);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 60/78] qga: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (58 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 59/78] hw/intc: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 61/78] semihosting: " Emmanouil Pitsidianakis
` (18 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Michael Roth, Konstantin Kostiuk
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
qga/main.c | 2 +-
qga/vss-win32/requester.cpp | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/qga/main.c b/qga/main.c
index 8668b9f3d3..40471e8a0b 100644
--- a/qga/main.c
+++ b/qga/main.c
@@ -644,37 +644,37 @@ end:
/* false return signals GAChannel to close the current client connection */
static gboolean channel_event_cb(GIOCondition condition, gpointer data)
{
GAState *s = data;
gchar buf[QGA_READ_COUNT_DEFAULT + 1];
gsize count;
GIOStatus status = ga_channel_read(s->channel, buf, QGA_READ_COUNT_DEFAULT, &count);
switch (status) {
case G_IO_STATUS_ERROR:
g_warning("error reading channel");
stop_agent(s, false);
return false;
case G_IO_STATUS_NORMAL:
buf[count] = 0;
g_debug("read data, count: %d, data: %s", (int)count, buf);
json_message_parser_feed(&s->parser, (char *)buf, (int)count);
break;
case G_IO_STATUS_EOF:
g_debug("received EOF");
if (!s->virtio) {
return false;
}
- /* fall through */
+ fallthrough;
case G_IO_STATUS_AGAIN:
/* virtio causes us to spin here when no process is attached to
* host-side chardev. sleep a bit to mitigate this
*/
if (s->virtio) {
g_usleep(G_USEC_PER_SEC / 10);
}
return true;
default:
g_warning("unknown channel read status, closing");
return false;
}
return true;
}
diff --git a/qga/vss-win32/requester.cpp b/qga/vss-win32/requester.cpp
index 9884c65e70..36fa4fdf28 100644
--- a/qga/vss-win32/requester.cpp
+++ b/qga/vss-win32/requester.cpp
@@ -563,72 +563,73 @@ out1:
void requester_thaw(int *num_vols, void *mountpints, ErrorSet *errset)
{
qga_debug_begin;
COMPointer<IVssAsync> pAsync;
if (!vss_ctx.hEventThaw) {
/*
* In this case, DoSnapshotSet is aborted or not started,
* and no volumes must be frozen. We return without an error.
*/
*num_vols = 0;
qga_debug("finished, no volumes were frozen");
return;
}
/* Tell the provider that the snapshot is finished. */
SetEvent(vss_ctx.hEventThaw);
assert(vss_ctx.pVssbc);
assert(vss_ctx.pAsyncSnapshot);
HRESULT hr = WaitForAsync(vss_ctx.pAsyncSnapshot);
switch (hr) {
case VSS_S_ASYNC_FINISHED:
hr = vss_ctx.pVssbc->BackupComplete(pAsync.replace());
if (SUCCEEDED(hr)) {
hr = WaitForAsync(pAsync);
}
if (FAILED(hr)) {
err_set(errset, hr, "failed to complete backup");
}
break;
case (HRESULT)VSS_E_OBJECT_NOT_FOUND:
/*
* On Windows earlier than 2008 SP2 which does not support
* VSS_VOLSNAP_ATTR_NO_AUTORECOVERY context, the final commit is not
* skipped and VSS is aborted by VSS_E_OBJECT_NOT_FOUND. However, as
* the system had been frozen until fsfreeze-thaw command was issued,
* we ignore this error.
*/
vss_ctx.pVssbc->AbortBackup();
break;
case VSS_E_UNEXPECTED_PROVIDER_ERROR:
if (WaitForSingleObject(vss_ctx.hEventTimeout, 0) != WAIT_OBJECT_0) {
err_set(errset, hr, "unexpected error in VSS provider");
break;
}
/* fall through if hEventTimeout is signaled */
+ fallthrough;
case (HRESULT)VSS_E_HOLD_WRITES_TIMEOUT:
err_set(errset, hr, "couldn't hold writes: "
"fsfreeze is limited up to 10 seconds");
break;
default:
err_set(errset, hr, "failed to do snapshot set");
}
if (err_is_set(errset)) {
vss_ctx.pVssbc->AbortBackup();
}
*num_vols = vss_ctx.cFrozenVols;
requester_cleanup();
CoUninitialize();
StopService();
qga_debug_end;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 61/78] semihosting: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (59 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 60/78] qga: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 62/78] hw/gpio: " Emmanouil Pitsidianakis
` (17 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Alex Bennée
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
semihosting/arm-compat-semi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
index 329ea11260..c7d32cfca0 100644
--- a/semihosting/arm-compat-semi.c
+++ b/semihosting/arm-compat-semi.c
@@ -354,446 +354,446 @@ static const uint8_t featurefile_data[] = {
/*
* Do a semihosting call.
*
* The specification always says that the "return register" either
* returns a specific value or is corrupted, so we don't need to
* report to our caller whether we are returning a value or trying to
* leave the register unchanged.
*/
void do_common_semihosting(CPUState *cs)
{
CPUArchState *env = cpu_env(cs);
target_ulong args;
target_ulong arg0, arg1, arg2, arg3;
target_ulong ul_ret;
char * s;
int nr;
int64_t elapsed;
nr = common_semi_arg(cs, 0) & 0xffffffffU;
args = common_semi_arg(cs, 1);
switch (nr) {
case TARGET_SYS_OPEN:
{
int ret, err = 0;
int hostfd;
GET_ARG(0);
GET_ARG(1);
GET_ARG(2);
s = lock_user_string(arg0);
if (!s) {
goto do_fault;
}
if (arg1 >= 12) {
unlock_user(s, arg0, 0);
common_semi_cb(cs, -1, EINVAL);
break;
}
if (strcmp(s, ":tt") == 0) {
/*
* We implement SH_EXT_STDOUT_STDERR, so:
* open for read == stdin
* open for write == stdout
* open for append == stderr
*/
if (arg1 < 4) {
hostfd = STDIN_FILENO;
} else if (arg1 < 8) {
hostfd = STDOUT_FILENO;
} else {
hostfd = STDERR_FILENO;
}
ret = alloc_guestfd();
associate_guestfd(ret, hostfd);
} else if (strcmp(s, ":semihosting-features") == 0) {
/* We must fail opens for modes other than 0 ('r') or 1 ('rb') */
if (arg1 != 0 && arg1 != 1) {
ret = -1;
err = EACCES;
} else {
ret = alloc_guestfd();
staticfile_guestfd(ret, featurefile_data,
sizeof(featurefile_data));
}
} else {
unlock_user(s, arg0, 0);
semihost_sys_open(cs, common_semi_cb, arg0, arg2 + 1,
gdb_open_modeflags[arg1], 0644);
break;
}
unlock_user(s, arg0, 0);
common_semi_cb(cs, ret, err);
break;
}
case TARGET_SYS_CLOSE:
GET_ARG(0);
semihost_sys_close(cs, common_semi_cb, arg0);
break;
case TARGET_SYS_WRITEC:
/*
* FIXME: the byte to be written is in a target_ulong slot,
* which means this is wrong for a big-endian guest.
*/
semihost_sys_write_gf(cs, common_semi_dead_cb,
&console_out_gf, args, 1);
break;
case TARGET_SYS_WRITE0:
{
ssize_t len = target_strlen(args);
if (len < 0) {
common_semi_dead_cb(cs, -1, EFAULT);
} else {
semihost_sys_write_gf(cs, common_semi_dead_cb,
&console_out_gf, args, len);
}
}
break;
case TARGET_SYS_WRITE:
GET_ARG(0);
GET_ARG(1);
GET_ARG(2);
semihost_sys_write(cs, common_semi_rw_cb, arg0, arg1, arg2);
break;
case TARGET_SYS_READ:
GET_ARG(0);
GET_ARG(1);
GET_ARG(2);
semihost_sys_read(cs, common_semi_rw_cb, arg0, arg1, arg2);
break;
case TARGET_SYS_READC:
semihost_sys_read_gf(cs, common_semi_readc_cb, &console_in_gf,
common_semi_stack_bottom(cs) - 1, 1);
break;
case TARGET_SYS_ISERROR:
GET_ARG(0);
common_semi_set_ret(cs, (target_long)arg0 < 0);
break;
case TARGET_SYS_ISTTY:
GET_ARG(0);
semihost_sys_isatty(cs, common_semi_istty_cb, arg0);
break;
case TARGET_SYS_SEEK:
GET_ARG(0);
GET_ARG(1);
semihost_sys_lseek(cs, common_semi_seek_cb, arg0, arg1, GDB_SEEK_SET);
break;
case TARGET_SYS_FLEN:
GET_ARG(0);
semihost_sys_flen(cs, common_semi_flen_fstat_cb, common_semi_cb,
arg0, common_semi_flen_buf(cs));
break;
case TARGET_SYS_TMPNAM:
{
int len;
char *p;
GET_ARG(0);
GET_ARG(1);
GET_ARG(2);
len = asprintf(&s, "%s/qemu-%x%02x", g_get_tmp_dir(),
getpid(), (int)arg1 & 0xff);
if (len < 0) {
common_semi_set_ret(cs, -1);
break;
}
/* Allow for trailing NUL */
len++;
/* Make sure there's enough space in the buffer */
if (len > arg2) {
free(s);
common_semi_set_ret(cs, -1);
break;
}
p = lock_user(VERIFY_WRITE, arg0, len, 0);
if (!p) {
free(s);
goto do_fault;
}
memcpy(p, s, len);
unlock_user(p, arg0, len);
free(s);
common_semi_set_ret(cs, 0);
break;
}
case TARGET_SYS_REMOVE:
GET_ARG(0);
GET_ARG(1);
semihost_sys_remove(cs, common_semi_cb, arg0, arg1 + 1);
break;
case TARGET_SYS_RENAME:
GET_ARG(0);
GET_ARG(1);
GET_ARG(2);
GET_ARG(3);
semihost_sys_rename(cs, common_semi_cb, arg0, arg1 + 1, arg2, arg3 + 1);
break;
case TARGET_SYS_CLOCK:
common_semi_set_ret(cs, clock() / (CLOCKS_PER_SEC / 100));
break;
case TARGET_SYS_TIME:
ul_ret = time(NULL);
common_semi_cb(cs, ul_ret, ul_ret == -1 ? errno : 0);
break;
case TARGET_SYS_SYSTEM:
GET_ARG(0);
GET_ARG(1);
semihost_sys_system(cs, common_semi_cb, arg0, arg1 + 1);
break;
case TARGET_SYS_ERRNO:
common_semi_set_ret(cs, get_swi_errno(cs));
break;
case TARGET_SYS_GET_CMDLINE:
{
/* Build a command-line from the original argv.
*
* The inputs are:
* * arg0, pointer to a buffer of at least the size
* specified in arg1.
* * arg1, size of the buffer pointed to by arg0 in
* bytes.
*
* The outputs are:
* * arg0, pointer to null-terminated string of the
* command line.
* * arg1, length of the string pointed to by arg0.
*/
char *output_buffer;
size_t input_size;
size_t output_size;
int status = 0;
#if !defined(CONFIG_USER_ONLY)
const char *cmdline;
#else
TaskState *ts = cs->opaque;
#endif
GET_ARG(0);
GET_ARG(1);
input_size = arg1;
/* Compute the size of the output string. */
#if !defined(CONFIG_USER_ONLY)
cmdline = semihosting_get_cmdline();
if (cmdline == NULL) {
cmdline = ""; /* Default to an empty line. */
}
output_size = strlen(cmdline) + 1; /* Count terminating 0. */
#else
unsigned int i;
output_size = ts->info->env_strings - ts->info->arg_strings;
if (!output_size) {
/*
* We special-case the "empty command line" case (argc==0).
* Just provide the terminating 0.
*/
output_size = 1;
}
#endif
if (output_size > input_size) {
/* Not enough space to store command-line arguments. */
common_semi_cb(cs, -1, E2BIG);
break;
}
/* Adjust the command-line length. */
if (SET_ARG(1, output_size - 1)) {
/* Couldn't write back to argument block */
goto do_fault;
}
/* Lock the buffer on the ARM side. */
output_buffer = lock_user(VERIFY_WRITE, arg0, output_size, 0);
if (!output_buffer) {
goto do_fault;
}
/* Copy the command-line arguments. */
#if !defined(CONFIG_USER_ONLY)
pstrcpy(output_buffer, output_size, cmdline);
#else
if (output_size == 1) {
/* Empty command-line. */
output_buffer[0] = '\0';
goto out;
}
if (copy_from_user(output_buffer, ts->info->arg_strings,
output_size)) {
unlock_user(output_buffer, arg0, 0);
goto do_fault;
}
/* Separate arguments by white spaces. */
for (i = 0; i < output_size - 1; i++) {
if (output_buffer[i] == 0) {
output_buffer[i] = ' ';
}
}
out:
#endif
/* Unlock the buffer on the ARM side. */
unlock_user(output_buffer, arg0, output_size);
common_semi_cb(cs, status, 0);
}
break;
case TARGET_SYS_HEAPINFO:
{
target_ulong retvals[4];
int i;
#ifdef CONFIG_USER_ONLY
TaskState *ts = cs->opaque;
target_ulong limit;
#else
LayoutInfo info = common_semi_find_bases(cs);
#endif
GET_ARG(0);
#ifdef CONFIG_USER_ONLY
/*
* Some C libraries assume the heap immediately follows .bss, so
* allocate it using sbrk.
*/
if (!ts->heap_limit) {
abi_ulong ret;
ts->heap_base = do_brk(0);
limit = ts->heap_base + COMMON_SEMI_HEAP_SIZE;
/* Try a big heap, and reduce the size if that fails. */
for (;;) {
ret = do_brk(limit);
if (ret >= limit) {
break;
}
limit = (ts->heap_base >> 1) + (limit >> 1);
}
ts->heap_limit = limit;
}
retvals[0] = ts->heap_base;
retvals[1] = ts->heap_limit;
retvals[2] = ts->stack_base;
retvals[3] = 0; /* Stack limit. */
#else
retvals[0] = info.heapbase; /* Heap Base */
retvals[1] = info.heaplimit; /* Heap Limit */
retvals[2] = info.heaplimit; /* Stack base */
retvals[3] = info.heapbase; /* Stack limit. */
#endif
for (i = 0; i < ARRAY_SIZE(retvals); i++) {
bool fail;
if (is_64bit_semihosting(env)) {
fail = put_user_u64(retvals[i], arg0 + i * 8);
} else {
fail = put_user_u32(retvals[i], arg0 + i * 4);
}
if (fail) {
/* Couldn't write back to argument block */
goto do_fault;
}
}
common_semi_set_ret(cs, 0);
}
break;
case TARGET_SYS_EXIT:
case TARGET_SYS_EXIT_EXTENDED:
{
uint32_t ret;
if (common_semi_sys_exit_extended(cs, nr)) {
/*
* The A64 version of SYS_EXIT takes a parameter block,
* so the application-exit type can return a subcode which
* is the exit status code from the application.
* SYS_EXIT_EXTENDED is an a new-in-v2.0 optional function
* which allows A32/T32 guests to also provide a status code.
*/
GET_ARG(0);
GET_ARG(1);
if (arg0 == ADP_Stopped_ApplicationExit) {
ret = arg1;
} else {
ret = 1;
}
} else {
/*
* The A32/T32 version of SYS_EXIT specifies only
* Stopped_ApplicationExit as normal exit, but does not
* allow the guest to specify the exit status code.
* Everything else is considered an error.
*/
ret = (args == ADP_Stopped_ApplicationExit) ? 0 : 1;
}
gdb_exit(ret);
exit(ret);
}
case TARGET_SYS_ELAPSED:
elapsed = get_clock() - clock_start;
if (sizeof(target_ulong) == 8) {
if (SET_ARG(0, elapsed)) {
goto do_fault;
}
} else {
if (SET_ARG(0, (uint32_t) elapsed) ||
SET_ARG(1, (uint32_t) (elapsed >> 32))) {
goto do_fault;
}
}
common_semi_set_ret(cs, 0);
break;
case TARGET_SYS_TICKFREQ:
/* qemu always uses nsec */
common_semi_set_ret(cs, 1000000000);
break;
case TARGET_SYS_SYNCCACHE:
/*
* Clean the D-cache and invalidate the I-cache for the specified
* virtual address range. This is a nop for us since we don't
* implement caches. This is only present on A64.
*/
if (common_semi_has_synccache(env)) {
common_semi_set_ret(cs, 0);
break;
}
- /* fall through */
+ fallthrough;
default:
fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr);
cpu_dump_state(cs, stderr, 0);
abort();
do_fault:
common_semi_cb(cs, -1, EFAULT);
break;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 62/78] hw/gpio: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (60 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 61/78] semihosting: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 63/78] hw/ipmi: " Emmanouil Pitsidianakis
` (16 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Peter Maydell, open list:OMAP
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/gpio/omap_gpio.c | 2 +-
hw/i2c/bitbang_i2c.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
index a3341d70f1..82a9ea4810 100644
--- a/hw/gpio/omap_gpio.c
+++ b/hw/gpio/omap_gpio.c
@@ -532,54 +532,54 @@ static uint64_t omap2_gpio_module_readp(void *opaque, hwaddr addr,
static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
uint32_t cur = 0;
uint32_t mask = 0xffff;
if (size == 4) {
omap2_gpio_module_write(opaque, addr, value);
return;
}
switch (addr & ~3) {
case 0x00: /* GPIO_REVISION */
case 0x14: /* GPIO_SYSSTATUS */
case 0x38: /* GPIO_DATAIN */
OMAP_RO_REG(addr);
break;
case 0x10: /* GPIO_SYSCONFIG */
case 0x1c: /* GPIO_IRQENABLE1 */
case 0x20: /* GPIO_WAKEUPENABLE */
case 0x2c: /* GPIO_IRQENABLE2 */
case 0x30: /* GPIO_CTRL */
case 0x34: /* GPIO_OE */
case 0x3c: /* GPIO_DATAOUT */
case 0x40: /* GPIO_LEVELDETECT0 */
case 0x44: /* GPIO_LEVELDETECT1 */
case 0x48: /* GPIO_RISINGDETECT */
case 0x4c: /* GPIO_FALLINGDETECT */
case 0x50: /* GPIO_DEBOUNCENABLE */
case 0x54: /* GPIO_DEBOUNCINGTIME */
cur = omap2_gpio_module_read(opaque, addr & ~3) &
~(mask << ((addr & 3) << 3));
- /* Fall through. */
+ fallthrough;
case 0x18: /* GPIO_IRQSTATUS1 */
case 0x28: /* GPIO_IRQSTATUS2 */
case 0x60: /* GPIO_CLEARIRQENABLE1 */
case 0x64: /* GPIO_SETIRQENABLE1 */
case 0x70: /* GPIO_CLEARIRQENABLE2 */
case 0x74: /* GPIO_SETIREQNEABLE2 */
case 0x80: /* GPIO_CLEARWKUENA */
case 0x84: /* GPIO_SETWKUENA */
case 0x90: /* GPIO_CLEARDATAOUT */
case 0x94: /* GPIO_SETDATAOUT */
value <<= (addr & 3) << 3;
omap2_gpio_module_write(opaque, addr, cur | value);
break;
default:
OMAP_BAD_REG(addr);
return;
}
}
diff --git a/hw/i2c/bitbang_i2c.c b/hw/i2c/bitbang_i2c.c
index de5f5aacf5..3d768ae564 100644
--- a/hw/i2c/bitbang_i2c.c
+++ b/hw/i2c/bitbang_i2c.c
@@ -79,99 +79,99 @@ static int bitbang_i2c_nop(bitbang_i2c_interface *i2c)
/* Returns data line level. */
int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level)
{
int data;
if (level != 0 && level != 1) {
abort();
}
if (line == BITBANG_I2C_SDA) {
if (level == i2c->last_data) {
return bitbang_i2c_nop(i2c);
}
i2c->last_data = level;
if (i2c->last_clock == 0) {
return bitbang_i2c_nop(i2c);
}
if (level == 0) {
/* START condition. */
bitbang_i2c_set_state(i2c, SENDING_BIT7);
i2c->current_addr = -1;
} else {
/* STOP condition. */
bitbang_i2c_enter_stop(i2c);
}
return bitbang_i2c_ret(i2c, 1);
}
data = i2c->last_data;
if (i2c->last_clock == level) {
return bitbang_i2c_nop(i2c);
}
i2c->last_clock = level;
if (level == 0) {
/* State is set/read at the start of the clock pulse.
release the data line at the end. */
return bitbang_i2c_ret(i2c, 1);
}
switch (i2c->state) {
case STOPPED:
case SENT_NACK:
return bitbang_i2c_ret(i2c, 1);
case SENDING_BIT7 ... SENDING_BIT0:
i2c->buffer = (i2c->buffer << 1) | data;
/* will end up in WAITING_FOR_ACK */
bitbang_i2c_set_state(i2c, i2c->state + 1);
return bitbang_i2c_ret(i2c, 1);
case WAITING_FOR_ACK:
{
int ret;
if (i2c->current_addr < 0) {
i2c->current_addr = i2c->buffer;
trace_bitbang_i2c_addr(i2c->current_addr);
ret = i2c_start_transfer(i2c->bus, i2c->current_addr >> 1,
i2c->current_addr & 1);
} else {
trace_bitbang_i2c_send(i2c->buffer);
ret = i2c_send(i2c->bus, i2c->buffer);
}
if (ret) {
/* NACK (either addressing a nonexistent device, or the
* device we were sending to decided to NACK us).
*/
bitbang_i2c_set_state(i2c, SENT_NACK);
bitbang_i2c_enter_stop(i2c);
return bitbang_i2c_ret(i2c, 1);
}
if (i2c->current_addr & 1) {
bitbang_i2c_set_state(i2c, RECEIVING_BIT7);
} else {
bitbang_i2c_set_state(i2c, SENDING_BIT7);
}
return bitbang_i2c_ret(i2c, 0);
}
case RECEIVING_BIT7:
i2c->buffer = i2c_recv(i2c->bus);
trace_bitbang_i2c_recv(i2c->buffer);
- /* Fall through... */
+ fallthrough;
case RECEIVING_BIT6 ... RECEIVING_BIT0:
data = i2c->buffer >> 7;
/* will end up in SENDING_ACK */
bitbang_i2c_set_state(i2c, i2c->state + 1);
i2c->buffer <<= 1;
return bitbang_i2c_ret(i2c, data);
case SENDING_ACK:
if (data != 0) {
bitbang_i2c_set_state(i2c, SENT_NACK);
i2c_nack(i2c->bus);
} else {
bitbang_i2c_set_state(i2c, RECEIVING_BIT7);
}
return bitbang_i2c_ret(i2c, 1);
}
abort();
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 63/78] hw/ipmi: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (61 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 62/78] hw/gpio: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 64/78] hw/mips: " Emmanouil Pitsidianakis
` (15 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Corey Minyard
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/ipmi/ipmi_bmc_extern.c | 2 +-
hw/ipmi/smbus_ipmi.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ipmi/ipmi_bmc_extern.c b/hw/ipmi/ipmi_bmc_extern.c
index e232d35ba2..b2ca02b21f 100644
--- a/hw/ipmi/ipmi_bmc_extern.c
+++ b/hw/ipmi/ipmi_bmc_extern.c
@@ -168,15 +168,15 @@ static void extern_timeout(void *opaque)
static void addchar(IPMIBmcExtern *ibe, unsigned char ch)
{
switch (ch) {
case VM_MSG_CHAR:
case VM_CMD_CHAR:
case VM_ESCAPE_CHAR:
ibe->outbuf[ibe->outlen] = VM_ESCAPE_CHAR;
ibe->outlen++;
ch |= 0x10;
- /* fall through */
+ fallthrough;
default:
ibe->outbuf[ibe->outlen] = ch;
ibe->outlen++;
}
}
diff --git a/hw/ipmi/smbus_ipmi.c b/hw/ipmi/smbus_ipmi.c
index d0991ab7f9..58f5328a19 100644
--- a/hw/ipmi/smbus_ipmi.c
+++ b/hw/ipmi/smbus_ipmi.c
@@ -207,90 +207,90 @@ static int ipmi_load_readbuf(SMBusIPMIDevice *sid)
static int ipmi_write_data(SMBusDevice *dev, uint8_t *buf, uint8_t len)
{
SMBusIPMIDevice *sid = SMBUS_IPMI(dev);
bool send = false;
uint8_t cmd;
int ret = 0;
/* length is guaranteed to be >= 1. */
cmd = *buf++;
len--;
/* Handle read request, which don't have any data in the write part. */
switch (cmd) {
case SSIF_IPMI_RESPONSE:
sid->currblk = 0;
ret = ipmi_load_readbuf(sid);
break;
case SSIF_IPMI_MULTI_PART_RESPONSE_MIDDLE:
sid->currblk++;
ret = ipmi_load_readbuf(sid);
break;
case SSIF_IPMI_MULTI_PART_RETRY:
if (len >= 1) {
sid->currblk = buf[0];
ret = ipmi_load_readbuf(sid);
} else {
ret = -1;
}
break;
default:
break;
}
/* This should be a message write, make the length is there and correct. */
if (len >= 1) {
if (*buf != len - 1 || *buf > MAX_SSIF_IPMI_MSG_CHUNK) {
return -1; /* Bogus message */
}
buf++;
len--;
}
switch (cmd) {
case SSIF_IPMI_REQUEST:
send = true;
- /* FALLTHRU */
+ fallthrough;
case SSIF_IPMI_MULTI_PART_REQUEST_START:
if (len < 2) {
return -1; /* Bogus. */
}
memcpy(sid->inmsg, buf, len);
sid->inlen = len;
break;
case SSIF_IPMI_MULTI_PART_REQUEST_END:
send = true;
- /* FALLTHRU */
+ fallthrough;
case SSIF_IPMI_MULTI_PART_REQUEST_MIDDLE:
if (!sid->inlen) {
return -1; /* Bogus. */
}
if (sid->inlen + len > MAX_SSIF_IPMI_MSG_SIZE) {
sid->inlen = 0; /* Discard the message. */
return -1; /* Bogus. */
}
if (len < 32) {
/*
* Special hack, a multi-part middle that is less than 32 bytes
* marks the end of a message. The specification is fairly
* confusing, so some systems to this, even sending a zero
* length end message to mark the end.
*/
send = true;
}
if (len > 0) {
memcpy(sid->inmsg + sid->inlen, buf, len);
}
sid->inlen += len;
break;
}
if (send && sid->inlen) {
smbus_ipmi_send_msg(sid);
}
return ret;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 64/78] hw/mips: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (62 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 63/78] hw/ipmi: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 65/78] hw/nvme: " Emmanouil Pitsidianakis
` (14 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Paul Burton, Aleksandar Rikalo,
Philippe Mathieu-Daudé, Jiaxun Yang
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/mips/boston.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 4e11ff6cd6..4ca53b790a 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -164,27 +164,27 @@ static void boston_lcd_event(void *opaque, QEMUChrEvent event)
static uint64_t boston_lcd_read(void *opaque, hwaddr addr,
unsigned size)
{
BostonState *s = opaque;
uint64_t val = 0;
switch (size) {
case 8:
val |= (uint64_t)s->lcd_content[(addr + 7) & 0x7] << 56;
val |= (uint64_t)s->lcd_content[(addr + 6) & 0x7] << 48;
val |= (uint64_t)s->lcd_content[(addr + 5) & 0x7] << 40;
val |= (uint64_t)s->lcd_content[(addr + 4) & 0x7] << 32;
- /* fall through */
+ fallthrough;
case 4:
val |= (uint64_t)s->lcd_content[(addr + 3) & 0x7] << 24;
val |= (uint64_t)s->lcd_content[(addr + 2) & 0x7] << 16;
- /* fall through */
+ fallthrough;
case 2:
val |= (uint64_t)s->lcd_content[(addr + 1) & 0x7] << 8;
- /* fall through */
+ fallthrough;
case 1:
val |= (uint64_t)s->lcd_content[(addr + 0) & 0x7];
break;
}
return val;
}
@@ -192,27 +192,27 @@ static uint64_t boston_lcd_read(void *opaque, hwaddr addr,
static void boston_lcd_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
BostonState *s = opaque;
switch (size) {
case 8:
s->lcd_content[(addr + 7) & 0x7] = val >> 56;
s->lcd_content[(addr + 6) & 0x7] = val >> 48;
s->lcd_content[(addr + 5) & 0x7] = val >> 40;
s->lcd_content[(addr + 4) & 0x7] = val >> 32;
- /* fall through */
+ fallthrough;
case 4:
s->lcd_content[(addr + 3) & 0x7] = val >> 24;
s->lcd_content[(addr + 2) & 0x7] = val >> 16;
- /* fall through */
+ fallthrough;
case 2:
s->lcd_content[(addr + 1) & 0x7] = val >> 8;
- /* fall through */
+ fallthrough;
case 1:
s->lcd_content[(addr + 0) & 0x7] = val;
break;
}
qemu_chr_fe_printf(&s->lcd_display,
"\r%-8.8s", s->lcd_content);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 65/78] hw/nvme: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (63 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 64/78] hw/mips: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 66/78] hw/nvram/eeprom_at24c.c: " Emmanouil Pitsidianakis
` (13 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Keith Busch, Klaus Jensen,
open list:nvme
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/nvme/ctrl.c | 24 ++++++++++++------------
hw/nvme/dif.c | 4 ++--
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index f026245d1e..acb2012fb9 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -1912,29 +1912,29 @@ static uint16_t nvme_check_zone_read(NvmeNamespace *ns, uint64_t slba,
static uint16_t nvme_zrm_finish(NvmeNamespace *ns, NvmeZone *zone)
{
switch (nvme_get_zone_state(zone)) {
case NVME_ZONE_STATE_FULL:
return NVME_SUCCESS;
case NVME_ZONE_STATE_IMPLICITLY_OPEN:
case NVME_ZONE_STATE_EXPLICITLY_OPEN:
nvme_aor_dec_open(ns);
- /* fallthrough */
+ fallthrough;
case NVME_ZONE_STATE_CLOSED:
nvme_aor_dec_active(ns);
if (zone->d.za & NVME_ZA_ZRWA_VALID) {
zone->d.za &= ~NVME_ZA_ZRWA_VALID;
if (ns->params.numzrwa) {
ns->zns.numzrwa++;
}
}
- /* fallthrough */
+ fallthrough;
case NVME_ZONE_STATE_EMPTY:
nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_FULL);
return NVME_SUCCESS;
default:
return NVME_ZONE_INVAL_TRANSITION;
}
}
@@ -1942,15 +1942,15 @@ static uint16_t nvme_zrm_finish(NvmeNamespace *ns, NvmeZone *zone)
static uint16_t nvme_zrm_close(NvmeNamespace *ns, NvmeZone *zone)
{
switch (nvme_get_zone_state(zone)) {
case NVME_ZONE_STATE_EXPLICITLY_OPEN:
case NVME_ZONE_STATE_IMPLICITLY_OPEN:
nvme_aor_dec_open(ns);
nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_CLOSED);
- /* fall through */
+ fallthrough;
case NVME_ZONE_STATE_CLOSED:
return NVME_SUCCESS;
default:
return NVME_ZONE_INVAL_TRANSITION;
}
}
@@ -1958,29 +1958,29 @@ static uint16_t nvme_zrm_close(NvmeNamespace *ns, NvmeZone *zone)
static uint16_t nvme_zrm_reset(NvmeNamespace *ns, NvmeZone *zone)
{
switch (nvme_get_zone_state(zone)) {
case NVME_ZONE_STATE_EXPLICITLY_OPEN:
case NVME_ZONE_STATE_IMPLICITLY_OPEN:
nvme_aor_dec_open(ns);
- /* fallthrough */
+ fallthrough;
case NVME_ZONE_STATE_CLOSED:
nvme_aor_dec_active(ns);
if (zone->d.za & NVME_ZA_ZRWA_VALID) {
if (ns->params.numzrwa) {
ns->zns.numzrwa++;
}
}
- /* fallthrough */
+ fallthrough;
case NVME_ZONE_STATE_FULL:
zone->w_ptr = zone->d.zslba;
zone->d.wp = zone->w_ptr;
nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_EMPTY);
- /* fallthrough */
+ fallthrough;
case NVME_ZONE_STATE_EMPTY:
return NVME_SUCCESS;
default:
return NVME_ZONE_INVAL_TRANSITION;
}
}
@@ -2010,57 +2010,57 @@ enum {
static uint16_t nvme_zrm_open_flags(NvmeCtrl *n, NvmeNamespace *ns,
NvmeZone *zone, int flags)
{
int act = 0;
uint16_t status;
switch (nvme_get_zone_state(zone)) {
case NVME_ZONE_STATE_EMPTY:
act = 1;
- /* fallthrough */
+ fallthrough;
case NVME_ZONE_STATE_CLOSED:
if (n->params.auto_transition_zones) {
nvme_zrm_auto_transition_zone(ns);
}
status = nvme_zns_check_resources(ns, act, 1,
(flags & NVME_ZRM_ZRWA) ? 1 : 0);
if (status) {
return status;
}
if (act) {
nvme_aor_inc_active(ns);
}
nvme_aor_inc_open(ns);
if (flags & NVME_ZRM_AUTO) {
nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_IMPLICITLY_OPEN);
return NVME_SUCCESS;
}
- /* fallthrough */
+ fallthrough;
case NVME_ZONE_STATE_IMPLICITLY_OPEN:
if (flags & NVME_ZRM_AUTO) {
return NVME_SUCCESS;
}
nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_EXPLICITLY_OPEN);
- /* fallthrough */
+ fallthrough;
case NVME_ZONE_STATE_EXPLICITLY_OPEN:
if (flags & NVME_ZRM_ZRWA) {
ns->zns.numzrwa--;
zone->d.za |= NVME_ZA_ZRWA_VALID;
}
return NVME_SUCCESS;
default:
return NVME_ZONE_INVAL_TRANSITION;
}
}
@@ -3508,135 +3508,135 @@ static void nvme_do_write_fdp(NvmeCtrl *n, NvmeRequest *req, uint64_t slba,
static uint16_t nvme_do_write(NvmeCtrl *n, NvmeRequest *req, bool append,
bool wrz)
{
NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
NvmeNamespace *ns = req->ns;
uint64_t slba = le64_to_cpu(rw->slba);
uint32_t nlb = (uint32_t)le16_to_cpu(rw->nlb) + 1;
uint16_t ctrl = le16_to_cpu(rw->control);
uint8_t prinfo = NVME_RW_PRINFO(ctrl);
uint64_t data_size = nvme_l2b(ns, nlb);
uint64_t mapped_size = data_size;
uint64_t data_offset;
NvmeZone *zone;
NvmeZonedResult *res = (NvmeZonedResult *)&req->cqe;
BlockBackend *blk = ns->blkconf.blk;
uint16_t status;
if (nvme_ns_ext(ns)) {
mapped_size += nvme_m2b(ns, nlb);
if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) {
bool pract = prinfo & NVME_PRINFO_PRACT;
if (pract && ns->lbaf.ms == nvme_pi_tuple_size(ns)) {
mapped_size -= nvme_m2b(ns, nlb);
}
}
}
trace_pci_nvme_write(nvme_cid(req), nvme_io_opc_str(rw->opcode),
nvme_nsid(ns), nlb, mapped_size, slba);
if (!wrz) {
status = nvme_check_mdts(n, mapped_size);
if (status) {
goto invalid;
}
}
status = nvme_check_bounds(ns, slba, nlb);
if (status) {
goto invalid;
}
if (ns->params.zoned) {
zone = nvme_get_zone_by_slba(ns, slba);
assert(zone);
if (append) {
bool piremap = !!(ctrl & NVME_RW_PIREMAP);
if (unlikely(zone->d.za & NVME_ZA_ZRWA_VALID)) {
return NVME_INVALID_ZONE_OP | NVME_DNR;
}
if (unlikely(slba != zone->d.zslba)) {
trace_pci_nvme_err_append_not_at_start(slba, zone->d.zslba);
status = NVME_INVALID_FIELD;
goto invalid;
}
if (n->params.zasl &&
data_size > (uint64_t)n->page_size << n->params.zasl) {
trace_pci_nvme_err_zasl(data_size);
return NVME_INVALID_FIELD | NVME_DNR;
}
slba = zone->w_ptr;
rw->slba = cpu_to_le64(slba);
res->slba = cpu_to_le64(slba);
switch (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) {
case NVME_ID_NS_DPS_TYPE_1:
if (!piremap) {
return NVME_INVALID_PROT_INFO | NVME_DNR;
}
- /* fallthrough */
+ fallthrough;
case NVME_ID_NS_DPS_TYPE_2:
if (piremap) {
uint32_t reftag = le32_to_cpu(rw->reftag);
rw->reftag = cpu_to_le32(reftag + (slba - zone->d.zslba));
}
break;
case NVME_ID_NS_DPS_TYPE_3:
if (piremap) {
return NVME_INVALID_PROT_INFO | NVME_DNR;
}
break;
}
}
status = nvme_check_zone_write(ns, zone, slba, nlb);
if (status) {
goto invalid;
}
status = nvme_zrm_auto(n, ns, zone);
if (status) {
goto invalid;
}
if (!(zone->d.za & NVME_ZA_ZRWA_VALID)) {
zone->w_ptr += nlb;
}
} else if (ns->endgrp && ns->endgrp->fdp.enabled) {
nvme_do_write_fdp(n, req, slba, nlb);
}
data_offset = nvme_l2b(ns, slba);
if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) {
return nvme_dif_rw(n, req);
}
if (!wrz) {
status = nvme_map_data(n, nlb, req);
if (status) {
goto invalid;
}
block_acct_start(blk_get_stats(blk), &req->acct, data_size,
BLOCK_ACCT_WRITE);
nvme_blk_write(blk, data_offset, BDRV_SECTOR_SIZE, nvme_rw_cb, req);
} else {
req->aiocb = blk_aio_pwrite_zeroes(blk, data_offset, data_size,
BDRV_REQ_MAY_UNMAP, nvme_rw_cb,
req);
}
return NVME_NO_COMPLETE;
@@ -3734,13 +3734,13 @@ static uint16_t nvme_finish_zone(NvmeNamespace *ns, NvmeZone *zone,
static uint16_t nvme_offline_zone(NvmeNamespace *ns, NvmeZone *zone,
NvmeZoneState state, NvmeRequest *req)
{
switch (state) {
case NVME_ZONE_STATE_READ_ONLY:
nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_OFFLINE);
- /* fall through */
+ fallthrough;
case NVME_ZONE_STATE_OFFLINE:
return NVME_SUCCESS;
default:
return NVME_ZONE_INVAL_TRANSITION;
}
}
@@ -4902,39 +4902,39 @@ static uint16_t nvme_changed_nslist(NvmeCtrl *n, uint8_t rae, uint32_t buf_len,
static uint16_t nvme_cmd_effects(NvmeCtrl *n, uint8_t csi, uint32_t buf_len,
uint64_t off, NvmeRequest *req)
{
NvmeEffectsLog log = {};
const uint32_t *src_iocs = NULL;
uint32_t trans_len;
if (off >= sizeof(log)) {
trace_pci_nvme_err_invalid_log_page_offset(off, sizeof(log));
return NVME_INVALID_FIELD | NVME_DNR;
}
switch (NVME_CC_CSS(ldl_le_p(&n->bar.cc))) {
case NVME_CC_CSS_NVM:
src_iocs = nvme_cse_iocs_nvm;
- /* fall through */
+ fallthrough;
case NVME_CC_CSS_ADMIN_ONLY:
break;
case NVME_CC_CSS_CSI:
switch (csi) {
case NVME_CSI_NVM:
src_iocs = nvme_cse_iocs_nvm;
break;
case NVME_CSI_ZONED:
src_iocs = nvme_cse_iocs_zoned;
break;
}
}
memcpy(log.acs, nvme_cse_acs, sizeof(nvme_cse_acs));
if (src_iocs) {
memcpy(log.iocs, src_iocs, sizeof(log.iocs));
}
trans_len = MIN(sizeof(log) - off, buf_len);
return nvme_c2h(n, ((uint8_t *)&log) + off, trans_len, req);
}
diff --git a/hw/nvme/dif.c b/hw/nvme/dif.c
index 01b19c3373..00dd96bdb3 100644
--- a/hw/nvme/dif.c
+++ b/hw/nvme/dif.c
@@ -153,58 +153,58 @@ void nvme_dif_pract_generate_dif(NvmeNamespace *ns, uint8_t *buf, size_t len,
static uint16_t nvme_dif_prchk_crc16(NvmeNamespace *ns, NvmeDifTuple *dif,
uint8_t *buf, uint8_t *mbuf, size_t pil,
uint8_t prinfo, uint16_t apptag,
uint16_t appmask, uint64_t reftag)
{
switch (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) {
case NVME_ID_NS_DPS_TYPE_3:
if (be32_to_cpu(dif->g16.reftag) != 0xffffffff) {
break;
}
- /* fallthrough */
+ fallthrough;
case NVME_ID_NS_DPS_TYPE_1:
case NVME_ID_NS_DPS_TYPE_2:
if (be16_to_cpu(dif->g16.apptag) != 0xffff) {
break;
}
trace_pci_nvme_dif_prchk_disabled_crc16(be16_to_cpu(dif->g16.apptag),
be32_to_cpu(dif->g16.reftag));
return NVME_SUCCESS;
}
if (prinfo & NVME_PRINFO_PRCHK_GUARD) {
uint16_t crc = crc16_t10dif(0x0, buf, ns->lbasz);
if (pil) {
crc = crc16_t10dif(crc, mbuf, pil);
}
trace_pci_nvme_dif_prchk_guard_crc16(be16_to_cpu(dif->g16.guard), crc);
if (be16_to_cpu(dif->g16.guard) != crc) {
return NVME_E2E_GUARD_ERROR;
}
}
if (prinfo & NVME_PRINFO_PRCHK_APP) {
trace_pci_nvme_dif_prchk_apptag(be16_to_cpu(dif->g16.apptag), apptag,
appmask);
if ((be16_to_cpu(dif->g16.apptag) & appmask) != (apptag & appmask)) {
return NVME_E2E_APP_ERROR;
}
}
if (prinfo & NVME_PRINFO_PRCHK_REF) {
trace_pci_nvme_dif_prchk_reftag_crc16(be32_to_cpu(dif->g16.reftag),
reftag);
if (be32_to_cpu(dif->g16.reftag) != reftag) {
return NVME_E2E_REF_ERROR;
}
}
return NVME_SUCCESS;
}
@@ -212,66 +212,66 @@ static uint16_t nvme_dif_prchk_crc16(NvmeNamespace *ns, NvmeDifTuple *dif,
static uint16_t nvme_dif_prchk_crc64(NvmeNamespace *ns, NvmeDifTuple *dif,
uint8_t *buf, uint8_t *mbuf, size_t pil,
uint8_t prinfo, uint16_t apptag,
uint16_t appmask, uint64_t reftag)
{
uint64_t r = 0;
r |= (uint64_t)dif->g64.sr[0] << 40;
r |= (uint64_t)dif->g64.sr[1] << 32;
r |= (uint64_t)dif->g64.sr[2] << 24;
r |= (uint64_t)dif->g64.sr[3] << 16;
r |= (uint64_t)dif->g64.sr[4] << 8;
r |= (uint64_t)dif->g64.sr[5];
switch (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) {
case NVME_ID_NS_DPS_TYPE_3:
if (r != 0xffffffffffff) {
break;
}
- /* fallthrough */
+ fallthrough;
case NVME_ID_NS_DPS_TYPE_1:
case NVME_ID_NS_DPS_TYPE_2:
if (be16_to_cpu(dif->g64.apptag) != 0xffff) {
break;
}
trace_pci_nvme_dif_prchk_disabled_crc64(be16_to_cpu(dif->g16.apptag),
r);
return NVME_SUCCESS;
}
if (prinfo & NVME_PRINFO_PRCHK_GUARD) {
uint64_t crc = crc64_nvme(~0ULL, buf, ns->lbasz);
if (pil) {
crc = crc64_nvme(~crc, mbuf, pil);
}
trace_pci_nvme_dif_prchk_guard_crc64(be64_to_cpu(dif->g64.guard), crc);
if (be64_to_cpu(dif->g64.guard) != crc) {
return NVME_E2E_GUARD_ERROR;
}
}
if (prinfo & NVME_PRINFO_PRCHK_APP) {
trace_pci_nvme_dif_prchk_apptag(be16_to_cpu(dif->g64.apptag), apptag,
appmask);
if ((be16_to_cpu(dif->g64.apptag) & appmask) != (apptag & appmask)) {
return NVME_E2E_APP_ERROR;
}
}
if (prinfo & NVME_PRINFO_PRCHK_REF) {
trace_pci_nvme_dif_prchk_reftag_crc64(r, reftag);
if (r != reftag) {
return NVME_E2E_REF_ERROR;
}
}
return NVME_SUCCESS;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 66/78] hw/nvram/eeprom_at24c.c: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (64 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 65/78] hw/nvme: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 67/78] hw/pci-host/pnv_phb3.c: " Emmanouil Pitsidianakis
` (12 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/nvram/eeprom_at24c.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c
index 3272068663..aa3685db33 100644
--- a/hw/nvram/eeprom_at24c.c
+++ b/hw/nvram/eeprom_at24c.c
@@ -66,28 +66,28 @@ static
int at24c_eeprom_event(I2CSlave *s, enum i2c_event event)
{
EEPROMState *ee = AT24C_EE(s);
switch (event) {
case I2C_START_SEND:
case I2C_FINISH:
ee->haveaddr = 0;
- /* fallthrough */
+ fallthrough;
case I2C_START_RECV:
DPRINTK("clear\n");
if (ee->blk && ee->changed) {
int ret = blk_pwrite(ee->blk, 0, ee->rsize, ee->mem, 0);
if (ret < 0) {
ERR(TYPE_AT24C_EE
" : failed to write backing file\n");
}
DPRINTK("Wrote to backing file\n");
}
ee->changed = false;
break;
case I2C_NACK:
break;
default:
return -1;
}
return 0;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 67/78] hw/pci-host/pnv_phb3.c: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (65 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 66/78] hw/nvram/eeprom_at24c.c: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 68/78] hw/pci: " Emmanouil Pitsidianakis
` (11 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Cédric Le Goater, Nicholas Piggin,
Frédéric Barrat
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/pci-host/pnv_phb3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
index c5e58f4086..6a805d3900 100644
--- a/hw/pci-host/pnv_phb3.c
+++ b/hw/pci-host/pnv_phb3.c
@@ -470,121 +470,121 @@ static void pnv_phb3_update_all_msi_regions(PnvPHB3 *phb)
void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size)
{
PnvPHB3 *phb = opaque;
bool changed;
/* Special case configuration data */
if ((off & 0xfffc) == PHB_CONFIG_DATA) {
pnv_phb3_config_write(phb, off & 0x3, size, val);
return;
}
/* Other registers are 64-bit only */
if (size != 8 || off & 0x7) {
phb3_error(phb, "Invalid register access, offset: 0x%"PRIx64" size: %d",
off, size);
return;
}
/* Handle masking & filtering */
switch (off) {
case PHB_M64_UPPER_BITS:
val &= 0xfffc000000000000ull;
break;
case PHB_Q_DMA_R:
/*
* This is enough logic to make SW happy but we aren't actually
* quiescing the DMAs
*/
if (val & PHB_Q_DMA_R_AUTORESET) {
val = 0;
} else {
val &= PHB_Q_DMA_R_QUIESCE_DMA;
}
break;
/* LEM stuff */
case PHB_LEM_FIR_AND_MASK:
phb->regs[PHB_LEM_FIR_ACCUM >> 3] &= val;
return;
case PHB_LEM_FIR_OR_MASK:
phb->regs[PHB_LEM_FIR_ACCUM >> 3] |= val;
return;
case PHB_LEM_ERROR_AND_MASK:
phb->regs[PHB_LEM_ERROR_MASK >> 3] &= val;
return;
case PHB_LEM_ERROR_OR_MASK:
phb->regs[PHB_LEM_ERROR_MASK >> 3] |= val;
return;
case PHB_LEM_WOF:
val = 0;
break;
}
/* Record whether it changed */
changed = phb->regs[off >> 3] != val;
/* Store in register cache first */
phb->regs[off >> 3] = val;
/* Handle side effects */
switch (off) {
case PHB_PHB3_CONFIG:
if (changed) {
pnv_phb3_update_all_msi_regions(phb);
}
- /* fall through */
+ fallthrough;
case PHB_M32_BASE_ADDR:
case PHB_M32_BASE_MASK:
case PHB_M32_START_ADDR:
if (changed) {
pnv_phb3_check_m32(phb);
}
break;
case PHB_M64_UPPER_BITS:
if (changed) {
pnv_phb3_check_all_m64s(phb);
}
break;
case PHB_LSI_SOURCE_ID:
if (changed) {
pnv_phb3_lsi_src_id_write(phb, val);
}
break;
/* IODA table accesses */
case PHB_IODA_DATA0:
pnv_phb3_ioda_write(phb, val);
break;
/* RTC invalidation */
case PHB_RTC_INVALIDATE:
pnv_phb3_rtc_invalidate(phb, val);
break;
/* FFI request */
case PHB_FFI_REQUEST:
pnv_phb3_msi_ffi(&phb->msis, val);
break;
/* Silent simple writes */
case PHB_CONFIG_ADDRESS:
case PHB_IODA_ADDR:
case PHB_TCE_KILL:
case PHB_TCE_SPEC_CTL:
case PHB_PEST_BAR:
case PHB_PELTV_BAR:
case PHB_RTT_BAR:
case PHB_RBA_BAR:
case PHB_IVT_BAR:
case PHB_FFI_LOCK:
case PHB_LEM_FIR_ACCUM:
case PHB_LEM_ERROR_MASK:
case PHB_LEM_ACTION0:
case PHB_LEM_ACTION1:
break;
/* Noise on anything else */
default:
qemu_log_mask(LOG_UNIMP, "phb3: reg_write 0x%"PRIx64"=%"PRIx64"\n",
off, val);
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 68/78] hw/pci: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (66 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 67/78] hw/pci-host/pnv_phb3.c: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 69/78] hw/rdma/rdma_backend.c: " Emmanouil Pitsidianakis
` (10 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Michael S. Tsirkin, Marcel Apfelbaum,
Huai-Cheng Kuo, Chris Browy
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/pci/pcie_aer.c | 3 ++-
hw/pci/pcie_doe.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c
index b68c7ecb49..c99ecce2a1 100644
--- a/hw/pci/pcie_aer.c
+++ b/hw/pci/pcie_aer.c
@@ -97,71 +97,72 @@ static void aer_log_clear_all_err(PCIEAERLog *aer_log)
int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset,
uint16_t size, Error **errp)
{
pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, cap_ver,
offset, size);
dev->exp.aer_cap = offset;
/* clip down the value to avoid unreasonable memory usage */
if (dev->exp.aer_log.log_max > PCIE_AER_LOG_MAX_LIMIT) {
error_setg(errp, "Invalid aer_log_max %d. The max number of aer log "
"is %d", dev->exp.aer_log.log_max, PCIE_AER_LOG_MAX_LIMIT);
return -EINVAL;
}
dev->exp.aer_log.log = g_malloc0(sizeof dev->exp.aer_log.log[0] *
dev->exp.aer_log.log_max);
pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS,
PCI_ERR_UNC_SUPPORTED);
if (dev->cap_present & QEMU_PCIE_ERR_UNC_MASK) {
pci_set_long(dev->config + offset + PCI_ERR_UNCOR_MASK,
PCI_ERR_UNC_MASK_DEFAULT);
pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_MASK,
PCI_ERR_UNC_SUPPORTED);
}
pci_set_long(dev->config + offset + PCI_ERR_UNCOR_SEVER,
PCI_ERR_UNC_SEVERITY_DEFAULT);
pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_SEVER,
PCI_ERR_UNC_SUPPORTED);
pci_long_test_and_set_mask(dev->w1cmask + offset + PCI_ERR_COR_STATUS,
PCI_ERR_COR_SUPPORTED);
pci_set_long(dev->config + offset + PCI_ERR_COR_MASK,
PCI_ERR_COR_MASK_DEFAULT);
pci_set_long(dev->wmask + offset + PCI_ERR_COR_MASK,
PCI_ERR_COR_SUPPORTED);
/* capabilities and control. multiple header logging is supported */
if (dev->exp.aer_log.log_max > 0) {
pci_set_long(dev->config + offset + PCI_ERR_CAP,
PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_CHKC |
PCI_ERR_CAP_MHRC);
pci_set_long(dev->wmask + offset + PCI_ERR_CAP,
PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE |
PCI_ERR_CAP_MHRE);
} else {
pci_set_long(dev->config + offset + PCI_ERR_CAP,
PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_CHKC);
pci_set_long(dev->wmask + offset + PCI_ERR_CAP,
PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
}
switch (pcie_cap_get_type(dev)) {
case PCI_EXP_TYPE_ROOT_PORT:
/* this case will be set by pcie_aer_root_init() */
- /* fallthrough */
+ fallthrough;
case PCI_EXP_TYPE_DOWNSTREAM:
+ fallthrough;
case PCI_EXP_TYPE_UPSTREAM:
pci_word_test_and_set_mask(dev->wmask + PCI_BRIDGE_CONTROL,
PCI_BRIDGE_CTL_SERR);
pci_long_test_and_set_mask(dev->w1cmask + PCI_STATUS,
PCI_SEC_STATUS_RCV_SYSTEM_ERROR);
break;
default:
/* nothing */
break;
}
return 0;
}
diff --git a/hw/pci/pcie_doe.c b/hw/pci/pcie_doe.c
index 2210f86968..f04a36e664 100644
--- a/hw/pci/pcie_doe.c
+++ b/hw/pci/pcie_doe.c
@@ -295,73 +295,73 @@ bool pcie_doe_read_config(DOECap *doe_cap, uint32_t addr, int size,
/*
* Write to DOE config space.
* Return if the address not within DOE_CAP range or receives an abort
*/
void pcie_doe_write_config(DOECap *doe_cap,
uint32_t addr, uint32_t val, int size)
{
uint16_t doe_offset = doe_cap->offset;
uint32_t shift;
if (!range_covers_byte(doe_offset + PCI_EXP_DOE_CAP,
PCI_DOE_SIZEOF - 4, addr)) {
return;
}
/* Process Alignment */
shift = addr % DWORD_BYTE;
addr -= (doe_offset + shift);
val = deposit32(val, shift * 8, size * 8, val);
switch (addr) {
case PCI_EXP_DOE_CTRL:
if (FIELD_EX32(val, PCI_DOE_CAP_CONTROL, DOE_ABORT)) {
pcie_doe_set_ready(doe_cap, 0);
pcie_doe_set_error(doe_cap, 0);
pcie_doe_reset_mbox(doe_cap);
return;
}
if (FIELD_EX32(val, PCI_DOE_CAP_CONTROL, DOE_GO)) {
pcie_doe_prepare_rsp(doe_cap);
}
if (FIELD_EX32(val, PCI_DOE_CAP_CONTROL, DOE_INTR_EN)) {
doe_cap->ctrl.intr = 1;
/* Clear interrupt bit located within the first byte */
} else if (shift == 0) {
doe_cap->ctrl.intr = 0;
}
break;
case PCI_EXP_DOE_STATUS:
if (FIELD_EX32(val, PCI_DOE_CAP_STATUS, DOE_INTR_STATUS)) {
doe_cap->status.intr = 0;
}
break;
case PCI_EXP_DOE_RD_DATA_MBOX:
/* Mailbox should be DW accessed */
if (size != DWORD_BYTE) {
return;
}
doe_cap->read_mbox_idx++;
if (doe_cap->read_mbox_idx == doe_cap->read_mbox_len) {
pcie_doe_reset_mbox(doe_cap);
pcie_doe_set_ready(doe_cap, 0);
} else if (doe_cap->read_mbox_idx > doe_cap->read_mbox_len) {
/* Underflow */
pcie_doe_set_error(doe_cap, 1);
}
break;
case PCI_EXP_DOE_WR_DATA_MBOX:
/* Mailbox should be DW accessed */
if (size != DWORD_BYTE) {
return;
}
doe_cap->write_mbox[doe_cap->write_mbox_len] = val;
doe_cap->write_mbox_len++;
break;
case PCI_EXP_DOE_CAP:
- /* fallthrough */
+ fallthrough;
default:
break;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 69/78] hw/rdma/rdma_backend.c: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (67 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 68/78] hw/pci: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 70/78] hw/rtc: " Emmanouil Pitsidianakis
` (9 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Yuval Shaia, Marcel Apfelbaum
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/rdma/rdma_backend.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/rdma/rdma_backend.c b/hw/rdma/rdma_backend.c
index 6dcdfbbbe2..09e5ad961e 100644
--- a/hw/rdma/rdma_backend.c
+++ b/hw/rdma/rdma_backend.c
@@ -800,50 +800,50 @@ void rdma_backend_destroy_cq(RdmaBackendCQ *cq)
int rdma_backend_create_qp(RdmaBackendQP *qp, uint8_t qp_type,
RdmaBackendPD *pd, RdmaBackendCQ *scq,
RdmaBackendCQ *rcq, RdmaBackendSRQ *srq,
uint32_t max_send_wr, uint32_t max_recv_wr,
uint32_t max_send_sge, uint32_t max_recv_sge)
{
struct ibv_qp_init_attr attr = {};
qp->ibqp = 0;
switch (qp_type) {
case IBV_QPT_GSI:
return 0;
case IBV_QPT_RC:
- /* fall through */
+ fallthrough;
case IBV_QPT_UD:
/* do nothing */
break;
default:
rdma_error_report("Unsupported QP type %d", qp_type);
return -EIO;
}
attr.qp_type = qp_type;
attr.send_cq = scq->ibcq;
attr.recv_cq = rcq->ibcq;
attr.cap.max_send_wr = max_send_wr;
attr.cap.max_recv_wr = max_recv_wr;
attr.cap.max_send_sge = max_send_sge;
attr.cap.max_recv_sge = max_recv_sge;
if (srq) {
attr.srq = srq->ibsrq;
}
qp->ibqp = ibv_create_qp(pd->ibpd, &attr);
if (!qp->ibqp) {
rdma_error_report("ibv_create_qp fail, errno=%d", errno);
return -EIO;
}
rdma_protected_gslist_init(&qp->cqe_ctx_list);
qp->ibpd = pd->ibpd;
/* TODO: Query QP to get max_inline_data and save it to be used in send */
return 0;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 70/78] hw/rtc: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (68 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 69/78] hw/rdma/rdma_backend.c: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 71/78] hw/s390x: " Emmanouil Pitsidianakis
` (8 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Cédric Le Goater, Peter Maydell,
Andrew Jeffery, Joel Stanley, Michael S. Tsirkin, Paolo Bonzini,
open list:ASPEED BMCs
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/rtc/aspeed_rtc.c | 4 ++--
hw/rtc/mc146818rtc.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c
index fa861e2d49..59c64b01b9 100644
--- a/hw/rtc/aspeed_rtc.c
+++ b/hw/rtc/aspeed_rtc.c
@@ -68,28 +68,28 @@ static uint32_t aspeed_rtc_get_counter(AspeedRtcState *rtc, int r)
static uint64_t aspeed_rtc_read(void *opaque, hwaddr addr,
unsigned size)
{
AspeedRtcState *rtc = opaque;
uint64_t val;
uint32_t r = addr >> 2;
switch (r) {
case COUNTER1:
case COUNTER2:
if (rtc->reg[CONTROL] & RTC_ENABLED) {
rtc->reg[r] = aspeed_rtc_get_counter(rtc, r);
}
- /* fall through */
+ fallthrough;
case CONTROL:
val = rtc->reg[r];
break;
case ALARM:
case ALARM_STATUS:
default:
qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx "\n", __func__, addr);
return 0;
}
trace_aspeed_rtc_read(addr, val);
return val;
}
@@ -97,25 +97,25 @@ static uint64_t aspeed_rtc_read(void *opaque, hwaddr addr,
static void aspeed_rtc_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
AspeedRtcState *rtc = opaque;
uint32_t r = addr >> 2;
switch (r) {
case COUNTER1:
case COUNTER2:
if (!(rtc->reg[CONTROL] & RTC_UNLOCKED)) {
break;
}
- /* fall through */
+ fallthrough;
case CONTROL:
rtc->reg[r] = val;
aspeed_rtc_calc_offset(rtc);
break;
case ALARM:
case ALARM_STATUS:
default:
qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx "\n", __func__, addr);
break;
}
trace_aspeed_rtc_write(addr, val);
}
diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c
index c27c362db9..6b6eef94fd 100644
--- a/hw/rtc/mc146818rtc.c
+++ b/hw/rtc/mc146818rtc.c
@@ -439,120 +439,120 @@ static void rtc_update_timer(void *opaque)
static void cmos_ioport_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
MC146818RtcState *s = opaque;
uint32_t old_period;
bool update_periodic_timer;
if ((addr & 1) == 0) {
s->cmos_index = data & 0x7f;
} else {
CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02" PRIx64 "\n",
s->cmos_index, data);
switch(s->cmos_index) {
case RTC_SECONDS_ALARM:
case RTC_MINUTES_ALARM:
case RTC_HOURS_ALARM:
s->cmos_data[s->cmos_index] = data;
check_update_timer(s);
break;
case RTC_IBM_PS2_CENTURY_BYTE:
s->cmos_index = RTC_CENTURY;
- /* fall through */
+ fallthrough;
case RTC_CENTURY:
case RTC_SECONDS:
case RTC_MINUTES:
case RTC_HOURS:
case RTC_DAY_OF_WEEK:
case RTC_DAY_OF_MONTH:
case RTC_MONTH:
case RTC_YEAR:
s->cmos_data[s->cmos_index] = data;
/* if in set mode, do not update the time */
if (rtc_running(s)) {
rtc_set_time(s);
check_update_timer(s);
}
break;
case RTC_REG_A:
update_periodic_timer = (s->cmos_data[RTC_REG_A] ^ data) & 0x0f;
old_period = rtc_periodic_clock_ticks(s);
if ((data & 0x60) == 0x60) {
if (rtc_running(s)) {
rtc_update_time(s);
}
/* What happens to UIP when divider reset is enabled is
* unclear from the datasheet. Shouldn't matter much
* though.
*/
s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
} else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) &&
(data & 0x70) <= 0x20) {
/* when the divider reset is removed, the first update cycle
* begins one-half second later*/
if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
s->offset = 500000000;
rtc_set_time(s);
}
s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
}
/* UIP bit is read only */
s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
(s->cmos_data[RTC_REG_A] & REG_A_UIP);
if (update_periodic_timer) {
periodic_timer_update(s, qemu_clock_get_ns(rtc_clock),
old_period, true);
}
check_update_timer(s);
break;
case RTC_REG_B:
update_periodic_timer = (s->cmos_data[RTC_REG_B] ^ data)
& REG_B_PIE;
old_period = rtc_periodic_clock_ticks(s);
if (data & REG_B_SET) {
/* update cmos to when the rtc was stopping */
if (rtc_running(s)) {
rtc_update_time(s);
}
/* set mode: reset UIP mode */
s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
data &= ~REG_B_UIE;
} else {
/* if disabling set mode, update the time */
if ((s->cmos_data[RTC_REG_B] & REG_B_SET) &&
(s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) {
s->offset = get_guest_rtc_ns(s) % NANOSECONDS_PER_SECOND;
rtc_set_time(s);
}
}
/* if an interrupt flag is already set when the interrupt
* becomes enabled, raise an interrupt immediately. */
if (data & s->cmos_data[RTC_REG_C] & REG_C_MASK) {
s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
qemu_irq_raise(s->irq);
} else {
s->cmos_data[RTC_REG_C] &= ~REG_C_IRQF;
qemu_irq_lower(s->irq);
}
s->cmos_data[RTC_REG_B] = data;
if (update_periodic_timer) {
periodic_timer_update(s, qemu_clock_get_ns(rtc_clock),
old_period, true);
}
check_update_timer(s);
break;
case RTC_REG_C:
case RTC_REG_D:
/* cannot write to them */
break;
default:
s->cmos_data[s->cmos_index] = data;
break;
}
}
}
@@ -678,63 +678,63 @@ static int update_in_progress(MC146818RtcState *s)
static uint64_t cmos_ioport_read(void *opaque, hwaddr addr,
unsigned size)
{
MC146818RtcState *s = opaque;
int ret;
if ((addr & 1) == 0) {
return 0xff;
} else {
switch(s->cmos_index) {
case RTC_IBM_PS2_CENTURY_BYTE:
s->cmos_index = RTC_CENTURY;
- /* fall through */
+ fallthrough;
case RTC_CENTURY:
case RTC_SECONDS:
case RTC_MINUTES:
case RTC_HOURS:
case RTC_DAY_OF_WEEK:
case RTC_DAY_OF_MONTH:
case RTC_MONTH:
case RTC_YEAR:
/* if not in set mode, calibrate cmos before
* reading*/
if (rtc_running(s)) {
rtc_update_time(s);
}
ret = s->cmos_data[s->cmos_index];
break;
case RTC_REG_A:
ret = s->cmos_data[s->cmos_index];
if (update_in_progress(s)) {
ret |= REG_A_UIP;
}
break;
case RTC_REG_C:
ret = s->cmos_data[s->cmos_index];
qemu_irq_lower(s->irq);
s->cmos_data[RTC_REG_C] = 0x00;
if (ret & (REG_C_UF | REG_C_AF)) {
check_update_timer(s);
}
if(s->irq_coalesced &&
(s->cmos_data[RTC_REG_B] & REG_B_PIE) &&
s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
s->irq_reinject_on_ack_count++;
s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF;
DPRINTF_C("cmos: injecting on ack\n");
if (rtc_policy_slew_deliver_irq(s)) {
s->irq_coalesced--;
DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
s->irq_coalesced);
}
}
break;
default:
ret = s->cmos_data[s->cmos_index];
break;
}
CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
s->cmos_index, ret);
return ret;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 71/78] hw/s390x: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (69 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 70/78] hw/rtc: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 8:03 ` David Hildenbrand
2023-10-13 7:57 ` [RFC PATCH v2 72/78] hw/ssi: " Emmanouil Pitsidianakis
` (7 subsequent siblings)
78 siblings, 1 reply; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Christian Borntraeger, Thomas Huth,
Halil Pasic, Eric Farman, Richard Henderson, David Hildenbrand,
Ilya Leoshkevich, Matthew Rosato, open list:S390-ccw boot
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/s390x/ipl.c | 1 +
hw/s390x/s390-pci-inst.c | 4 ++--
hw/s390x/sclp.c | 4 ++--
3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c
index 515dcf51b5..da2333846f 100644
--- a/hw/s390x/ipl.c
+++ b/hw/s390x/ipl.c
@@ -394,57 +394,58 @@ static CcwDevice *s390_get_ccw_device(DeviceState *dev_st, int *devtype)
static bool s390_gen_initial_iplb(S390IPLState *ipl)
{
DeviceState *dev_st;
CcwDevice *ccw_dev = NULL;
SCSIDevice *sd;
int devtype;
dev_st = get_boot_device(0);
if (dev_st) {
ccw_dev = s390_get_ccw_device(dev_st, &devtype);
}
/*
* Currently allow IPL only from CCW devices.
*/
if (ccw_dev) {
switch (devtype) {
case CCW_DEVTYPE_SCSI:
sd = SCSI_DEVICE(dev_st);
ipl->iplb.len = cpu_to_be32(S390_IPLB_MIN_QEMU_SCSI_LEN);
ipl->iplb.blk0_len =
cpu_to_be32(S390_IPLB_MIN_QEMU_SCSI_LEN - S390_IPLB_HEADER_LEN);
ipl->iplb.pbt = S390_IPL_TYPE_QEMU_SCSI;
ipl->iplb.scsi.lun = cpu_to_be32(sd->lun);
ipl->iplb.scsi.target = cpu_to_be16(sd->id);
ipl->iplb.scsi.channel = cpu_to_be16(sd->channel);
ipl->iplb.scsi.devno = cpu_to_be16(ccw_dev->sch->devno);
ipl->iplb.scsi.ssid = ccw_dev->sch->ssid & 3;
break;
case CCW_DEVTYPE_VFIO:
ipl->iplb.len = cpu_to_be32(S390_IPLB_MIN_CCW_LEN);
ipl->iplb.pbt = S390_IPL_TYPE_CCW;
ipl->iplb.ccw.devno = cpu_to_be16(ccw_dev->sch->devno);
ipl->iplb.ccw.ssid = ccw_dev->sch->ssid & 3;
break;
case CCW_DEVTYPE_VIRTIO_NET:
ipl->netboot = true;
/* Fall through to CCW_DEVTYPE_VIRTIO case */
+ fallthrough;
case CCW_DEVTYPE_VIRTIO:
ipl->iplb.len = cpu_to_be32(S390_IPLB_MIN_CCW_LEN);
ipl->iplb.blk0_len =
cpu_to_be32(S390_IPLB_MIN_CCW_LEN - S390_IPLB_HEADER_LEN);
ipl->iplb.pbt = S390_IPL_TYPE_CCW;
ipl->iplb.ccw.devno = cpu_to_be16(ccw_dev->sch->devno);
ipl->iplb.ccw.ssid = ccw_dev->sch->ssid & 3;
break;
}
if (!s390_ipl_set_loadparm(ipl->iplb.loadparm)) {
ipl->iplb.flags |= DIAG308_FLAGS_LP_VALID;
}
return true;
}
return false;
}
diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
index 30149546c0..171320384c 100644
--- a/hw/s390x/s390-pci-inst.c
+++ b/hw/s390x/s390-pci-inst.c
@@ -1330,83 +1330,83 @@ int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
uintptr_t ra)
{
CPUS390XState *env = &cpu->env;
uint8_t dmaas;
uint32_t fh;
ZpciFib fib;
S390PCIBusDevice *pbdev;
uint32_t data;
uint64_t cc = ZPCI_PCI_LS_OK;
if (env->psw.mask & PSW_MASK_PSTATE) {
s390_program_interrupt(env, PGM_PRIVILEGED, ra);
return 0;
}
fh = env->regs[r1] >> 32;
dmaas = (env->regs[r1] >> 16) & 0xff;
if (dmaas) {
setcc(cpu, ZPCI_PCI_LS_ERR);
s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_INVAL_DMAAS);
return 0;
}
if (fiba & 0x7) {
s390_program_interrupt(env, PGM_SPECIFICATION, ra);
return 0;
}
pbdev = s390_pci_find_dev_by_idx(s390_get_phb(), fh & FH_MASK_INDEX);
if (!pbdev) {
setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
return 0;
}
memset(&fib, 0, sizeof(fib));
switch (pbdev->state) {
case ZPCI_FS_RESERVED:
case ZPCI_FS_STANDBY:
setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
return 0;
case ZPCI_FS_DISABLED:
if (fh & FH_MASK_ENABLE) {
setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
return 0;
}
goto out;
/* BLOCKED bit is set to one coincident with the setting of ERROR bit.
* FH Enabled bit is set to one in states of ENABLED, BLOCKED or ERROR. */
case ZPCI_FS_ERROR:
fib.fc |= 0x20;
- /* fallthrough */
+ fallthrough;
case ZPCI_FS_BLOCKED:
fib.fc |= 0x40;
- /* fallthrough */
+ fallthrough;
case ZPCI_FS_ENABLED:
fib.fc |= 0x80;
if (pbdev->iommu->enabled) {
fib.fc |= 0x10;
}
if (!(fh & FH_MASK_ENABLE)) {
env->regs[r1] |= 1ULL << 63;
}
break;
case ZPCI_FS_PERMANENT_ERROR:
setcc(cpu, ZPCI_PCI_LS_ERR);
s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_PERM_ERROR);
return 0;
}
stq_p(&fib.pba, pbdev->iommu->pba);
stq_p(&fib.pal, pbdev->iommu->pal);
stq_p(&fib.iota, pbdev->iommu->g_iota);
stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr);
stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr);
stq_p(&fib.fmb_addr, pbdev->fmb_addr);
data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) |
((uint32_t)pbdev->routes.adapter.ind_offset << 8) |
((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset;
stl_p(&fib.data, data);
diff --git a/hw/s390x/sclp.c b/hw/s390x/sclp.c
index eff74479f4..9b8c7ff043 100644
--- a/hw/s390x/sclp.c
+++ b/hw/s390x/sclp.c
@@ -50,28 +50,28 @@ static inline bool sclp_command_code_valid(uint32_t code)
static bool sccb_verify_boundary(uint64_t sccb_addr, uint16_t sccb_len,
uint32_t code)
{
uint64_t sccb_max_addr = sccb_addr + sccb_len - 1;
uint64_t sccb_boundary = (sccb_addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
switch (code & SCLP_CMD_CODE_MASK) {
case SCLP_CMDW_READ_SCP_INFO:
case SCLP_CMDW_READ_SCP_INFO_FORCED:
case SCLP_CMDW_READ_CPU_INFO:
/*
* An extended-length SCCB is only allowed for Read SCP/CPU Info and
* is allowed to exceed the 4k boundary. The respective commands will
* set the length field to the required length if an insufficient
* SCCB length is provided.
*/
if (s390_has_feat(S390_FEAT_EXTENDED_LENGTH_SCCB)) {
return true;
}
- /* fallthrough */
+ fallthrough;
default:
if (sccb_max_addr < sccb_boundary) {
return true;
}
}
return false;
}
@@ -207,28 +207,28 @@ static void sclp_read_cpu_info(SCLPDevice *sclp, SCCB *sccb)
static void sclp_configure_io_adapter(SCLPDevice *sclp, SCCB *sccb,
bool configure)
{
int rc;
if (be16_to_cpu(sccb->h.length) < 16) {
rc = SCLP_RC_INSUFFICIENT_SCCB_LENGTH;
goto out_err;
}
switch (((IoaCfgSccb *)sccb)->atype) {
case SCLP_RECONFIG_PCI_ATYPE:
if (s390_has_feat(S390_FEAT_ZPCI)) {
if (configure) {
s390_pci_sclp_configure(sccb);
} else {
s390_pci_sclp_deconfigure(sccb);
}
return;
}
- /* fallthrough */
+ fallthrough;
default:
rc = SCLP_RC_ADAPTER_TYPE_NOT_RECOGNIZED;
}
out_err:
sccb->h.response_code = cpu_to_be16(rc);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* Re: [RFC PATCH v2 71/78] hw/s390x: add fallthrough pseudo-keyword
2023-10-13 7:57 ` [RFC PATCH v2 71/78] hw/s390x: " Emmanouil Pitsidianakis
@ 2023-10-13 8:03 ` David Hildenbrand
0 siblings, 0 replies; 91+ messages in thread
From: David Hildenbrand @ 2023-10-13 8:03 UTC (permalink / raw)
To: Emmanouil Pitsidianakis, qemu-devel
Cc: Christian Borntraeger, Thomas Huth, Halil Pasic, Eric Farman,
Richard Henderson, Ilya Leoshkevich, Matthew Rosato,
open list:S390-ccw boot
On 13.10.23 09:57, Emmanouil Pitsidianakis wrote:
> In preparation of raising -Wimplicit-fallthrough to 5, replace all
> fall-through comments with the fallthrough attribute pseudo-keyword.
>
> Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
> ---
Reviewed-by: David Hildenbrand <david@redhat.com>
See Rb's on the other two patches I was CCed in v1.
--
Cheers,
David / dhildenb
^ permalink raw reply [flat|nested] 91+ messages in thread
* [RFC PATCH v2 72/78] hw/ssi: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (70 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 71/78] hw/s390x: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 73/78] hw/watchdog/wdt_diag288.c: " Emmanouil Pitsidianakis
` (6 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Tyrone Ting, Hao Wu, Alistair Francis,
Peter Maydell, open list:Nuvoton NPCM7xx
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/ssi/npcm7xx_fiu.c | 14 ++++++-------
hw/ssi/omap_spi.c | 48 ++++++++++++++++++++++----------------------
2 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
index 4eedb2927e..fadd66a675 100644
--- a/hw/ssi/npcm7xx_fiu.c
+++ b/hw/ssi/npcm7xx_fiu.c
@@ -145,103 +145,103 @@ static void npcm7xx_fiu_deselect(NPCM7xxFIUState *s)
/* Direct flash memory read handler. */
static uint64_t npcm7xx_fiu_flash_read(void *opaque, hwaddr addr,
unsigned int size)
{
NPCM7xxFIUFlash *f = opaque;
NPCM7xxFIUState *fiu = f->fiu;
uint64_t value = 0;
uint32_t drd_cfg;
int dummy_cycles;
int i;
if (fiu->active_cs != -1) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: direct flash read with CS%d already active",
DEVICE(fiu)->canonical_path, fiu->active_cs);
}
npcm7xx_fiu_select(fiu, npcm7xx_fiu_cs_index(fiu, f));
drd_cfg = fiu->regs[NPCM7XX_FIU_DRD_CFG];
ssi_transfer(fiu->spi, FIU_DRD_CFG_RDCMD(drd_cfg));
switch (FIU_DRD_CFG_ADDSIZ(drd_cfg)) {
case FIU_ADDSIZ_4BYTES:
ssi_transfer(fiu->spi, extract32(addr, 24, 8));
- /* fall through */
+ fallthrough;
case FIU_ADDSIZ_3BYTES:
ssi_transfer(fiu->spi, extract32(addr, 16, 8));
ssi_transfer(fiu->spi, extract32(addr, 8, 8));
ssi_transfer(fiu->spi, extract32(addr, 0, 8));
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: bad address size %d\n",
DEVICE(fiu)->canonical_path, FIU_DRD_CFG_ADDSIZ(drd_cfg));
break;
}
/* Flash chip model expects one transfer per dummy bit, not byte */
dummy_cycles =
(FIU_DRD_CFG_DBW(drd_cfg) * 8) >> FIU_DRD_CFG_ACCTYPE(drd_cfg);
for (i = 0; i < dummy_cycles; i++) {
ssi_transfer(fiu->spi, 0);
}
for (i = 0; i < size; i++) {
value = deposit64(value, 8 * i, 8, ssi_transfer(fiu->spi, 0));
}
trace_npcm7xx_fiu_flash_read(DEVICE(fiu)->canonical_path, fiu->active_cs,
addr, size, value);
npcm7xx_fiu_deselect(fiu);
return value;
}
/* Direct flash memory write handler. */
static void npcm7xx_fiu_flash_write(void *opaque, hwaddr addr, uint64_t v,
unsigned int size)
{
NPCM7xxFIUFlash *f = opaque;
NPCM7xxFIUState *fiu = f->fiu;
uint32_t dwr_cfg;
unsigned cs_id;
int i;
if (fiu->active_cs != -1) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: direct flash write with CS%d already active",
DEVICE(fiu)->canonical_path, fiu->active_cs);
}
cs_id = npcm7xx_fiu_cs_index(fiu, f);
trace_npcm7xx_fiu_flash_write(DEVICE(fiu)->canonical_path, cs_id, addr,
size, v);
npcm7xx_fiu_select(fiu, cs_id);
dwr_cfg = fiu->regs[NPCM7XX_FIU_DWR_CFG];
ssi_transfer(fiu->spi, FIU_DWR_CFG_WRCMD(dwr_cfg));
switch (FIU_DWR_CFG_ADDSIZ(dwr_cfg)) {
case FIU_ADDSIZ_4BYTES:
ssi_transfer(fiu->spi, extract32(addr, 24, 8));
- /* fall through */
+ fallthrough;
case FIU_ADDSIZ_3BYTES:
ssi_transfer(fiu->spi, extract32(addr, 16, 8));
ssi_transfer(fiu->spi, extract32(addr, 8, 8));
ssi_transfer(fiu->spi, extract32(addr, 0, 8));
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: bad address size %d\n",
DEVICE(fiu)->canonical_path, FIU_DWR_CFG_ADDSIZ(dwr_cfg));
break;
}
for (i = 0; i < size; i++) {
ssi_transfer(fiu->spi, extract64(v, i * 8, 8));
}
npcm7xx_fiu_deselect(fiu);
}
@@ -282,22 +282,22 @@ static uint64_t npcm7xx_fiu_ctrl_read(void *opaque, hwaddr addr,
/* Send the specified number of address bytes from the UMA address register. */
static void send_address(SSIBus *spi, unsigned int addsiz, uint32_t addr)
{
switch (addsiz) {
case 4:
ssi_transfer(spi, extract32(addr, 24, 8));
- /* fall through */
+ fallthrough;
case 3:
ssi_transfer(spi, extract32(addr, 16, 8));
- /* fall through */
+ fallthrough;
case 2:
ssi_transfer(spi, extract32(addr, 8, 8));
- /* fall through */
+ fallthrough;
case 1:
ssi_transfer(spi, extract32(addr, 0, 8));
- /* fall through */
+ fallthrough;
case 0:
break;
}
}
/* Send the number of dummy bits specified in the UMA config register. */
@@ -378,79 +378,79 @@ static void npcm7xx_fiu_uma_transaction(NPCM7xxFIUState *s)
/* Control register write handler. */
static void npcm7xx_fiu_ctrl_write(void *opaque, hwaddr addr, uint64_t v,
unsigned int size)
{
hwaddr reg = addr / sizeof(uint32_t);
NPCM7xxFIUState *s = opaque;
uint32_t value = v;
trace_npcm7xx_fiu_ctrl_write(DEVICE(s)->canonical_path, addr, value);
switch (reg) {
case NPCM7XX_FIU_UMA_CFG:
if (s->regs[reg] & FIU_UMA_CFG_CMMLCK) {
value &= ~FIU_UMA_CFG_CMMLCK_MASK;
value |= (s->regs[reg] & FIU_UMA_CFG_CMMLCK_MASK);
}
- /* fall through */
+ fallthrough;
case NPCM7XX_FIU_DRD_CFG:
case NPCM7XX_FIU_DWR_CFG:
if (s->regs[reg] & NPCM7XX_FIU_CFG_LCK) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: write to locked register @ 0x%" PRIx64 "\n",
DEVICE(s)->canonical_path, addr);
return;
}
s->regs[reg] = value;
break;
case NPCM7XX_FIU_UMA_CTS:
if (value & FIU_UMA_CTS_RDYST) {
value &= ~FIU_UMA_CTS_RDYST;
} else {
value |= s->regs[reg] & FIU_UMA_CTS_RDYST;
}
if ((s->regs[reg] ^ value) & FIU_UMA_CTS_SW_CS) {
if (value & FIU_UMA_CTS_SW_CS) {
/*
* Don't drop CS if there's a transfer in progress, or we're
* about to start one.
*/
if (!((value | s->regs[reg]) & FIU_UMA_CTS_EXEC_DONE)) {
npcm7xx_fiu_deselect(s);
}
} else {
int cs_id = FIU_UMA_CTS_DEV_NUM(s->regs[NPCM7XX_FIU_UMA_CTS]);
npcm7xx_fiu_select(s, cs_id);
}
}
s->regs[reg] = value | (s->regs[reg] & FIU_UMA_CTS_EXEC_DONE);
if (value & FIU_UMA_CTS_EXEC_DONE) {
npcm7xx_fiu_uma_transaction(s);
}
break;
case NPCM7XX_FIU_UMA_DR0 ... NPCM7XX_FIU_UMA_DR3:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: write to read-only register @ 0x%" PRIx64 "\n",
DEVICE(s)->canonical_path, addr);
return;
case NPCM7XX_FIU_PRT_CFG:
case NPCM7XX_FIU_PRT_CMD0 ... NPCM7XX_FIU_PRT_CMD9:
qemu_log_mask(LOG_UNIMP, "%s: PRT is not implemented\n", __func__);
break;
case NPCM7XX_FIU_UMA_CMD:
case NPCM7XX_FIU_UMA_ADDR:
case NPCM7XX_FIU_UMA_DW0 ... NPCM7XX_FIU_UMA_DW3:
case NPCM7XX_FIU_CFG:
s->regs[reg] = value;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: write to invalid offset 0x%" PRIx64 "\n",
DEVICE(s)->canonical_path, addr);
return;
}
}
diff --git a/hw/ssi/omap_spi.c b/hw/ssi/omap_spi.c
index 8f85c3e391..a0f367bd17 100644
--- a/hw/ssi/omap_spi.c
+++ b/hw/ssi/omap_spi.c
@@ -137,87 +137,87 @@ void omap_mcspi_reset(struct omap_mcspi_s *s)
static uint64_t omap_mcspi_read(void *opaque, hwaddr addr, unsigned size)
{
struct omap_mcspi_s *s = opaque;
int ch = 0;
uint32_t ret;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) {
case 0x00: /* MCSPI_REVISION */
return 0x91;
case 0x10: /* MCSPI_SYSCONFIG */
return s->sysconfig;
case 0x14: /* MCSPI_SYSSTATUS */
return 1; /* RESETDONE */
case 0x18: /* MCSPI_IRQSTATUS */
return s->irqst;
case 0x1c: /* MCSPI_IRQENABLE */
return s->irqen;
case 0x20: /* MCSPI_WAKEUPENABLE */
return s->wken;
case 0x24: /* MCSPI_SYST */
return s->systest;
case 0x28: /* MCSPI_MODULCTRL */
return s->control;
case 0x68: ch ++;
- /* fall through */
+ fallthrough;
case 0x54: ch ++;
- /* fall through */
+ fallthrough;
case 0x40: ch ++;
- /* fall through */
+ fallthrough;
case 0x2c: /* MCSPI_CHCONF */
return s->ch[ch].config;
case 0x6c: ch ++;
- /* fall through */
+ fallthrough;
case 0x58: ch ++;
- /* fall through */
+ fallthrough;
case 0x44: ch ++;
- /* fall through */
+ fallthrough;
case 0x30: /* MCSPI_CHSTAT */
return s->ch[ch].status;
case 0x70: ch ++;
- /* fall through */
+ fallthrough;
case 0x5c: ch ++;
- /* fall through */
+ fallthrough;
case 0x48: ch ++;
- /* fall through */
+ fallthrough;
case 0x34: /* MCSPI_CHCTRL */
return s->ch[ch].control;
case 0x74: ch ++;
- /* fall through */
+ fallthrough;
case 0x60: ch ++;
- /* fall through */
+ fallthrough;
case 0x4c: ch ++;
- /* fall through */
+ fallthrough;
case 0x38: /* MCSPI_TX */
return s->ch[ch].tx;
case 0x78: ch ++;
- /* fall through */
+ fallthrough;
case 0x64: ch ++;
- /* fall through */
+ fallthrough;
case 0x50: ch ++;
- /* fall through */
+ fallthrough;
case 0x3c: /* MCSPI_RX */
s->ch[ch].status &= ~(1 << 0); /* RXS */
ret = s->ch[ch].rx;
omap_mcspi_transfer_run(s, ch);
return ret;
}
OMAP_BAD_REG(addr);
return 0;
}
@@ -225,117 +225,117 @@ static uint64_t omap_mcspi_read(void *opaque, hwaddr addr, unsigned size)
static void omap_mcspi_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mcspi_s *s = opaque;
int ch = 0;
if (size != 4) {
omap_badwidth_write32(opaque, addr, value);
return;
}
switch (addr) {
case 0x00: /* MCSPI_REVISION */
case 0x14: /* MCSPI_SYSSTATUS */
case 0x30: /* MCSPI_CHSTAT0 */
case 0x3c: /* MCSPI_RX0 */
case 0x44: /* MCSPI_CHSTAT1 */
case 0x50: /* MCSPI_RX1 */
case 0x58: /* MCSPI_CHSTAT2 */
case 0x64: /* MCSPI_RX2 */
case 0x6c: /* MCSPI_CHSTAT3 */
case 0x78: /* MCSPI_RX3 */
OMAP_RO_REG(addr);
return;
case 0x10: /* MCSPI_SYSCONFIG */
if (value & (1 << 1)) /* SOFTRESET */
omap_mcspi_reset(s);
s->sysconfig = value & 0x31d;
break;
case 0x18: /* MCSPI_IRQSTATUS */
if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) {
s->irqst &= ~value;
omap_mcspi_interrupt_update(s);
}
break;
case 0x1c: /* MCSPI_IRQENABLE */
s->irqen = value & 0x1777f;
omap_mcspi_interrupt_update(s);
break;
case 0x20: /* MCSPI_WAKEUPENABLE */
s->wken = value & 1;
break;
case 0x24: /* MCSPI_SYST */
if (s->control & (1 << 3)) /* SYSTEM_TEST */
if (value & (1 << 11)) { /* SSB */
s->irqst |= 0x1777f;
omap_mcspi_interrupt_update(s);
}
s->systest = value & 0xfff;
break;
case 0x28: /* MCSPI_MODULCTRL */
if (value & (1 << 3)) /* SYSTEM_TEST */
if (s->systest & (1 << 11)) { /* SSB */
s->irqst |= 0x1777f;
omap_mcspi_interrupt_update(s);
}
s->control = value & 0xf;
break;
case 0x68: ch ++;
- /* fall through */
+ fallthrough;
case 0x54: ch ++;
- /* fall through */
+ fallthrough;
case 0x40: ch ++;
- /* fall through */
+ fallthrough;
case 0x2c: /* MCSPI_CHCONF */
if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */
omap_mcspi_dmarequest_update(s->ch + ch);
if (((value >> 12) & 3) == 3) { /* TRM */
qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid TRM value (3)\n",
__func__);
}
if (((value >> 7) & 0x1f) < 3) { /* WL */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid WL value (%" PRIx64 ")\n",
__func__, (value >> 7) & 0x1f);
}
s->ch[ch].config = value & 0x7fffff;
break;
case 0x70: ch ++;
- /* fall through */
+ fallthrough;
case 0x5c: ch ++;
- /* fall through */
+ fallthrough;
case 0x48: ch ++;
- /* fall through */
+ fallthrough;
case 0x34: /* MCSPI_CHCTRL */
if (value & ~s->ch[ch].control & 1) { /* EN */
s->ch[ch].control |= 1;
omap_mcspi_transfer_run(s, ch);
} else
s->ch[ch].control = value & 1;
break;
case 0x74: ch ++;
- /* fall through */
+ fallthrough;
case 0x60: ch ++;
- /* fall through */
+ fallthrough;
case 0x4c: ch ++;
- /* fall through */
+ fallthrough;
case 0x38: /* MCSPI_TX */
s->ch[ch].tx = value;
s->ch[ch].status &= ~(1 << 1); /* TXS */
omap_mcspi_transfer_run(s, ch);
break;
default:
OMAP_BAD_REG(addr);
return;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 73/78] hw/watchdog/wdt_diag288.c: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (71 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 72/78] hw/ssi: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 74/78] hw/cxl/cxl-device-utils.c: " Emmanouil Pitsidianakis
` (5 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Thomas Huth, Halil Pasic,
Christian Borntraeger, open list:S390 general arch...
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/watchdog/wdt_diag288.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/watchdog/wdt_diag288.c b/hw/watchdog/wdt_diag288.c
index 76d89fbf78..24fb7fcb62 100644
--- a/hw/watchdog/wdt_diag288.c
+++ b/hw/watchdog/wdt_diag288.c
@@ -66,28 +66,28 @@ static void diag288_timer_expired(void *dev)
static int wdt_diag288_handle_timer(DIAG288State *diag288,
uint64_t func, uint64_t timeout)
{
switch (func) {
case WDT_DIAG288_INIT:
diag288->enabled = true;
- /* fall through */
+ fallthrough;
case WDT_DIAG288_CHANGE:
if (!diag288->enabled) {
return -1;
}
timer_mod(diag288->timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
timeout * NANOSECONDS_PER_SECOND);
break;
case WDT_DIAG288_CANCEL:
if (!diag288->enabled) {
return -1;
}
diag288->enabled = false;
timer_del(diag288->timer);
break;
default:
return -1;
}
return 0;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 74/78] hw/cxl/cxl-device-utils.c: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (72 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 73/78] hw/watchdog/wdt_diag288.c: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 75/78] migration: " Emmanouil Pitsidianakis
` (4 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis, Jonathan Cameron, Fan Ni
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/cxl/cxl-device-utils.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c
index bd68328032..63f009847e 100644
--- a/hw/cxl/cxl-device-utils.c
+++ b/hw/cxl/cxl-device-utils.c
@@ -78,18 +78,18 @@ static uint64_t mailbox_reg_read(void *opaque, hwaddr offset, unsigned size)
static void mailbox_mem_writel(uint32_t *reg_state, hwaddr offset,
uint64_t value)
{
switch (offset) {
case A_CXL_DEV_MAILBOX_CTRL:
- /* fallthrough */
+ fallthrough;
case A_CXL_DEV_MAILBOX_CAP:
/* RO register */
break;
default:
qemu_log_mask(LOG_UNIMP,
"%s Unexpected 32-bit access to 0x%" PRIx64 " (WI)\n",
__func__, offset);
return;
}
reg_state[offset / sizeof(*reg_state)] = value;
}
@@ -97,22 +97,22 @@ static void mailbox_mem_writel(uint32_t *reg_state, hwaddr offset,
static void mailbox_mem_writeq(uint64_t *reg_state, hwaddr offset,
uint64_t value)
{
switch (offset) {
case A_CXL_DEV_MAILBOX_CMD:
break;
case A_CXL_DEV_BG_CMD_STS:
/* BG not supported */
- /* fallthrough */
+ fallthrough;
case A_CXL_DEV_MAILBOX_STS:
/* Read only register, will get updated by the state machine */
return;
default:
qemu_log_mask(LOG_UNIMP,
"%s Unexpected 64-bit access to 0x%" PRIx64 " (WI)\n",
__func__, offset);
return;
}
reg_state[offset / sizeof(*reg_state)] = value;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 75/78] migration: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (73 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 74/78] hw/cxl/cxl-device-utils.c: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 8:55 ` Juan Quintela
2023-10-13 7:57 ` [RFC PATCH v2 76/78] qemu-img.c: " Emmanouil Pitsidianakis
` (3 subsequent siblings)
78 siblings, 1 reply; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Juan Quintela, Peter Xu, Fabiano Rosas,
Leonardo Bras
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
migration/migration.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/migration/migration.c b/migration/migration.c
index 585d3c8f55..fdad37efbb 100644
--- a/migration/migration.c
+++ b/migration/migration.c
@@ -2772,38 +2772,38 @@ static MigIterateState migration_iteration_run(MigrationState *s)
static void migration_iteration_finish(MigrationState *s)
{
/* If we enabled cpu throttling for auto-converge, turn it off. */
cpu_throttle_stop();
qemu_mutex_lock_iothread();
switch (s->state) {
case MIGRATION_STATUS_COMPLETED:
migration_calculate_complete(s);
runstate_set(RUN_STATE_POSTMIGRATE);
break;
case MIGRATION_STATUS_COLO:
assert(migrate_colo());
migrate_start_colo_process(s);
s->vm_old_state = RUN_STATE_RUNNING;
- /* Fallthrough */
+ fallthrough;
case MIGRATION_STATUS_FAILED:
case MIGRATION_STATUS_CANCELLED:
case MIGRATION_STATUS_CANCELLING:
if (s->vm_old_state == RUN_STATE_RUNNING) {
if (!runstate_check(RUN_STATE_SHUTDOWN)) {
vm_start();
}
} else {
if (runstate_check(RUN_STATE_FINISH_MIGRATE)) {
runstate_set(s->vm_old_state);
}
}
break;
default:
/* Should not reach here, but if so, forgive the VM. */
error_report("%s: Unknown ending state %d", __func__, s->state);
break;
}
migrate_fd_cleanup_schedule(s);
qemu_mutex_unlock_iothread();
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* Re: [RFC PATCH v2 75/78] migration: add fallthrough pseudo-keyword
2023-10-13 7:57 ` [RFC PATCH v2 75/78] migration: " Emmanouil Pitsidianakis
@ 2023-10-13 8:55 ` Juan Quintela
0 siblings, 0 replies; 91+ messages in thread
From: Juan Quintela @ 2023-10-13 8:55 UTC (permalink / raw)
To: Emmanouil Pitsidianakis
Cc: qemu-devel, Peter Xu, Fabiano Rosas, Leonardo Bras
Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org> wrote:
> In preparation of raising -Wimplicit-fallthrough to 5, replace all
> fall-through comments with the fallthrough attribute pseudo-keyword.
>
> Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Juan Quintela <quintela@redhat.com>
To make things easier for everybody involved, I think it is better than
this patch goes through your tree.
I didn't know about this C language feature. Find it very useful.
Thanks, Juan.
^ permalink raw reply [flat|nested] 91+ messages in thread
* [RFC PATCH v2 76/78] qemu-img.c: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (74 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 75/78] migration: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 77/78] tests/unit/test-char.c: " Emmanouil Pitsidianakis
` (2 subsequent siblings)
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Kevin Wolf, Hanna Reitz,
open list:Block layer core
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
qemu-img.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qemu-img.c b/qemu-img.c
index 6068ab0d27..df2457a6fe 100644
--- a/qemu-img.c
+++ b/qemu-img.c
@@ -1870,63 +1870,63 @@ static int coroutine_fn convert_co_read(ImgConvertState *s, int64_t sector_num,
static int coroutine_fn convert_co_write(ImgConvertState *s, int64_t sector_num,
int nb_sectors, uint8_t *buf,
enum ImgConvertBlockStatus status)
{
int ret;
while (nb_sectors > 0) {
int n = nb_sectors;
BdrvRequestFlags flags = s->compressed ? BDRV_REQ_WRITE_COMPRESSED : 0;
switch (status) {
case BLK_BACKING_FILE:
/* If we have a backing file, leave clusters unallocated that are
* unallocated in the source image, so that the backing file is
* visible at the respective offset. */
assert(s->target_has_backing);
break;
case BLK_DATA:
/* If we're told to keep the target fully allocated (-S 0) or there
* is real non-zero data, we must write it. Otherwise we can treat
* it as zero sectors.
* Compressed clusters need to be written as a whole, so in that
* case we can only save the write if the buffer is completely
* zeroed. */
if (!s->min_sparse ||
(!s->compressed &&
is_allocated_sectors_min(buf, n, &n, s->min_sparse,
sector_num, s->alignment)) ||
(s->compressed &&
!buffer_is_zero(buf, n * BDRV_SECTOR_SIZE)))
{
ret = blk_co_pwrite(s->target, sector_num << BDRV_SECTOR_BITS,
n << BDRV_SECTOR_BITS, buf, flags);
if (ret < 0) {
return ret;
}
break;
}
- /* fall-through */
+ fallthrough;
case BLK_ZERO:
if (s->has_zero_init) {
assert(!s->target_has_backing);
break;
}
ret = blk_co_pwrite_zeroes(s->target,
sector_num << BDRV_SECTOR_BITS,
n << BDRV_SECTOR_BITS,
BDRV_REQ_MAY_UNMAP);
if (ret < 0) {
return ret;
}
break;
}
sector_num += n;
nb_sectors -= n;
buf += n * BDRV_SECTOR_SIZE;
}
return 0;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 77/78] tests/unit/test-char.c: add fallthrough pseudo-keyword
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (75 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 76/78] qemu-img.c: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-13 7:57 ` [RFC PATCH v2 78/78] meson.build: increase -Wimplicit-fallthrough to 5 Emmanouil Pitsidianakis
2023-10-17 21:52 ` [RFC PATCH v2 00/78] Strict disable implicit fallthrough Eric Blake
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Emmanouil Pitsidianakis
In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
tests/unit/test-char.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/unit/test-char.c b/tests/unit/test-char.c
index 649fdf64e1..6f5a2c4108 100644
--- a/tests/unit/test-char.c
+++ b/tests/unit/test-char.c
@@ -56,25 +56,25 @@ static void fe_read(void *opaque, const uint8_t *buf, int size)
static void fe_event(void *opaque, QEMUChrEvent event)
{
FeHandler *h = opaque;
bool new_open_state;
h->last_event = event;
switch (event) {
case CHR_EVENT_BREAK:
break;
case CHR_EVENT_OPENED:
case CHR_EVENT_CLOSED:
h->openclose_count++;
new_open_state = (event == CHR_EVENT_OPENED);
if (h->is_open == new_open_state) {
h->openclose_mismatch = true;
}
h->is_open = new_open_state;
- /* fallthrough */
+ fallthrough;
default:
quit = true;
break;
}
}
#ifdef _WIN32
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* [RFC PATCH v2 78/78] meson.build: increase -Wimplicit-fallthrough to 5
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (76 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 77/78] tests/unit/test-char.c: " Emmanouil Pitsidianakis
@ 2023-10-13 7:57 ` Emmanouil Pitsidianakis
2023-10-17 21:52 ` [RFC PATCH v2 00/78] Strict disable implicit fallthrough Eric Blake
78 siblings, 0 replies; 91+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: Emmanouil Pitsidianakis, Alex Bennée,
Daniel P. Berrangé, Thomas Huth, Markus Armbruster,
Philippe Mathieu-Daudé, Juan Quintela, Paolo Bonzini,
Marc-André Lureau
Make GCC's implicit fall-through static analysis stricter by requiring
the use of the fallthrough attribute statement instead of comments.
This makes the QEMU code style more consistent.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
docs/devel/style.rst | 23 +++++++++++++++++++++++
meson.build | 2 +-
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/docs/devel/style.rst b/docs/devel/style.rst
index 2f68b50079..f473dd24e9 100644
--- a/docs/devel/style.rst
+++ b/docs/devel/style.rst
@@ -612,28 +612,51 @@ While this generally results in simpler, less leak-prone code, there
are still some caveats to beware of
* Variables declared with g_auto* MUST always be initialized,
otherwise the cleanup function will use uninitialized stack memory
* If a variable declared with g_auto* holds a value which must
live beyond the life of the function, that value must be saved
and the original variable NULL'd out. This can be simpler using
g_steal_pointer
.. code-block:: c
char *somefunc(void)
{
g_autofree char *foo = g_strdup_printf("foo%", "wibble");
g_autoptr (GList) bar = .....
if (eek) {
return NULL;
}
return g_steal_pointer(&foo);
}
+Implicit switch case fall-through
+=================================
+
+The C language allows switch cases to "fall-through" when a "break" statement
+is missing at the end of a case. This, however, introduces ambiguity in the
+code, as it's not always clear if the missing break is intentional or a bug.
+
+As this behaviour allows for bugs we do not allow "implicit fall-through".
+
+In order to identify intentional fall-through cases, we have adopted a
+pseudo-keyword macro 'fallthrough' which expands to gcc's extension
+__attribute__((__fallthrough__)). `Statement Attributes
+<https://gcc.gnu.org/onlinedocs/gcc/Statement-Attributes.html>`_
+
+All switch/case blocks must end in one of:
+
+.. code-block:: c
+
+ break;
+ fallthrough;
+ continue;
+ goto <label>;
+ return [expression];
QEMU Specific Idioms
********************
diff --git a/meson.build b/meson.build
index 79aef19bdc..e8805f0e0c 100644
--- a/meson.build
+++ b/meson.build
@@ -438,28 +438,28 @@ add_global_link_arguments(qemu_ldflags, native: false, language: all_languages)
warn_flags = [
'-Wundef',
'-Wwrite-strings',
'-Wmissing-prototypes',
'-Wstrict-prototypes',
'-Wredundant-decls',
'-Wold-style-declaration',
'-Wold-style-definition',
'-Wtype-limits',
'-Wformat-security',
'-Wformat-y2k',
'-Winit-self',
'-Wignored-qualifiers',
'-Wempty-body',
'-Wnested-externs',
'-Wendif-labels',
'-Wexpansion-to-defined',
- '-Wimplicit-fallthrough=2',
+ '-Wimplicit-fallthrough=5',
'-Wmissing-format-attribute',
'-Wno-initializer-overrides',
'-Wno-missing-include-dirs',
'-Wno-shift-negative-value',
'-Wno-string-plus-int',
'-Wno-typedef-redefinition',
'-Wno-tautological-type-limit-compare',
'-Wno-psabi',
'-Wno-gnu-variable-sized-type-not-at-end',
]
--
2.39.2
^ permalink raw reply related [flat|nested] 91+ messages in thread* Re: [RFC PATCH v2 00/78] Strict disable implicit fallthrough
2023-10-13 7:56 [RFC PATCH v2 00/78] Strict disable implicit fallthrough Emmanouil Pitsidianakis
` (77 preceding siblings ...)
2023-10-13 7:57 ` [RFC PATCH v2 78/78] meson.build: increase -Wimplicit-fallthrough to 5 Emmanouil Pitsidianakis
@ 2023-10-17 21:52 ` Eric Blake
78 siblings, 0 replies; 91+ messages in thread
From: Eric Blake @ 2023-10-17 21:52 UTC (permalink / raw)
To: Emmanouil Pitsidianakis; +Cc: qemu-devel
On Fri, Oct 13, 2023 at 10:56:27AM +0300, Emmanouil Pitsidianakis wrote:
> /* resubmitted because git-send-email crashed with previous attempt */
>
> Hello,
>
> This RFC is inspired by the kernel's move to -Wimplicit-fallthrough=3
> back in 2019.[0]
> We take one step (or two) further by increasing it to 5 which rejects
> fall through comments and requires an attribute statement.
>
> [0]:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a035d552a93b
>
> The line differences are not many, but they spread all over different
> subsystems, architectures and devices. An attempt has been made to split
> them in cohesive patches to aid post-RFC review. Part of the RFC is to
> determine whether these patch divisions needs improvement.
>
> Main questions this RFC poses
> =============================
>
> - Is this change desirable and net-positive.
I think so - consistency eases code maintenance, and being able to
define a keyword-like macro used like any other control-flow statement
is nicer than a magic comment.
> - Should the `fallthrough;` pseudo-keyword be defined like in the Linux
> kernel, or use glib's G_GNUC_FALLTHROUGH, or keep the already existing
> QEMU_FALLTHROUGH macro.
This seems like it only affects the one place where we define the
keyword. As long as all switch statements actually using it stick to
one style, I'm less concerned about the magic used to get the style
working in the first place.
> - Should fallthrough comments be removed if they do not include extra
> information.
That would be fine by me - but we'll see what other reviewers say.
I'm going to review on just the files I normally touch.
>
> Some external resources
> =======================
>
> See the RFC discussion in the kernel:
>
> https://lore.kernel.org/lkml/1d2830aadbe9d8151728a7df5b88528fc72a0095.1564549413.git.joe@perches.com/
>
> The `fallthrough;` pseudo-keyword in the kernel source code:
>
> https://elixir.bootlin.com/linux/latest/C/ident/fallthrough
>
> In summary, I quote the doc comment and definition:
>
> /*
> * Add the pseudo keyword 'fallthrough' so case statement blocks
> * must end with any of these keywords:
> * break;
> * fallthrough;
> * continue;
> * goto <label>;
> * return [expression];
> *
> * gcc: https://gcc.gnu.org/onlinedocs/gcc/Statement-Attributes.html#Statement-Attributes
> */
> #if __has_attribute(__fallthrough__)
> # define fallthrough __attribute__((__fallthrough__))
> #else
> # define fallthrough do {} while (0) /* fallthrough */
> #endif
>
> Background - Motivation
> =======================
>
> The C switch statement allows you to conditionally goto different labels
> depending on a value. A break; statement conveniently goto's the end of
> the switch. If a "case" does not end in a break, we say that the control
> flow falls through the next case label, if any, implicitly. This can
> lead to bugs and QEMU uses the GCC warning -Wimplicit-fallthrough to
> prevent this.
>
> Currently, QEMU is built with -Wimplicit-fallthrough=2. This makes GCC's
> static analyzer check for a case-insensitive matches of the .*falls?[
> \t-]*thr(ough|u).* regular expression. This means the following list of
> comments taken from QEMU all disable the implicit fallthrough warning:
>
> - /* FALLTHRU */
> - /* fall through */
> - /* Fall through. */
> - /* Fall through... */
> - /* fall through if hEventTimeout is signaled */
> - /* FALL THROUGH */
>
> To keep a constistent code style, this commit adds a macro `fallthrough`
> that looks like a C keyword but expands to an attribute statement in
> supported compilers (GCC at the moment).
>
> Note: there was already such a macro, QEMU_FALLTHROUGH, and it was used
> only around 7 times in the code base. The first commit replaces it.
Seems reasonable to me; we'll see what other comments you get.
--
Eric Blake, Principal Software Engineer
Red Hat, Inc.
Virtualization: qemu.org | libguestfs.org
^ permalink raw reply [flat|nested] 91+ messages in thread