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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id a2sm13548051qtj.76.2021.03.16.08.43.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Mar 2021 08:43:54 -0700 (PDT) Subject: Re: [RFC PATCH 5/8] qtest/libqos: Restrict CPU I/O instructions To: Laszlo Ersek , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org References: <20210314232913.2607360-1-f4bug@amsat.org> <20210314232913.2607360-6-f4bug@amsat.org> From: Richard Henderson Message-ID: <66630c68-d8ff-45ca-24e6-bbef1fc566ee@linaro.org> Date: Tue, 16 Mar 2021 09:43:51 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::830; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x830.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Thomas Huth , Claudio Fontana , Paolo Bonzini , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Gerd Hoffmann Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 3/16/21 9:37 AM, Laszlo Ersek wrote: > (+Peter, comment below) > > On 03/15/21 00:29, Philippe Mathieu-Daudé wrote: >> Restrict CPU I/O instructions to architectures providing >> I/O bus. >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> tests/qtest/libqos/fw_cfg.h | 3 +++ >> tests/qtest/libqos/fw_cfg.c | 2 ++ >> 2 files changed, 5 insertions(+) >> >> diff --git a/tests/qtest/libqos/fw_cfg.h b/tests/qtest/libqos/fw_cfg.h >> index c6a7cf8cf05..3bfb6d6d55b 100644 >> --- a/tests/qtest/libqos/fw_cfg.h >> +++ b/tests/qtest/libqos/fw_cfg.h >> @@ -36,6 +36,8 @@ size_t qfw_cfg_get_file(QFWCFG *fw_cfg, const char *filename, >> >> QFWCFG *mm_fw_cfg_init(QTestState *qts, uint64_t base); >> void mm_fw_cfg_uninit(QFWCFG *fw_cfg); >> + >> +#ifdef TARGET_HAS_IOPORT >> QFWCFG *io_fw_cfg_init(QTestState *qts, uint16_t base); >> void io_fw_cfg_uninit(QFWCFG *fw_cfg); >> >> @@ -48,6 +50,7 @@ static inline void pc_fw_cfg_uninit(QFWCFG *fw_cfg) >> { >> io_fw_cfg_uninit(fw_cfg); >> } >> +#endif /* TARGET_HAS_IOPORT */ >> >> G_DEFINE_AUTOPTR_CLEANUP_FUNC(QFWCFG, mm_fw_cfg_uninit) >> >> diff --git a/tests/qtest/libqos/fw_cfg.c b/tests/qtest/libqos/fw_cfg.c >> index 6b8e1babe51..db2b83f5212 100644 >> --- a/tests/qtest/libqos/fw_cfg.c >> +++ b/tests/qtest/libqos/fw_cfg.c >> @@ -131,6 +131,7 @@ void mm_fw_cfg_uninit(QFWCFG *fw_cfg) >> g_free(fw_cfg); >> } >> >> +#ifdef TARGET_HAS_IOPORT >> static void io_fw_cfg_select(QFWCFG *fw_cfg, uint16_t key) >> { >> qtest_outw(fw_cfg->qts, fw_cfg->base, key); >> @@ -162,3 +163,4 @@ void io_fw_cfg_uninit(QFWCFG *fw_cfg) >> { >> g_free(fw_cfg); >> } >> +#endif /* TARGET_HAS_IOPORT */ >> > > I'm not sure the macro name is ideal; the PCI host on aarch64/"virt" > emulates IO Ports (it's possible to allocate PCI IO resources on > "virt"). From patch#3, TARGET_HAS_IOPORT does not seem to extend to arm64. Correct, aarch64 has memory-mapped pci io resources, they are not on a separate ioport address space as for x86 and avr. r~