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Iglesias" References: <20230619142333.429028-1-richard.henderson@linaro.org> <20230619142333.429028-2-richard.henderson@linaro.org> <2974a774-b55d-371a-5596-5be1938ad4af@linaro.org> From: Richard Henderson In-Reply-To: <2974a774-b55d-371a-5596-5be1938ad4af@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x62a.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/20/23 17:41, Philippe Mathieu-Daudé wrote: > On 19/6/23 16:23, Richard Henderson wrote: >> The microblaze architecture does not reorder instructions. >> While there is an MBAR wait-for-data-access instruction, >> this concerns synchronizing with DMA. >> >> This should have been defined when enabling MTTCG. >> >> Cc: Alistair Francis >> Cc: Edgar E. Iglesias >> Fixes: d449561b130 ("configure: microblaze: Enable mttcg") >> Signed-off-by: Richard Henderson >> --- >>   target/microblaze/cpu.h | 3 +++ >>   1 file changed, 3 insertions(+) >> >> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h >> index 88324d0bc1..b474abcc2a 100644 >> --- a/target/microblaze/cpu.h >> +++ b/target/microblaze/cpu.h >> @@ -24,6 +24,9 @@ >>   #include "exec/cpu-defs.h" >>   #include "qemu/cpu-float.h" >> +/* MicroBlaze is always in-order. */ >> +#define TCG_GUEST_DEFAULT_MO  TCG_MO_ALL > > Targets missing such definition: > > - cris > - m68k > - nios2 > - rx > - sh4 > - sparc/64 (!) > - tricore > > I expect targets designed for embedded systems > to be in-order for power efficiency. > > What about having each target being explicit about that, > having a build failure if TCG_GUEST_DEFAULT_MO is not defined, > instead of the '#ifdef TCG_GUEST_DEFAULT_MO' in accel/tcg/? I'd be ok with that. r~