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[176.184.54.166]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8d25cebcb2sm366448166b.153.2024.09.09.10.40.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Sep 2024 10:40:34 -0700 (PDT) Message-ID: <667c28a5-3c00-4de2-b37e-566dc7ffca14@linaro.org> Date: Mon, 9 Sep 2024 19:40:32 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] hw/char/stm32l4x5_usart.c: Fix ACK and min access size To: Peter Maydell , Jacob Abrams Cc: qemu-devel@nongnu.org, Arnaud Minier , =?UTF-8?Q?In=C3=A8s_Varhol?= References: <20240902061944.526873-1-satur9nine@gmail.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=philmd@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, (Cc'ing Arnaud & Inès who are listed as maintainers) On 6/9/24 18:12, Peter Maydell wrote: > On Mon, 2 Sept 2024 at 14:38, Jacob Abrams wrote: >> >> These changes allow the official STM32L4xx HAL UART driver to function >> properly with the b-l475e-iot01a machine. >> >> Modifying USART_CR1 TE bit should alter USART_ISR TEACK bit, and >> likewise for RE and REACK bit. >> >> USART registers may be accessed via 16-bit instructions. >> >> Reseting USART_CR1 UE bit should restore ISR to default value. >> >> Fixes: 87b77e6e01ca ("hw/char/stm32l4x5_usart: Enable serial read and write") >> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2540 >> Signed-off-by: Jacob Abrams > > Thanks for this patch. I have one question below, and one > minor nit. > >> --- >> hw/char/stm32l4x5_usart.c | 29 +++++++++++++++++++--- >> tests/qtest/stm32l4x5_usart-test.c | 39 +++++++++++++++++++++++++++++- >> 2 files changed, 64 insertions(+), 4 deletions(-) >> static void stm32l4x5_update_irq(Stm32l4x5UsartBaseState *s) >> { >> if (((s->isr & R_ISR_WUF_MASK) && (s->cr3 & R_CR3_WUFIE_MASK)) || >> @@ -367,7 +389,7 @@ static void stm32l4x5_usart_base_reset_hold(Object *obj, ResetType type) >> s->brr = 0x00000000; >> s->gtpr = 0x00000000; >> s->rtor = 0x00000000; >> - s->isr = 0x020000C0; >> + s->isr = ISR_RESET_VALUE; >> s->rdr = 0x00000000; >> s->tdr = 0x00000000; >> >> @@ -456,6 +478,7 @@ static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr, >> case A_CR1: >> s->cr1 = value; >> stm32l4x5_update_params(s); >> + stm32l4x5_update_isr(s); >> stm32l4x5_update_irq(s); >> return; >> case A_CR2: >> @@ -508,12 +531,12 @@ static const MemoryRegionOps stm32l4x5_usart_base_ops = { >> .endianness = DEVICE_NATIVE_ENDIAN, >> .valid = { >> .max_access_size = 4, >> - .min_access_size = 4, >> + .min_access_size = 2, >> .unaligned = false >> }, >> .impl = { >> .max_access_size = 4, >> - .min_access_size = 4, >> + .min_access_size = 2, >> .unaligned = false >> }, > > The effect of these is that a 16-bit write not aligned > to a (4-aligned) register offset will generate a GUEST_ERROR > logged message, and a 16-bit write aligned to a 4-aligned > register offset will write the value zero-extended to 32 bits. > That seems reasonable to me. Peter, are you describing the .valid.min_access_size 4 -> 2 change or the .impl.min_access_size one? My understanding of the implementation is a 32-bit one: REG32(CR1, 0x00) struct Stm32l4x5UsartBaseState { ... uint32_t cr1; static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr, uint64_t val64, unsigned int size) { ... switch (addr) { case A_CR1: s->cr1 = value; Am I missing something? Now, back to .valid.min_access_size, per the section "40.8 USART registers" of the reference manual: The peripheral registers have to be accessed by words (32 bits). So I don't get the "USART registers may be accessed via 16-bit instructions." part of this patch. Jacob, for clarity, can you split this patch in 3 distinct parts (TE bit, UE bit, unaligned access) so this discussion doesn't delay the part which are OK? Thanks, Phil.