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Tsirkin" , Paolo Bonzini , =?UTF-8?Q?Corvin_K=C3=B6hne?= References: <20250206121341.118337-1-corvin.koehne@gmail.com> <20250206121341.118337-5-corvin.koehne@gmail.com> Content-Language: en-US From: Tomita Moeko In-Reply-To: <20250206121341.118337-5-corvin.koehne@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=tomitamoeko@gmail.com; helo=mail-pl1-x641.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/6/25 20:13, Corvin Köhne wrote: > From: Corvin Köhne > > We're currently missing some GPU IDs already supported by the i915 > kernel driver. Additionally, we've treated IvyBridge as gen 6 in the > past. According to i915 it's gen 7 [1]. It shouldn't cause any issues > yet because we treat gen 6 and gen 7 the same way. Nevertheless, we > should use the correct generation to avoid any confusion. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/i915/i915_pci.c?h=v6.13#n330 > > Signed-off-by: Corvin Köhne > --- > hw/vfio/igd.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c > index e5d7006ce2..7bbf018efc 100644 > --- a/hw/vfio/igd.c > +++ b/hw/vfio/igd.c > @@ -64,7 +64,7 @@ struct igd_device { > > static const struct igd_device igd_devices[] = { > INTEL_SNB_IDS(IGD_DEVICE, 6), > - INTEL_IVB_IDS(IGD_DEVICE, 6), > + INTEL_IVB_IDS(IGD_DEVICE, 7), > INTEL_HSW_IDS(IGD_DEVICE, 7), > INTEL_VLV_IDS(IGD_DEVICE, 7), > INTEL_BDW_IDS(IGD_DEVICE, 8), > @@ -73,8 +73,10 @@ static const struct igd_device igd_devices[] = { > INTEL_BXT_IDS(IGD_DEVICE, 9), > INTEL_KBL_IDS(IGD_DEVICE, 9), > INTEL_CFL_IDS(IGD_DEVICE, 9), > + INTEL_WHL_IDS(IGD_DEVICE, 9), > INTEL_CML_IDS(IGD_DEVICE, 9), > INTEL_GLK_IDS(IGD_DEVICE, 9), > + INTEL_CNL_IDS(IGD_DEVICE, 9), > INTEL_ICL_IDS(IGD_DEVICE, 11), > INTEL_EHL_IDS(IGD_DEVICE, 11), > INTEL_JSL_IDS(IGD_DEVICE, 11), > @@ -86,6 +88,8 @@ static const struct igd_device igd_devices[] = { > INTEL_RPLS_IDS(IGD_DEVICE, 12), > INTEL_RPLU_IDS(IGD_DEVICE, 12), > INTEL_RPLP_IDS(IGD_DEVICE, 12), > + INTEL_ARL_IDS(IGD_DEVICE, 12), > + INTEL_MTL_IDS(IGD_DEVICE, 12), According to i915 driver [1], DSM becomes a part of BAR 2 in MTL/ARL. All accesses to DSM from CPU should be via BAR I think. BARs are mapped in guest address space to host address space by QEMU when passthrough, as a common behavior, just like normal discrete GPUs. Though IGD takes a memory region as DSM, it should be reserved by firmware and not directly accessible by host also, like GTT memory, since arch/x86/kernel/early-quirks.c no longer reserves DSM for MTL/ ARL. Appling the BDSM quirk would bring issues to MTL/ARL. Probably there is no special workarounds needed for MTL and later IGD devices. But intel hasn't made the MTL/ARL/LNL datasheet publicly available yet, I can not confirm it :( If Intel really decided to not using BDSM on MTL+, we can just have a fixed id list for igd devices. [1] https://github.com/torvalds/linux/blob/69b8923f5003664e3ffef102e73333edfa2abdcf/drivers/gpu/drm/i915/gem/i915_gem_stolen.c#L918 > }; > > /*