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[88.21.68.240]) by smtp.gmail.com with ESMTPSA id y12sm3382411wrn.74.2019.09.26.08.46.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 Sep 2019 08:46:38 -0700 (PDT) Subject: Re: illegal hardware instruction during MIPS-I ELF linux useremulation To: Libo Zhou , "Peter&nbsp;Maydell" References: From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: <66b6b01d-f2b9-7715-982d-ae8106e40dc7@redhat.com> Date: Thu, 26 Sep 2019 17:46:37 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: r-Ecg--AP-uHKbnOOcXZaA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel , "Aleksandar& nbsp; Markovic" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/26/19 4:31 PM, Libo Zhou wrote: >> If you look at the mips_defs[] array in >> target/mips/translate_init.inc.c, the older ISA implemented is MIPS-II: >=20 >> $ git grep .insn_flags target/mips/translate_init.inc.c >> translate_init.inc.c:75: .insn_flags =3D CPU_MIPS32, >> translate_init.inc.c:97: .insn_flags =3D CPU_MIPS32 | ASE_MIPS16, >> translate_init.inc.c:117: .insn_flags =3D CPU_MIPS32, >> translate_init.inc.c:137: .insn_flags =3D CPU_MIPS32 | ASE_MIPS16= , >> translate_init.inc.c:158: .insn_flags =3D CPU_MIPS32R2, >> translate_init.inc.c:179: .insn_flags =3D CPU_MIPS32R2 | ASE_MIPS= 16, >> translate_init.inc.c:201: .insn_flags =3D CPU_MIPS32R2 | ASE_MIPS= 16, >> translate_init.inc.c:223: .insn_flags =3D CPU_MIPS32R2 | ASE_MIPS= 16 | ASE_DSP, >> translate_init.inc.c:249: .insn_flags =3D CPU_MIPS32R2 | ASE_MIPS= 16, >> translate_init.inc.c:297: .insn_flags =3D CPU_MIPS32R2 | ASE_MIPS= 16 | ASE_DSP | ASE_MT, >> translate_init.inc.c:323: .insn_flags =3D CPU_MIPS32R2 | ASE_MIPS= 16 | ASE_DSP | ASE_DSP_R2, >> translate_init.inc.c:343: .insn_flags =3D CPU_MIPS32R2 | ASE_MICR= OMIPS, >> translate_init.inc.c:364: .insn_flags =3D CPU_MIPS32R2 | ASE_MICR= OMIPS, >> translate_init.inc.c:410: .insn_flags =3D CPU_MIPS32R5 | ASE_MSA, >> translate_init.inc.c:449: .insn_flags =3D CPU_MIPS32R6 | ASE_MICR= OMIPS, >> translate_init.inc.c:488: .insn_flags =3D CPU_NANOMIPS32 | ASE_DS= P | ASE_DSP_R2 | ASE_DSP_R3 | >> translate_init.inc.c:511: .insn_flags =3D CPU_MIPS3, >> translate_init.inc.c:531: .insn_flags =3D CPU_VR54XX, >> translate_init.inc.c:552: .insn_flags =3D CPU_MIPS64, >> translate_init.inc.c:578: .insn_flags =3D CPU_MIPS64, >> translate_init.inc.c:607: .insn_flags =3D CPU_MIPS64 | ASE_MIPS3D= , >> translate_init.inc.c:636: .insn_flags =3D CPU_MIPS64R2 | ASE_MIPS= 3D, >> translate_init.inc.c:657: .insn_flags =3D CPU_MIPS64R2, >> translate_init.inc.c:681: .insn_flags =3D CPU_MIPS64R2, >> translate_init.inc.c:721: .insn_flags =3D CPU_MIPS64R6 | ASE_MSA, >> translate_init.inc.c:761: .insn_flags =3D CPU_MIPS64R6 | ASE_MSA, >> translate_init.inc.c:781: .insn_flags =3D CPU_LOONGSON2E, >> translate_init.inc.c:801: .insn_flags =3D CPU_LOONGSON2F, >> translate_init.inc.c:830: .insn_flags =3D CPU_MIPS64R2 | ASE_DSP = | ASE_DSP_R2, >=20 >> So currently there is no MIPS-I only CPU. >> Note that the code got written with MIPS32 in mind, and implementing >> MIPS-I requires a considerable amount of change in the codebase. >=20 > Hi Philippe, >=20 > I just figured out what the problem was. The custom compiler I used just = modified the opcode fields of sw and lw instructions of MIPS, so QEMU didn'= t recognize them out of the box. > I just added the support in decode_opc function in translate.c, and I als= o added my own CPU model in translate_init.inc.c. However, the illegal inst= ruction exception is still there. >=20 > I am suspecting that the way I added my own CPU model in translate_init.i= nc.c is wrong. Below is what I added: > ... > +{ > + .name =3D "MyCPU", > + .insn_flags =3D CPU_MIPS1 | INSN_MYCPU, > +}, > ... > I just need to simulate it's instruction set in linux user emulation, I d= idn't include CP0* items in the list. Is this good enough to add a new CPU = model? Something like that might be acceptable for linux-user. You should at least set CP0_PRid/Config0/Status_mask. Look at this patch where Aleksandar accepted the R5900 CPU: https://git.qemu.org/?p=3Dqemu.git;a=3Dcommitdiff;h=3Ded4f49ba9bb56 Can you share what is your CPU?