From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, bmeng.cn@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH v2 5/5] target/riscv: Split the Hypervisor execute load helpers
Date: Wed, 28 Oct 2020 08:22:29 -0700 [thread overview]
Message-ID: <66b758d2-395f-142c-aa66-ba197c926364@linaro.org> (raw)
In-Reply-To: <a88d9bdcebe49ada0d0a69b37ac532124971c91c.1603896076.git.alistair.francis@wdc.com>
On 10/28/20 7:42 AM, Alistair Francis wrote:
> +target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address)
> {
> if (env->priv == PRV_M ||
> (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
> (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
> get_field(env->hstatus, HSTATUS_HU))) {
> + int mmu_idx = cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
> +
> + return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC());
> + }
> +
> + if (riscv_cpu_virt_enabled(env)) {
> + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
> + } else {
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + }
> + return 0;
> +}
> +
> +target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address)
> +{
> + if (env->priv == PRV_M ||
> + (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
> + (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
> + get_field(env->hstatus, HSTATUS_HU))) {
> + int mmu_idx = cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
>
> + return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC());
> }
Do not replicate the PRV tests.
My first suggestion is to compute this into TBFLAGS and test it at translate
time, so that these functions just become the one cpu_ld* call.
But failing that, at least split out the test + exception into a common helper
function.
r~
prev parent reply other threads:[~2020-10-28 15:26 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-28 14:42 [PATCH v2 0/5] Fix the Hypervisor access functions Alistair Francis
2020-10-28 14:42 ` [PATCH v2 1/5] target/riscv: Add a virtualised MMU Mode Alistair Francis
2020-10-28 15:13 ` Richard Henderson
2020-10-28 20:51 ` Alistair Francis
2020-10-28 21:33 ` Richard Henderson
2020-10-28 14:42 ` [PATCH v2 2/5] target/riscv: Set the virtualised MMU mode when doing hyp accesses Alistair Francis
2020-10-28 15:08 ` Richard Henderson
2020-10-28 14:42 ` [PATCH v2 3/5] target/riscv: Remove the HS_TWO_STAGE flag Alistair Francis
2020-10-28 15:11 ` Richard Henderson
2020-10-28 14:42 ` [PATCH v2 4/5] target/riscv: Remove the hyp load and store functions Alistair Francis
2020-10-28 15:18 ` Richard Henderson
2020-10-28 14:42 ` [PATCH v2 5/5] target/riscv: Split the Hypervisor execute load helpers Alistair Francis
2020-10-28 15:22 ` Richard Henderson [this message]
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